TWI717063B - Three-dimensional and type flash memory and manufacturing method thereof - Google Patents

Abstract

A three-dimensional AND type flash memory and a manufacturing method thereof includes steps below is provided. A stacked structure includes a first insulating layer and a first sacrificial layer is formed. A first pillar structure through the stacked structure includes a second insulating layer and a second sacrificial layer surrounded by thereof is formed. A second pillar structure through the stacked structure includes a channel layer and an insulating pillar surrounded by thereof is formed. The second sacrificial layer is located on both sides of the channel layer. The first sacrificial layer is removed. A lateral opening exposing a portion of the second insulating layer and the channel layer is formed. A gate insulating layer surrounding the exposed second insulating layer and channel layer is formed in the lateral opening. A gate layer is filled in the lateral opening. A conductive layer is used to replace the second sacrificial layer.

Description

Three-dimensional and type flash memory and manufacturing method thereof

The present invention relates to a three-dimensional flash memory and a manufacturing method thereof, and in particular to a three-dimensional flash memory and a manufacturing method thereof.

Non-volatile memory (such as flash memory) has the advantage that the stored data will not disappear even after power is off, so it has become a type of memory widely used in personal computers and other electronic devices.

At present, the flash memory commonly used in the industry includes NOR flash memory and NAND flash memory, but less attention is paid to AND flash memory. Since the AND flash memory can also be used in a multi-dimensional flash memory cell array, it has as much integration and area utilization as the reverse flash memory. Therefore, the development of plus-type flash memory has become the current trend.

The invention provides a method for manufacturing a three-dimensional sum-type flash memory, which has the effects of simple manufacturing process, high manufacturing process yield and the like.

The manufacturing method of the three-dimensional and type flash memory of the present invention includes the following steps. First, a stacked structure is formed on the substrate. The stacked structure includes first insulating layers and first sacrificial layers stacked alternately. Then, a first pillar structure penetrating the stack structure and having a rectangular-like outline is formed. The first pillar structure includes a second insulating layer and a second sacrificial layer, and the second insulating layer surrounds the second sacrificial layer. Afterwards, a second pillar structure penetrating the stack structure and having an elliptical profile is formed. The second pillar structure includes a channel layer and an insulating pillar, and the channel layer surrounds the insulating pillar. The second sacrificial layer is located on both sides of the channel layer and is in contact with the channel layer, and the second sacrificial layer faces the long axis section of the second column structure. Then, the first sacrificial layer is removed to form a lateral opening. The lateral opening exposes part of the second insulating layer and part of the channel layer. Then, a gate dielectric layer is formed in the lateral opening. The gate dielectric layer surrounds the exposed second insulating layer and the channel layer. Then, fill the gate layer in the lateral opening. Finally, the second sacrificial layer is replaced with a conductive layer.

The invention provides a three-dimensional and type flash memory, which has a fast operating speed.

The three-dimensional and type flash memory of the present invention includes a stacked structure and a pillar structure. The stacked structure is located on the substrate and includes first insulating layers and gate layers alternately arranged. A gate dielectric layer is arranged between the first insulating layer and the gate layer. The pillar structure penetrates the stack structure and includes an insulating pillar, a channel layer, a conductor layer, and a second insulating layer. The insulating column has an elliptical profile. The channel layer surrounds the insulating pillar. The conductor layer is located on both sides of the channel layer and is in contact with the channel layer, and the conductor layer faces the long axis section of the insulating column. The second insulating layer surrounds the sidewall of the conductor layer that is not in contact with the channel layer. Wherein, the gate dielectric layer surrounds the sidewalls of the pillar structure exposed by the first insulating layer.

Based on the above, the present invention can define the position where the conductor layer is to be formed later by sequentially forming the first pillar structure and the second pillar structure, so that the conductor layer can be formed by a simple process with high process yield. In addition, in the three-dimensional and type flash memory of the present invention, each pillar structure has an independent conductor layer. Therefore, the memory cell (gate electrode) can be arbitrarily selected by selecting a certain layer of gate layer and a certain layer of conductor layer. The intersection of the layer and column structure), so that the three-dimensional and type flash memory of the present invention has a fast operating speed.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

10.20: Three-dimensional and flash memory

100: base

101, 101a, 101b: stacked structure

102: first insulating layer

104: The first sacrifice layer

106: first opening

108, 108a, 108b: second insulating layer

110, 110a, 110b: second sacrificial layer

112: second opening

114: Channel layer

116: Insulating column

118: Ditch

120: side opening

122: gate dielectric layer

124: Gate layer

126, 126a, 126b: conductor layer

128: third insulating layer

130: first contact

132: second contact

134: Source line connection line

136: bit line connection line

D1: First direction

D2: second direction

P: Column structure

P1: The first column structure

P1’: The remaining first column structure

P2: Second column structure

R1: unit cell area

R2: Surrounding area

1A to 1L are schematic diagrams of a method for manufacturing a three-dimensional sum flash memory according to an embodiment of the invention.

Fig. 2 is a schematic side view of Fig. 1I.

3 is a schematic diagram of a three-dimensional sum flash memory according to another embodiment of the invention.

1A to 1L are schematic diagrams of a method for manufacturing a three-dimensional sum flash memory according to an embodiment of the invention. Fig. 2 is a schematic side view of Fig. 1I.

1A, a stacked structure 101 is formed on the substrate 100. The substrate 100 may be a semiconductor substrate, for example, the substrate 100 may be a silicon substrate. In some real In an embodiment, a doped region (for example, an N+ doped region or an N-type well region) can be formed in the substrate 100 according to design requirements. In other embodiments, a buried oxide layer (not shown) may be further formed on the substrate 100. In this embodiment, the substrate 100 can define a unit cell region and a peripheral region due to subsequent processes.

The stacked structure 101 includes a plurality of first insulating layers 102 and a plurality of first sacrificial layers 104 alternately stacked. The material of the first insulating layer 102 is, for example, a dielectric material. For example, the material of the first insulating layer 102 may be silicon oxide. The material of the first sacrificial layer 104 is different from the material of the first insulating layer 102 and has a sufficient etching selection ratio with the first insulating layer 102. In some embodiments, the material of the first sacrificial layer 104 may be silicon nitride. The first insulating layer 102 and the first sacrificial layer 104 are formed, for example, by performing multiple chemical vapor deposition processes. It should be noted here that the number of layers of the first insulating layer 102 and the first sacrificial layer 104 in the stacked structure 101 is not limited to the embodiment shown in FIG. 1A. In detail, the first insulating layer 102 and the first The number of layers of a sacrificial layer 104 can be at least greater than 16, for example, the number of layers of the first insulating layer 102 and the first sacrificial layer 104 can be, for example, 56, 64, 96; however, the present invention is not limited thereto. The number of layers of the first insulating layer 102 and the first sacrificial layer 104 in the stacked structure 101 may depend on the design and density of the desired three-dimensional flash memory.

Next, referring to FIG. 1B, a first opening 106 penetrating through the stack structure 101 is formed. The first opening 106 has, for example, a rectangular-like contour, that is, the contour from the top end to the bottom end of the first opening 106 is rectangular-like. It should be noted here that a rectangle-like can mean that at least one side of the rectangle is rounded instead of square, but the present invention is not limited to this, that is, the first An opening 106 may also have a rectangular outline. The side surface of the first opening 106 exposes, for example, a portion of the first insulating layer 102 and the first sacrificial layer 104, and the bottom surface of the first opening 106 exposes, for example, a portion of the substrate 100. Forming the first opening 106 through the stack structure 101 may be, for example, performing the following steps. First, a mask layer (not shown) is formed on the stacked structure 101. The mask layer has, for example, openings with a rectangular-like outline. After that, an etching process is performed on the stacked structure 101 by using the mask layer to form the first opening 106 in the stacked structure 101. In this embodiment, the first opening 106 may have substantially vertical side walls. Based on this, the first opening 106 is also referred to as a first vertical channel (VC) opening.

After that, referring to FIG. 1C, a second insulating layer 108 is formed on the sidewall of the first opening 106. The second insulating layer 108 may be, for example, a conformal layer. In detail, the second insulating layer 108 may conform to the shape of the first opening 106 to cover the first insulating layer 102 and the first sacrificial layer on the sidewall of the first opening 106 104, and expose the substrate 100 at the bottom surface of the first opening 106. In other words, the second insulating layer 108 and the first opening 106 have similar shapes and contours. The second insulating layer 108 may have a material similar to the first insulating layer 102, for example, the material of the second insulating layer 108 may be silicon oxide.

Please continue to refer to FIG. 1C to fill the second sacrificial layer 110 in the first opening 106. When the second insulating layer 108 is conformal to the first opening 106, the second sacrificial layer 110 also has a rectangular-like profile, for example. In this embodiment, the second sacrificial layer 110 fills the first opening 106. The second sacrificial layer 110 may, for example, have the same type as the first sacrificial layer 104 Similar materials, for example, the material of the second sacrificial layer 110 may be silicon nitride. In this embodiment, the second insulating layer 108 and the second sacrificial layer 110 constitute the first pillar structure P1, and the second insulating layer 108 surrounds the sidewall of the second sacrificial layer 110.

Next, referring to FIG. 1D, a second opening 112 penetrating through the stack structure 101 is formed. The second opening 112 has, for example, an elliptical contour, that is, the contour from the top end to the bottom end of the second opening 112 is elliptical. In this embodiment, the second opening 112 partially overlaps the first opening 106, and the extending direction of the long axis of the second opening 112 is orthogonal to the extending direction of the length of the first opening 106. In detail, in addition to removing part of the first insulating layer 102 and the first sacrificial layer 104, the formed second opening 112 will also remove part of the first pillar structure P1. In detail, in this embodiment, part of the second insulating layer 108 and the second sacrificial layer 110 are removed to form two second insulating layers 108a, 108b and two second sacrificial layers 110a, 110b, respectively. This is the remaining first pillar structure P1'. Based on this, the side surface of the second opening 112 exposes, for example, part of the first insulating layer 102, the first sacrificial layer 104, the second insulating layers 108a, 108b, and the two second sacrificial layers 110a, 110b. In addition, the bottom surface of the second opening 112 exposes a portion of the substrate 100, for example. Forming the second opening 112 penetrating the stack structure 101 may be, for example, performing the following steps. First, a mask layer (not shown) is formed on the stacked structure 101. The mask layer has, for example, an opening with an oval contour. After that, an etching process is performed on the stacked structure 101 by using the mask layer to form the second opening 112 in the stacked structure 101. In this embodiment, the second opening 112 may have substantially vertical sidewalls. Based on this, the second opening 112 is also referred to as a second vertical channel (VC) opening.

After that, referring to FIG. 1E, a channel layer 114 is formed on the sidewall of the second opening 112. The channel layer 114 can be, for example, a conformal layer. In detail, the channel layer 114 can conform to the shape of the second opening 112 to cover the first insulating layer 102, the first sacrificial layer 104, and the second insulating layer 102 on the sidewall of the second opening 112. The insulating layers 108a, 108b and the two second sacrificial layers 110a, 110b expose a portion of the substrate 100 on the bottom surface of the second opening 112. In other words, the channel layer 114 and the second opening 112 have similar shapes and contours. The material of the channel layer 114 may be a semiconductor material, for example, the material of the channel layer 114 may be polysilicon or doped polysilicon. The above-mentioned doped polysilicon can be doped by in-situ doping or ion implantation process. The channel layer 114 can be used as a bit line, for example.

Please continue to refer to FIG. 1E to fill the insulating pillar 116 in the second opening 112. When the channel layer 114 is conformal to the second opening 112, the insulating pillar 116 also has an elliptical profile, for example. In this embodiment, the insulating pillar 116 fills the second opening 112. The insulating pillar 116 may have a material similar to the first insulating layer 102 and the second insulating layer 108, for example, the material of the insulating pillar 116 may be silicon oxide. In this embodiment, the channel layer 114 and the insulating pillar 116 constitute the second pillar structure P2, and the channel layer 114 surrounds the sidewall of the insulating pillar 116.

Next, referring to FIG. 1F, after the second pillar structure P2 is formed, the stacked structure 101 is patterned to form a stepped structure. It is pre-explained here that after the second column structure P2 is formed, the unit cell region R1 and the peripheral region R2 can be defined. In detail, the remaining first pillar structure P1' and the second pillar structure P2 formed are the unit cell region R1, and The remaining area is the peripheral area R2, and the step structure is formed in the peripheral area R2. The formation of the step structure is to perform a continuous patterning process on the part of the stack structure 101 where the first pillar structure P1 and the second pillar structure P2 are not formed. From another perspective, the distance between the first insulating layer 102 and the first sacrificial layer 104 protruding from the cell region R1 decreases as they gradually move away from the substrate 100. Afterwards, a planarization process is performed on the stepped structure (not shown in FIG. 1F). In other words, the step structure is filled with an insulating layer (not shown in FIG. 1F) to form a planarized surface.

After that, referring to FIG. 1G, a trench 118 penetrating the stacked structure 101 is formed. In this embodiment, the trench 118 is formed along the formation direction of the stepped structure to divide the stacked structure 101 into a pair of stacked structures 101a and 101b. The trench 118 exposes, for example, the first insulating layer 102 and the first sacrificial layer 104 on the sidewalls of the pair of stacked structures 101a and 101b facing each other. The formation of the trench 118 penetrating the stack structure 101 may be, for example, performing the following steps. First, a mask layer (not shown) is formed on the stacked structure 101. After that, an etching process is performed on the stacked structure 101 by using the mask layer to form a trench 118 in the stacked structure 101. In some embodiments, part of the substrate 100 is also removed after the trench is formed.

Next, referring to FIG. 1H, the first sacrificial layer 104 exposed by the lateral opening 120 is removed to form the lateral opening 120. The lateral opening 120 exposes, for example, a portion of the second insulating layer 108a, 108b and the channel layer 114, which is more clearly shown in FIG. 2A. The method for removing the first sacrificial layer 104 exposed by the lateral opening 120 is, for example, a dry etching method or a wet etching method, wherein the etchant used in the dry etching method is, for example, NF ₃ , H ₂ , HBr, O ₂ , N ₂ , He or a combination thereof, and the etchant used in the wet etching method is, for example, a phosphoric acid (H ₃ PO ₄ ) solution. In this embodiment, a wet etching method is used to remove the first sacrificial layer 104 exposed by the lateral opening 120.

After that, referring to FIG. 1I and FIG. 2 at the same time, a gate dielectric layer 122 is formed in the lateral opening 120. The gate dielectric layer 122 may be, for example, a conformal layer. In detail, the gate dielectric layer 122 may conform to the shape of the lateral opening 120 to cover the second insulating layers 108a, 108b and the channel layer 114 exposed by the lateral opening 120 ,as shown in picture 2. In addition, the gate dielectric layer 122 needs to have good step coverage to obtain good film thickness uniformity. The material of the gate dielectric layer 122 may be, for example, oxide, nitride, or a combination thereof. In some embodiments, the gate dielectric layer 122 includes an oxide-nitride-oxide (ONO) composite layer. For example, the gate dielectric layer 122 may include a composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. In other embodiments, the gate dielectric layer 122 may include an oxide-nitride-oxide-nitride-oxide (ONONO) composite layer. For example, the gate dielectric layer 122 may include a composite layer composed of a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. In addition, in some embodiments, the gate dielectric layer 122 may be further formed on the sidewalls of the first insulating layer 102 facing each other in the pair of stacked structures 101a and 101b.

After that, referring to FIG. 1J, the gate layer 124 is filled in the lateral opening 120. The material of the gate layer 124 can be, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi _x ), or cobalt silicide (CoSi _x ). The method of forming the gate layer 124 may be, for example, a chemical vapor deposition method. In this embodiment, the gate layer 124 can be used as a word line. In some embodiments, before filling the gate layer 124 in the lateral opening 120, a buffer layer (not shown) and a barrier layer (not shown) may be sequentially formed in the lateral opening 120. The material of the buffer layer can be, for example, a material with a high dielectric constant with a dielectric constant greater than 7, for example, the material of the buffer layer can be aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₅ ), transition metal oxides, lanthanide oxides, or combinations thereof. The method of forming the buffer layer may be, for example, a chemical vapor deposition method or an atomic layer deposition method. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The method of forming the barrier layer may be, for example, a chemical vapor deposition method.

After that, referring to FIG. 1K, the conductor layer 126 is used to replace the second sacrificial layers 110a and 110b. For example, the following steps are performed. First, dry etching or wet etching is performed to remove the second sacrificial layers 110a and 110b to form a third opening (not shown). Then, the conductive layer 126 is filled in the third opening. The material of the conductive layer 126 can be, for example, polysilicon, doped polysilicon, or other conductive metal materials. In this embodiment, the conductive layer 126 can be used as a source layer or a drain layer. For example, the conductive layer 126 of the second sacrificial layer 110a is replaced as a source layer, and the conductive layer 126 of the second sacrificial layer 110b is replaced as a drain layer, but the invention is not limited to this. The cross-sectional area of the conductor layer 126 replacing the second sacrificial layer 110a and the conductor layer 126 replacing the second sacrificial layer 110b may be the same or different, and the present invention is not particularly limited. The method for forming the source/drain layer of this embodiment is to use the conductor layer 126 to replace the previously formed second sacrificial layers 110a, 110b, which is a self-aligned process, therefore, it has a simple process and a high process yield. Wait effect. In addition, the formed source layer/drain layer has substantially the same distance from the gate layer 124 because the outer periphery is respectively provided with the second insulating layers 108a, 108b conformal to the gate layer 124, so that the three-dimensional sum of the embodiment of the present invention The flash memory 10 can operate stably.

In addition, before replacing the second sacrificial layers 110 a and 110 b with the conductive layer 126, a third insulating layer 128 may be filled in the trench 118 first. The third insulating layer 128 covers, for example, the gate dielectric layer 122 and the gate layer 124 on the sidewalls of the pair of stacked structures 101a and 101b facing each other.

Finally, referring to FIG. 1L, a first contact 130 electrically connected to the conductor layer 126 located in the unit cell region R1 and a second contact member 130 electrically connected to the gate layer 124 (which is a stepped structure) located in the peripheral region R2 are formed. Contact 132. For example, each conductor layer 126 is provided with a first contact 130 correspondingly, and each stepped gate layer 124 is provided with a second contact 132 correspondingly. Next, a source line connection line 134 and a bit line connection line 136 are formed. The source line connection line 134 connects the conductor layers 126 as the source layers in the pair of stacked structures 101a and 101b to each other through the first contact 130, for example. The bit line connection line 136 also electrically connects the conductive layer 126 as the drain layer in the pair of stacked structures 101a and 101b through the first contact 130, for example. The material of the source line connection line 134 and the bit line connection line 136 may be, for example, a metal material.

So far, the production of the three-dimensional and type flash memory 10 of the present invention is completed.

Although the method for manufacturing the three-dimensional sum flash memory 10 of this embodiment is described by taking the above-mentioned method as an example, the method for forming the three-dimensional sum flash memory 10 of the present invention is not limited to this.

Please continue to refer to FIG. 1L. FIG. 1L illustrates a schematic diagram of a three-dimensional plus flash memory according to an embodiment of the present invention. The three-dimensional plus flash memory 10 of the embodiment of the present invention includes a substrate 100, a stack structure 101, and a pillar structure P, wherein the pillar structure P penetrates the stack structure 101. The substrate 100 has, for example, a unit cell region R1 and a peripheral region R2, wherein the column structure P is located in the unit cell region, and a step structure is formed in the peripheral region R2. The stacked structure 101 is located on the substrate 100 and includes, for example, a pair of stacked structures 101a, 101b. A third insulating layer 128 may be provided between the pair of stacked structures 101a, 101b, for example. In an embodiment, the stacked structure 101 includes first insulating layers 102 and gate layers 124 alternately arranged. The portions of the first insulating layer 102 and the gate layer 124 protruding from the cell region R1 may form a stepped structure in the peripheral region R2, for example. In this embodiment, a gate dielectric layer 122 is provided between the first insulating layer 102 and the gate layer 124. It should be noted here that the gate dielectric layer 122 is not only disposed between the first insulating layer 102 and the gate layer 124. In detail, the gate dielectric layer 122 may be further disposed on the sidewalls of the first insulating layer 102 facing each other in the pair of stacked structures 101a and 101b. In addition, the gate dielectric layer 122 may be further disposed on the sidewall of the pillar structure P exposed by the first insulating layer 102, that is, the gate dielectric layer 122 surrounds the sidewall of the pillar structure P exposed by the first insulating layer 102.

In an embodiment, the pillar structure P includes an insulating pillar 116, a channel layer 114, a conductor layer 126, and second insulating layers 108a, 108b. The insulating column 116 has, for example, an elliptical contour, that is, the contour from the top end to the bottom end of the insulating column 116 is elliptical. The channel layer 114 surrounds the insulating pillar 116 and conforms to the insulating pillar 116. The conductor layer 126 is located on both sides of the channel layer 114 and is in contact with the channel layer 114. In other words, the conductor layer 126 can It includes two conductor layers 126a, 126b each located on the opposite side of the channel layer 114, and each can serve as a source and a drain. In this embodiment, the conductor layer 126 faces the long axis section of the insulating pillar 116. The second insulating layers 108a and 108b respectively surround the sidewalls of the conductor layer 126 that are not in contact with the channel layer 114, for example.

The three-dimensional and type flash memory 10 of the embodiment of the present invention may further include a first contact 130, a second contact 132, a source line connection line 134, and a bit line connection line 136. The first contact 130 is, for example, located on the cell region R1 and is electrically connected to the conductor layer 126, and the second contact 132 is, for example, located on the peripheral region R2 and is electrically connected to the gate layer 124. The source line connection line 134 electrically connects the conductor layer 126 as the source layer in the pair of stacked structures 101a, 101b, for example, through the first contact 130, and the bit line connection line 136, for example, also through the first contact The element 130 electrically connects the conductor layers 126 as drain layers in the pair of stacked structures 101a and 101b to each other.

In this embodiment, the column structures P are multiple and separated from each other. The pillar structures P are, for example, arranged in sequence along the first direction D1 and staggered in the second direction D2, where the second direction D2 is orthogonal to the first direction D1. Since the plurality of pillar structures P are separated from each other, each pillar structure P has an independent source and drain (conductor layer 126). Therefore, it can be arbitrarily selected by selecting a certain layer of gate layer 124 and a certain layer of conductor layer 126 The memory cell (the crossing point of the gate layer 124 and the pillar structure P) enables the three-dimensional and flash memory 10 of this embodiment to have a fast operating speed.

3 is a schematic diagram of a three-dimensional sum flash memory according to another embodiment of the invention. It must be noted here that the embodiment of FIG. 3 follows the elements of the embodiment of FIG. 1L Part numbers and part of the content, where the same or similar numbers are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the description and effects of the foregoing embodiments. The following embodiments will not be repeated, and at least part of the descriptions not omitted in the embodiment of FIG. 3 can be referred to the subsequent content.

The difference between the three-dimensional sum flash memory 20 of this embodiment and the three-dimensional sum flash memory 10 of the previous embodiment is that the plurality of pillar structures P are not arranged in the first direction D1, and each pillar structure P It includes a plurality of insulating pillars 116, a plurality of channel layers 114, a plurality of conductor layers 126, and a plurality of second insulating layers 108a, 108b. In detail, since one pillar structure P has a plurality of insulating pillars 116 and a plurality of channel layers 114, most of the conductive layers 126 will contact the two adjacent channel layers 114 in the first direction D1, so that they It has an outline similar to the shape of a candied fruit. In addition, the plurality of pillar structures P are separated from each other in the second direction D2, and each pillar structure P has a plurality of shared source and drain electrodes (conductor layer 126). Therefore, it is possible to select a certain layer of gate layer 124 and certain two conductor layers 126 and arbitrarily select the memory cell (the intersection of the gate layer 124 and the pillar structure P), so that the three-dimensional sum flash memory 20 of this embodiment has a fast operating speed. In addition, since the source and drain (conductor layer 126) of each pillar structure P can be shared by adjacent memory cells, the size of the three-dimensional flash memory 20 can be further reduced.

In summary, in the above embodiment, by sequentially forming the first pillar structure and the second pillar structure, the position where the source layer/drain layer is to be formed subsequently can be defined, so that the source layer/drain layer It can be formed by a simple process with high process yield, and the shape The formed source/drain layer has substantially the same distance as the gate layer due to the conformal second insulating layer, so that the three-dimensional sum flash memory of the present invention can operate stably. In addition, in the three-dimensional and type flash memory of the present invention, each pillar structure has an independent conductor layer. Therefore, the memory cell (gate electrode) can be arbitrarily selected by selecting a certain layer of gate layer and a certain layer of conductor layer. The intersection of the layer and column structure), so that the three-dimensional and type flash memory of the present invention has a fast operating speed.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

10: Three-dimensional and type flash memory

100: base

101, 101a, 101b: stacked structure

108a, 108b: second insulating layer

114: Channel layer

116: Insulating column

122: gate dielectric layer

124: Gate layer

126, 126a, 126b: conductor layer

128: third insulating layer

130: first contact

132: second contact

134: Source line connection line

136: bit line connection line

D1: First direction

D2: second direction

P: Column structure

R1: unit cell area

R2: Surrounding area

Claims (10)

A method for manufacturing a three-dimensional and type flash memory includes: Forming a stacked structure on the substrate, wherein the stacked structure includes a first insulating layer and a first sacrificial layer alternately stacked; Forming a first pillar structure penetrating the stack structure and having a rectangular-like outline, wherein the first pillar structure includes a second insulating layer and a second sacrificial layer, and the second insulating layer surrounds the second sacrificial layer; A second pillar structure having an elliptical profile penetrating through the stack structure is formed, wherein the second pillar structure includes a channel layer and an insulating pillar, the channel layer surrounds the insulating pillar, and the second sacrificial layer is located at the Both sides of the channel layer are in contact with the channel layer, wherein the second sacrificial layer faces the long axis cross section of the second column structure; Removing the first sacrificial layer to form a side opening, wherein the side opening exposes part of the second insulating layer and part of the channel layer; Forming a gate dielectric layer in the lateral opening, wherein the gate dielectric layer surrounds the exposed second insulating layer and the channel layer; Filling the gate layer in the lateral opening; and The second sacrificial layer is replaced with a conductor layer. According to the method for manufacturing a three-dimensional sum flash memory described in the scope of the patent application, the step of forming the first pillar structure includes: Forming a first opening penetrating the stack structure, wherein the first opening has a rectangular-like outline; Forming the second insulating layer on the sidewall of the first opening; and Filling the second sacrificial layer in the first opening. According to the method for manufacturing a three-dimensional sum flash memory described in the scope of patent application 1, the step of forming the second pillar structure includes: Forming a second opening penetrating the stacked structure, wherein the second opening has an elliptical outline, and part of the second insulating layer and the second sacrificial layer are removed; Forming the channel layer on the sidewall of the second opening; and Fill the insulating column in the second opening. According to the method for manufacturing a three-dimensional sum flash memory described in claim 1, wherein the step of removing the first sacrificial layer to form the lateral opening includes: Forming a trench penetrating the stacked structure, wherein the trench exposes the first sacrificial layer; and The first sacrificial layer is etched sideways. The method for manufacturing a three-dimensional sum flash memory as described in claim 4, wherein after filling the gate layer in the lateral opening, a third insulating layer is filled in the trench . A three-dimensional and type flash memory, including: The stacked structure is located on the substrate and includes a first insulating layer and a gate layer alternately arranged, wherein a gate dielectric layer is arranged between the first insulating layer and the gate layer; and The column structure, which penetrates the stack structure, includes: Insulating column with an oval profile; A channel layer surrounding the insulating column; A conductor layer located on both sides of the channel layer and in contact with the channel layer, wherein the conductor layer faces the long axis section of the insulating column; and The second insulating layer surrounds the sidewall of the conductor layer that is not in contact with the channel layer, The gate dielectric layer surrounds the sidewalls of the pillar structure exposed by the first insulating layer. The three-dimensional sum flash memory described in item 6 of the scope of patent application includes a pair of the stacked structures, and a third insulating layer is arranged between the pair of stacked structures. In the three-dimensional sum flash memory described in claim 7, wherein the gate dielectric layer is provided on the sidewalls of the first insulating layer in the pair of stacked structures that face each other. The three-dimensional sum flash memory described in claim 6, wherein there are a plurality of the pillar structures, and the plurality of pillar structures are sequentially arranged in a first direction and aligned with the first direction. Staggered in the second orthogonal direction. The three-dimensional sum flash memory according to claim 6, wherein the pillar structure is multiple, and one of the multiple pillar structures includes a plurality of the insulating pillars and a plurality of the channels Layer, a plurality of the conductor layers, and a plurality of the second insulating layers.

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