TW202105344A - Display and driving circuit thereof - Google Patents

Abstract

A driving circuit applied in a display includes at least one X-direction shift register for outputting an X control signal; and at least one data driving block, coupled to the X-direction shift register. The data driving block selects a plurality of sub-pixels based on the X control signal from the X-direction shift register, a plurality of control signals and a plurality of selection signals, and writes a gray data signal into the selected sub-pixels.

Description

Display and its driving circuit

The invention relates to a display and its driving circuit.

Displays have been widely used in human daily life. For example, large-size monitors can be used as TVs, computer screens, etc. The small-size display can be used in small-size electronic products such as watches and bracelets.

For the existing display architecture of small-size displays, chip on film (COF) has foldability (flexibility), so it is more commonly used. However, due to the need for the relationship between the data driver IC and the COF, in the prior art, the small-size display also encounters the problem of a wider frame.

Therefore, how to save unnecessary costs (such as data driver IC and COF) and make the frame narrower is one of the directions of the industry.

According to an example of the present invention, a display driving circuit is provided for use in a display. The display driving circuit includes: at least one X-direction shift register for outputting an X control signal; and at least one data driving block, Coupled to the X-direction shift register, wherein the data drive block selects a plurality of selection signals through a plurality of selection signals according to the X control signal output by the X-direction shift register and a plurality of control signals Sub-pixels to write a grayscale data signal to the selected sub-pixels.

According to another example of the present invention, a display is provided, including: a power supply circuit that outputs a grayscale data signal and n control signals, where n is a positive integer; y columns, each of which includes m sub-pixels, m is a positive integer; (m/n) X-direction shift registers are coupled to the power circuit for outputting (m/n) X control signals; (m/n) data drive blocks are coupled Connected to the power circuit and the rows, wherein each of the data driving blocks is selected by a plurality of selection signals according to the X control signals output by the X direction shift registers and the control signals The sub-pixels in each row are used to write a gray-scale data signal to the selected sub-pixels.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

The technical terms in this specification refer to the customary terms in the technical field. If there are descriptions or definitions for some terms in this specification, the explanation of the part of the terms is based on the description or definitions in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

Figure 1 shows a schematic diagram of the structure of a display according to an exemplary embodiment of the present invention. As shown in FIG. 1, the display 100 according to an exemplary embodiment of the present case includes: a power supply circuit 110, a plurality of X-direction shift registers XSR1-XSR (m/n), and a plurality of data driving blocks B1-B ( m/n), a plurality of Y-direction shift registers YSR1-YSRy, and a plurality of sub-pixels P11, P12,..., P1(n-1), P1n,..., P1(m-n+1), P1(m-n+2), P1(m-1), P1m, P21, P22,..., P2(n-1), P2n,..., P2(m-n+1), P2(m-n+ 2), P2(m-1), P2m, Py1, Py2,..., Py(n-1), Pyn,..., Py(m-n+1), Py(m-n+2),..., Py (m-1), Pym. Among them, m represents the total number of sub-pixels in each column, n represents the total number of control signals C1-Cn output by the power supply circuit 110 (or the total number of control lines of the power supply circuit 110), and also represents The number of sub-pixels that can be updated during each sub-pixel charging time, and y represents the total number of columns in the display 100. Each data driving block B1-B (m/n) includes 2n transistors, and these transistors can be P-type transistors or N-type transistors or other similar circuits. For example, the data driving block B1 includes transistors T11,..., T1n, T21,..., T2n. Similarly, the data drive block B(m/n) includes transistors T1(m-n+1), T1(m-n+2),..., T1(m-1), T1m, T2(m-n+ 1), T2(m-n+2),..., T2(m-1), T2m.

The power supply circuit 110 is used for outputting clock signals CK1-CK4, an operating voltage VSS (for example, a ground voltage), and a start signal VST to the X-direction shift register XSR1. How the X-direction shift register XSR1-XSR(m/n) generates the X control signal XG1-XG(m/n) according to the clock signal CK1-CK4, the operating voltage VSS and the start signal VST can be found here. Omit it.

For the data driving block B1, the X control signal XG1 is further input to the control terminals of the transistors T11,..., T1n of the data driving block B1 (the transistors T11,..., T1n can also be referred to as the first group), To control whether the control signals C1, C2,..., C(n-1), and Cn output by the power supply circuit 110 can become the selection signals Sel1, Sel2,..., Sel(n-1), and Seln. The start signal VST is further input to the control terminals of the transistors T21,..., T2n of the data drive block B1 (the transistors T21,..., T2n can also be referred to as the second group) to reset the selection signals Sel1, Sel2 ,..., Sel(n-1) and Seln.

Similarly, for the data driving block B (m/n), the X control signal XG (m/n) is further input to the transistors T1 (m-n+1) and T1 of the data driving block B (m/n). (m-n+2),..., T1(m-1), T1m control terminals to control whether the control signals C1, C2,..., C(n-1) and Cn output by the power supply circuit 110 can become Select signals Sel(m-n+1), Sel(m-n+2),..., Sel(m-1), Selm. The X control signal XG(m/n)-1 is further input to the transistors T2(m-n+1), T2(m-n+2),..., T2(m- 1) The control terminal of T2m resets the selection signals Sel(m-n+1), Sel(m-n+2),..., Sel(m-1), Selm.

The power circuit 110 further outputs a gray-scale data signal VDATA, which represents the gray-scale voltage to be written into the sub-pixels P11~Pym. Of course, the grayscale voltages to be written in the pixels P11 to Pym of each time are independent of each other, and are determined by the power supply circuit 110.

The power supply circuit 110 further outputs a reference voltage VH for resetting the selection signals Sel1~Selm. For example, but not limited to, the reference voltage VH may be a logic high potential.

In the data drive block B1, the control ends of the transistors T11-T1n are all coupled to the X control signal XG1, and one ends of the transistors T11-T1n are respectively coupled to the control signals C1, C2,..., C(n-1 ), the other ends of the transistors T11-T1n respectively output selection signals Sel1, Sel2,..., Sel(n-1) and Seln to the sub-pixels P11, P12,..., P1(n-1), P1n. The control terminals of the transistors T21-T2n are all coupled to the start signal VST, one end of the transistors T21-T2n are all coupled to the reference voltage VH, and the other ends of the transistors T21-T2n output the selection signals Sel1 and Sel2 respectively. ,..., Sel(n-1) and Seln give sub-pixels P11, P12,..., P1(n-1), P1n.

Similarly, in the data drive block B(m/n), the control terminals of the transistors T1(m-n+1)-T1m are all coupled to the X control signal XG(m/n), and the transistor T1( One end of m-n+1)-T1m is respectively coupled to control signals C1, C2,..., C(n-1), and the other end of transistor T1(m-n+1)-T1m respectively outputs selection signal Sel1 , Sel2,..., Sel(n-1) and Seln give the sub-pixels P1(m-n+1)-P1m. The control ends of the transistors T2(m-n+1)-T2m are all coupled to the X control signal XG(m/n)-1, and the ends of the transistors T2(m-n+1)-T2m are all coupled To the reference voltage VH, the other end of the transistor T2(m-n+1)-T2m respectively outputs selection signals Sel1, Sel2,..., Sel(n-1) and Seln to the sub-pixel P1(m-n+1) )-P1m.

The Y-direction shift registers YSR1-YSRy respectively output Y control signals YG1-YGy to the sub-pixels of each column.

Figure 2 shows a signal waveform diagram of the display according to an exemplary embodiment of the present case. As shown in Figure 2, after the X-direction shift register XSR1 receives the start signal VST, the X-direction shift register XSR1 generates the X control signal XG1. After that, after the X direction shift register XSR2 receives the X control signal XG1 generated by the X direction shift register XSR1, the X direction shift register XSR2 generates the X control signal XG2. The rest can be deduced by analogy. In the exemplary embodiment of this case, during the period during which the Y-direction shift register XSR1 generates the Y control signal YG1, the data driving blocks B1-B(m/n) can respectively write the gray-scale data signal VDATA to the first The sub-pixels P11~P1m of a column. The rest can be deduced by analogy.

FIG. 3 shows a circuit structure diagram of the sub-pixels of the display according to an exemplary embodiment of the present application. As shown in Figure 3, the sub-pixel Pab includes: transistors TA, TB, and a pixel circuit 30, a=1~y, b=1~m. Here, the actual circuit composition of the pixel circuit 30 may not be particularly limited. The control end of the transistor TA is coupled to the Y control signal YGi (i=1~y) output by the Y direction shift register, and one end of the transistor TA is coupled to the data line signal DLj (j=1~m) , The other end of the transistor TA is coupled to one end of the transistor TB. The control end of the transistor TB is coupled to the selection signal Selj, one end of the transistor TB is coupled to the other end of the transistor TA, and the other end of the transistor TB is coupled to the pixel circuit 30. The transistors TA and TB are illustrated by taking PMOS transistors as an example, but it should be understood that this case is not limited to this. When the Y control signal YGi and the selection signal Selj are both VL (VL=0 and VH=1), the data line signal DLj (that is, the gray-scale data signal VDATA) can be written into the pixel circuit 30.

The operation of the display 100 according to an exemplary embodiment of the present case will now be explained. Please refer to Figure 2, Figure 3, Figure 4A to Figure 4D. FIGS. 4A to 4D show that in the display 100 according to an exemplary embodiment of the present invention, the gray-scale voltage VL0 (VDATA=VL0) is written to the selected sub-pixel. The gray-scale voltages VL0~VL3 represent the gray-scale voltages with a gray-scale value of 0~3, and the rest can be deduced by analogy.

As shown in FIG. 4A, before starting to write the gray-scale data signal VDATA to the sub-pixels P11 to P1n in the first row, the selection signals Sel1 to Seln need to be reset. That is, at the time sequence E1 in Figure 2, the power supply circuit 110 outputs a high logic start signal VST to the control terminals of the transistors T21,..., T2n of the data driving block B1 to turn on the transistors T21,..., T2n, Therefore, the selection signals Sel1~Seln are reset by the high logic reference voltage VH. At this time, the Y-direction shift register YSR1 outputs a high-logic Y control signal YG1, as shown in timing E4 in Figure 3.

After that, at the time sequence E2, as shown in FIG. 4B, the X control signal XG1 is input to the control terminals of the transistors T11,..., T1n of the data driving block B1. In addition, in Figure 4B, the sub-pixels P11 and P12 are written with the gray-scale voltage VL0, and the sub-pixels P1(n-1) and P1n are written with the gray-scale voltage VL1. Therefore, the power supply circuit 110 outputs a high The logic control signals C1 and C2, and the power supply circuit 110 outputs low logic control signals C(n-1) and Cn. Therefore, the selection signals Sel1 and Sel2 are high logic, and the selection signals Sel(n-1) and Seln are low logic. Therefore, in Figure 4B, the transistors TA and TB in the sub-pixels P11 and P12 are both turned on, so that the gray-scale data signal VDATA (VDATA=VL0) can be written to the sub-pixels P11 and P12, on the contrary , The transistors TB in the sub-pixels P1(n-1) and P1n are both turned off, so that the gray-scale data signal VDATA (VDATA=VL0) cannot be written to the sub-pixels P1(n-1) and P1n. That is, the power supply circuit 110 outputs high logic or low logic control signals C1-Cn according to whether the grayscale data signals are to be written into the sub-pixels.

Similarly, as shown in Figure 4C, before writing the grayscale data signal VDATA to the sub-pixels P1(m+n-1)~P1m in the first row, the selection signals Sel(m+n- 1)~ Selm reset. That is, when the X control signal XG(m/n)-1 is high logic, the transistors T2(m+n-1),..., T2m are turned on, so that the selection signals Sel(m+n-1) )~ Selm is reset by the high logic reference voltage VH.

After that, at timing E3, as shown in Figure 4D, the X control signal XG(m/n) is input to the transistors T1(m+n-1),..., T1m of the data drive block B(m/n) Control terminal. In addition, in Figure 4D, the sub-pixel P1m needs to be written with the gray-scale voltage VL0, while the other sub-pixels are not written with the gray-scale voltage. Therefore, the power supply circuit 110 outputs a high-logic control signal Cn, and other control signals It is low logic. Therefore, the selection signal Selm is high logic, and the other selection signals are low logic. Therefore, in Figure 4D, the gray-scale data signal VDATA (VDATA=VL0) can be written to the sub-pixel P1m, and the gray-scale data signal VDATA (VDATA=VL0) cannot be written to other sub-pixels.

As for whether individual sub-pixels of other columns need to be written into VDATA (VDATA=VL0), it can be deduced from the operations in Figures 4A to 4D, which will not be repeated here.

The operation of writing the gray-scale voltage VL1 (VDATA=VL1) to the selected sub-pixel in the display 100 according to an exemplary embodiment of the present case will now be described. Please refer to Figure 2, Figure 3, Figure 5A to Figure 5D together.

As shown in FIG. 5A, before starting to write the grayscale data signal VDATA (=VL1) to the sub-pixels P11 to P1n in the first row, the selection signals Sel1 to Seln need to be reset. That is, the power supply circuit 110 outputs a high logic start signal VST to the control terminals of the transistors T21,..., T2n of the data driving block B1 to turn on the transistors T21,..., T2n, so that the selection signals Sel1~ Seln is reset by the high logic reference voltage VH. At this time, the Y direction shift register YSR1 outputs a high logic Y control signal YG1.

After that, as shown in FIG. 5B, the X control signal XG1 is input to the control terminals of the transistors T11,..., T1n of the data driving block B1. In addition, in Fig. 5B, the sub-pixels P1(n-1) and P1n need to be written with the gray-scale voltage VL1, while the remaining sub-pixels are not written with the gray-scale voltage VL1. Therefore, the power supply circuit 110 outputs a high logic level. The control signals C(n-1) and Cn, and the power supply circuit 110 outputs other control signals of low logic. Therefore, the selection signals Sel(n-1) and Seln are high logic, and the remaining selection signals are low logic. Therefore, in Figure 5B, the transistors TA and TB in the sub-pixels P1(n-1) and P1n are both turned on, so that the gray-scale data signal VDATA (VDATA=VL1) can be written to the sub-pixel P1 (n-1) In contrast to P1n, the transistors TB in the other sub-pixels are all turned off, so that the gray-scale data signal VDATA (VDATA=VL1) cannot be written to the remaining sub-pixels. That is, according to whether the sub-pixels are to be written into the grayscale data signal (VDATA=VL1), the power supply circuit 110 outputs the high logic or low logic control signals C1-Cn.

Similarly, as shown in FIG. 5C, when writing the gray-scale data signal VDATA Before (VL=1) to the sub-pixels P1(m+n-1)~P1m in the first column, the selection signals Sel(m+n-1)~Selm need to be reset. That is, when the X control signal XG(m/n)-1 is high logic, the transistors T2(m+n-1),..., T2m are turned on, so that the selection signals Sel(m+n-1) )~ Selm is reset by the high logic reference voltage VH.

After that, as shown in FIG. 5D, the X control signal XG (m/n) is input to the control terminals of the transistors T1 (m+n-1),..., T1m of the data driving block B (m/n). In addition, in Fig. 5D, the sub-pixel P1(m-1) needs to be written with the gray-scale voltage VL1, while the other sub-pixels are not written with the gray-scale voltage. Therefore, the power supply circuit 110 outputs a high logic control signal C(n-1), other control signals are low logic. Therefore, the selection signal Sel(m-1) is high logic, and the other selection signals are low logic. Therefore, in Figure 5D, the gray-scale data signal VDATA (VDATA=VL1) can be written to the sub-pixel P1 (m-1), and the gray-scale data signal VDATA (VDATA=VL1) cannot be written to other pixels. Sub-pixel.

As for whether the sub-pixels of other columns need to be written into VDATA (VDATA=VL1), it can be deduced by analogy with the operations in Figures 5A to 5D, which will not be repeated here.

That is, in the exemplary embodiment of this case, when writing the gray-scale voltage VL0, select the first row (YG1 is high logic), and select the sub-pixels to be driven by the data drive block B1 Write the sub-pixels of the gray-scale voltage VL0 and write the gray-scale voltage VL0 (that is, the corresponding selected control signal (C1-Cn) is high logic, and the remaining unselected control signals are low logic ); Then, from the sub-pixels driven by the data drive block B2, select the sub-pixels to be written with the gray-scale voltage VL0 and write the gray-scale voltage VL0, and so on, until it is driven by the data Among the sub-pixels driven by the block B (m/n), select the sub-pixel to be written with the gray-scale voltage VL0 and write the gray-scale voltage VL0. According to this, the gray-scale voltage VL0 is written into the selected sub-pixels in the first column.

After that, as described above, the second column is selected (YG2 is high logic), and the gray-scale voltage VL0 is written to the selected sub-pixel.

According to the above method, the third row to the y-th row are selected in sequence, and the gray-scale voltage VL0 is written to the selected sub-pixel.

After writing the gray-scale voltage VL0 to the selected sub-pixels in the first to y-th columns, the gray-scale voltage VL1~VLz (z is the total number of gray-scale voltages) is written to the first pixel as described above. The selected pixel from column to yth column.

Accordingly, it is possible to complete the writing of the gray-scale voltages VL0 to VLz to the selected sub-pixels from the first column to the y-th column.

The total data refreshing time per frame of each frame according to the exemplary embodiment of the present case will now be described. (Total data refreshing time per frame)=(c*m*y*z)/n, where c is a sub-frame The data charging time required for the pixel, and m is the total number of sub-pixels in a column, y is the total number of columns in the display 100, z is the total number of gray-scale voltages, and n is the control signal C1 output by the power circuit 110 -The total number of Cn (or the total number of control lines of the power supply circuit 110, also represents the number of sub-pixels that can be updated during each sub-pixel charging time).

In the embodiment of this case, n sub-pixels can be updated at a time (the upper limit of the sub-pixels that can be updated at one time depends on the total number of control lines), so for each gray-scale voltage, the update time for the display 100 is (c*m*y)/n, there are z gray-scale voltages, the total update time is (c*m*y*z)/n. From this, it can be deduced that the highest frame rate (Highest frame rate) that the display 100 can achieve: 1/((c*m*y*z)/n)=n/(c*m*y*z).

It can be seen from the above description that the advantages of the above exemplary embodiments of the present case are that since data driver ICs may not be required, unnecessary costs (such as data driver ICs and COF) can be saved, and the advantages of narrower borders can also be achieved.

To sum up, although the present invention has been disclosed as above by embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to those defined by the attached patent scope.

100: display 110: power supply circuit XSR1-XSR(m/n): X direction shift register B1-B(m/n): Data-driven block YSR1-YSRy: Y direction shift register P11-Pym: Sub-pixel C1-Cn: control signal T11~T2m: Transistor CK1-CK4: Clock signal VSS: Operating voltage VST: Start signal XG1-XG(m/n): X control signal Sel1, Sel2,..., Sel(n-1) and Seln: select signal VDATA: Grayscale data signal VH: Reference voltage YG1-YGy: Y control signal DL1~DLm: data line signal E1-E4: Timing Pab: sub-pixel TA, TB: Transistor 30: Pixel circuit VL0, VL1, VL2, VL3: grayscale voltage

Figure 1 shows a schematic diagram of the structure of a display according to an exemplary embodiment of the present invention. Figure 2 shows a signal waveform diagram of the display according to an exemplary embodiment of the present case. FIG. 3 shows a circuit structure diagram of the sub-pixels of the display according to an exemplary embodiment of the present application. 4A to 4D show that in the display according to an exemplary embodiment of the present application, the gray-scale voltage VL0 is written to the selected sub-pixel. FIG. 5A to FIG. 5D show that in the display according to an exemplary embodiment of the present application, the gray-scale voltage VL1 is written to the selected sub-pixel.

100: display

110: power supply circuit

XSR1-XSR(m/n): X direction shift register

B1-B(m/n): Data-driven block

YSR1-YSRy: Y direction shift register

P11-Pym: Sub-pixel

C1-Cn: control signal

T11~T2m: Transistor

CK1-CK4: Clock signal

VSS: Operating voltage

VST: Start signal

XG1-XG(m/n): X control signal

Sel1, Sel2,..., Sel(n-1) and Seln: select signal

VDATA: Grayscale data signal

VH: Reference voltage

YG1-YGy: Y control signal

DL1~DLm: data line signal

Claims (12)

A display driving circuit applied to a display, the display driving circuit includes: At least one X-direction shift register for outputting an X control signal; and At least one data drive block is coupled to the X-direction shift register, wherein the data drive block transmits a plurality of control signals according to the X control signal output by the X-direction shift register and a plurality of control signals The selection signal selects a plurality of sub-pixels to write a gray-scale data signal to the selected sub-pixels. According to the display driving circuit described in claim 1, wherein the data driving block includes a plurality of transistors, the transistors are divided into a first group and a second group, and the first group is controlled The X control signal is used to output the control signals as the selection signals. The selection signals control one of the sub-pixels one-to-one, and the second group is controlled by a start signal or a previous one The X control signal uses a reference voltage to reset the selection signals. According to the display driving circuit described in item 2 of the scope of patent application, the at least one X-direction shift register includes (m/n) X-direction shift registers to generate a plurality of X control signals, and the at least one X-direction shift register includes A data drive block includes (m/n) data drive blocks, where m represents the total number of all sub-pixels in a row, n represents the total number of the control signals, and each of the data drive blocks is responsible for driving the data in a row N sub-pixels of. According to the display driving circuit described in item 3 of the scope of patent application, before starting to write a first gray-scale data signal to the sub-pixels of the row, in the at least one data driving block, according to the start The start signal or the previous X control signal is used to reset the selection signals using the reference voltage. Such as the display driving circuit described in item 4 of the scope of patent application, wherein, when writing the first gray-scale data signal, According to the X control signals generated by the X-direction shift registers and according to the control signals, the data driving block writes the first gray-scale data signal to the selected time of each row of the display Within pixels. For the display driving circuit described in item 5 of the scope of patent application, wherein when writing a second gray-scale data signal, the first gray-scale data signal is different from the second gray-scale data signal, According to the X control signals generated by the X-direction shift registers and according to the control signals, the data driving block writes the second gray-scale data signal to the selected time of each row of the display Within pixels. A display including: A power supply circuit that outputs a gray-scale data signal and n control signals, where n is a positive integer; y columns, each of which includes m sub-pixels, and m is a positive integer; (m/n) X-direction shift registers, coupled to the power circuit, for outputting (m/n) X control signals; (m/n) data drive blocks, coupled to the power circuit and the rows, Wherein, each of the data driving blocks selects the sub-pixels in each row through a plurality of selection signals according to the X control signals output by the X direction shift registers and the control signals, To write a grayscale data signal to the selected sub-pixels. The display device described in claim 7, wherein each of the sub-pixels includes a first transistor, a second transistor, and a pixel circuit, wherein the first transistor is controlled by a Y A control signal, the second transistor is controlled by one of the selection signals, and the gray-scale data signal is written to the pixel circuit through the first and second transistors. The display according to claim 7, wherein each of the data driving blocks includes a plurality of transistors, and the transistors are divided into a first group and a second group, and the first group is controlled Output the control signals as the selection signals on one of the X control signals, the selection signals control one of the sub-pixels one-to-one, and the second group is controlled by a start signal or A previous X control signal is used to reset the selection signals using a reference voltage. For the display described in claim 9, wherein before starting to write a first gray-scale data signal to the sub-pixels of the series, in each of the data drive blocks, according to the start Signal or the previous X control signal and use the reference voltage to reset the selection signals. Such as the display described in item 10 of the scope of patent application, wherein, when writing the first gray-scale data signal, According to the X control signals generated by the X-direction shift registers and according to the control signals, the data driving block writes the first gray-scale data signal to the selected time of each row of the display Within pixels. For the display described in item 11 of the scope of patent application, wherein when writing a second gray-scale data signal, the first gray-scale data signal is different from the second gray-scale data signal, According to the X control signals generated by the X-direction shift registers and according to the control signals, the data driving block writes the second gray-scale data signal to the selected time of each row of the display Within pixels.

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