TW202046269A - Driving signal generator - Google Patents

Driving signal generator Download PDF

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TW202046269A
TW202046269A TW108119980A TW108119980A TW202046269A TW 202046269 A TW202046269 A TW 202046269A TW 108119980 A TW108119980 A TW 108119980A TW 108119980 A TW108119980 A TW 108119980A TW 202046269 A TW202046269 A TW 202046269A
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signal
transistor
level
voltage level
clock signal
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TW108119980A
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TWI709123B (en
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賴柏君
吳韋霆
施璇
張瑋軒
陳勇志
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友達光電股份有限公司
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Priority to CN201911258775.8A priority patent/CN110992865B/en
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

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  • Computer Hardware Design (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

A driving signal generator is provided. The driving signal generator includes a first stage generation circuit of emission signal, a second stage generation circuit of emission signal and a third stage generation circuit of emission signal. The first stage generation circuit of emission signal generates a first stage emission signal according to a former stage emission signal, a first clock signal and a third clock signal. The second stage generation circuit of emission signal generates a second stage emission signal according to the first stage emission signal, a second clock signal and the first clock signal. The third stage generation circuit of emission signal generates a third stage emission signal according to the second stage emission signal, a third clock signal and the second clock signal. In addition, the first clock signal, the second clock signal and the third clock signal are sequentially switched to a first voltage level.

Description

驅動訊號產生器Drive signal generator

本發明是有關於一種驅動訊號產生器,且特別是有關於一種可藉由較少數量的時脈訊號以驅動顯示面板中的畫素電路的驅動訊號產生器。The present invention relates to a driving signal generator, and more particularly to a driving signal generator that can drive pixel circuits in a display panel with a small number of clock signals.

在習知技術中,為了驅動顯示面板中的畫素電路,驅動訊號產生器需要較多數量的時脈訊號,以正確地驅動顯示面板中的畫素電路進行顯示動作。如此一來,驅動訊號產生器中增加的時脈訊號不但增加電路面積以及設計複雜度,更增加顯示面板的功率消耗。In the prior art, in order to drive the pixel circuits in the display panel, the driving signal generator requires a larger number of clock signals to correctly drive the pixel circuits in the display panel to perform display operations. In this way, the added clock signal in the driving signal generator not only increases the circuit area and design complexity, but also increases the power consumption of the display panel.

本發明提供一種驅動訊號產生器,可有效降低驅動顯示面板中的畫素電路所需的時脈訊號數量,進而降低硬體設計的複雜度以及顯示面板的功率消耗。The present invention provides a driving signal generator, which can effectively reduce the number of clock signals required for driving pixel circuits in a display panel, thereby reducing the complexity of hardware design and the power consumption of the display panel.

本發明提供一種驅動訊號產生器,其包含第一級激光訊號產生電路、第二級激光訊號產生電路及第三級激光訊號產生電路。當第一時脈訊號在第一電壓準位時,第一級激光訊號產生電路根據前級激光訊號輸出第一級激光訊號,且當第一時脈訊號在第二電壓準位時,第一級激光訊號產生電路透過第三時脈訊號維持第一級激光訊號之電壓準位。當第二時脈訊號在第一電壓準位時,第二級激光訊號產生電路根據第一級激光訊號輸出第二級激光訊號,且當第二時脈訊號在第二電壓準位時,第二級激光訊號產生電路透過第一時脈訊號維持第二級激光訊號之電壓準位。當第三時脈訊號在第一電壓準位時,第三級激光訊號產生電路根據第二級激光訊號輸出第三級激光訊號,且當第三時脈訊號在第二電壓準位時,第三級激光訊號產生電路透過第二時脈訊號維持第三級激光訊號之電壓準位。其中第一時脈訊號、第二時脈訊號及第三時脈訊號依序切換至第一電壓準位。The invention provides a drive signal generator, which includes a first-level laser signal generating circuit, a second-level laser signal generating circuit, and a third-level laser signal generating circuit. When the first clock signal is at the first voltage level, the first-level laser signal generating circuit outputs the first-level laser signal according to the previous laser signal, and when the first clock signal is at the second voltage level, the first-level laser signal The first-level laser signal generating circuit maintains the voltage level of the first-level laser signal through the third clock signal. When the second clock signal is at the first voltage level, the second-level laser signal generating circuit outputs the second-level laser signal according to the first-level laser signal, and when the second clock signal is at the second voltage level, the second-level laser signal The second-level laser signal generating circuit maintains the voltage level of the second-level laser signal through the first clock signal. When the third clock signal is at the first voltage level, the third-level laser signal generating circuit outputs the third-level laser signal according to the second-level laser signal, and when the third clock signal is at the second voltage level, the third-level laser signal The third-level laser signal generating circuit maintains the voltage level of the third-level laser signal through the second clock signal. The first clock signal, the second clock signal, and the third clock signal are sequentially switched to the first voltage level.

本發明還提供一種驅動訊號產生器,其包含第一級掃描訊號產生電路、第二級掃描訊號產生電路及第三級掃描訊號產生電路。當前級掃描訊號在第一電壓準位時,第一級掃描訊號產生電路根據第二時脈訊號輸出第一級掃描訊號,且當前級掃描訊號在第二電壓準位時,第一級掃描訊號產生電路透過第三時脈訊號維持第一級掃描訊號之電壓準位。當第一級掃描訊號在第一電壓準位時,第二級掃描訊號產生電路根據第三時脈訊號輸出第二級掃描訊號,且當第一級掃描訊號在第二電壓準位時,第二級掃描訊號產生電路透過第一時脈訊號維持第二級掃描訊號之電壓準位。當第二級掃描訊號在第一電壓準位時,第三級掃描訊號產生電路根據第一時脈訊號輸出第三級掃描訊號,且當第二級掃描訊號在第二電壓準位時,第三級掃描訊號產生電路透過第二時脈訊號維持第三級掃描訊號之電壓準位。其中第一時脈訊號、第二時脈訊號及第三時脈訊號依序切換至第一電壓準位。The present invention also provides a driving signal generator, which includes a first-stage scanning signal generating circuit, a second-stage scanning signal generating circuit, and a third-stage scanning signal generating circuit. When the current level scan signal is at the first voltage level, the first level scan signal generating circuit outputs the first level scan signal according to the second clock signal, and when the current level scan signal is at the second voltage level, the first level scan signal The generating circuit maintains the voltage level of the first-level scanning signal through the third clock signal. When the first level scan signal is at the first voltage level, the second level scan signal generating circuit outputs the second level scan signal according to the third clock signal, and when the first level scan signal is at the second voltage level, the second level scan signal The secondary scanning signal generating circuit maintains the voltage level of the secondary scanning signal through the first clock signal. When the second level scan signal is at the first voltage level, the third level scan signal generating circuit outputs the third level scan signal according to the first clock signal, and when the second level scan signal is at the second voltage level, the third level scan signal The three-level scanning signal generating circuit maintains the voltage level of the third-level scanning signal through the second clock signal. The first clock signal, the second clock signal, and the third clock signal are sequentially switched to the first voltage level.

基於上述,本發明的實施例藉由驅動訊號產生器可有效降低驅動顯示面板中的畫素電路所需的時脈訊號數量,進而降低硬體設計的複雜度以及顯示面板的功率消耗。Based on the above, the embodiment of the present invention can effectively reduce the number of clock signals required to drive the pixel circuits in the display panel by driving the signal generator, thereby reducing the complexity of hardware design and the power consumption of the display panel.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

請參考圖1,圖1為本發明實施例一驅動訊號產生器1的示意圖。驅動訊號產生器1適於提供驅動訊號至顯示面板,以驅動顯示面板中的畫素電路。其中,顯示面板中的畫素電路是透過依序致能(Enable)的激光訊號來進行驅動,以進行顯示動作且將畫面顯示於顯示面板上。因此,本發明的驅動訊號產生器1適於透過接收依序致能且致能時間不互相重疊的時脈訊號CK1、CK2、CK3,以產生依序致能的激光訊號EM1、EM2、EM3來驅動顯示面板中的畫素電路來進行顯示動作。Please refer to FIG. 1, which is a schematic diagram of a driving signal generator 1 according to an embodiment of the present invention. The driving signal generator 1 is suitable for providing driving signals to the display panel to drive the pixel circuits in the display panel. Among them, the pixel circuit in the display panel is driven by sequentially enabling (Enable) laser signals to perform display actions and display images on the display panel. Therefore, the driving signal generator 1 of the present invention is suitable for generating sequentially enabled laser signals EM1, EM2, EM3 by receiving clock signals CK1, CK2, CK3 that are sequentially enabled and the enabling time does not overlap with each other. The pixel circuits in the display panel are driven to perform display operations.

如圖1所示,驅動訊號產生器1包含串接連接的激光訊號產生電路10、11、12。激光訊號產生電路10接收前級激光訊號EM0以及時脈訊號CK1、CK3以產生激光訊號EM1。激光訊號產生電路11接收激光訊號EM0以及時脈訊號CK2、CK1以產生激光訊號EM2。激光訊號產生電路12接收激光訊號EM2以及時脈訊號CK3、CK2以產生激光訊號EM3。As shown in FIG. 1, the driving signal generator 1 includes laser signal generating circuits 10, 11, and 12 connected in series. The laser signal generating circuit 10 receives the previous laser signal EM0 and the clock signals CK1 and CK3 to generate the laser signal EM1. The laser signal generating circuit 11 receives the laser signal EM0 and the clock signals CK2 and CK1 to generate the laser signal EM2. The laser signal generating circuit 12 receives the laser signal EM2 and the clock signals CK3 and CK2 to generate the laser signal EM3.

關於激光訊號產生電路10/11/12的詳細結構請參考圖2,圖2為本發明一實施例激光訊號產生電路10/11/12的示意圖。如圖2所示,激光訊號產生電路10/11/12包含電晶體M11、上拉電路PU1、下拉電路PD1。電晶體M11的一端(例如源極)接收前級激光訊號EM0、激光訊號EM1、EM2的其中之一(激光訊號產生電路10中的電晶體M11接收前級激光訊號EM0,激光訊號產生電路11中的電晶體M11接收前級激光訊號EM1,激光訊號產生電路12中的電晶體M11接收前級激光訊號EM2,依此類推),電晶體M11的一端(例如汲極)耦接於節點N11,電晶體M11的控制端(例如閘極)接收時脈訊號CK1、CK2、CK3的其中之一。上拉電路PU1耦接於節點N11與激光輸出節點NO_EM之間,透過接收前級激光訊號EM0、激光訊號EM1、EM2的其中之一以及時脈訊號CK1、CK2、CK3的其中之一,以提供電壓準位Vref2至激光輸出點NO_EM。下拉電路PD1耦接於節點N11與激光輸出節點NO_EM之間,其接收時脈訊號CK3、CK1、CK2的其中之一,以提供電壓準位Vref1至激光輸出點NO_EM。激光訊號產生電路10/11/12透過激光輸出節點NO_EM輸出激光訊號EM1、EM2、EM3的其中之一。For the detailed structure of the laser signal generating circuit 10/11/12, please refer to FIG. 2. FIG. 2 is a schematic diagram of the laser signal generating circuit 10/11/12 according to an embodiment of the present invention. As shown in FIG. 2, the laser signal generating circuit 10/11/12 includes a transistor M11, a pull-up circuit PU1, and a pull-down circuit PD1. One end (such as the source) of the transistor M11 receives one of the pre-stage laser signal EM0, laser signals EM1 and EM2 (the transistor M11 in the laser signal generating circuit 10 receives the pre-stage laser signal EM0, and the laser signal generating circuit 11 The transistor M11 receives the pre-stage laser signal EM1, the transistor M11 in the laser signal generating circuit 12 receives the pre-stage laser signal EM2, and so on), one end (such as the drain) of the transistor M11 is coupled to the node N11, The control terminal (such as the gate) of the crystal M11 receives one of the clock signals CK1, CK2, CK3. The pull-up circuit PU1 is coupled between the node N11 and the laser output node NO_EM, and receives the pre-laser signal EM0, one of the laser signals EM1, EM2, and one of the clock signals CK1, CK2, CK3 to provide Voltage level Vref2 to laser output point NO_EM. The pull-down circuit PD1 is coupled between the node N11 and the laser output node NO_EM, and receives one of the clock signals CK3, CK1, CK2 to provide a voltage level Vref1 to the laser output node NO_EM. The laser signal generating circuit 10/11/12 outputs one of the laser signals EM1, EM2, EM3 through the laser output node NO_EM.

在一實施例中,上拉電路PU1包含有電晶體M12~M16及電容C11。電晶體M12的一端(例如汲極)耦接於節點N12,電晶體M12的一端(例如源極)接收電壓準位Vref2,電晶體M12的控制端(例如閘極)接收前級激光訊號EM0、激光訊號EM1、EM2的其中之一。電容C11的一端接收時脈訊號CK1、CK2、CK3的其中之一,且另一端耦接於節點N12。電晶體M13的一端(例如汲極)耦接於節點N13,電晶體M13的一端(例如源極)接收電壓準位Vref2,電晶體M13的控制端(例如閘極)耦接於節點N11。電晶體M14的一端(例如汲極)接收電壓準位Vref1,電晶體M14的一端(例如源極)耦接於節點N13,電晶體M14的控制端(例如閘極)耦接於節點N12。電晶體M15的一端(例如汲極)耦接於節點N11,電晶體M15的一端(例如源極)接收電壓準位Vref2,電晶體M15的控制端(例如閘極)耦接於節點N13。電晶體M16的一端(例如汲極)耦接於激光輸出節點NO_EM,電晶體M16的一端(例如源極)接收電壓準位Vref2,電晶體M16的控制端(例如閘極)耦接於節點N13。In one embodiment, the pull-up circuit PU1 includes transistors M12 to M16 and a capacitor C11. One end (for example, the drain) of the transistor M12 is coupled to the node N12, one end (for example, the source) of the transistor M12 receives the voltage level Vref2, and the control end (for example, the gate) of the transistor M12 receives the previous laser signal EM0, One of the laser signals EM1 and EM2. One end of the capacitor C11 receives one of the clock signals CK1, CK2, CK3, and the other end is coupled to the node N12. One end (such as the drain) of the transistor M13 is coupled to the node N13, one end (such as the source) of the transistor M13 receives the voltage level Vref2, and the control end (such as the gate) of the transistor M13 is coupled to the node N11. One end (such as the drain) of the transistor M14 receives the voltage level Vref1, one end (such as the source) of the transistor M14 is coupled to the node N13, and the control end (such as the gate) of the transistor M14 is coupled to the node N12. One end (such as the drain) of the transistor M15 is coupled to the node N11, one end (such as the source) of the transistor M15 receives the voltage level Vref2, and the control end (such as the gate) of the transistor M15 is coupled to the node N13. One end (such as the drain) of the transistor M16 is coupled to the laser output node NO_EM, one end (such as the source) of the transistor M16 receives the voltage level Vref2, and the control terminal (such as the gate) of the transistor M16 is coupled to the node N13 .

在一實施例中,下拉電路PD1包含有電晶體M17及電容C12。電晶體M17的一端(例如汲極)接收電壓準位Vref1,電晶體M17的一端(例如源極)耦接於激光輸出節點NO_EM,電晶體M16的控制端(例如閘極)耦接於節點N11。電容C12的一端接收時脈訊號CK3、CK1、CK2的其中之一,且另一端耦接於節點N11。In one embodiment, the pull-down circuit PD1 includes a transistor M17 and a capacitor C12. One end (such as the drain) of the transistor M17 receives the voltage level Vref1, one end (such as the source) of the transistor M17 is coupled to the laser output node NO_EM, and the control end (such as the gate) of the transistor M16 is coupled to the node N11 . One end of the capacitor C12 receives one of the clock signals CK3, CK1, CK2, and the other end is coupled to the node N11.

請參考圖3,圖3為本發明實施例激光訊號產生電路10的操作波型示意圖。由於激光訊號產生電路10/11/12具有相似的結構,因此本發明接著針對激光訊號產生電路10的操作以較佳地說明激光訊號產生電路10/11/12的操作。在本實施例中,激光訊號產生電路10接收前級激光訊號EM0以及時脈訊號CK1、CK3以輸出激光訊號EM1。電壓準位Vref1為接地電壓準位,電壓準位Vref2為工作電壓準位。電壓準位Vref1低於電壓準位Vref2。電晶體M11~M17為P型金氧半場效電晶體(P-Type Metal-Oxide-Semiconductor Field-Effect Transistor,PMOSFET)。Please refer to FIG. 3, which is a schematic diagram of the operation waveform of the laser signal generating circuit 10 according to the embodiment of the present invention. Since the laser signal generating circuit 10/11/12 has a similar structure, the present invention then focuses on the operation of the laser signal generating circuit 10 to better describe the operation of the laser signal generating circuit 10/11/12. In this embodiment, the laser signal generating circuit 10 receives the previous laser signal EM0 and the clock signals CK1 and CK3 to output the laser signal EM1. The voltage level Vref1 is the ground voltage level, and the voltage level Vref2 is the working voltage level. The voltage level Vref1 is lower than the voltage level Vref2. Transistors M11~M17 are P-Type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET).

如圖3所示,當激光訊號產生電路10操作在時間區間T10中時,前級激光訊號EM0在電壓準位Vref2,時脈訊號CK1在電壓準位Vref2,時脈訊號CK3在電壓準位Vref1。節點N11的電壓透過電容C12耦合時脈訊號CK3,會下拉至低於電壓準位Vref1,進而致能下拉電路PD1。因此,在時間區間T10中,激光訊號產生電路10透過時脈訊號CK3維持激光輸出節點NO_EM的電壓在電壓準位Vref1。As shown in FIG. 3, when the laser signal generating circuit 10 operates in the time interval T10, the previous laser signal EM0 is at the voltage level Vref2, the clock signal CK1 is at the voltage level Vref2, and the clock signal CK3 is at the voltage level Vref1. . The voltage of the node N11 is coupled to the clock signal CK3 through the capacitor C12, and is pulled down below the voltage level Vref1, thereby enabling the pull-down circuit PD1. Therefore, in the time interval T10, the laser signal generating circuit 10 maintains the voltage of the laser output node NO_EM at the voltage level Vref1 through the clock signal CK3.

當激光訊號產生電路10操作在時間區間T11中時,時脈訊號CK1由電壓準位Vref2切換至電壓準位Vref1,時脈訊號CK3由電壓準位Vref1切換至電壓準位Vref2。節點N11的電壓透過電晶體M11傳遞前級激光訊號EM0,會被上拉至電壓準位Vref2,進而失能下拉電路PD1。節點N12的電壓透過電容C11耦合時脈訊號CK1,會被下拉至電壓準位Vref1。節點N13的電壓透過電晶體M14提供電壓準位Vref1,會被下拉至電壓準位Vref1,進而致能上拉電路PU1。因此,在時間區間T11中,激光訊號產生電路10透過時脈訊號CK1提供電壓準位Vref2至激光輸出節點NO_EM。When the laser signal generating circuit 10 operates in the time interval T11, the clock signal CK1 is switched from the voltage level Vref2 to the voltage level Vref1, and the clock signal CK3 is switched from the voltage level Vref1 to the voltage level Vref2. The voltage of the node N11 transmits the pre-laser signal EM0 through the transistor M11, and is pulled up to the voltage level Vref2, thereby disabling the pull-down circuit PD1. The voltage of the node N12 is coupled to the clock signal CK1 through the capacitor C11, and is pulled down to the voltage level Vref1. The voltage of the node N13 provides a voltage level Vref1 through the transistor M14, and is pulled down to the voltage level Vref1, thereby enabling the pull-up circuit PU1. Therefore, in the time interval T11, the laser signal generating circuit 10 provides the voltage level Vref2 to the laser output node NO_EM through the clock signal CK1.

當激光訊號產生電路10操作在時間區間T12中時,時脈訊號CK1由電壓準位Vref2切換至電壓準位Vref1。節點N12的電壓可透過電容C11耦合時脈訊號CK1,會被上拉至電壓準位Vref2。因此,在時間區間T12中,激光訊號產生電路10透過電容C12儲存之前級激光訊號EM0的資料失能下拉電路PD1,且透過上拉電路PU1提供電壓準位Vref2至激光輸出節點NO_EM。When the laser signal generating circuit 10 operates in the time interval T12, the clock signal CK1 is switched from the voltage level Vref2 to the voltage level Vref1. The voltage of the node N12 can be coupled to the clock signal CK1 through the capacitor C11, and it will be pulled up to the voltage level Vref2. Therefore, in the time interval T12, the laser signal generating circuit 10 stores the data disabled pull-down circuit PD1 of the previous laser signal EM0 through the capacitor C12, and provides the voltage level Vref2 to the laser output node NO_EM through the pull-up circuit PU1.

當激光訊號產生電路10操作在時間區間T13中時,前級激光訊號EM0由電壓準位Vref2切換至電壓準位Vref1,時脈訊號CK3由電壓準位Vref2切換至電壓準位Vref1。雖然節點N11的電壓透過電容C12耦合時脈訊號CK3,會被下拉至稍微低於電壓準位Vref2,但節點N11的電壓仍可失能下拉電路PD1。因此,在時間區間T13中,激光訊號產生電路10可透過時脈訊號CK3致能上拉電路PU1,以維持激光輸出節點NO_EM的電壓在電壓準位Vref2。When the laser signal generating circuit 10 operates in the time interval T13, the previous laser signal EM0 is switched from the voltage level Vref2 to the voltage level Vref1, and the clock signal CK3 is switched from the voltage level Vref2 to the voltage level Vref1. Although the voltage of the node N11 is coupled to the clock signal CK3 through the capacitor C12 and will be pulled down slightly below the voltage level Vref2, the voltage of the node N11 can still disable the pull-down circuit PD1. Therefore, in the time interval T13, the laser signal generating circuit 10 can enable the pull-up circuit PU1 through the clock signal CK3 to maintain the voltage of the laser output node NO_EM at the voltage level Vref2.

當激光訊號產生電路10操作在時間區間T14中時,時脈訊號CK1由電壓準位Vref2切換至電壓準位Vref1,時脈訊號CK3由電壓準位Vref1切換至電壓準位Vref2。節點N11的電壓透過電晶體M11傳遞前級激光訊號EM0,會下拉至電壓準位Vref2,進而致能下拉電路PD1。節點N13的電壓可透過電晶體M13上拉至電壓準位Vref2,進而失能上拉電路PU1。因此,在時間區間T14中,激光訊號產生電路10可透過前級激光訊號EM0輸出電壓準位Vref1。When the laser signal generating circuit 10 operates in the time interval T14, the clock signal CK1 is switched from the voltage level Vref2 to the voltage level Vref1, and the clock signal CK3 is switched from the voltage level Vref1 to the voltage level Vref2. The voltage of the node N11 transmits the pre-laser signal EM0 through the transistor M11, and is pulled down to the voltage level Vref2, thereby enabling the pull-down circuit PD1. The voltage of the node N13 can be pulled up to the voltage level Vref2 through the transistor M13, thereby disabling the pull-up circuit PU1. Therefore, in the time interval T14, the laser signal generating circuit 10 can output the voltage level Vref1 through the previous laser signal EM0.

因此,本發明的驅動訊號產生器1中互相串接的激光訊號產生電路10、11、12,可根據前級激光訊號EM0及時脈訊號CK1~CK3產生依序致能的激光訊號EM1~EM3。如此一來,本發明的驅動訊號產生器1僅需要較少的時脈訊號的數量,因而有效降低硬體設計的複雜度以及顯示面板的功率消耗。Therefore, the laser signal generating circuits 10, 11, and 12 connected in series in the driving signal generator 1 of the present invention can generate sequentially enabled laser signals EM1 to EM3 according to the preceding laser signal EM0 and the clock signals CK1 to CK3. In this way, the driving signal generator 1 of the present invention requires only a small number of clock signals, thereby effectively reducing the complexity of hardware design and the power consumption of the display panel.

請參考圖4,圖4為本發明實施例一驅動訊號產生器2的示意圖。如圖4所示,驅動訊號產生器2相似於圖1所繪示的驅動訊號產生器1,關於激光訊號產生電路10、11、12的細節已詳述於前面相關段落,且於此不贅述。驅動訊號產生器2與驅動訊號產生器1的差別在於,驅動訊號產生器2另外具有掃描訊號產生電路20、21、22。驅動訊號產生器2的掃描訊號產生電路20、21、22依據前級掃描訊號SC0、時脈訊號CK1、CK2、CK3可產生掃描訊號SC1、SC2、SC3。因此,本發明的驅動訊號產生器2可配合激光訊號EM1、EM2、EM3的顯示動作來驅動顯示面板中的畫素電路以寫入顯示資料。Please refer to FIG. 4, which is a schematic diagram of a driving signal generator 2 according to an embodiment of the present invention. As shown in FIG. 4, the driving signal generator 2 is similar to the driving signal generator 1 shown in FIG. 1. The details of the laser signal generating circuits 10, 11, and 12 have been detailed in the previous relevant paragraphs, and will not be repeated here. . The difference between the driving signal generator 2 and the driving signal generator 1 is that the driving signal generator 2 additionally has scanning signal generating circuits 20, 21, and 22. The scan signal generating circuits 20, 21, and 22 of the driving signal generator 2 can generate scan signals SC1, SC2, SC3 according to the previous scan signal SC0 and clock signals CK1, CK2, CK3. Therefore, the driving signal generator 2 of the present invention can cooperate with the display actions of the laser signals EM1, EM2, EM3 to drive the pixel circuits in the display panel to write display data.

關於掃描訊號產生電路20/21/22的詳細結構請參考圖5,圖5為本發明一實施例掃描訊號產生電路20/21/22的示意圖。如圖5所示,掃描訊號產生電路20/21/22包含電晶體M21、上拉電路PU2、下拉電路PD2。電晶體M21的一端(例如源極)接收前級掃描訊號SC0、掃描訊號SC1、掃描訊號SC2的其中之一(掃描訊號產生電路20中的電晶體M21接收前級掃描訊號SC0,掃描訊號產生電路21中的電晶體M21接收前級掃描訊號SC1、掃描訊號產生電路22中的電晶體M21接收前級掃描訊號SC2,依此類推),電晶體M21的一端(例如汲極)耦接於節點N21,電晶體M21的控制端(例如閘極)耦接於電晶體M21的一端(例如源極)。上拉電路PU2耦接於節點N21及掃描輸出節點NO_SC之間。下拉電路耦接於節點N21及掃描輸出節點NO_SC之間。掃描訊號產生電路20/21/22透過掃描輸出節點NO_SC輸出掃描訊號SC1、SC2、SC3的其中之一。For the detailed structure of the scanning signal generating circuit 20/21/22, please refer to FIG. 5, which is a schematic diagram of the scanning signal generating circuit 20/21/22 according to an embodiment of the present invention. As shown in FIG. 5, the scanning signal generating circuit 20/21/22 includes a transistor M21, a pull-up circuit PU2, and a pull-down circuit PD2. One end (such as the source) of the transistor M21 receives one of the previous scan signal SC0, the scan signal SC1, and the scan signal SC2 (the transistor M21 in the scan signal generating circuit 20 receives the previous scan signal SC0, and the scan signal generating circuit The transistor M21 in 21 receives the previous scan signal SC1, the transistor M21 in the scan signal generating circuit 22 receives the previous scan signal SC2, and so on), and one end (for example, the drain) of the transistor M21 is coupled to the node N21 , The control end (for example, the gate) of the transistor M21 is coupled to one end (for example, the source) of the transistor M21. The pull-up circuit PU2 is coupled between the node N21 and the scan output node NO_SC. The pull-down circuit is coupled between the node N21 and the scan output node NO_SC. The scan signal generating circuit 20/21/22 outputs one of the scan signals SC1, SC2, SC3 through the scan output node NO_SC.

在一實施例中,上拉電路PU2包含有電晶體M22~M25及電容C21。電晶體M22的一端(例如汲極)耦接於節點N22,電晶體M22的一端(例如源極)接收電壓準位Vref2,電晶體M22的控制端(例如閘極)耦接於節點N21。電晶體M23的一端(例如汲極)接收時脈訊號CK3、CK1、CK2的其中之一,電晶體M23的一端(例如源極)耦接於節點N22,電晶體M23的控制端(例如閘極)耦接於電晶體M23的一端(例如汲極)。電容C21的一端耦接於節點N22,且另一端接收電壓準位Vref2。電晶體M24的一端(例如汲極)耦接於節點N21,電晶體M24的一端(例如源極)接收電壓準位Vref2,電晶體M24的控制端(例如閘極)耦接於節點N22。電晶體M25的一端(例如汲極)耦接於掃描輸出節點NO_SC,電晶體M25的一端(例如源極)接收電壓準位Vref2,電晶體M25的控制端(例如閘極)耦接於節點N22。In one embodiment, the pull-up circuit PU2 includes transistors M22 to M25 and a capacitor C21. One end (for example, the drain) of the transistor M22 is coupled to the node N22, one end (for example, the source) of the transistor M22 receives the voltage level Vref2, and the control end (for example, the gate) of the transistor M22 is coupled to the node N21. One end (such as the drain) of the transistor M23 receives one of the clock signals CK3, CK1, CK2, one end (such as the source) of the transistor M23 is coupled to the node N22, and the control terminal (such as the gate) of the transistor M23 ) Is coupled to one end (for example, the drain) of the transistor M23. One end of the capacitor C21 is coupled to the node N22, and the other end receives the voltage level Vref2. One end (such as the drain) of the transistor M24 is coupled to the node N21, one end (such as the source) of the transistor M24 receives the voltage level Vref2, and the control end (such as the gate) of the transistor M24 is coupled to the node N22. One end (such as the drain) of the transistor M25 is coupled to the scan output node NO_SC, one end (such as the source) of the transistor M25 receives the voltage level Vref2, and the control terminal (such as the gate) of the transistor M25 is coupled to the node N22 .

在一實施例中,下拉電路PD2包含有電晶體M26。電晶體M26的一端(例如汲極)接收時脈訊號CK2、CK3、CK1的其中之一,電晶體M26的一端(例如源極)耦接於掃描輸出節點NO_SC,電晶體M26的控制端(例如閘極)耦接於節點N21。In one embodiment, the pull-down circuit PD2 includes a transistor M26. One end (such as the drain) of the transistor M26 receives one of the clock signals CK2, CK3, CK1, one end (such as the source) of the transistor M26 is coupled to the scan output node NO_SC, and the control terminal (such as The gate) is coupled to the node N21.

請參考圖6,圖6為本發明一實施例掃描訊號產生電路20的操作波型示意圖。由於掃描訊號產生電路20/21/22具有相似的結構,因此本發明接著針對掃描訊號產生電路20的操作以較佳地說明掃描訊號產生電路20的操作。在本實施例中,掃描訊號產生電路20接收前級掃描訊號SC0以及時脈訊號CK1、CK2以輸出掃描訊號SC1。電壓準位Vref1為接地電壓準位,電壓準位Vref2為工作電壓準位,電壓準位Vref1低於電壓準位Vref2。電晶體M21~M26為P型金氧半場效電晶體。Please refer to FIG. 6, which is a schematic diagram of the operation waveform of the scanning signal generating circuit 20 according to an embodiment of the present invention. Since the scanning signal generating circuit 20/21/22 has a similar structure, the present invention then focuses on the operation of the scanning signal generating circuit 20 to better describe the operation of the scanning signal generating circuit 20. In this embodiment, the scan signal generating circuit 20 receives the previous scan signal SC0 and the clock signals CK1 and CK2 to output the scan signal SC1. The voltage level Vref1 is the ground voltage level, the voltage level Vref2 is the working voltage level, and the voltage level Vref1 is lower than the voltage level Vref2. Transistors M21~M26 are P-type metal oxide half field effect transistors.

如圖6所示,當掃描訊號產生電路20操作在時間區間T20中時,前級激光訊號SC0在電壓準位Vref2,因而失能下拉電路PD2。時脈訊號CK3在電壓準位Vref1,因而致能上拉電路PU2。因此,在時間區間T20中,掃描訊號產生電路20透過時脈訊號CK3以提供電壓準位Vref2至掃描輸出節點NO_SC。As shown in FIG. 6, when the scanning signal generating circuit 20 is operating in the time interval T20, the previous laser signal SC0 is at the voltage level Vref2, and the pull-down circuit PD2 is disabled. The clock signal CK3 is at the voltage level Vref1, thus enabling the pull-up circuit PU2. Therefore, in the time interval T20, the scan signal generating circuit 20 provides the voltage level Vref2 to the scan output node NO_SC through the clock signal CK3.

當掃描訊號產生電路20操作在時間區間T21中時,前級掃描訊號SC0由電壓準位Vref2切換至電壓準位Vref1,因而致能下拉電路PD2。時脈訊號CK3由電壓準位Vref1切換至電壓準位Vref2,因而失能上拉電路PU2。因此,在時間區間T21中,掃描訊號產生電路20透過前級掃描訊號SC0以將時脈訊號CK2輸出至掃描輸出節點NO_SC。When the scan signal generating circuit 20 is operating in the time interval T21, the previous scan signal SC0 is switched from the voltage level Vref2 to the voltage level Vref1, thereby enabling the pull-down circuit PD2. The clock signal CK3 is switched from the voltage level Vref1 to the voltage level Vref2, and thus the pull-up circuit PU2 is disabled. Therefore, in the time interval T21, the scan signal generating circuit 20 outputs the clock signal CK2 to the scan output node NO_SC through the previous scan signal SC0.

當掃描訊號產生電路20操作在時間區間T22中時,前級掃描訊號SC0由電壓準位Vref1切換至電壓準位Vref2,節點N21的電壓透過電晶體M26的寄生電容耦合時脈訊號CK2,會被下拉至稍微低於電壓準位Vref1,因而致能下拉電路PD2。因此,在時間區間T22中,掃描訊號產生電路20透過時脈訊號CK2致能下拉電路PD2及時脈訊號CK3失能上拉電路PU2,以維持掃描輸出節點NO_SC在電壓準位Vref1。When the scan signal generating circuit 20 operates in the time interval T22, the previous scan signal SC0 is switched from the voltage level Vref1 to the voltage level Vref2. The voltage of the node N21 is coupled to the clock signal CK2 through the parasitic capacitance of the transistor M26. It is pulled down to slightly lower than the voltage level Vref1, thus enabling the pull-down circuit PD2. Therefore, in the time interval T22, the scan signal generating circuit 20 enables the pull-down circuit PD2 through the clock signal CK2 and the clock signal CK3 disables the pull-up circuit PU2 to maintain the scan output node NO_SC at the voltage level Vref1.

當掃描訊號產生電路20操作在時間區間T23中時,時脈訊號CK3由電壓準位Vref2切換至電壓準位Vref1,致能電晶體M23。節點N22的電壓會被下拉至電壓準位Vref1,致能電晶體M24、M25。因此,在時間區間T23中,掃描訊號產生電路20透過時脈訊號CK3失能下拉電路PD2且提供電壓準位Vref2至掃描輸出節點NO_SC。When the scanning signal generating circuit 20 operates in the time interval T23, the clock signal CK3 is switched from the voltage level Vref2 to the voltage level Vref1, enabling the transistor M23. The voltage of the node N22 will be pulled down to the voltage level Vref1, enabling the transistors M24 and M25. Therefore, in the time interval T23, the scan signal generating circuit 20 disables the pull-down circuit PD2 through the clock signal CK3 and provides the voltage level Vref2 to the scan output node NO_SC.

當掃描訊號產生電路20操作在時間區間T24中時,時脈訊號CK3由電壓準位Vref1切換至電壓準位Vref2,上拉電路PU2依據電容C21維持致能電晶體M24、M25。。因此,在時間區間T24中,掃描訊號產生電路20提供電壓準位Vref2至掃描輸出節點NO_SC。When the scanning signal generating circuit 20 operates in the time interval T24, the clock signal CK3 switches from the voltage level Vref1 to the voltage level Vref2, and the pull-up circuit PU2 maintains the enabling transistors M24 and M25 according to the capacitor C21. . Therefore, in the time interval T24, the scan signal generating circuit 20 provides the voltage level Vref2 to the scan output node NO_SC.

因此,本發明的驅動訊號產生器2中互相串接的掃描訊號產生電路20、21、22,可根據前級掃描訊號SC0及時脈訊號CK1~CK3產生依序致能的掃描訊號SC1~SC3,其可配合激光訊號EM1、EM2、EM3的顯示動作來驅動顯示面板中的畫素電路寫入顯示資料。如此一來,本發明的驅動訊號產生器2僅需要較少的時脈訊號的數量,因而有效降低硬體設計的複雜度以及顯示面板的功率消耗。Therefore, the scan signal generating circuits 20, 21, and 22 connected in series in the driving signal generator 2 of the present invention can generate sequentially enabled scan signals SC1 to SC3 according to the previous scan signal SC0 and clock signals CK1 to CK3. It can cooperate with the display actions of the laser signals EM1, EM2, and EM3 to drive the pixel circuit in the display panel to write display data. In this way, the driving signal generator 2 of the present invention requires only a small number of clock signals, thereby effectively reducing the complexity of hardware design and the power consumption of the display panel.

需注意的是,前述實施例係用以說明本發明之概念,本領域具通常知識者當可據以做不同之修飾,而不限於此。舉例來說,驅動訊號產生器2中的電晶體並非僅限於P型金氧半場效電晶體,亦可為N型金氧半場效電晶體。在一實施例中,驅動訊號產生器2中的所有電晶體為N型金氧半場效電晶體,電壓準位Vref1為工作電壓準位,電壓準位Vref2為接地電壓準位,電壓準位Vref1高於電壓準位Vref2。It should be noted that the foregoing embodiments are used to illustrate the concept of the present invention, and those with ordinary knowledge in the art can make various modifications accordingly, and are not limited thereto. For example, the transistors in the driving signal generator 2 are not limited to P-type MOSFETs, but can also be N-type MOSFETs. In one embodiment, all the transistors in the driving signal generator 2 are N-type MOSFETs, the voltage level Vref1 is the working voltage level, the voltage level Vref2 is the ground voltage level, and the voltage level Vref1 Higher than the voltage level Vref2.

綜上所述,本發明的驅動訊號產生器僅需三個依序致能且致能時間不互相重疊的時脈訊號,即可產生依序致能的激光訊號及掃描訊號來驅動顯示面板中的畫素電路。因此,本發明的驅動訊號產生器可僅需要較少的時脈訊號的數量,因而有效降低硬體設計的複雜度以及顯示面板的功率消耗。In summary, the driving signal generator of the present invention only needs three clock signals that are sequentially enabled and the enabling time does not overlap each other, and can generate sequentially enabled laser signals and scanning signals to drive the display panel Pixel circuit. Therefore, the driving signal generator of the present invention can only require a small number of clock signals, thereby effectively reducing the complexity of hardware design and the power consumption of the display panel.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

1、2:驅動訊號產生器 10~12:激光訊號產生電路 20~22:掃描訊號產生電路 C11、C12、C21:電容 CK1~CK3:時脈訊號 EM0:前級激光訊號 EM1~EM3:激光訊號 M11~M17、M21~M26:電晶體 N11~N13、N21、N22:節點 NO_EM:激光輸出節點 NO_SC:掃描輸出節點 SC0:前級掃描訊號 SC1~SC3:掃描訊號 T10~T14、T20~T24:時間區間 PD1、PD2:下拉電路 PU1、PU2:上拉電路 Vref1、Vref2:電壓準位1, 2: Drive signal generator 10~12: Laser signal generating circuit 20~22: Scanning signal generating circuit C11, C12, C21: capacitance CK1~CK3: Clock signal EM0: Pre-level laser signal EM1~EM3: Laser signal M11~M17, M21~M26: Transistor N11~N13, N21, N22: Node NO_EM: Laser output node NO_SC: Scan output node SC0: pre-scan signal SC1~SC3: Scan signal T10~T14, T20~T24: time interval PD1, PD2: pull-down circuit PU1, PU2: pull-up circuit Vref1, Vref2: voltage level

圖1為本發明實施例驅動訊號產生器的示意圖。 圖2為本發明實施例激光訊號產生電路的示意圖。 圖3為本發明實施例激光訊號產生電路的操作波型示意圖。 圖4為本發明實施例驅動訊號產生器的示意圖。 圖5為本發明實施例掃描訊號產生電路的示意圖。 圖6為本發明實施例掃描訊號產生電路的操作波型示意圖。FIG. 1 is a schematic diagram of a driving signal generator according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a laser signal generating circuit according to an embodiment of the present invention. 3 is a schematic diagram of the operating waveform of the laser signal generating circuit according to the embodiment of the present invention. 4 is a schematic diagram of a driving signal generator according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a scanning signal generating circuit according to an embodiment of the present invention. 6 is a schematic diagram of the operation waveform of the scanning signal generating circuit according to the embodiment of the present invention.

1:驅動訊號產生器 1: Drive signal generator

10~12:激光訊號產生電路 10~12: Laser signal generating circuit

CK1~CK3:時脈訊號 CK1~CK3: Clock signal

EM0:前級激光訊號 EM0: Pre-level laser signal

EM1~EM3:激光訊號 EM1~EM3: Laser signal

Claims (18)

一種驅動訊號產生器,包括: 一第一級激光訊號產生電路,當一第一時脈訊號在一第一電壓準位時根據一前級激光訊號輸出一第一級激光訊號,且當該第一時脈訊號在一第二電壓準位時透過一第三時脈訊號維持該第一級激光訊號之電壓準位; 一第二級激光訊號產生電路,當一第二時脈訊號在該第一電壓準位時根據該第一級激光訊號輸出一第二級激光訊號,且當該第二時脈訊號在該第二電壓準位時透過該第一時脈訊號維持該第二級激光訊號之電壓準位;以及 一第三級激光訊號產生電路,當該第三時脈訊號在該第一電壓準位時根據該第二級激光訊號輸出一第三級激光訊號,且當該第三時脈訊號在該第二電壓準位時透過該第二時脈訊號維持該第三級激光訊號之電壓準位, 其中該第一時脈訊號、該第二時脈訊號及該第三時脈訊號依序切換至該第一電壓準位。A drive signal generator includes: A first-level laser signal generating circuit, when a first clock signal is at a first voltage level, a first-level laser signal is output according to a previous laser signal, and when the first clock signal is a second Maintain the voltage level of the first-level laser signal through a third clock signal when the voltage level is applied; A second-level laser signal generating circuit that outputs a second-level laser signal according to the first-level laser signal when a second clock signal is at the first voltage level, and when the second-level clock signal is at the first voltage level Maintain the voltage level of the second-level laser signal through the first clock signal when the two voltage levels are in use; and A third-level laser signal generating circuit that outputs a third-level laser signal according to the second-level laser signal when the third clock signal is at the first voltage level, and when the third-level clock signal is at the first voltage level At the second voltage level, the voltage level of the third level laser signal is maintained through the second clock signal, The first clock signal, the second clock signal, and the third clock signal are sequentially switched to the first voltage level. 如申請專利範圍第1項所述的驅動訊號產生器,其中該第一時脈訊號、該第二時脈訊號及該第三時脈訊號等於該第一電壓準位的時間區間不相重疊。For the driving signal generator described in item 1 of the scope of patent application, the time intervals during which the first clock signal, the second clock signal and the third clock signal are equal to the first voltage level do not overlap. 如申請專利範圍第1項所述的驅動訊號產生器,其中該第一級訊號產生電路、該第二級訊號產生電路及該第三級訊號產生電路的其中之一包括: 一第一電晶體,該第一電晶體的第一端接收該前級激光訊號、該第一級激光訊號或該第二級激光訊號,該第一電晶體的第二端耦接至一第一節點,該第一電晶體的控制端接收該第一時脈訊號、該第二時脈訊號或該第三時脈訊號; 一第一上拉電路,耦接於該第一節點及一激光輸出節點之間,依據該前級激光訊號、該第一級激光訊號或該第二級激光訊的其中之一,以及該第一時脈訊號、該第二時脈訊號或該第三時脈訊號的其中之一以提供該第二電壓準位至該激光輸出節點;以及 一第一下拉電路,耦接於該第一節點及該激光輸出節點之間,當該第一節點為該第一電壓準位時,提供該第一電壓準位至該激光輸出節點,其中該第一下拉電路透過該第三時脈訊號、該第一時脈訊號或該二時脈訊號維持該第一節點之電壓準位, 其中該激光輸出節點輸出該第一級激光訊號、該第二級激光訊號或該第三級激光訊號。According to the driving signal generator described in item 1 of the scope of patent application, one of the first-stage signal generating circuit, the second-stage signal generating circuit, and the third-stage signal generating circuit includes: A first transistor, the first end of the first transistor receives the pre-laser signal, the first-level laser signal or the second-level laser signal, and the second end of the first transistor is coupled to a first A node where the control terminal of the first transistor receives the first clock signal, the second clock signal, or the third clock signal; A first pull-up circuit, coupled between the first node and a laser output node, is based on one of the front-level laser signal, the first-level laser signal, or the second-level laser signal, and the first One of a clock signal, the second clock signal, or the third clock signal to provide the second voltage level to the laser output node; and A first pull-down circuit, coupled between the first node and the laser output node, when the first node is the first voltage level, provides the first voltage level to the laser output node, wherein The first pull-down circuit maintains the voltage level of the first node through the third clock signal, the first clock signal or the second clock signal, The laser output node outputs the first-level laser signal, the second-level laser signal, or the third-level laser signal. 如申請專利範圍第3項所述的驅動訊號產生器,其中該第一上拉電路包括: 一第二電晶體,該第二電晶體的第一端耦接於一第二節點,該第二電晶體的第二端接收該第二電壓準位,該第二電晶體的控制端接收該前級激光訊號、該第一級激光訊號或該第二級激光訊的其中之一; 一第三電晶體,該第三電晶體的第一端耦接於一第三節點,該第三電晶體的第二端接收該第二電壓準位,該第三電晶體的控制端耦接於該第一節點; 一第四電晶體,該第四電晶體的第一端接收該第一電壓準位,該第四電晶體的第二端耦接於該第三節點,該第四電晶體的控制端耦接於該第二節點; 一第五電晶體,該第五電晶體的第一端耦接於該第一節點,該第五電晶體的第二端接收該第二電壓準位,該第五電晶體的控制端耦接於該第三節點; 一第六電晶體,該第六電晶體的第一端耦接於該激光輸出節點,該第六電晶體的第二端接收該第二電壓準位,該第六電晶體的控制端耦接於該第三節點;以及 一第一電容,該第一電容的第一端接收該第一時脈訊號、該第二時脈訊號或該第三時脈訊號的其中之一,該第一電容的第二端耦接於該第二節點。The driving signal generator described in item 3 of the scope of patent application, wherein the first pull-up circuit includes: A second transistor, the first terminal of the second transistor is coupled to a second node, the second terminal of the second transistor receives the second voltage level, and the control terminal of the second transistor receives the One of the front-level laser signal, the first-level laser signal, or the second-level laser signal; A third transistor, the first terminal of the third transistor is coupled to a third node, the second terminal of the third transistor receives the second voltage level, and the control terminal of the third transistor is coupled At the first node; A fourth transistor, the first terminal of the fourth transistor receives the first voltage level, the second terminal of the fourth transistor is coupled to the third node, and the control terminal of the fourth transistor is coupled to At the second node; A fifth transistor, the first terminal of the fifth transistor is coupled to the first node, the second terminal of the fifth transistor receives the second voltage level, and the control terminal of the fifth transistor is coupled At the third node; A sixth transistor, the first end of the sixth transistor is coupled to the laser output node, the second end of the sixth transistor receives the second voltage level, and the control end of the sixth transistor is coupled At the third node; and A first capacitor, the first terminal of the first capacitor receives one of the first clock signal, the second clock signal or the third clock signal, and the second terminal of the first capacitor is coupled to The second node. 如申請專利範圍第3項所述的驅動訊號產生器,其中該第一下拉電路包括: 一第二電晶體,該第二電晶體的第一端接收該第一電壓準位,該第二電晶體的第二端耦接於該激光輸出節點,該第二電晶體的控制端耦接於該第一節點;以及 一第一電容,該第一電容的第一端接收該第三時脈訊號、該第一時脈訊號或該第二時脈訊號的其中之一,該第一電容的第二端耦接於該第一節點。The driving signal generator described in item 3 of the scope of patent application, wherein the first pull-down circuit includes: A second transistor, the first terminal of the second transistor receives the first voltage level, the second terminal of the second transistor is coupled to the laser output node, and the control terminal of the second transistor is coupled to At the first node; and A first capacitor. The first terminal of the first capacitor receives one of the third clock signal, the first clock signal or the second clock signal, and the second terminal of the first capacitor is coupled to The first node. 如申請專利範圍第1項所述的驅動訊號產生器,另包括: 一第一級掃描訊號產生電路,當一前級掃描訊號在該第一電壓準位時根據該第二時脈訊號輸出一第一級掃描訊號,且當該前級掃描訊號在該第二電壓準位時透過該第三時脈訊號維持該第一級掃描訊號之電壓準位; 一第二級掃描訊號產生電路,當該第一級掃描訊號在該第一電壓準位時根據該第三時脈訊號輸出一第二級掃描訊號,且當該第一級掃描訊號在該第二電壓準位時透過該第一時脈訊號維持該第二級掃描訊號之電壓準位;以及 一第三級掃描訊號產生電路,當該第二級掃描訊號在該第一電壓準位時根據該第一時脈訊號輸出一第三級掃描訊號,且當該第二級掃描訊號在該第二電壓準位時透過該第二時脈訊號維持該第三級掃描訊號之電壓準位, 其中該掃描輸出節點輸出該第一級掃描訊號、該第二級掃描訊號或該第三級掃描訊號。The drive signal generator described in item 1 of the scope of patent application also includes: A first-stage scan signal generating circuit, when a previous-stage scan signal is at the first voltage level, outputs a first-stage scan signal according to the second clock signal, and when the previous-stage scan signal is at the second voltage Maintain the voltage level of the first-level scanning signal through the third clock signal when the level is set; A second-level scan signal generating circuit, when the first-level scan signal is at the first voltage level, outputs a second-level scan signal according to the third clock signal, and when the first-level scan signal is at the first voltage level Maintain the voltage level of the second-level scanning signal through the first clock signal when the voltage level is two; and A third-level scan signal generating circuit, when the second-level scan signal is at the first voltage level, outputs a third-level scan signal according to the first clock signal, and when the second-level scan signal is at the first voltage level At the second voltage level, the voltage level of the third level scanning signal is maintained through the second clock signal, The scan output node outputs the first level scan signal, the second level scan signal or the third level scan signal. 如申請專利範圍第6項所述的驅動訊號產生器,其中該第一級掃描訊號產生電路、該第二級掃描訊或該第三級掃描訊號產生電路號產生電路的其中之一包括: 一第一電晶體,該第一電晶體的第一端接收該前級掃描訊號、該第一級掃描訊號或該第二級掃描訊號,該第一電晶體的第二端耦接於一第一節點,該第一電晶體的控制端耦接於該第一電晶體的第一端; 一第一上拉電路,耦接於該第一節點及一掃描輸出節點之間,透過該前級掃描訊號、該第一級掃描訊號或該第二級掃描訊號的其中之一,以及該第三時脈訊號、該第一時脈訊號或該第一時脈訊號的其中之一以提供該第二電壓準位至該掃描輸出節點;以及 一第一下拉電路,耦接於該第一節點及該掃描輸出節點之間,其中當該第一節點在該第一電壓準位時,該第一下拉電路將該第二時脈訊號、該第三時脈訊號或該第一時脈訊號傳遞至該掃描輸出節點。For the driving signal generator described in item 6 of the scope of patent application, one of the first-stage scanning signal generating circuit, the second-stage scanning signal or the third-stage scanning signal generating circuit includes: A first transistor, the first end of the first transistor receives the previous scan signal, the first scan signal or the second scan signal, and the second end of the first transistor is coupled to a first A node, the control terminal of the first transistor is coupled to the first terminal of the first transistor; A first pull-up circuit, coupled between the first node and a scan output node, passes through one of the previous scan signal, the first scan signal, or the second scan signal, and the first scan signal One of a three-clock signal, the first clock signal, or the first clock signal to provide the second voltage level to the scan output node; and A first pull-down circuit is coupled between the first node and the scan output node, wherein when the first node is at the first voltage level, the first pull-down circuit generates the second clock signal , The third clock signal or the first clock signal is transmitted to the scan output node. 如申請專利範圍第7項所述的驅動訊號產生器,其中該第一上拉電路包括: 一第二電晶體,該第二電晶體的第一端耦接於一第二節點,該第二電晶體的第二端接收該第二電壓準位,該第二電晶體的控制端耦接於該第一節點; 一第三電晶體,該第三電晶體的第一端接收該第三時脈訊號、該第一時脈訊號或該第二時脈訊號,該第三電晶體的第二端耦接於該第二節點,該第三電晶體的控制端耦接於該第三電晶體的第一端; 一第四電晶體,該第四電晶體的第一端耦接於該第一節點,該第四電晶體的第二端接收該第二電壓準位,該第四電晶體的控制端耦接於該第二節點; 一第五電晶體,該第五電晶體的第一端耦接於該掃描輸出節點,該第五電晶體的第二端接收該第二電壓準位,該第五電晶體的控制端耦接於該第二節點;以及 一第一電容,該第一電容的第一端耦接於該第二節點,該第一電容的第二端接收該第二電壓準位。In the driving signal generator described in item 7 of the scope of patent application, the first pull-up circuit includes: A second transistor, the first terminal of the second transistor is coupled to a second node, the second terminal of the second transistor receives the second voltage level, and the control terminal of the second transistor is coupled At the first node; A third transistor, the first end of the third transistor receives the third clock signal, the first clock signal or the second clock signal, and the second end of the third transistor is coupled to the At the second node, the control terminal of the third transistor is coupled to the first terminal of the third transistor; A fourth transistor, the first terminal of the fourth transistor is coupled to the first node, the second terminal of the fourth transistor receives the second voltage level, and the control terminal of the fourth transistor is coupled At the second node; A fifth transistor, the first terminal of the fifth transistor is coupled to the scan output node, the second terminal of the fifth transistor receives the second voltage level, and the control terminal of the fifth transistor is coupled At the second node; and A first capacitor, the first terminal of the first capacitor is coupled to the second node, and the second terminal of the first capacitor receives the second voltage level. 如申請專利範圍第7項所述的驅動訊號產生器,其中該第一下拉電路包括: 一第二電晶體,該第二電晶體的第一端接收該第二時脈訊號、該第三時脈訊號或該第一時脈訊號,該第二電晶體的第二端耦接於該掃描輸出節點,該第二電晶體的控制端耦接於該第一節點。In the driving signal generator described in item 7 of the scope of patent application, the first pull-down circuit includes: A second transistor, the first end of the second transistor receives the second clock signal, the third clock signal or the first clock signal, and the second end of the second transistor is coupled to the Scan output node, and the control terminal of the second transistor is coupled to the first node. 如申請專利範圍第1項所述的驅動訊號產生器,其中該第一電壓準位低於該第二電壓準位,該驅動訊號產生器中的所有電晶體為P型金氧半場效電晶體。The driving signal generator described in item 1 of the scope of patent application, wherein the first voltage level is lower than the second voltage level, and all transistors in the driving signal generator are P-type metal oxide half field effect transistors . 如申請專利範圍第1項所述的驅動訊號產生器,其中該第一電壓準位高於該第二電壓準位,該驅動訊號產生器中的所有電晶體為N型金氧半場效電晶體。The driving signal generator described in item 1 of the scope of patent application, wherein the first voltage level is higher than the second voltage level, and all transistors in the driving signal generator are N-type metal oxide half field effect transistors . 一種驅動訊號產生器,包括: 一第一級掃描訊號產生電路,當一前級掃描訊號在一第一電壓準位時根據一第二時脈訊號輸出一第一級掃描訊號,且當該前級掃描訊號在一第二電壓準位時透過一第三時脈訊號維持該第一級掃描訊號之電壓準位; 一第二級掃描訊號產生電路,當該第一級掃描訊號在該第一電壓準位時根據該第三時脈訊號輸出一第二級掃描訊號,且當該第一級掃描訊號在該第二電壓準位時透過一第一時脈訊號維持該第二級掃描訊號之電壓準位;以及 一第三級掃描訊號產生電路,當該第二級掃描訊號在該第一電壓準位時根據該第一時脈訊號輸出一第三級掃描訊號,且當該第二級掃描訊號在該第二電壓準位時透過該第二時脈訊號維持該第三級掃描訊號之電壓準位, 其中該第一時脈訊號、該第二時脈訊號及該第三時脈訊號依序切換至該第一電壓準位。A drive signal generator includes: A first-stage scan signal generating circuit, when a previous-stage scan signal is at a first voltage level, outputs a first-stage scan signal according to a second clock signal, and when the previous-stage scan signal is at a second voltage Maintain the voltage level of the first-level scanning signal through a third clock signal at the level; A second-level scan signal generating circuit, when the first-level scan signal is at the first voltage level, outputs a second-level scan signal according to the third clock signal, and when the first-level scan signal is at the first voltage level Maintain the voltage level of the second-level scanning signal through a first clock signal when the two voltage levels are used; and A third-level scan signal generating circuit, when the second-level scan signal is at the first voltage level, outputs a third-level scan signal according to the first clock signal, and when the second-level scan signal is at the first voltage level At the second voltage level, the voltage level of the third level scanning signal is maintained through the second clock signal, The first clock signal, the second clock signal, and the third clock signal are sequentially switched to the first voltage level. 如申請專利範圍第12項所述的驅動訊號產生器,其中該第一時脈訊號、該第二時脈訊號及該第三時脈訊號等於該第一電壓準位的時間區間不相重疊。For the driving signal generator described in item 12 of the scope of patent application, the time intervals during which the first clock signal, the second clock signal and the third clock signal are equal to the first voltage level do not overlap. 如申請專利範圍第12項所述的驅動訊號產生器,其中該第一級掃描訊號產生電路、該第二級掃描訊或該第三級掃描訊號產生電路號產生電路的其中之一包括: 一第一電晶體,該第一電晶體的第一端接收該前級掃描訊號、該第一級掃描訊號或該第二級掃描訊號,該第一電晶體的第二端耦接於一第一節點,該第一電晶體的控制端耦接於該第一電晶體的第一端; 一第一上拉電路,耦接於該第一節點及一掃描輸出節點之間,透過該前級掃描訊號、該第一級掃描訊號或該第二級掃描訊號的其中之一,以及該第三時脈訊號、該第一時脈訊號或該第一時脈訊號的其中之一以提供該第二電壓準位至該掃描輸出節點;以及 一第一下拉電路,耦接於該第一節點及該掃描輸出節點之間,其中當該第一節點在該第一電壓準位時,該第一下拉電路將該第二時脈訊號、該第三時脈訊號或該第一時脈訊號傳遞至該掃描輸出節點, 其中該掃描輸出節點輸出該第一級掃描訊號、該第二級掃描訊號或該第三級掃描訊號。For the driving signal generator described in item 12 of the scope of patent application, one of the first-stage scanning signal generating circuit, the second-stage scanning signal or the third-stage scanning signal generating circuit number generating circuit includes: A first transistor, the first end of the first transistor receives the previous scan signal, the first scan signal or the second scan signal, and the second end of the first transistor is coupled to a first A node, the control terminal of the first transistor is coupled to the first terminal of the first transistor; A first pull-up circuit, coupled between the first node and a scan output node, passes through one of the previous scan signal, the first scan signal, or the second scan signal, and the first scan signal One of a three-clock signal, the first clock signal, or the first clock signal to provide the second voltage level to the scan output node; and A first pull-down circuit is coupled between the first node and the scan output node, wherein when the first node is at the first voltage level, the first pull-down circuit generates the second clock signal , The third clock signal or the first clock signal is transmitted to the scan output node, The scan output node outputs the first level scan signal, the second level scan signal or the third level scan signal. 如申請專利範圍第14項所述的驅動訊號產生器,其中該第一上拉電路包括: 一第二電晶體,該第二電晶體的第一端耦接於一第二節點,該第二電晶體的第二端接收該第二電壓準位,該第二電晶體的控制端耦接於該第一節點; 一第三電晶體,該第三電晶體的第一端接收該第三時脈訊號、該第一時脈訊號或該第二時脈訊號,該第三電晶體的第二端耦接於該第二節點,該第三電晶體的控制端耦接於該第三電晶體的第一端; 一第四電晶體,該第四電晶體的第一端耦接於該第一節點,該第四電晶體的第二端接收該第二電壓準位,該第四電晶體的控制端耦接於該第二節點; 一第五電晶體,該第五電晶體的第一端耦接於該掃描輸出節點,該第五電晶體的第二端接收該第二電壓準位,該第五電晶體的控制端耦接於該第二節點;以及 一第一電容,該第一電容的第一端耦接於該第二節點,該第一電容的第二端接收該第二電壓準位。According to the driving signal generator described in item 14 of the scope of patent application, the first pull-up circuit includes: A second transistor, the first terminal of the second transistor is coupled to a second node, the second terminal of the second transistor receives the second voltage level, and the control terminal of the second transistor is coupled At the first node; A third transistor, the first end of the third transistor receives the third clock signal, the first clock signal or the second clock signal, and the second end of the third transistor is coupled to the At the second node, the control terminal of the third transistor is coupled to the first terminal of the third transistor; A fourth transistor, the first terminal of the fourth transistor is coupled to the first node, the second terminal of the fourth transistor receives the second voltage level, and the control terminal of the fourth transistor is coupled At the second node; A fifth transistor, the first terminal of the fifth transistor is coupled to the scan output node, the second terminal of the fifth transistor receives the second voltage level, and the control terminal of the fifth transistor is coupled At the second node; and A first capacitor, the first terminal of the first capacitor is coupled to the second node, and the second terminal of the first capacitor receives the second voltage level. 如申請專利範圍第14項所述的驅動訊號產生器,其中該第一下拉電路包括: 一第二電晶體,該第二電晶體的第一端接收該第二時脈訊號、該第三時脈訊號或該第一時脈訊號,該第二電晶體的第二端耦接於該掃描輸出節點,該第二電晶體的控制端耦接於該第一節點。According to the driving signal generator described in item 14 of the scope of patent application, the first pull-down circuit includes: A second transistor, the first end of the second transistor receives the second clock signal, the third clock signal or the first clock signal, and the second end of the second transistor is coupled to the Scan output node, and the control terminal of the second transistor is coupled to the first node. 如申請專利範圍第12項所述的驅動訊號產生器,其中該第一電壓準位低於該第二電壓準位,該驅動訊號產生器中的所有電晶體為P型金氧半場效電晶體。The driving signal generator described in item 12 of the scope of patent application, wherein the first voltage level is lower than the second voltage level, and all transistors in the driving signal generator are P-type metal oxide half field effect transistors . 如申請專利範圍第12項所述的驅動訊號產生器,其中該第一電壓準位高於該第二電壓準位,該驅動訊號產生器中的所有電晶體為N型金氧半場效電晶體。The driving signal generator described in item 12 of the scope of patent application, wherein the first voltage level is higher than the second voltage level, and all transistors in the driving signal generator are N-type metal oxide half field effect transistors .
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