TWI729825B - Driving circuit and shift register - Google Patents

Abstract

A shift register includes a scan circuit, a mode control circuit and a synchronous circuit coupled to the scan circuit and the mode control circuit. The mode control circuit decides the shift register to be operated in a scan mode or a synchronous mode. In the scan mode, the scan circuit outputs a current-stage output signal. In the synchronous mode, the synchronous circuit outputs the current-stage output signal.

Description

Drive circuit and shift register

The invention relates to a driving circuit and a shift register.

Liquid crystal displays have the advantages of low radiation and low power, and have become the mainstream of the display market.

The gate drive circuit of the liquid crystal display includes a plurality of shift registers. The current shift register may have some disadvantages, for example, the circuit size is large, the rise time and the fall time are too long, which results in slow operation speed, and the need for additional control signals results in a complex structure.

According to an example of this case, a shift register is proposed, including: a scanning circuit; a mode control circuit; and a synchronization circuit, coupled to the scanning circuit and the mode control circuit, wherein the mode control circuit determines the shift The bit register operates in a scan mode or a synchronization mode; in the scan mode, the scan circuit outputs an output signal of the current stage; and in the synchronization mode, the synchronization circuit outputs the output signal of the current stage.

According to an example of this case, a driving circuit including a plurality of stages of shift registers is proposed. Each of the shift registers includes: a scanning circuit; a mode control circuit; and a synchronization circuit coupled to the scanning circuit and the mode A control circuit, wherein the mode control circuit determines that the shift register is operated in a scan mode or a synchronization mode; in the scan mode, the scan circuits of the shift registers sequentially output a plurality of copies Stage output signal; and in the synchronization mode, the synchronization circuits of the shift registers synchronously output the current stage output signals.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100: shift register

110: Scanning circuit

130: Mode control circuit

150: Synchronous circuit

112: Scan control circuit

114: Scan pull-down circuit

116: Scanning pull-up circuit

152: Synchronous control circuit

154: Synchronous pull-down circuit

156: Synchronous pull-up circuit

T1~T14: Transistor

C: Capacitance

FIG. 1 shows a circuit structure diagram of a shift register according to an embodiment of the present application.

Figures 2A to 2L show the operation and signal timing diagrams of the shift register of the embodiment of the present application.

FIG. 3 shows the signal timing diagram of the multiple shift registers in the synchronous mode and the scan mode of the embodiment of this case.

The technical terms in this specification refer to the customary terms in the technical field. If there are descriptions or definitions for some terms in this specification, the explanation of the part of the terms is based on the description or definitions in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in any of the embodiments. The technical features of the department are combined.

Please refer to FIG. 1, which shows a circuit structure diagram of a shift register according to an embodiment of the present application. The gate drive circuit of the liquid crystal display device may include a multi-stage shift register. The shift register of the embodiment of the present application shown in FIG. 1 can be used to implement various levels of shift register.

As shown in FIG. 1, the shift register 100 of the embodiment of this case includes: a scanning circuit 110, a mode control circuit 130, and a synchronization circuit 150. The synchronization circuit 150 is coupled to the scanning circuit 110 and the mode control circuit 130. The scanning circuit 110 includes a scanning control circuit 112, a scanning pull-down circuit 114, and a scanning pull-up circuit 116. The synchronization circuit 150 includes: a synchronization control circuit 152, a synchronization pull-down circuit 154, and a synchronization pull-up circuit 156. The scan control circuit 112 includes transistors T1 to T4. The scan pull-down circuit 114 includes a transistor T5. The scan pull-up circuit 116 includes a transistor T6. The mode control circuit 130 includes transistors T7 to T8. The synchronization control circuit 152 includes transistors T9 to T12 and a capacitor C. The synchronous pull-down circuit 154 includes a transistor T13. The synchronous pull-up circuit 156 includes a transistor T14.

Transistor T1 includes: a source, which receives the start signal STV or the output signal of the previous stage of shift register or the output signal of the previous stages of shift register; the gate, which receives one of the clock signals CK1~CK3; And the drain is coupled to the node SQ. In the embodiment of this case, in the Nth stage shift register (N is a positive integer), the gate of the transistor T1 receives the clock signal CK3; in the N+1 stage shift register, the transistor The gate of T1 receives the clock signal CK1; in the N+2 stage shift register, the gate of the transistor T1 receives the clock signal CK2.

The transistor T2 includes: a source, which receives a reference voltage VGH (which is a high-level reference voltage); a gate, which is coupled to the node SQ; and a drain, which is coupled to the node SBT.

The transistor T3 includes: a source, which receives the reference voltage VGH; a gate, which is coupled to the node SBT; and a drain, which is coupled to the node SQ.

The transistor T4 includes: a source, which is coupled to the node SBT; a gate and a drain, which receive one of the clock signals CK1 to CK3. In the embodiment of this case, in the Nth stage shift register (N is a positive integer), the drain of the transistor T4 receives the clock signal CK2; in the N+1 stage shift register, the transistor The drain of T4 receives the clock signal CK3; in the N+2 stage shift register, the drain of the transistor T4 receives the clock signal CK1.

The transistor T5 includes: a source, which receives the reference voltage VGH; a gate, which is coupled to the node SBT; and a drain, which outputs the output signal SQ_OUT of this stage.

The transistor T6 includes: a source, which outputs the output signal SQ_OUT of the current stage; a gate, which is coupled to the node SQ; and a drain, which receives one of the clock signals CK1~CK3. In the embodiment of this case, in the Nth stage shift register (N is a positive integer), the drain of the transistor T6 receives the clock signal CK1; in the N+1 stage shift register, the transistor The drain of T6 receives the clock signal CK2; in the N+2 stage shift register, the drain of the transistor T6 receives the clock signal CK3.

The transistor T7 includes: a source, which receives the reference voltage VGH; a gate, which receives the mode control signal FL1; and a drain, which is coupled to the node SQ.

Transistor T8 includes: source, receiving reference voltage VGH; gate Pole, receiving mode control signal FL1; and drain pole, coupled to node SBT.

The transistor T9 includes: a source, which receives a reference voltage VGL (which is a low-level reference voltage); a gate, which receives a control signal CL2; and a drain, which is coupled to the node QB2.

The transistor T10 includes: a source, which is coupled to the node QB2; a gate, which receives the control signal CL3; and a drain, which receives the reference voltage VGH.

The transistor T11 includes: a source, which is coupled to the node Q2; a gate, which receives the control signal CL2; and a drain, which receives the reference voltage VGH.

The transistor T12 includes: a source, which receives the reference voltage VGL; a gate, which receives the control signal CL1; and a drain, which is coupled to the node Q2.

The capacitor C is coupled between the node Q2 and the output signal SQ_OUT of this stage.

The transistor T13 includes: a source, which receives the reference voltage VGL; a gate, which is coupled to the node Q2; and a drain, which outputs the output signal SQ_OUT of this stage.

The transistor T14 includes: a source, which outputs the output signal SQ_OUT of the current stage; a gate, which is coupled to the node QB2; and a drain, which receives the reference voltage VGH.

The operation of the shift register of the embodiment of this case will now be explained. Figures 2A to 2L show the operation and signal timing diagrams of the shift register of the embodiment of the present application. Below, the shift register operates in the synchronous mode first, and then switches to the scan mode as an example for illustration. It should be understood that this case is not limited to this. In other possible embodiments, the shift register operates in the scan mode first, and then switches to the synchronous mode This is also within the spirit of this case. When the mode control signal FL1 is in the first logic state (for example, but not limited to, logic low), the shift register operates in the synchronous mode; and when the mode control signal FL1 is in the second logic state (for example, but not limited to, logic low) At logic high), the shift register operates in scan mode.

As shown in Figure 2A, in the initial phase P1 of the synchronization mode, the mode control signal FL1 is L, so that the transistors T7 and T8 are turned on. The reference voltage VGH passes through the transistors T7 and T8 and enters the gates of the transistors T6 and T5, respectively, so the transistors T6 and T5 are turned off. Transistors T6 and T5 are the output transistors of the scanning circuit 110. In the synchronous mode, turning off the transistors T6 and T5 will not affect the output. In addition, in the synchronous mode, the scanning circuit 110 is turned off (that is, the transistors T1 to T6 are all turned off). Therefore, when describing the synchronization mode below, the on and off states of the transistors T9 to T14 of the synchronization circuit 150 will be described. The gate of the transistor T1 receives the clock signal CK3, and the source of the transistor T6 receives the clock signal CK1. Since the clock signal CK3 is H, the transistor T1 is turned off, and the start signal STV cannot enter the shift register of this stage. Since the control signal CL1 is H, the transistor T12 is turned off, and the control signal CL2 is L, the transistors T9 and T11 are both turned on. Since the transistor T9 is turned on, the reference voltage VGL is led to the gate of the transistor T14, so that the transistor T14 is also turned on. Therefore, the transistor T14 can output the current-level output signal SQ_OUT of H (reference voltage VGH). Since the transistor T11 is turned on, the reference voltage VGH is introduced to the node Q2, so that the transistor T13 is turned off.

Please refer to Figure 2B, which is shown in the hold phase of the synchronization mode P2. Since the signal timing in the holding phase P2 is basically the same as the signal timing in the initial phase P1, the detailed description is omitted here.

Please refer to Figure 2C, which is shown in the pull-down phase P3 of the synchronization mode. As shown in FIG. 2C, the control signal CL1 is L, the transistor T12 is turned on, and the reference voltage VGL is conducted through the transistor T12 to the node Q2, turning the transistor T13 on. The control signal CL2 is H, turning off the transistors T9 and T11. The control signal CL3 is L, which turns on the transistor T10. Therefore, the gate voltage of the transistor T14 is pulled up to the reference voltage VGH, so that the transistor T14 is turned off. Since the transistor T14 is turned off and the transistor T13 is turned on, the transistor T13 pulls the output signal SQ_OUT of this stage down to L.

Please refer to Figure 2D, which is shown in the pull-up phase P4 of the synchronous mode. As shown in Figure 2D, the control signal CL1 is H, so the transistor T12 is turned off. The control signal CL2 is L, and the transistors T9 and T11 are turned on. The control signal CL3 is H, turning off the transistor T10. The transistor T9 is turned on and the transistor T10 is turned off, so that the reference voltage VGL is introduced to the gate of the transistor T14, and the transistor T14 is turned on. Since the transistor T11 is turned on, the reference voltage VGH is introduced to the node Q2, so that the transistor T13 is turned off. Since the transistor T14 is turned on and the transistor T13 is turned off, the output of the transistor T14 is the H-level output signal SQ_OUT.

Please refer to Figure 2E, which shows that in the hold phase P5 of the synchronization mode, the hold phase P5 is to prepare for the subsequent scan mode. The control signal CL1 is H, and the transistor T12 is turned off. The control signal CL2 turns to H, so that the Crystals T9 and T11 are closed. The control signal CL3 turns to L, so that the transistor T10 is turned on, the gate voltage of the transistor T14 is pulled up, and the transistor T14 is turned off. The transistors T14 and T13 are both off, so the output signal SQ_OUT of this stage maintains the H level.

Please refer to Figure 2F, which is shown in the hold phase P6 of the synchronization mode. The signal timing of the holding phase P6 is basically the same as the signal timing of the holding phase P5. The transistors T14 and T13 are both off, so the output signal SQ_OUT of this stage maintains the H level.

Please refer to Figure 2G, which is shown at P7 in the initial stage of the scan mode. Since it enters the scan mode, the mode control signal FL1 turns to H, and the transistors T7 and T8 are turned off. In addition, in scan mode, T9-T14 are all closed. The clock signal CK1 is L, and the clock signal CK1 is input to the source of the transistor T6 (if this is the case in this stage of the shift register, then in the next stage of the shift register, the clock signal CK2 is input to the electric The source of the transistor T6 is the clock signal CK3 input to the source of the transistor T6 in the next two-level shift register). The clock signal CK2 is H, the clock signal CK2 is input to the source and gate of the transistor T4, and the transistor T4 is turned off (if this is the case in this stage of shift register, in the next stage of shift register, The clock signal CK3 is input to the source of the transistor T4, and in the next two-level shift register, the clock signal CK1 is input to the source of the transistor T4). The clock signal CK3 is H, and the transistor T1 is off. Due to the previous stage P6, the gate voltage of the transistor T2 (that is, the node SQ) is still H, and the transistor T2 remains closed. Similarly, due to the previous stage P6, the section The point SBT is still H, and the transistor T3 remains closed. That is, in this stage P7, all the transistors T1 to T14 are turned off, and the output signal SQ_OUT of this stage maintains the level of the previous stage.

Please refer to Figure 2H, which is shown in the hold phase P8 of the scan mode. The clock signal CK1 is H. The clock signal CK2 is L, the transistor T4 is turned on, the node SBT is turned to L, the transistor T3 is turned on, and the transistor T5 is turned on, and the output signal SQ_OUT of this stage is maintained at H (the transistor T5 provides a reference Voltage VGH to the output signal SQ_OUT of this stage). Since the transistor T3 is turned on, the reference voltage VGH is introduced to the node SQ, and the transistors T2 and T6 are turned off. The clock signal CK3 is still H, and the transistor T1 is still off.

Please refer to Figure 2I, which is shown in the hold phase P9 of the scan mode. The clock signal CK1 is still H. The clock signal CK2 is H, turning off the transistor T4. The clock signal CK3 is L, the transistor T1 is turned on to allow the start signal STV to enter (the start signal STV is L at this time), the node SQ is pulled to L, and the transistor T2 is turned on. Since the transistor T2 is turned on, the reference voltage VGH enters the node SBT, turning off the transistors T3 and T5. Since the node SQ is L, the transistor T6 is turned on, so that the output signal SQ_OUT of this stage is equal to the clock signal CK1 (which is H and is provided by the transistor T6).

Please refer to Figure 2J, which is shown in the pull-down stage P10 of the scan mode. The clock signal CK1 is L. The clock signal CK2 is H, and the transistor T4 is turned off. The clock signal CK3 is H, and the transistor T1 is off. Because the node SQ in the previous stage is L, and the instantaneous clock signal CK1 turns to L, making the node SQ is further pulled down from L to L', and the transistor T6 is still turned on, so the output signal SQ_OUT of this stage is pulled down to L. Since the node SQ is L', the transistor T2 is turned on, the node SBT is pulled up to the reference voltage VGH, and the transistors T3 and T5 are turned off.

Please refer to Figure 2K, which is shown in the pull-up phase P11 of the scan mode. The clock signal CK1 is H. The clock signal CK2 is L, the transistor T4 is turned on, and the node SBT is pulled low, and the transistors T5 and T3 are turned on. Because the transistor T3 is turned on, the reference voltage VGH pulls the node SQ high through the transistor T3, and the transistor T6 is turned off . Since the transistor T5 is turned on, the reference voltage VGH pulls the output signal SQ_OUT of this stage high through the transistor T5. The clock signal CK3 is H, and the transistor T1 is turned off.

Please refer to Figure 2L, which is shown in the hold phase P12 of the scan mode. The clock signal CK1 is H. The clock signal CK2 is H, the transistor T4 is turned off, the node SBT is maintained at L, and the transistors T3 and T5 are turned on. The transistor T3 is turned on, and the reference voltage VGH pulls the node SQ to H through the transistor T3. Since the transistor T5 is turned on, the reference voltage VGH pulls the output signal SQ_OUT of this stage high through the transistor T5. The clock signal CK3 is L, the transistor T1 is turned on, the start signal STV is introduced to the node SQ, and the node SQ is H to turn off the transistors T6 and T2. After that, the output signal SQ_OUT of this stage is maintained at H, and will not act until the next frame (the "synchronous mode" of the next frame).

Please refer to FIG. 3, which shows the signal timing diagram of the multiple shift registers in the embodiment of the present application in the synchronous mode and the scan mode. In Figure 3, SQ_OUT(1)~SQ_OUT(4) represent the output signals of 4 shift registers, but this case is not limited to this. As shown in Figure 3, in the synchronous mode, the synchronous circuits of all the shift registers synchronously output the output signal of the current stage; and, in the scan mode, the scans of all the shift registers The circuit outputs the output signal of this stage in sequence.

In the above-mentioned embodiment of this case, since no additional control signal is required for control, the structure is relatively simple. In addition, the output capacity has been strengthened, and the rise time and fall time have also been improved.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: shift register

110: Scanning circuit

130: Mode control circuit

150: Synchronous circuit

112: Scan control circuit

114: Scan pull-down circuit

116: Scanning pull-up circuit

152: Synchronous control circuit

154: Synchronous pull-down circuit

156: Synchronous pull-up circuit

T1~T14: Transistor

C: Capacitance

Claims (7)

A shift register includes: a scan circuit; a mode control circuit; and a synchronization circuit, coupled to the scan circuit and the mode control circuit, wherein the mode control circuit determines the shift register to operate on A scanning mode or a synchronization mode; in the scanning mode, the scanning circuit outputs an output signal of the current stage; and in the synchronization mode, the synchronization circuit outputs the output signal of the current stage; and wherein, in the synchronization mode, The scanning circuit is turned off; and, in the scanning mode, the synchronization circuit and the mode control circuit are turned off. The shift register according to claim 1, wherein the scanning circuit includes: a first transistor, including: a source, receiving a start signal; a gate, receiving one of the plurality of clock signals A clock signal; and a drain, coupled to a first node; a second transistor including: a source, receiving a first reference voltage; a gate, coupled to the first node; and a A drain, coupled to a second node; a third transistor, including: a source, receiving the first reference voltage; a gate, coupled to the second node; and a drain, coupled to the A first node; a fourth transistor including: a source, coupled to the second node; a gate and a drain, receiving a second clock signal of the clock signals; a fifth transistor Including: a source for receiving the first reference voltage; a gate Pole, coupled to the second node; and a drain pole, outputting the output signal of the current stage; and a sixth transistor including: a source pole, outputting the output signal of the current stage; a gate electrode, coupled to the first Node; and a drain, which receives a third clock signal of the clock signals. The shift register according to claim 2, wherein the mode control circuit includes: a seventh transistor including: a source for receiving the first reference voltage; a gate for receiving a mode control signal, the The mode control signal determines that the shift register is operated in the scan mode or the synchronization mode; and a drain, coupled to the first node; and an eighth transistor including: a source, which receives the first reference Voltage; a gate, receiving the mode control signal; and a drain, coupled to the second node. The shift register according to claim 3, wherein the synchronization circuit includes: a ninth transistor including: a source, receiving a second reference voltage; a gate, receiving a second control signal; and A drain, coupled to a third node; a tenth transistor including: a source, coupled to the third node; a gate, receiving a third control signal; and a drain, receiving the third node A reference voltage; an eleventh transistor including: a source, coupled to a fourth node; a gate, receiving the second control signal; and a drain, receiving the first reference voltage; A twelfth transistor includes: a source, receiving the second reference voltage; a gate, receiving a first control signal; and a drain, coupled to the fourth node; a capacitor, coupled to the Between the fourth node and the output signal of the current stage; a thirteenth transistor includes: a source, receiving the second reference voltage; a gate, coupled to the fourth node; and a drain, outputting the The output signal of the current stage; and a fourteenth transistor including: a source to output the output signal of the current stage; a gate coupled to the third node; and a drain to receive the first reference voltage. The shift register according to claim 4, wherein, in an initial stage of the synchronization mode, the mode control signal is a first logic state, so that the seventh transistor and the eighth transistor are turned on, The first reference voltage passes through the seventh transistor and the eighth transistor to turn off the sixth transistor and the fifth transistor. The first transistor is turned off. In response to the first control signal, the tenth transistor is turned off. The second transistor is turned off, and in response to the second control signal, the ninth transistor and the eleventh transistor are turned on, and in response to the ninth transistor being turned on, the second reference voltage is conducted to the first The fourteenth transistor turns on the fourteenth transistor with the output of the current stage output as a logic high, in response to the eleventh transistor being turned on, so that the first reference voltage is introduced to the fourth node to allow the tenth The tri-transistor is turned off; in a first holding phase of the synchronization mode, the output of the current stage is maintained at logic high; in the pull-down phase of the synchronization mode, the first control signal changes the tenth Two transistors are turned on, the second reference voltage is conducted to the fourth node through the twelfth transistor to turn on the thirteenth transistor, and the second control signal is the ninth transistor and the eleventh transistor. The transistor is turned off, the third control signal turns on the tenth transistor so that the fourteenth transistor is turned off, and the thirteenth transistor pulls the output signal of this stage down to logic low; in the synchronous mode In a pull-up phase, the first control signal turns off the twelfth transistor, the second control signal turns on the ninth transistor and the eleventh transistor, and the third control signal turns off the tenth transistor , The ninth transistor is turned on and the tenth transistor is turned off so that the second reference voltage turns on the fourteenth transistor, because the eleventh transistor is turned on, the first reference voltage is introduced to the fourth node In order to make the thirteenth transistor turn off, the fourteenth transistor outputs the output signal of the current stage with logic high; in a second holding phase of the synchronization mode, the first control signal turns the twelfth transistor off. The crystal is turned off, the second control signal turns off the ninth transistor and the eleventh transistor, the third control signal turns on the tenth transistor to turn off the fourteenth transistor, the output signal of this stage Maintaining a logic high; and in a third holding phase of the synchronization mode, the fourteenth transistor and the thirteenth are both turned off to maintain the output signal of the current stage at a logic high. The shift register according to claim 5, wherein, in an initial stage of the scan mode, the first transistor to the fourteenth transistor are all turned off, and the output signal of the current stage is maintained at logic high ; In a first hold phase of the scan mode, the fourth transistor is turned on to turn on the third transistor and the fifth transistor to maintain the output signal of the current stage Is held at logic high, and the second transistor and the sixth transistor are turned off, the first transistor is turned off; in a second holding phase of the scan mode, the fourth transistor is turned off, and the first transistor is turned off. The crystal is turned on and the second transistor is turned on to turn off the third transistor and the fifth transistor, and the sixth transistor is turned on so that the output signal of the current stage is logic high; in the pull-down phase of the scan mode, The fourth transistor is turned off, the first transistor is turned off, the first node is further pulled down, the sixth transistor is turned on to pull the output signal of the current stage low, the second transistor is turned on, and the second transistor is turned on. The three transistors and the fifth transistor are turned off; in a pull-up phase of the scan mode, the third transistor to the fifth transistor are turned on, the sixth transistor is turned off, and the fifth transistor turns off When the output signal of this stage is pulled high, the first transistor is turned off; in a third hold phase of the scan mode, the fourth transistor is turned off, the third transistor is connected to the fifth transistor, and the fifth transistor The output signal of the current stage is pulled high, the first transistor is turned on, the sixth transistor and the second transistor are turned off, and the output signal of the current stage is maintained at logic high. A drive circuit includes a plurality of stages of shift registers, each of the shift registers includes: a scanning circuit; a mode control circuit; and a synchronization circuit coupled to the scanning circuit and the mode control circuit, wherein , The mode control circuit determines the shift register to operate in a scan mode or a synchronization mode; In the scan mode, the scan circuits of the shift registers sequentially output a plurality of output signals of the current stage; and in the synchronization mode, the synchronization circuits of the shift registers output the output signals synchronously. The output signals of the current stage; and wherein, in the synchronization mode, the scanning circuits of the shift registers are turned off; and, in the scanning mode, the synchronization circuits of the shift registers And these mode control circuits are closed.

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