TWI529731B - Display panel and bi-directional shift register circuit - Google Patents

Description

Display panel and bidirectional shift register circuit

The present invention relates to a shift register, and more particularly to a bidirectional shift register that supports reverse scan sequence operations.

The shift register is widely used in the data driving circuit and the gate driving circuit for respectively controlling the timing of the sampling data signals of each data line and generating the timing of the scanning signals for each gate line. In the data driving circuit, the shift register is configured to output a selected signal to each data line, so that the image data can be sequentially written into each data line. On the other hand, in the gate driving circuit, the shift register is configured to generate a scan signal to each gate line for sequentially writing the image signals supplied to the data lines to the pixels of the pixel matrix.

Conventional shift registers can only generate sampled or scanned signals in a single scan order. However, a single scanning sequence has been unable to meet the needs of today's image display system products. For example, the display screen of some digital cameras can be rotated according to the angle at which the camera is placed. In addition, some image display systems may include the function of rotating the screen. Therefore, there is a need for a new bidirectional shift register architecture that can produce output signals in different scan orders.

According to an embodiment of the invention, a bidirectional shift register circuit includes a plurality of shift registers, and one of the shift registers is an Nth stage shift register Including the input stage circuit, the output stage circuit, the control circuit and the pull-down circuit. The input stage circuit is coupled to the first signal input end and the second signal input end for receiving the first input signal and the second input signal, wherein the first input signal is a start pulse or a (N-1)th shift The gate driving signal generated by the register, the second input signal is a gate driving signal or a starting pulse generated by the (N+1)th stage shift register, wherein N is a positive integer greater than one The output stage circuit is coupled to the first clock input end and the output end, and coupled to the input stage circuit to the first control point and the second control point for receiving the first clock signal from the first clock input end And outputting a gate driving signal according to the first control voltage level of the first control point and the second control voltage level of the second control point. The control circuit and the input stage circuit and the output stage circuit are coupled to the first control point and the second control point, and coupled to the input stage circuit to the third control point for controlling the first control voltage level and the second control voltage Level. The pull-down circuit is coupled to the output end and coupled to the control circuit to the third control point; wherein, when the bidirectional shift register circuit operates in the forward scan, the shift register sequentially outputs the corresponding output in the first order The gate drive signal, when the bidirectional shift register circuit operates in the reverse scan, the shift register sequentially outputs the corresponding gate drive signal in a second order.

According to another embodiment of the present invention, a display panel includes a pixel matrix, a control chip, a data driving circuit, and a gate driving circuit. The pixel matrix includes complex pixels. The control chip is used to generate a complex clock signal and a start pulse. The data driving circuit is configured to generate a plurality of data driving signals to provide data to the pixels. The gate driving circuit is configured to generate a plurality of gate driving signals to drive pixels, wherein the gate driving circuit comprises a bidirectional shift register circuit, and the bidirectional shift register circuit comprises a plurality of shift registers, wherein the Nth The stage shift register includes an input stage circuit, an output stage circuit, a control circuit, and a pull-down circuit. The input stage circuit is coupled to the first a signal input end and a second signal input end for receiving the first input signal and the second input signal, wherein the first input signal is a start pulse or the gate generated by the (N-1)th stage shift register a pole drive signal, the second input signal is a gate drive signal or a start pulse generated by the (N+1)th stage shift register, wherein N is a positive integer greater than one; the output stage circuit is coupled to the first a clock input end and an output end, and coupled to the input stage circuit to the first control point and the second control point for receiving the first clock signal from the first clock input end, and according to the first control point The first control voltage level and the second control voltage of the second control point are at the output terminal output driving signal. The control circuit and the input stage circuit and the output stage circuit are coupled to the first control point and the second control point, and coupled to the input stage circuit to the third control point for controlling the first control voltage level and the second control voltage Level. The pull-down circuit is coupled to the output end and coupled to the control circuit to the third control point; wherein, when the bidirectional shift register circuit operates in the forward scan, the shift register sequentially outputs the corresponding output in the first order The gate drive signal, when the bidirectional shift register circuit operates in the reverse scan, the shift register sequentially outputs the corresponding gate drive signal in a second order.

100‧‧‧Image display system

101‧‧‧ display panel

102‧‧‧Input unit

110‧‧‧ gate drive circuit

120‧‧‧Data Drive Circuit

130‧‧‧ pixel matrix

140‧‧‧Control chip

200‧‧‧Bidirectional shift register circuit

300, 400, SR[1], SR[2], SR[N-1], SR[N]‧‧‧ shift register

310‧‧‧Input stage circuit

320‧‧‧Output stage circuit

330‧‧‧Control circuit

340‧‧‧ Pulldown circuit

C1, C2‧‧‧ capacitor

CK1, CK2‧‧‧ clock input

CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10, CLK11, CLK12, DATA, G(1), G(2), G(3), G(4), G(5) , G(6), G(7), G(8), G(N-7), G(N-6), G(N-5), G(N-4), G(N-3) , G(N-2), G(N-1), G(N)‧‧‧ signals

IN1, IN2‧‧‧ signal input

N1, N2, N3‧‧‧ control points

OUT‧‧‧ output

SP‧‧‧ starting pulse

T1, T2, T3, T4, T5, T6, T7, T8, T9‧‧‧ transistors

Ta, Tb, Tc, Td‧‧‧

VH, VH', VH", VL, Vth‧‧‧ voltage

1 is a diagram showing an embodiment of an image display system according to an embodiment of the present invention.

2 is a block diagram showing a bidirectional shift register circuit according to an embodiment of the present invention.

Figure 3 is a block diagram showing a shift register in accordance with an embodiment of the present invention.

Figure 4 is a circuit diagram showing a shift register according to an embodiment of the present invention.

Figure 5 is a waveform diagram showing control voltages and signals of respective control points when the shift register operates in the forward scan according to an embodiment of the present invention.

Figure 6 is a diagram showing waveforms of control voltages and signals of respective control points when the shift register is operated in reverse scanning according to an embodiment of the present invention.

Figure 7 is a diagram showing an exemplary waveform of a clock signal according to an embodiment of the present invention.

Figure 8 is a diagram showing an exemplary waveform of a gate driving signal according to an embodiment of the present invention.

Figure 9 is a diagram showing an exemplary waveform of a clock signal according to another embodiment of the present invention.

Figure 10 is a diagram showing an exemplary waveform of a clock signal according to still another embodiment of the present invention.

In order to make the invention, the method, the objects and the advantages of the present invention more obvious, the following detailed description of the preferred embodiments and the accompanying drawings An embodiment of an image display system according to an embodiment. As shown, the image display system 100 can include a display panel 101. The display panel 101 includes a gate driving circuit 110, a data driving circuit 120, a pixel matrix 130, and a control wafer 140. The gate driving circuit 110 is configured to generate a plurality of gate driving signals to drive the plurality of pixels of the pixel matrix 130. The data driving circuit 120 is configured to generate a plurality of data driving signals to provide data to the pixel matrix 130 plural pixels. The control chip 140 is configured to generate a complex timing signal including a clock signal, a reset signal, a start pulse, and the like. In some embodiments of the present invention, the image display system 100 may further include an input unit 102. In addition, the image display system 100 has various embodiments including: a mobile phone, a digital camera, a mobile computer, a desktop computer, a television, a display for a car, or any device including an image display function. According to an embodiment of the present invention, the gate driving circuit 110 may include a bidirectional shift register circuit that sequentially generates a gate driving in different scanning orders (for example, the first sequential scanning and the second sequential scanning). The signals are sent to the gate lines to sequentially write the image signals supplied to the data lines into the pixels of the pixel matrix 130.

2 is a block diagram showing a bidirectional shift register circuit according to an embodiment of the present invention. The bidirectional shift register circuit 200 includes a plurality of serially connected shift registers SR[1], SR[2], ...SR[N-1], SR[N] for generating gate drive signals G, respectively. (1) One of ~G(N). Each shift register includes a signal input terminal IN1 and IN2, a clock input terminal CK1 and CK2, and an output terminal OUT. The first stage shift register SR[1] receives the start pulse SP through the input terminal IN1, and the input terminal IN1 of the other stage shift register SR[2]~SR[N] is coupled to the adjacent one. The output terminal OUT of the shift register (for example, the shift register SR[1]~SR[N-1] of the previous stage) is used to receive the corresponding gate drive signal from the shift register. The other input terminal IN2 of the shift register SR[1]~SR[N-1] is coupled to another adjacent shift register (for example, the shift register SR[2] of the latter stage The output terminal OUT of ~SR[N]) is used to receive a corresponding gate drive signal from the shift register, and the last stage shift register SR[N] receives the start pulse SP through the input terminal IN2. When the bidirectional shift register circuit 200 operates in the forward scan, the shift registers SR[1]~SR[N] output the corresponding gate drive signals in a first order. G(1)~G(N), and when the bidirectional shift register circuit 200 operates in the reverse scan, the shift register SR[N]~SR[1] outputs the corresponding gate in a second sequence. The pole drive signal G(N)~G(1).

It should be noted that, as shown in FIG. 2, the bidirectional shift register circuit can receive four clock signals CLK1 CLK CLK4 and can include at least four stages of serial shift register. According to an embodiment of the present invention, taking an active high clock signal as an example, time intervals in which the clock signal has a high voltage level may partially overlap. In addition, it should be noted that in the preferred embodiment of the present invention, the shift registers SR[1]~SR[N] receive the clock signals CLK1 CLK CLK4 in a round-robin manner. For example, as shown in FIG. 2, the first stage shift register SR[1] receives the clock signals CLK1 and CLK3 through the clock input terminals CK1 and CK2, respectively, and the second stage shift register SR[ 2] receiving the clock signals CLK2 and CLK4 through the clock input terminals CK1 and CK2, respectively, and the third-stage shift register SR[3] receives the clock signals CLK3 and CLK1 through the clock input terminals CK1 and CK2, respectively. The stage shift register SR[4] receives the clock signals CLK4 and CLK2 through the clock input terminals CK1 and CK2, respectively, wherein a four-stage shift register constitutes a loop, and the subsequent shift is temporarily performed. The register can repeat this loop.

It should be noted that in different embodiments of the present invention, taking an active high clock signal as an example, the time interval of the clock signal having a high voltage level can be designed to have two horizontal periods. The length of the horizontal period (ie, 2H), or the length of two horizontal periods or more. For example, when the number of current pulse signals increases, the time interval in which the clock signal has a high voltage level can be further extended to the length of three horizontal periods (ie, 3H), and the length of four horizontal periods (ie, 4H). ), the length of five horizontal periods (ie, 5H), the length of six horizontal periods Degree (ie, 6H) and so on. The horizontal period is equivalent to one cycle time of the horizontal synchronization signal and the data enable signal DE. The following paragraphs will describe various embodiments corresponding to different clock signal designs.

Figure 3 is a block diagram showing a shift register in accordance with an embodiment of the present invention. The shift register 300 can include an input stage circuit 310, an output stage circuit 320, a control circuit 330, and a pull down circuit 340. The input stage circuit 310 is coupled to the signal input terminals IN1 and IN2 for receiving a corresponding gate drive signal and/or a start pulse from an adjacent shift register. The output stage circuit 320 is coupled to the clock input terminal CK1 and the output terminal OUT, and is coupled to the input stage circuit 310 to the first control point and the second control point (not shown in FIG. 3) for transmitting through the clock. The terminal CK1 receives a clock signal, and according to the first control voltage level of the first control point and the second control voltage level of the second control point, timely outputs the clock signal to the output terminal OUT for use as a corresponding gate The pole drive signal (described in more detail below). The control circuit 330 is coupled to the first control point and the second control point, and is coupled to the input control circuit 310 to the third control point for controlling the first control point and the second The control voltage level of the control point and the third control point (described in more detail below). The pull-down circuit 340 is coupled to the output terminal OUT and coupled to the control circuit 330 to the third control point.

Figure 4 is a circuit diagram showing a shift register according to an embodiment of the present invention. According to an embodiment of the present invention, the shift register 400 may include transistors T1 to T9 and capacitors C1 and C2, wherein the transistors T1 and T2 and the capacitors C1 and C2 are included in the output stage circuit, and the transistors T3 and T4 The system is included in the input stage circuit, the transistor T5 is included in the pull-down circuit, and the transistors T6~T9 are included in the control circuit. In addition, in the embodiment of the present invention, the capacitors C1 and C2 may be additionally coupled capacitors. The parasitic capacitance of the transistor is set, and the invention is not limited to any of the embodiments.

The first end of the transistor T1 is coupled to the clock input terminal CK1, the second end is coupled to the first control point N1, and the third end is coupled to the output terminal OUT. The first end of the transistor T2 is coupled to the clock input terminal CK1, the second end is coupled to the second control point N2, and the third end is coupled to the output terminal OUT. The capacitor C1 is coupled between the first control point N1 and the output terminal OUT, and the capacitor C2 is coupled between the second control point N2 and the output terminal OUT. As shown in the figure, the transistors T1 and T2 and the capacitors C1 and C2 are symmetrically coupled between the clock input terminal CK1 and the output terminal OUT.

The first end of the transistor T3 is coupled to the signal input terminal IN1, the second end is coupled to the third control point N3, and the third end is coupled to the first control point N1. The first end of the transistor T4 is coupled to the signal input terminal IN2, the second end is coupled to the third control point N3, and the third end is coupled to the second control point N2. In an embodiment of the invention, the transistors T3 and T4 are turned on or off according to a third control voltage level of the third control point N3.

The first end of the transistor T5 is coupled to the output terminal OUT, the second end is coupled to the third control point N3, and the third end is coupled to the low operating voltage VL. In an embodiment of the invention, the transistor T5 is turned on or off according to a third control voltage level of the third control point N3.

The first end of the transistor T6 is coupled to the high operating voltage VH, the second end is coupled to the clock input terminal CK2, and the third terminal is coupled to the third control point N3. The first end of the transistor T7 is coupled to the third control point N3, and the second end is coupled to the first control point N1. The first end of the transistor T8 is coupled to the third control point N3, and the second end is coupled to the second control point N2. The third end of the transistor T9 coupled to the transistor T7 and the third end and the second end of the transistor T8 are coupled to the clock input terminal CK1 and the third terminal are coupled to the low operating voltage VL.

Figure 5 is a diagram showing shifting according to an embodiment of the present invention. The register operates on the waveforms of the control voltage and signal of each control point during forward scanning, wherein the voltage and signal waveforms shown in FIG. 5 are the voltages and signals corresponding to the first stage shift register SR[1]. Waveform. In conjunction with Figures 4 and 5, the following paragraphs provide a more detailed description of the operation of the shift register proposed by the present invention.

In an initial stage, for example, before the first stage Ta in FIG. 5, the control voltages of the first control point N1 and the second control point N2 are set to have a low voltage level, for example, a voltage level having a low operating voltage VL. The control voltage of the third control point N3 is set to have a high voltage level, for example, a voltage level close to the high operating voltage VH minus the threshold voltage of the transistor T6. According to an embodiment of the invention, the initial control voltage of the third control point N3 can be set by the reset circuit. For example, in the circuit shown in FIG. 4, a reset transistor can be further coupled in parallel with the transistor T6 between the high operating voltage VH and the third control point N3, and can be turned on according to a reset signal. The initial third control voltage of the third control point N3 is set to have a high voltage level in an initial stage. Once the initial third control voltage of the third control point N3 is set to have a high voltage level, the initial first control voltage level of the first control point N1 and the initial second control voltage level of the second control point N2 are permeable. The turned-on transistors T3 and T4 are set to have a low voltage level. At this time, since the transistor T5 is turned on, the gate driving signal G(1) also has a low voltage level.

In the first phase Ta, the start pulse SP arrives, causing the first control point N1 to be charged to approximately the high operating voltage VH minus one of the threshold voltages of the transistor T3 and the transistor T6 (as shown) (VH-2Vth), where it is assumed here that all transistors have the same threshold voltage). At this time, the control voltage levels of the second control point N2 and the third control point N3 remain unchanged, and the transistors T1 and T7 are turned on in response to the high voltage level of the first control point N1, and the capacitor C1 will store the first. Control point N1 and output The voltage difference of OUT.

At the beginning of the second phase Tb, the voltage at the clock input terminal CK1 is raised to a high voltage level close to the high operating voltage VH in response to the arrival of the pulse of the clock signal CLK1. The voltage change at the clock input CK1 further raises the first control voltage level of the first control point N1 to a higher voltage level (VH' as shown). Since the first control voltage level of the first control point N1 is further pulled high, the voltage of the second terminal of the transistor T1 is increased, causing the conduction current of the transistor T1 to increase, and the clock signal CLK1 can directly pass through the conduction current. The crystal T1 is sent to the output terminal OUT without a threshold voltage loss, and the waveform of the gate drive signal G(1) is generated according to the clock signal CLK1. At the same time, the transistor T9 is also turned on according to the high voltage level of the clock input terminal CK1, so that the third control voltage level of the third control point N3 is pulled down to the low voltage level with the low operating voltage VL. At this time, the second control point N2 is also coupled to the small output voltage VH from the output terminal OUT through the capacitor C2.

In the third stage Tc, the voltage of the clock input terminal CK1 is pulled down to a low voltage level with a low operating voltage VL according to the end of the pulse of the clock signal CLK1, and the voltage level of the output terminal OUT is transmitted through the crystal. T1 is discharged to a low voltage level, and the pulse of the gate drive signal G(1) is successfully generated.

In the fourth phase Td, the voltage of the clock input terminal CK2 is raised to a high voltage level corresponding to the high operating voltage VH in response to the pulse of the clock signal CLK3. At this time, the transistor T6 is turned on, and the third control voltage level of the third control point N3 is pulled up to a voltage level similar to the high operating voltage VH minus the threshold voltage of the transistor T6 (as shown in the figure (VH- Vth)). At this time, the transistor T3 is turned on, and the input terminal IN1 has a low voltage level, so that the first control voltage of the first control point N1 is discharged to the low voltage level through the transistor T3. Similarly, at this time, the transistor T4 will be turned on, and the input terminal IN2 is blocked. The pulse of the pole drive signal G(2) arrives with a high voltage level, so that the second control voltage of the second control point N2 is pulled high through the transistor T4 to approximately the high operating voltage VH minus the transistor T4 and One of the threshold voltages of the transistor T6 is a high voltage level (VH-2Vth) as shown.

As shown in FIG. 5, in the forward scanning, the gate driving signals G(1)~G(N) can be sequentially generated, so that the pixels on the gate line can be sequentially operated to receive the data driving signal. Corresponding data on DATA. It should be noted that although only the control point voltages and signal waveforms corresponding to the first-stage shift register SR[1] are shown in FIG. 5, those skilled in the art can derive other stages according to the above paragraphs. The shift register operates on the voltage and signal waveform of each control point during forward scanning, and therefore the related description will not be repeated here.

6 is a waveform diagram showing control voltages and signals of respective control points when the shift register is operated in reverse scanning according to an embodiment of the present invention, wherein the node voltage and signal waveforms shown in FIG. 6 are shown. The control voltage and signal waveform corresponding to the last stage shift register SR[N]. During the reverse scan, the start pulse is received by the shift register SR[N], and the shift register SR[N]~SR[1] can sequentially generate the gate drive signal G(N)~ G(1), so that the pixels on the gate line can be sequentially operated to receive the corresponding data on the data driving signal DATA.

Since the operation of the shift register in the reverse scan is similar to the operation in the forward scan, those skilled in the art can derive the operation of the shift register in the reverse scan according to the above paragraphs, The related description will not be repeated here.

It can be seen from the above embodiment that the time interval in which the clock signal has a high voltage level partially overlaps, thereby eliminating the pulse rise time Tr of the gate drive signal and the charging time of each pixel of the pixel matrix. Impact. In other words, Compared with the conventional technique, the charging time of each pixel of the pixel matrix is not shortened by the rise time Tr required for the pulse of the gate driving signal. In addition, as can be seen from the above implementation, the transistors T6, T7 and T9 in the control circuit, and T6, T8 and T9 are not turned on at the same time at any time, and therefore, will not be due to the high operating voltage VH and A conduction path is generated between the low operating voltages VL to generate a large current. As a result, the shift register circuit proposed by the present invention does not have a large current consumption at any stage as compared with the conventional technology.

As described above, when the number of the pulse signals is increased, taking the active high clock signal as an example, the time interval in which the clock signal has a high voltage level can be further extended to the length of three horizontal periods. (ie, 3H), the length of four horizontal periods (ie, 4H), the length of five horizontal periods (ie, 5H), the length of six horizontal periods (ie, 6H), and the like. For example, when the number of current pulse signals is increased from four to eight, the time interval of the clock signal having a high voltage level can be further extended to 3H or 4H, and the number of current pulse signals is increased to twelve. At the same time, the time interval in which the clock signal has a high voltage level can be further extended to 5H or 6H, and so on. More specifically, when the time interval of the pulse signal has a high voltage level is designed as [(2M+1)H] or [(2M+2)H], where M>=0, the required clock The number of signals is [4*(M+1)].

Figure 7 is a diagram showing an exemplary waveform of a clock signal according to an embodiment of the present invention. Figure 8 is a diagram showing an exemplary waveform of a gate driving signal according to an embodiment of the present invention. The signal waveforms shown in FIGS. 7 and 8 are the result of extending the time interval length of the clock signal having a high voltage level to the length of three horizontal periods, and are shown in FIGS. 7 and 8. The signal waveform can be applied to both forward and reverse scans. As shown in the figure, during forward scanning, the clock signals CLK1~CLK8 The pulses arrive in sequence, and the pulses of the gate drive signals G(1)~G(8) are also generated in sequence according to the pulses of the clock signals CLK1~CLK8. In the reverse scan, the signal waveforms shown in Figures 7 and 8 correspond to the order in parentheses, and the pulse of the gate drive signal G(N)~G(N-7) responds to the clock signal CLK8. The pulse of ~CLK1 is generated sequentially.

The signal waveforms shown in Figures 7 and 8 can be directly applied to the circuit diagrams shown in Figures 3 and 4, which can be used by those skilled in the art according to the above paragraphs and Figures 7 and 8. The illustrated signal waveform derives the operation of the shift register, so the related description will not be repeated here. It is worth noting that when the pulse signal is increased to eight, the cycle of the receiving register SR[1]~SR[N] for receiving the clock signal will also change. For example, the first stage shift register SR[1] receives the clock signals CLK1 and CLK5 through the clock input terminals CK1 and CK2, respectively, and the second stage shift register SR[2] respectively transmits the clock input. The terminals CK1 and CK2 receive the clock signals CLK2 and CLK6, and the third stage shift register SR[3] receives the clock signals CLK3 and CLK7 through the clock input terminals CK1 and CK2, respectively, and the fourth stage shift register SR [4] receiving the clock signals CLK4 and CLK8 through the clock input terminals CK1 and CK2, respectively, and the fifth-stage shift register SR[5] receives the clock signals CLK5 and CLK1 through the clock input terminals CK1 and CK2, respectively. The six-stage shift register SR[6] receives the clock signals CLK6 and CLK2 through the clock input terminals CK1 and CK2, respectively, and the seventh-stage shift register SR[7] receives the clock input terminals CK1 and CK2, respectively. The clock signals CLK7 and CLK3, the eighth-stage shift register SR[8] receive the clock signals CLK8 and CLK4 through the clock input terminals CK1 and CK2, respectively, wherein the eight-stage shift register constitutes a loop. Preferably, this loop can be repeated in subsequent shift registers.

Figure 9 is a diagram showing a clock according to another embodiment of the present invention. The signal waveform of the sample example, the signal waveform shown in Fig. 9 is the result of extending the length of the time interval in which the clock signal has a high voltage level to the length of four horizontal periods. As shown in the figure, during forward scanning, the pulses of the clock signals CLK1~CLK8 will arrive sequentially, while in the reverse scan, the signal waveforms shown in Figure 9 correspond to the order in parentheses, the clock. The pulses of signals CLK8~CLK1 will arrive in sequence.

The signal waveform shown in FIG. 9 can be directly applied to the circuit diagrams shown in FIGS. 3 and 4, and those skilled in the art can derive the shift according to the signal waveforms shown in the above paragraphs and FIG. The operation of the register and the corresponding gate drive signal waveform diagram, therefore, the relevant description will not be repeated here. In addition, when the time interval of the pulse signal has a high voltage level is extended to 4H, the shift register SR[1]~SR[N] is used to receive the clock signal cycle and the current pulse signal has a high voltage level. When the length of the time interval is extended to 3H, the related description will not be repeated here.

10 is a waveform diagram showing an example of a clock signal according to still another embodiment of the present invention, and the signal waveform shown in FIG. 10 is for extending the time interval length of the clock signal to a high voltage level to five. The result of the length of a horizontal period. As shown in the figure, during forward scanning, the pulses of the clock signals CLK1~CLK12 will arrive sequentially, while in the reverse scan, the signal waveforms shown in Figure 10 correspond to the order in parentheses, the clock. The pulses of signals CLK12~CLK1 will arrive in sequence.

The signal waveform shown in FIG. 10 can be directly applied to the circuit diagrams shown in FIGS. 3 and 4, and those skilled in the art can derive the shift according to the signal waveforms shown in the above paragraphs and FIG. The operation of the register and the corresponding gate drive signal waveform diagram, therefore, the relevant description will not be repeated here. In addition, when the pulse signal is increased to 12, the cycle of the receiving register SR[1]~SR[N] for receiving the clock signal also changes. For example, when the first stage shift register SR[1] is transmitted separately The pulse input terminals CK1 and CK2 receive the clock signals CLK1 and CLK7, and the second-stage shift register SR[2] receives the clock signals CLK2 and CLK8 through the clock input terminals CK1 and CK2, respectively, and the third-stage shift is temporarily stored. The SR[3] receives the clock signals CLK3 and CLK9 through the clock input terminals CK1 and CK2, respectively, and the fourth stage shift register SR[4] receives the clock signals CLK4 and CLK10 through the clock input terminals CK1 and CK2, respectively. The fifth-stage shift register SR[5] receives the clock signals CLK5 and CLK11 through the clock input terminals CK1 and CK2, respectively, and the sixth-stage shift register SR[6] respectively transmits the clock input terminal CK1 and CK2 receives the clock signals CLK6 and CLK12, and the seventh-stage shift register SR[7] receives the clock signals CLK7 and CLK1 through the clock input terminals CK1 and CK2, respectively, and the eighth-stage shift register SR[8] The clock signals CLK8 and CLK2 are received through the clock input terminals CK1 and CK2, respectively, and the ninth stage shift register SR[9] receives the clock signals CLK9 and CLK3 through the clock input terminals CK1 and CK2, respectively. The bit register SR[10] receives the clock signals CLK10 and CLK4 through the clock input terminals CK1 and CK2, respectively, and the eleventh level shift register SR[11] transmits the clock input terminals CK1 and CK2, respectively. Receiving the clock signals CLK11 and CLK5, the tenth-order second shift register SR[12] receives the clock signals CLK12 and CLK6 through the clock input terminals CK1 and CK2, respectively, wherein the twelve-stage shift register constitutes one The loop is preferred, and the loop can be repeated in subsequent shift registers.

As described above, the shift register circuit of the present invention can solve the pixel of the conventional technology regardless of the number of clock signals and how long the time interval length of the clock signal has a high voltage level is designed. There is a problem of insufficient charging time, and at the same time, there is no large current consumption in any operation stage of the shift register circuit.

The use of ordinal numbers such as "first," "second," etc. And only used as an identifier Differentiate between different components with the same name (with different ordinal numbers).

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

300‧‧‧Shift register

310‧‧‧Input stage circuit

320‧‧‧Output stage circuit

330‧‧‧Control circuit

340‧‧‧ Pulldown circuit

CK1, CK2‧‧‧ clock input

IN1, IN2‧‧‧ signal input

OUT‧‧‧ output

VH, VL‧‧‧ voltage

Claims (8)

A bidirectional shift register circuit for generating a plurality of gate drive signals, the bidirectional shift register circuit comprising a plurality of shift registers, and an Nth stage shift register of the shift registers The method includes: an input stage circuit coupled to a first signal input end and a second signal input end for receiving a first input signal and a second input signal, wherein the first input signal is a start pulse or The gate driving signal generated by the (N-1)th stage shift register, the second input signal is the gate driving signal generated by the (N+1)th stage shift register or a start pulse, wherein N is a positive integer greater than one; an output stage circuit coupled to a first clock input end and an output end, and coupled to the input stage circuit to a first control point and a first a second control point, configured to receive a first clock signal from the first clock input end, and according to one of the first control point, a first control voltage level and a second control voltage level of the second control point Outputting the gate drive signal to the output terminal, wherein the output stage circuit includes a first transistor And a second transistor, and a first capacitor and a second capacitor, the first transistor has a first end coupled to the first clock input terminal, and a gate terminal coupled to the first control point And a second end coupled to the output end, the second transistor has a first end coupled to the first clock input end, a gate end coupled to the second control point, and a second end coupling Connected to the output terminal, the first capacitor is coupled between the first control point and the output end, and the second capacitor is coupled between the second control point and the output end; a control circuit is coupled to the input stage circuit and the output stage circuit to the first control point and the second control point, and coupled to the input stage circuit to a third control point for controlling the first a control voltage level and the second control voltage level; and a pull-down circuit coupled to the output terminal and coupled to the control circuit to the third control point, wherein the bidirectional shift register circuit When operating in the forward scan, the shift registers sequentially output the corresponding gate drive signals in a first order, and when the bidirectional shift register circuit operates in the reverse scan, the shifts The register outputs the corresponding gate drive signal in a second order. The bidirectional shift register circuit of claim 1, wherein the input stage circuit comprises: a third transistor having a first end coupled to the first signal input end, and a gate extreme coupling Connected to the third control point, and a second end coupled to the first control point; and a fourth transistor having a first end coupled to the second signal input end and a gate terminal coupled to the The third control point and a second end are coupled to the second control point. The bidirectional shift register circuit of claim 1, wherein the pull-down circuit comprises: a fifth transistor having a first end coupled to the output end, and a gate terminal coupled to the first The three control points and a second end are coupled to a low operating voltage. The bidirectional shift register circuit of claim 1, wherein the control circuit comprises: a sixth transistor having a first end coupled to a high operating voltage, a gate terminal coupled to a second clock input terminal, and a second terminal coupled to the third control point; The transistor has a first end coupled to the third control point, and a gate terminal coupled to the first control point; an eighth transistor having a first end coupled to the third control point, And a gate electrode is coupled to the second control point; and a ninth transistor having a first end coupled to the second end of the seventh transistor and the second end of the eighth transistor, A gate is coupled to the first clock input terminal, and a second terminal is coupled to a low operating voltage. A display panel, wherein the display panel comprises: a pixel matrix comprising a plurality of pixels; a control chip for generating a complex clock signal and a start pulse; and a data driving circuit for generating a plurality of data driving signals to provide Data to the pixels; and a gate driving circuit for generating a plurality of gate driving signals for driving the pixels, wherein the gate driving circuit comprises a bidirectional shift register circuit, the bidirectional shifting The register circuit includes a plurality of shift registers, and the Nth stage shift register of the shift register includes: an input stage circuit coupled to a first signal input end and a second signal input end Receiving a first input signal and a second input signal, wherein the first input signal is the gate pulse generated by the start pulse or the (N-1)th stage shift register a driving signal, the second input signal being the gate driving signal generated by the (N+1)th stage shift register or the starting pulse, wherein N is a positive integer greater than one; an output stage circuit, The first clock input and the output are coupled to the first control point and the second control point for receiving a first time from the first clock input a clock signal, and outputting the gate drive signal to the output terminal according to a first control voltage level of the first control point and a second control voltage level of the second control point, wherein the output stage circuit comprises a first transistor and a second transistor, and a first capacitor and a second capacitor, the first transistor having a first end coupled to the first clock input terminal and a gate terminal coupled to the first transistor The first control point and the second end are coupled to the output end, the second transistor has a first end coupled to the first clock input terminal, a gate terminal coupled to the second control point, and a second end is coupled to the output end, the first capacitor is coupled to the first control point and the output end And the second capacitor is coupled between the second control point and the output end; a control circuit coupled to the input stage circuit and the output stage circuit to the first control point and the second control point And the input stage circuit is coupled to a third control point for controlling the first control voltage level and the second control voltage level; and a pull-down circuit coupled to the output end, and The control circuit is coupled to the third control point, wherein when the bidirectional shift register circuit operates in the forward scan, the shift registers sequentially output the corresponding gate drive in a first order Signal when the pair When the shift register circuit is operated in the reverse scan, the shift registers sequentially output the corresponding gate drive signals in a second order. The display panel of claim 5, wherein the input stage circuit comprises: a third transistor having a first end coupled to the first signal input end and a gate terminal coupled to the third a control point, and a second end coupled to the first control point; and a fourth transistor having a first end coupled to the second signal input end, a gate terminal coupled to the third control point And a second end coupled to the second control point. The display panel of claim 5, wherein the pull-down circuit comprises: a fifth transistor having a first end coupled to the output end, a gate terminal coupled to the third control point, and A second end is coupled to a low operating voltage. The display panel of claim 5, wherein the control circuit comprises: a sixth transistor having a first end coupled to a high operating voltage and a gate terminal coupled to a second clock input And a second end coupled to the third control point; a seventh transistor having a first end coupled to the third control point, and a gate terminal coupled to the first control point; An eighth transistor having a first end coupled to the third control point and a gate terminal coupled to the second control point; a ninth transistor having a first end coupled to a second end of the seventh transistor and a second end of the eighth transistor, a gate terminal coupled to the first clock input terminal, And a second end coupled to a low operating voltage.