TWI721935B - Driving signal generator - Google Patents

Abstract

A driving signal generator is provided. The driving signal generator includes a first stage generation circuit of emission signal, a second stage generation circuit of emission signal and a third stage generation circuit of emission signal. The first stage generation circuit of emission signal generates a first stage emission signal according to a former stage emission signal, a first clock signal and a third clock signal. The second stage generation circuit of emission signal generates a second stage emission signal according to the first stage emission signal, a second clock signal and the first clock signal. The third stage generation circuit of emission signal generates a third stage emission signal according to the second stage emission signal, a third clock signal and the second clock signal. In addition, the first clock signal, the second clock signal and the third clock signal are sequentially switched to a first voltage level.

Description

Drive signal generator

The present invention relates to a driving signal generator, and more particularly to a driving signal generator that can drive pixel circuits in a display panel with a smaller number of clock signals.

In the prior art, in order to drive the pixel circuits in the display panel, the driving signal generator requires a larger number of clock signals to correctly drive the pixel circuits in the display panel to perform display operations. In this way, the added clock signal in the driving signal generator not only increases the circuit area and design complexity, but also increases the power consumption of the display panel.

The present invention provides a driving signal generator, which can effectively reduce the number of clock signals required for driving pixel circuits in a display panel, thereby reducing the complexity of hardware design and the power consumption of the display panel.

The present invention provides a driving signal generator, which includes a first-level laser signal generating circuit, a second-level laser signal generating circuit, and a third-level laser signal generating circuit. When the first clock signal is at the first voltage level, the first-level laser signal generating circuit outputs the first-level laser signal according to the previous laser signal, and when the first clock signal is at the second voltage level, the first-level laser signal The first-level laser signal generating circuit maintains the voltage level of the first-level laser signal through the third clock signal. When the second clock signal is at the first voltage level, the second-level laser signal generating circuit outputs the second-level laser signal according to the first-level laser signal, and when the second clock signal is at the second voltage level, the second-level laser signal The second-level laser signal generating circuit maintains the voltage level of the second-level laser signal through the first clock signal. When the third clock signal is at the first voltage level, the third-level laser signal generating circuit outputs the third-level laser signal according to the second-level laser signal, and when the third clock signal is at the second voltage level, the third-level laser signal The third-level laser signal generating circuit maintains the voltage level of the third-level laser signal through the second clock signal. The first clock signal, the second clock signal, and the third clock signal are sequentially switched to the first voltage level.

The present invention also provides a driving signal generator, which includes a first-stage scanning signal generating circuit, a second-stage scanning signal generating circuit, and a third-stage scanning signal generating circuit. When the current level scan signal is at the first voltage level, the first level scan signal generating circuit outputs the first level scan signal according to the second clock signal, and when the current level scan signal is at the second voltage level, the first level scan signal The generating circuit maintains the voltage level of the first-level scanning signal through the third clock signal. When the first level scan signal is at the first voltage level, the second level scan signal generating circuit outputs the second level scan signal according to the third clock signal, and when the first level scan signal is at the second voltage level, the second level scan signal The second-level scan signal generating circuit maintains the voltage level of the second-level scan signal through the first clock signal. When the second-level scan signal is at the first voltage level, the third-level scan signal generating circuit outputs the third-level scan signal according to the first clock signal, and when the second-level scan signal is at the second voltage level, the third-level scan signal The three-level scanning signal generating circuit maintains the voltage level of the third-level scanning signal through the second clock signal. The first clock signal, the second clock signal, and the third clock signal are sequentially switched to the first voltage level.

Based on the above, the embodiment of the present invention can effectively reduce the number of clock signals required to drive the pixel circuits in the display panel by driving the signal generator, thereby reducing the complexity of hardware design and the power consumption of the display panel.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Please refer to FIG. 1, which is a schematic diagram of a driving signal generator 1 according to an embodiment of the present invention. The driving signal generator 1 is adapted to provide a driving signal to the display panel to drive the pixel circuit in the display panel. Among them, the pixel circuit in the display panel is driven by sequentially enabling (Enable) laser signals to perform display actions and display images on the display panel. Therefore, the driving signal generator 1 of the present invention is adapted to generate sequentially enabled laser signals EM1, EM2, and EM3 by receiving clock signals CK1, CK2, CK3 that are sequentially enabled and the enabling time does not overlap with each other. The pixel circuit in the display panel is driven to perform the display operation.

As shown in FIG. 1, the driving signal generator 1 includes laser signal generating circuits 10, 11, and 12 connected in series. The laser signal generating circuit 10 receives the previous laser signal EM0 and the clock signals CK1 and CK3 to generate the laser signal EM1. The laser signal generating circuit 11 receives the laser signal EM0 and the clock signals CK2 and CK1 to generate the laser signal EM2. The laser signal generating circuit 12 receives the laser signal EM2 and the clock signals CK3 and CK2 to generate the laser signal EM3.

For the detailed structure of the laser signal generating circuit 10/11/12, please refer to FIG. 2. FIG. 2 is a schematic diagram of the laser signal generating circuit 10/11/12 according to an embodiment of the present invention. As shown in FIG. 2, the laser signal generating circuit 10/11/12 includes a transistor M11, a pull-up circuit PU1, and a pull-down circuit PD1. One end (such as the source) of the transistor M11 receives one of the pre-stage laser signal EM0, laser signals EM1 and EM2 (the transistor M11 in the laser signal generating circuit 10 receives the pre-stage laser signal EM0, and the laser signal generating circuit 11 The transistor M11 receives the pre-stage laser signal EM1, the transistor M11 in the laser signal generating circuit 12 receives the pre-stage laser signal EM2, and so on), one end (for example, the drain) of the transistor M11 is coupled to the node N11, The control terminal (such as the gate) of the crystal M11 receives one of the clock signals CK1, CK2, CK3. The pull-up circuit PU1 is coupled between the node N11 and the laser output node NO_EM, and receives the pre-laser signal EM0, one of the laser signals EM1, EM2, and one of the clock signals CK1, CK2, CK3 to provide Voltage level Vref2 to laser output point NO_EM. The pull-down circuit PD1 is coupled between the node N11 and the laser output node NO_EM, and receives one of the clock signals CK3, CK1, CK2 to provide the voltage level Vref1 to the laser output node NO_EM. The laser signal generating circuit 10/11/12 outputs one of the laser signals EM1, EM2, EM3 through the laser output node NO_EM.

In one embodiment, the pull-up circuit PU1 includes transistors M12 to M16 and a capacitor C11. One end (such as the drain) of the transistor M12 is coupled to the node N12, one end (such as the source) of the transistor M12 receives the voltage level Vref2, and the control end (such as the gate) of the transistor M12 receives the previous laser signal EM0, One of the laser signals EM1 and EM2. One end of the capacitor C11 receives one of the clock signals CK1, CK2, CK3, and the other end is coupled to the node N12. One end (such as the drain) of the transistor M13 is coupled to the node N13, one end (such as the source) of the transistor M13 receives the voltage level Vref2, and the control end (such as the gate) of the transistor M13 is coupled to the node N11. One end (such as the drain) of the transistor M14 receives the voltage level Vref1, one end (such as the source) of the transistor M14 is coupled to the node N13, and the control end (such as the gate) of the transistor M14 is coupled to the node N12. One end (such as the drain) of the transistor M15 is coupled to the node N11, one end (such as the source) of the transistor M15 receives the voltage level Vref2, and the control end (such as the gate) of the transistor M15 is coupled to the node N13. One end (such as the drain) of the transistor M16 is coupled to the laser output node NO_EM, one end (such as the source) of the transistor M16 receives the voltage level Vref2, and the control terminal (such as the gate) of the transistor M16 is coupled to the node N13 .

In one embodiment, the pull-down circuit PD1 includes a transistor M17 and a capacitor C12. One end (such as the drain) of the transistor M17 receives the voltage level Vref1, one end (such as the source) of the transistor M17 is coupled to the laser output node NO_EM, and the control end (such as the gate) of the transistor M16 is coupled to the node N11 . One end of the capacitor C12 receives one of the clock signals CK3, CK1, CK2, and the other end is coupled to the node N11.

Please refer to FIG. 3, which is a schematic diagram of the operation waveform of the laser signal generating circuit 10 according to the embodiment of the present invention. Since the laser signal generating circuit 10/11/12 has a similar structure, the present invention then focuses on the operation of the laser signal generating circuit 10 to better describe the operation of the laser signal generating circuit 10/11/12. In this embodiment, the laser signal generating circuit 10 receives the previous laser signal EM0 and the clock signals CK1 and CK3 to output the laser signal EM1. The voltage level Vref1 is the ground voltage level, and the voltage level Vref2 is the working voltage level. The voltage level Vref1 is lower than the voltage level Vref2. Transistors M11～M17 are P-Type Metal-Oxide-Semiconductor Field-Effect Transistor (PMOSFET).

As shown in FIG. 3, when the laser signal generating circuit 10 operates in the time interval T10, the previous laser signal EM0 is at the voltage level Vref2, the clock signal CK1 is at the voltage level Vref2, and the clock signal CK3 is at the voltage level Vref1. . The voltage of the node N11 is coupled to the clock signal CK3 through the capacitor C12, and is pulled down below the voltage level Vref1, thereby enabling the pull-down circuit PD1. Therefore, in the time interval T10, the laser signal generating circuit 10 maintains the voltage of the laser output node NO_EM at the voltage level Vref1 through the clock signal CK3.

When the laser signal generating circuit 10 operates in the time interval T11, the clock signal CK1 is switched from the voltage level Vref2 to the voltage level Vref1, and the clock signal CK3 is switched from the voltage level Vref1 to the voltage level Vref2. The voltage of the node N11 transmits the pre-laser signal EM0 through the transistor M11, which will be pulled up to the voltage level Vref2, and the pull-down circuit PD1 is disabled. The voltage of the node N12 is coupled to the clock signal CK1 through the capacitor C11, and is pulled down to the voltage level Vref1. The voltage of the node N13 provides a voltage level Vref1 through the transistor M14, and is pulled down to the voltage level Vref1, thereby enabling the pull-up circuit PU1. Therefore, in the time interval T11, the laser signal generating circuit 10 provides the voltage level Vref2 to the laser output node NO_EM through the clock signal CK1.

When the laser signal generating circuit 10 operates in the time interval T12, the clock signal CK1 is switched from the voltage level Vref2 to the voltage level Vref1. The voltage of the node N12 can be coupled to the clock signal CK1 through the capacitor C11, and it will be pulled up to the voltage level Vref2. Therefore, in the time interval T12, the laser signal generating circuit 10 stores the data disable pull-down circuit PD1 of the previous laser signal EM0 through the capacitor C12, and provides the voltage level Vref2 to the laser output node NO_EM through the pull-up circuit PU1.

When the laser signal generating circuit 10 operates in the time interval T13, the previous laser signal EM0 is switched from the voltage level Vref2 to the voltage level Vref1, and the clock signal CK3 is switched from the voltage level Vref2 to the voltage level Vref1. Although the voltage of the node N11 is coupled to the clock signal CK3 through the capacitor C12 and will be pulled down slightly below the voltage level Vref2, the voltage of the node N11 can still disable the pull-down circuit PD1. Therefore, in the time interval T13, the laser signal generating circuit 10 can enable the pull-up circuit PU1 through the clock signal CK3 to maintain the voltage of the laser output node NO_EM at the voltage level Vref2.

When the laser signal generating circuit 10 operates in the time interval T14, the clock signal CK1 is switched from the voltage level Vref2 to the voltage level Vref1, and the clock signal CK3 is switched from the voltage level Vref1 to the voltage level Vref2. The voltage of the node N11 transmits the pre-laser signal EM0 through the transistor M11, and is pulled down to the voltage level Vref2, thereby enabling the pull-down circuit PD1. The voltage of the node N13 can be pulled up to the voltage level Vref2 through the transistor M13, thereby disabling the pull-up circuit PU1. Therefore, in the time interval T14, the laser signal generating circuit 10 can output the voltage level Vref1 through the previous laser signal EM0.

Therefore, the laser signal generating circuits 10, 11, and 12 connected in series in the driving signal generator 1 of the present invention can generate sequentially enabled laser signals EM1 to EM3 according to the preceding laser signal EM0 and the clock signals CK1 to CK3. In this way, the driving signal generator 1 of the present invention requires only a small number of clock signals, thereby effectively reducing the complexity of hardware design and the power consumption of the display panel.

Please refer to FIG. 4, which is a schematic diagram of a driving signal generator 2 according to an embodiment of the present invention. As shown in FIG. 4, the driving signal generator 2 is similar to the driving signal generator 1 shown in FIG. 1. The details of the laser signal generating circuits 10, 11, and 12 have been detailed in the previous relevant paragraphs, and will not be repeated here. . The difference between the driving signal generator 2 and the driving signal generator 1 is that the driving signal generator 2 additionally has scanning signal generating circuits 20, 21, and 22. The scanning signal generating circuits 20, 21, 22 of the driving signal generator 2 can generate the scanning signals SC1, SC2, SC3 according to the previous scanning signal SC0 and the clock signals CK1, CK2, CK3. Therefore, the driving signal generator 2 of the present invention can cooperate with the display actions of the laser signals EM1, EM2, and EM3 to drive the pixel circuits in the display panel to write display data.

For the detailed structure of the scanning signal generating circuit 20/21/22, please refer to FIG. 5, which is a schematic diagram of the scanning signal generating circuit 20/21/22 according to an embodiment of the present invention. As shown in FIG. 5, the scanning signal generating circuit 20/21/22 includes a transistor M21, a pull-up circuit PU2, and a pull-down circuit PD2. One end (such as the source) of the transistor M21 receives one of the previous scan signal SC0, the scan signal SC1, and the scan signal SC2 (the transistor M21 in the scan signal generating circuit 20 receives the previous scan signal SC0, and the scan signal generating circuit The transistor M21 in 21 receives the previous scan signal SC1, the transistor M21 in the scan signal generating circuit 22 receives the previous scan signal SC2, and so on), and one end (for example, the drain) of the transistor M21 is coupled to the node N21 , The control end (for example, the gate) of the transistor M21 is coupled to one end (for example, the source) of the transistor M21. The pull-up circuit PU2 is coupled between the node N21 and the scan output node NO_SC. The pull-down circuit is coupled between the node N21 and the scan output node NO_SC. The scan signal generating circuit 20/21/22 outputs one of the scan signals SC1, SC2, SC3 through the scan output node NO_SC.

In one embodiment, the pull-up circuit PU2 includes transistors M22 to M25 and a capacitor C21. One end (for example, drain) of transistor M22 is coupled to node N22, one end (for example, source) of transistor M22 receives voltage level Vref2, and the control end (for example, gate) of transistor M22 is coupled to node N21. One end (such as the drain) of the transistor M23 receives one of the clock signals CK3, CK1, CK2, one end (such as the source) of the transistor M23 is coupled to the node N22, and the control terminal (such as the gate) of the transistor M23 ) Is coupled to one end (for example, the drain) of the transistor M23. One end of the capacitor C21 is coupled to the node N22, and the other end receives the voltage level Vref2. One end (for example, the drain) of the transistor M24 is coupled to the node N21, one end (for example, the source) of the transistor M24 receives the voltage level Vref2, and the control end (for example, the gate) of the transistor M24 is coupled to the node N22. One end (such as the drain) of the transistor M25 is coupled to the scan output node NO_SC, one end (such as the source) of the transistor M25 receives the voltage level Vref2, and the control terminal (such as the gate) of the transistor M25 is coupled to the node N22 .

In one embodiment, the pull-down circuit PD2 includes a transistor M26. One end (for example, the drain) of the transistor M26 receives one of the clock signals CK2, CK3, CK1, one end (for example, the source) of the transistor M26 is coupled to the scan output node NO_SC, and the control end (for example, The gate) is coupled to the node N21.

Please refer to FIG. 6, which is a schematic diagram of the operation waveform of the scanning signal generating circuit 20 according to an embodiment of the present invention. Since the scanning signal generating circuit 20/21/22 has a similar structure, the present invention then focuses on the operation of the scanning signal generating circuit 20 to better describe the operation of the scanning signal generating circuit 20. In this embodiment, the scan signal generating circuit 20 receives the previous scan signal SC0 and the clock signals CK1 and CK2 to output the scan signal SC1. The voltage level Vref1 is the ground voltage level, the voltage level Vref2 is the working voltage level, and the voltage level Vref1 is lower than the voltage level Vref2. Transistors M21～M26 are P-type metal oxide half field effect transistors.

As shown in FIG. 6, when the scan signal generating circuit 20 operates in the time interval T20, the previous scan signal SC0 is at the voltage level Vref2, and the pull-down circuit PD2 is disabled. The clock signal CK3 is at the voltage level Vref1, thus enabling the pull-up circuit PU2. Therefore, in the time interval T20, the scan signal generating circuit 20 provides the voltage level Vref2 to the scan output node NO_SC through the clock signal CK3.

When the scan signal generating circuit 20 operates in the time interval T21, the previous scan signal SC0 is switched from the voltage level Vref2 to the voltage level Vref1, thereby enabling the pull-down circuit PD2. The clock signal CK3 is switched from the voltage level Vref1 to the voltage level Vref2, and thus the pull-up circuit PU2 is disabled. Therefore, in the time interval T21, the scan signal generating circuit 20 outputs the clock signal CK2 to the scan output node NO_SC through the previous scan signal SC0.

When the scan signal generating circuit 20 operates in the time interval T22, the previous scan signal SC0 is switched from the voltage level Vref1 to the voltage level Vref2, and the voltage of the node N21 is coupled to the clock signal CK2 through the parasitic capacitance of the transistor M26. It is pulled down to slightly lower than the voltage level Vref1, thus enabling the pull-down circuit PD2. Therefore, in the time interval T22, the scan signal generating circuit 20 enables the pull-down circuit PD2 through the clock signal CK2 and the clock signal CK3 disables the pull-up circuit PU2 to maintain the scan output node NO_SC at the voltage level Vref1.

When the scanning signal generating circuit 20 operates in the time interval T23, the clock signal CK3 is switched from the voltage level Vref2 to the voltage level Vref1, and the transistor M23 is enabled. The voltage of the node N22 will be pulled down to the voltage level Vref1, enabling the transistors M24 and M25. Therefore, in the time interval T23, the scan signal generating circuit 20 disables the pull-down circuit PD2 through the clock signal CK3 and provides the voltage level Vref2 to the scan output node NO_SC.

When the scanning signal generating circuit 20 operates in the time interval T24, the clock signal CK3 is switched from the voltage level Vref1 to the voltage level Vref2, and the pull-up circuit PU2 maintains the enabling transistors M24 and M25 according to the capacitor C21. Therefore, in the time interval T24, the scan signal generating circuit 20 provides the voltage level Vref2 to the scan output node NO_SC.

Therefore, the scan signal generating circuits 20, 21, and 22 connected in series in the driving signal generator 2 of the present invention can generate sequentially enabled scan signals SC1 to SC3 according to the previous scan signal SC0 and the clock signals CK1 to CK3. It can cooperate with the display actions of the laser signals EM1, EM2, EM3 to drive the pixel circuits in the display panel to write display data. In this way, the driving signal generator 2 of the present invention requires only a small number of clock signals, thereby effectively reducing the complexity of hardware design and the power consumption of the display panel.

It should be noted that the foregoing embodiments are used to illustrate the concept of the present invention, and those with ordinary knowledge in the art can make different modifications accordingly, and are not limited thereto. For example, the transistor in the driving signal generator 2 is not limited to a P-type MOSFET, but can also be an N-type MOSFET. In one embodiment, all the transistors in the driving signal generator 2 are N-type MOSFETs, the voltage level Vref1 is the working voltage level, the voltage level Vref2 is the ground voltage level, and the voltage level Vref1 Higher than the voltage level Vref2.

In summary, the drive signal generator of the present invention only needs three clock signals that are sequentially enabled and the enabling time does not overlap each other, and can generate sequentially enabled laser signals and scanning signals to drive the display panel Pixel circuit. Therefore, the driving signal generator of the present invention can only require a small number of clock signals, thereby effectively reducing the complexity of hardware design and the power consumption of the display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

1, 2: Drive signal generator 10～12: Laser signal generating circuit 20～22: Scanning signal generating circuit C11, C12, C21: Capacitor CK1～CK3: Clock signal EM0: Pre-level laser signal EM1～EM3: Laser signal M11～M17, M21～M26: Transistor N11～N13, N21, N22: Node NO_EM: Laser output node NO_SC: Scan output node SC0: pre-scan signal SC1～SC3: Scan signal T10～T14, T20～T24: time interval PD1, PD2: pull-down circuit PU1, PU2: pull-up circuit Vref1, Vref2: voltage level

FIG. 1 is a schematic diagram of a driving signal generator according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a laser signal generating circuit according to an embodiment of the present invention. 3 is a schematic diagram of the operation waveform of the laser signal generating circuit according to the embodiment of the present invention. FIG. 4 is a schematic diagram of a driving signal generator according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a scanning signal generating circuit according to an embodiment of the present invention. FIG. 6 is a schematic diagram of the operation waveform of the scanning signal generating circuit according to the embodiment of the present invention.

2: Drive signal generator

10~12: Laser signal generating circuit

20~22: Scanning signal generating circuit

CK1~CK3: Clock signal

EM0: Pre-level laser signal

EM1~EM3: Laser signal

SC0: pre-scan signal

SC1~SC3: Scan signal

Claims (7)

A drive signal generator includes: A first-stage scan signal generating circuit, when a previous-stage scan signal is at a first voltage level, a first-stage scan signal is output according to a second clock signal, and when the previous-stage scan signal is at a second voltage Maintain the voltage level of the first-level scanning signal through a third clock signal at the level; A second-level scan signal generating circuit, when the first-level scan signal is at the first voltage level, outputs a second-level scan signal according to the third clock signal, and when the first-level scan signal is at the first voltage level Maintain the voltage level of the second-level scanning signal through a first clock signal when the voltage levels are two; and A third-level scan signal generating circuit, when the second-level scan signal is at the first voltage level, a third-level scan signal is output according to the first clock signal, and when the second-level scan signal is at the first voltage level At the second voltage level, the voltage level of the third level scanning signal is maintained through the second clock signal, The first clock signal, the second clock signal, and the third clock signal are sequentially switched to the first voltage level. The driving signal generator according to claim 1, wherein the time intervals during which the first clock signal, the second clock signal, and the third clock signal are equal to the first voltage level do not overlap. The driving signal generator according to claim 1, wherein one of the first-stage scanning signal generating circuit, the second-stage scanning signal generating circuit, or the third-stage scanning signal generating circuit includes: A first transistor, the first end of the first transistor receives the previous scan signal, the first scan signal or the second scan signal, and the second end of the first transistor is coupled to a first scan signal A node, the control terminal of the first transistor is coupled to the first terminal of the first transistor; A first pull-up circuit, coupled between the first node and a scan output node, passes through one of the previous scan signal, the first scan signal, or the second scan signal, and the second scan signal One of a three-clock signal, the first clock signal, or the first clock signal to provide the second voltage level to the scan output node; and A first pull-down circuit is coupled between the first node and the scan output node, wherein when the first node is at the first voltage level, the first pull-down circuit generates the second clock signal , The third clock signal or the first clock signal is transmitted to the scan output node, The scan output node outputs the first level scan signal, the second level scan signal, or the third level scan signal. The driving signal generator according to claim 3, wherein the first pull-up circuit includes: A second transistor, the first terminal of the second transistor is coupled to a second node, the second terminal of the second transistor receives the second voltage level, and the control terminal of the second transistor is coupled At the first node; A third transistor, the first end of the third transistor receives the third clock signal, the first clock signal or the second clock signal, and the second end of the third transistor is coupled to the At the second node, the control terminal of the third transistor is coupled to the first terminal of the third transistor; A fourth transistor, the first terminal of the fourth transistor is coupled to the first node, the second terminal of the fourth transistor receives the second voltage level, and the control terminal of the fourth transistor is coupled At the second node; A fifth transistor, the first terminal of the fifth transistor is coupled to the scan output node, the second terminal of the fifth transistor receives the second voltage level, and the control terminal of the fifth transistor is coupled At the second node; and A first capacitor, the first terminal of the first capacitor is coupled to the second node, and the second terminal of the first capacitor receives the second voltage level. The driving signal generator according to claim 3, wherein the first pull-down circuit includes: A second transistor, the first end of the second transistor receives the second clock signal, the third clock signal or the first clock signal, and the second end of the second transistor is coupled to the Scan output node, the control terminal of the second transistor is coupled to the first node. The driving signal generator according to claim 1, wherein the first voltage level is lower than the second voltage level, and all transistors in the driving signal generator are P-type MOSFETs. The driving signal generator according to claim 1, wherein the first voltage level is higher than the second voltage level, and all transistors in the driving signal generator are N-type MOSFETs.

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