TWI564871B - Driver and display apparatus - Google Patents

Description

Driver and display device

The present invention relates to a driver and a display device, and more particularly to a driver and display device having a pull-down unit.

Generally, a liquid crystal display device includes a plurality of pixel units, a gate driving circuit, and a source driving circuit. The source driving circuit is used to provide a plurality of data voltage signals. The gate drive circuit includes a multi-stage shift register circuit for providing a plurality of gate signals. The gate signal is used to control the on and off of the pixel transistor in the pixel unit, thereby controlling the data signal to be written to the pixel unit.

The output transistors in each stage of the shift register circuit are controlled by the operating voltage and sequentially output the gate driving signals. However, with the development of the touch panel technology, the touch circuit needs to temporarily interrupt the output of a certain level (or multi-level) gate driving signal for touch detection (for example, determining whether a finger or a charged object slides on the display panel) Or stay). During the period in which the gate drive signal is interrupted, the output transistor in the interrupt register circuit interrupted by the stage will continue to be affected by the high logic level bias of the operating voltage, thus causing the output transistor to age and Decreased charging capability may also cause the pixel transistor to be accidentally turned on or leaked, or cause the driving circuit to operate abnormally.

One aspect of the present invention is to provide a driver. The driver includes a plurality of stages of shift register circuits for outputting the sequential complex drive signals. Each stage in the shift register circuit includes an output unit and a pull-down unit. The output unit is controlled by the voltage of the operating node to generate a corresponding driving signal in the driving signal according to the timing signal at the output end of the output unit. The pull-down unit is electrically coupled to the output unit at the operating node, and is configured to receive a touch enable signal that enables the touch circuit, and is enabled by the touch enable signal to pull down the voltage level of the operating node. Reference voltage level.

Another aspect of the present invention is to provide a driver. The driver includes a plurality of stages of shift register circuits for outputting the sequential complex drive signals. Wherein each stage of the shift register circuit comprises a first transistor and a second transistor. The control terminal of the first transistor is electrically coupled to the operating node. The first end of the first transistor is configured to receive the timing signal, and the second end of the first transistor is configured to generate a corresponding driving signal in the driving signal. The control end of the second transistor is configured to receive a touch enable signal for enabling the touch circuit, and the first end of the second transistor is electrically coupled to the control end of the first transistor, and the second transistor is The two ends are used to receive the reference voltage.

Another aspect of the present invention is to provide a display device. The display device contains a drive. The driver includes a complex stage shift register circuit. Each stage in the shift register circuit includes a drive signal generating circuit, a first transistor, and a second transistor. The driving signal generating circuit has an output for generating a driving signal at the output end. The control end of the first transistor is configured to receive a touch enable signal that enables the touch circuit. The first end of the first transistor is electrically coupled to the driving signal The circuit is generated at the operational node. The second end of the first transistor is configured to receive a reference voltage. The control end of the second transistor is configured to receive the touch enable signal. The first end of the second transistor is electrically coupled to the output end of the driving signal generating circuit. The second end of the second transistor is configured to receive a reference voltage.

In summary, by adding a pull-down unit to the shift register circuit and pulling the voltage level of the operating node to the reference voltage level according to the touch enable signal enable, the output unit can be avoided at the gate. During the period in which the driving signal is interrupted, the operating voltage is continuously affected by the operating logic high logic level bias, thereby preventing the output unit from aging and the charging capability from being lowered, further preventing the pixel transistor from being turned on or leaking and the operation of the driving circuit abnormally.

100‧‧‧ drive

110_(1)‧‧‧1st stage shift register circuit

110_(2)‧‧‧Level 2 shift register circuit

110_(n)‧‧‧n-level shift register circuit

110_(n+m)‧‧‧(n+m) level shift register circuit

200‧‧‧n-level shift register circuit unit

210‧‧‧Output unit

220‧‧‧Enable Control Unit

230‧‧‧ disable unit

240‧‧‧First disable control unit

250‧‧‧second disable control unit

400‧‧‧ display

410‧‧‧Touch circuit

600,1000,1100‧‧‧n-level shift register circuit

610‧‧‧ Pulldown circuit

611‧‧‧ Pulldown unit

612‧‧‧Control unit

TP_EN‧‧‧Touch enable signal

HC_(n-2)~HC_(n+2)‧‧‧ timing signals

G_(1)~G_(n+m)‧‧‧ drive signal

Q_(1)~Q_(n+m)‧‧‧Operation signal

Np, Nq‧‧‧ nodes

SCL, ST_(n-2)~ST_(n+2)‧‧‧ control signals

H_END‧‧‧First control signal

H_ST‧‧‧Second control signal

VSS, VSS_G, VSS_Q‧‧‧ reference voltage level

LC1‧‧‧first logic level signal

LC2‧‧‧second logic level signal

TR1~TR6, M1~M5‧‧‧O crystal

T1~t6, t1’~t4’‧‧‧ time

C, C1‧‧‧ capacitor

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; 2 is a schematic diagram of an nth stage shift register circuit unit according to an embodiment of the present disclosure; and FIG. 3 is a timing diagram of signals on the shift register circuit according to FIG. 2; 4 is a schematic diagram of a display device according to an embodiment of the present disclosure; FIG. 5 is a timing diagram of signals according to the display device in FIG. 4; and FIG. 6 is a diagram of implementation according to one of the disclosures. A schematic diagram of an nth stage shift register circuit in an example; 7 is a timing diagram of signals according to the shift register circuit in FIG. 6; and FIG. 8 is a schematic diagram showing operation in the period t1'~t2' according to the pull-down circuit of FIG. 7; FIG. FIG. 10 is a schematic diagram showing an operation of the n-th stage shift register circuit according to an embodiment of the present disclosure; and FIG. 10 is a schematic diagram showing an operation of the pull-down circuit according to FIG. 7 in a period t2′~t3′; 11 is a schematic diagram of an nth stage shift register circuit in accordance with an embodiment of the present disclosure.

The following disclosure provides many different embodiments or illustrations for implementing different features of the invention. The elements and configurations of the specific illustrations are used in the following discussion to simplify the disclosure. Any examples discussed are for illustrative purposes only and are not intended to limit the scope and meaning of the invention or its examples. In addition, the present disclosure may repeatedly recite numerical symbols and/or letters in different examples, which are for simplicity and elaboration, and do not specify the relationship between the various embodiments and/or configurations in the following discussion.

The terms used in the entire specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, the content disclosed herein, and the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

Regarding the "coupling" or "connection" used in this article, It can be noted that two or more elements are directly in physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "coupled" or "connected" may also mean that two or more element elements operate or act in each other. The use of the terms first, second, and third, etc., is used to describe various elements, components, regions, layers and/or blocks. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to identify a single element, component, region, layer, and/or block. Thus, a singular element, component, region, layer and/or block may be referred to as a second element, component, region, layer and/or block, without departing from the spirit of the invention. As used herein, the term "and/or" encompasses any combination of one or more of the listed associated items.

FIG. 1 is a schematic diagram of a driver 100 in accordance with an embodiment of the present disclosure. The driver 100 includes a first stage shift register circuit 110_(1), a second stage shift register circuit 110_(2), ..., an nth stage shift register circuit 110_(n), ..., (n+m) stage shift register circuit 110_(n+m), where n and m are natural numbers. Each stage shift register circuit 110_(1)~110_(n+m) is used to generate sequential drive signals G_(1)~G_(n+m), and each stage shift register circuit 110_(1) The ~110_(n+m) has a corresponding circuit structure, and the shift register circuits 110_(1)~110_(n+m) of each stage are electrically coupled in sequence to transmit necessary signals. The specific circuit and signal transmission mode are represented by the subsequent n-level shift register circuit. Each of the driving signals G_(1)~G_(n+m) can be respectively transmitted to a pixel array (not shown) via a scan line (not shown) connected to the driver 100, and used for A pixel transistor (not shown) connected to the scan line is sequentially turned on, thereby controlling A pixel unit in a pixel array (not shown).

Please refer to FIG. 2 and FIG. 3 together. FIG. 2 is a schematic diagram of an n-th stage shift register circuit unit 200 according to an embodiment of the present disclosure. FIG. 3 is a timing diagram of signals on the shift register circuit unit 200 according to FIG. 2. The shift register circuit unit 200 can be applied to the nth stage shift register circuit 110_(n) in FIG. The nth stage shift register circuit unit 200 includes an output unit 210, an enable control unit 220, a disable unit 230, a first disable control unit 240, and a second disable control unit 250. The output unit 210 is configured to be enabled by the nth operation signal Q_(n), and generate the nth driving signal G_(n) according to the received timing signal HC_(n), and transmit to the corresponding pixel transistor (not As shown in the figure, the pixel transistor is turned on so that the corresponding pixel unit (not shown) receives the data voltage.

Referring to FIG. 3 together, the enabling control unit 220 can generate the nth operating signal Q_(n) according to the signal generated by the previous stages of the shift register circuit (not shown) (eg, at t2) In the ~t3 sequence, the timing signal HC_(n-2), the (n-2)th operation signal Q_(n-2), and the (n-2)th stage drive signal G_(n-2) are pulled up to the nth stage. The operation signal Q_(n) to the enable level), and the coupling effect of the capacitor C is matched with the timing signal HC_(n) to pull up the voltage level of the nth operation signal Q_(n) in the timing of t3~t4. Exceeding the enable level (about twice the high logic level), thereby increasing the driving capability of the output unit 210, so that the output unit 210 generates the nth stage driving signal G_(n) according to the timing signal HC_(n). It should be noted that, in this embodiment, the order in which the driving signals are sequentially generated from each other is an interval of two levels, for example, sequentially generating the first-level driving signal G_(1) and the third-level driving signal G_(3). ), the fifth level drive signal G_(5), or sequentially generate the second level drive signal G_(2), the fourth-level driving signal G_(4), and the sixth-level driving signal G_(6). However, the order in which the actual driving signals are sequentially generated from each other may be any integer, and is not limit.

In addition, when the pixel transistor is to be turned off, the nth stage shift register circuit unit 200 operates the nth stage through the disable unit 230, the first disable control unit 240, and the second disable control unit 250. The voltage level of the signal Q_(n) and the nth stage driving signal G_(n) is converted and maintained at a low logic level (for example, the voltage level of the ground terminal).

Specifically, the disable unit 230, the first disable control unit 240, and the second disable control unit 250 can receive the reference voltage level VSS, and the reference voltage level VSS is at a low logic level. The disable unit 230 is enabled according to the control signal SCL, and pulls the voltage levels of the nth operation signal Q_(n) and the nth drive signal G_(n) to the reference voltage level VSS. In this architecture, the control signal SCL may be a signal generated by a subsequent stage of the shift register circuit (not shown) (for example, the (n+2)th stage drive signal G_(n+2)).

The first disable control unit 240 receives the first logic level signal LC1 and the nth level operation signal Q_(n), and the second disable control unit 250 receives the second logic level signal LC2 and the nth level operation signal Q_(n). ). The voltage levels of the first logic level signal LC1 and the second logic level signal LC2 are at a high logic level and are complementary to each other. When the nth operation signal Q_(n) is at the high logic level, the transistors TR3, TR4, TR5, and TR6 are turned off, and the first disable control unit 240 and the second disable control unit 250 are disabled. . When the nth operation signal Q_(n) is pulled down to the reference voltage level VSS (ie, low logic level) through the disable unit 230 at time t5, the first disable control unit 240 and the second The disable control unit 250 is enabled by the nth operation signal Q_(n), and is enabled in turn according to the first logic level signal LC1 and the second logic level signal LC2, respectively, and conducts the transistor TR3 and the transistor TR4. When the first logic level signal LC1 is a high logic level bias, the second logic level signal LC2 is a reference voltage level VSS (ie, a low logic level), and then the nth stage operation signal Q_(n) The voltage level of the nth stage driving signal G_(n) is maintained at the reference voltage level VSS.

FIG. 4 is a schematic diagram of a display device 400 in accordance with an embodiment of the present disclosure. The display device 400 includes a driver 100 and a touch circuit 410. The display device 400 can be a television screen, a computer screen, a mobile phone screen, a screen of a touch-type handheld device, and other display devices having display functions, and is not limited thereto. The driver 100, as shown in Fig. 1, includes shift register circuits 110_(1) to 110_(n+m). In this embodiment, the touch control circuit 120 is enabled by the touch enable signal TP_EN for touch detection (for example, determining whether a finger or a charged object slides or stays on the display panel). When the touch control circuit 120 performs touch detection, it is necessary to temporarily interrupt the output of a certain level (or multi-level) of the driving signal. For example, after the output of the driving signal G_(n), the driving signal G_(n+2) and the subsequent driving signal are temporarily stopped. The output of G_(n+4)~G_(n+m).

Fig. 5 is a timing chart showing signals according to the display device 400 in Fig. 4. It can be seen that after the output of the driving signal G_(5), the touch control circuit 120 is enabled for touch detection by the touch enable signal TP_EN, the driving signal G_(7) and the subsequent driving signal G_(9). )~G_(n+m) thus temporarily stops outputting. In addition, in the second stage of the shift register circuit, since the control signal SCL (ie, the drive signal G_(7)) has not been enabled, the disable unit 230 cannot operate the signal. The number Q_(5) is pulled down to the reference voltage level VSS, so that the operation signal Q_(5) is continuously maintained at a high logic level. That is, during the period in which the driving signal G_(7) is interrupted, the output unit 210 in the fifth-stage shift register circuit is continuously affected by the operating voltage high logic level bias, thus causing the The output unit 210 in the 5-stage shift register circuit is aged and the charging capability is lowered, which may also cause the pixel transistor to be accidentally turned on or leaked, or cause the driving circuit to operate abnormally.

FIG. 6 is a schematic diagram of an nth stage shift register circuit 600 in accordance with an embodiment of the present disclosure. The shift register circuit 600 includes the shift register circuit unit 200 and the pull-down circuit 610 shown in FIG. It should be added that the shift register circuit 600 is not limited to the shift register circuit unit 200 as shown in FIG. 2 in practical use. The pull-down circuit 610 includes a pull-down unit 611 and a control unit 612. The pull-down unit 611 includes a transistor M1 and a transistor M2. The transistor M1 is electrically coupled to the output node 210 and the transistor M2 is electrically coupled to the output unit 210 at the output terminal Nq. The transistors M1 and M2 are used. Receiving the touch enable signal TP_EN enabling the touch circuit 410 as shown in FIG. 4, and enabling the touch enable signal TP_EN to pull the voltage level of the operating node Np to the reference voltage level VSS ( That is, low logic level). The control unit 612 includes a transistor M3, a transistor M4, a transistor M5, and a capacitor C1. The first end of the transistor M3 is configured to receive the first control signal H_END, and the second end of the transistor M3 is electrically coupled to the operation node Np. The control terminal of the transistor M4 is configured to receive the driving signal G_(n-2) of the shift register circuit of the previous stage, and the first end of the transistor M4 is configured to receive the second control signal H_ST, and the second end of the transistor M4 Electrically coupled to the control terminal of the transistor M3. The control terminal of the transistor M5 is configured to receive the driving signal G_(n), and the first end of the transistor M5 is electrically coupled to the control terminal of the transistor M3. The second end of the crystal M5 is for receiving the reference voltage VSS. The first end of the capacitor C1 is electrically coupled to the control end of the transistor M3, and the second end of the capacitor C1 is used to receive the reference voltage VSS.

The output unit 210 has an output terminal Nq for generating a driving signal G_(n) at the output terminal Nq. The output unit 210 is controlled by the voltage Q_(n) of the operating node Np to generate the driving signal G_(n) at the output terminal Nq of the output unit 210 according to the timing signal (not shown). In this embodiment, when the touch control circuit 410 is enabled according to the touch enable signal TP_EN, the pull-down unit 611 is enabled to pull down the voltage Q_(n) of the operation node Np according to the touch enable signal TP_EN. To the reference voltage level VSS.

For example, please refer to Figure 7 and Figure 8 together. FIG. 7 is a timing diagram of signals according to the shift register circuit 600 in FIG. 6. Fig. 8 is a view showing the operation of the pull-down circuit 610 in the period t1'~t2' according to Fig. 7. It can be seen that the output of the driving signal G_(5) is completed at time t1, but since the touch circuit 410 is enabled according to the touch enable signal TP_EN during the period t1'~t2', the driving signal G_(7) Interrupted output. It should be noted that in this example, during the period t1'~t2', since the touch enable signal TP_EN also enables the transistor M1 and the transistor M2 in the pull-down unit 611, the voltage of the operation node Np Q_(5) And the voltage level of Q_(7) is pulled down to the reference voltage level VSS by the transistor M1 during the period t1'~t2'. In addition, the voltages G_(5) and G_(7) of the output terminal Nq of the output unit 210 are also pulled through the transistor M2 to the reference voltage level VSS during the period t1'~t2'. Thereby, the output unit 210 of the fifth-stage shift register circuit is prevented from being affected by the high logic level bias of the operating voltage Q_(5) during the period in which the driving signal G_(7) is interrupted, and the transmission is prevented. The aging of the unit 210 and the decrease in the charging capability further prevent the erroneous opening or leakage of the pixel transistor and the abnormal operation of the driving circuit. The driving signal G_(7) of the seventh-stage shift register circuit is interrupted as an example. In practical applications, the driving signal G_(n) of any one-stage shift register circuit can be interrupted, and the present disclosure does not This is limited.

Please refer to FIG. 9. FIG. 9 is a schematic diagram showing the operation of the pull-down circuit 610 in the period t2'~t3' according to FIG. As shown in FIG. 9, the touch enable signal TP_EN is switched from the enable level to the low logic level at time t2', that is, the touch circuit 410 is disabled at time t2'. It can be seen that the touch enable signal TP_EN also disables the transistor M1 and the transistor M2 in the pull-down unit 611 during the period t2'~t3', and the transistor M3 of the control unit 612 is used to touch After the control signal TP_EN is released, the voltage level of the operating node Np is pulled up to the operating voltage level according to the first control signal H_END. For example, the voltage level of the seventh stage operation signal Q_(7) in the period t2'~t3' is pulled up from the reference voltage level VSS to the operating voltage level.

It should be added that after the time t3', the touch enable signal TP_EN, the first control signal H_END and the second control signal H_ST are all disabled, so the pull-down circuit 610 has no pull-down voltage in the subsequent time. Therefore, each stage of the shift register circuit unit 200 returns to the original operation of sequentially outputting the drive signal G_(n). It can be seen that the driving signal G_(7) is output during the period t3'~t4', and the seventh-order operation signal Q_(7) is transmitted through the coupling effect of the capacitance C in the seventh-stage shift register circuit unit 200. The voltage level is pulled above the enable level (about twice the high logic level). In addition, since the disable unit 230 in the fifth stage shift register circuit unit 200 is based on the control signal SCL (herein The driving signal G_(7) is enabled, so the voltage levels of the fifth-level operation signal Q_(5) and the fifth-level driving signal G_(5) pass through the disable unit 230, the first disable control unit 240, and the second The disable control unit 250 is maintained at the reference voltage level VSS.

Please refer to FIG. 10 and FIG. 11 , which respectively illustrate schematic diagrams of an nth stage shift register circuit 1000 and an nth stage shift register circuit 1100 according to different embodiments of the present disclosure. As previously described, in practice the shift register circuit 600 is not limited to including the shift register circuit unit 200 as shown in FIG. 2, and may include any shift register circuit that outputs a drive signal. For example, shift register circuit 600 can include shift register circuit 1000 or shift register circuit 1100. The control signals ST_(n-2)~ST_(n+2) in the shift register circuit 1000 may be driving signals of a certain stage such as driving signals G_(n), G(n-2), and the reference voltage is Bits VSS_G and VSS_Q may be the same as the reference voltage level VSS or may be different stable voltage levels. The shift register circuit 1000 or the shift register circuit 1100 each include an output unit 210. Therefore, the output unit 210 can be electrically coupled to the output node 210 at the output node Nq and the transistor M2 via the transistor M1 in the pull-down unit 611, and can be enabled according to the touch enable signal TP_EN. The pull-down unit 611 pulls the voltage level of the operating node Np to the reference voltage level VSS (ie, a low logic level).

In summary, by adding a pull-down unit to the shift register circuit and pulling the voltage level of the operating node to the reference voltage level according to the touch enable signal enable, the output unit can be avoided at the gate. During the period in which the driving signal is interrupted, the operating voltage is constantly affected by the high logic level bias of the operating voltage, thereby preventing the output unit from aging and the charging capability from being lowered, thereby further preventing the pixel transistor from being turned on by mistake. Or leakage and abnormal operation of the drive circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

200‧‧‧n-level shift register circuit unit

600‧‧‧n-level shift register circuit

610‧‧‧ Pulldown circuit

611‧‧‧ Pulldown unit

612‧‧‧Control unit

TP_EN‧‧‧Touch enable signal

G_(n), G_(n-2)‧‧‧ drive signals

Np, Nq‧‧‧ nodes

H_END‧‧‧First control signal

H_ST‧‧‧Second control signal

VSS‧‧‧reference voltage level

M1~M5‧‧‧O crystal

C1‧‧‧ capacitor

Claims (12)

A driver for a display device, comprising: a plurality of shift register circuits for outputting a plurality of sequential drive signals, wherein each of the stages of the shift register circuit comprises: an output unit for Controlled by a voltage of an operating node, to generate a corresponding driving signal of the driving signals according to a timing signal at the output end of the output unit; a pull-down unit electrically coupled to the output unit at the operating node, And receiving a touch enable signal for enabling a touch circuit, wherein the touch enable signal is enabled to pull the voltage level of the operating node to a reference voltage level; and a control The unit is configured to pull the voltage level of the operating node to an operating voltage level according to a first control signal after the touch enable signal is released. The driver of claim 1, wherein the pull-down unit is further configured to enable the output of the output unit to be lowered to the reference voltage level by the touch enable signal. The driver of claim 1, wherein the pull-down unit is enabled by the touch enable signal during a period between two consecutive drive signals in the drive signals. The drive of claim 1, wherein the pull-down unit comprises: a first transistor, the control end of the first transistor is configured to receive the touch enable signal, the first end of the first transistor is electrically coupled to the operating node, and the second end of the first transistor Used to receive a reference voltage. The driver of claim 4, wherein the pull-down unit further comprises: a second transistor, the control end of the second transistor is configured to receive the touch enable signal, and the first end of the second transistor The output end of the output unit is electrically coupled to the second end of the second transistor for receiving the reference voltage. A driver for a display device, comprising: a plurality of shift register circuits for outputting a plurality of sequential drive signals, wherein each of the stages of the shift register circuits comprises: a first transistor, The control end of the first transistor is electrically coupled to an operating node, the first end of the first transistor is configured to receive a timing signal, and the second end of the first transistor is used to generate one of the driving signals Corresponding to the driving signal; a second transistor, the control end of the second transistor is configured to receive a touch enable signal for enabling a touch circuit, and the first end of the second transistor is electrically coupled a control terminal of the first transistor, the second end of the second transistor is configured to receive a reference voltage, and a control unit is configured to perform the operation according to a first control signal after the touch enable signal is released The voltage level of the node is pulled up to an operating voltage level. The driver of claim 6, wherein the control unit of each of the stages of the shift register circuit further comprises: a third transistor, the first end of the third transistor is configured to receive the first The second end of the third transistor is electrically coupled to the control end of the first transistor. The driver of claim 7, wherein each of the stages of the shift register circuit further comprises: a fourth transistor, wherein the control end of the fourth transistor is configured to receive the touch enable signal, The first end of the fourth transistor is electrically coupled to the second end of the first transistor, and the second end of the fourth transistor is configured to receive the reference voltage. The driver of claim 8, wherein the control unit of each of the stages of the shift register circuit further comprises: a fifth transistor, wherein the control end of the fifth transistor is electrically coupled to the first stage shift a second end of the first transistor of the bit register circuit, the first end of the fifth transistor is configured to receive a second control signal, and the second end of the fifth transistor is electrically coupled to the third end a control terminal of the transistor; a sixth transistor, the control terminal of the sixth transistor is electrically coupled to the second end of the first transistor, and the first end of the sixth transistor is electrically coupled to the third a control terminal of the transistor, the second end of the sixth transistor is configured to receive the reference voltage; and a capacitor, the first end of the capacitor is electrically coupled to the control end of the third transistor, and the second capacitor The terminal is configured to receive the reference voltage. A display device comprising: a driver comprising: a plurality of stages of shift register circuits, each of the stages of the shift register circuits comprising: a drive signal generating circuit having an output for The output terminal generates a driving signal, wherein the driving signal is used to drive the display device; and a first transistor, the control end of the first transistor is configured to receive a touch enable function for enabling a touch circuit The first end of the first transistor is electrically coupled to the driving signal generating circuit at an operating node, the second end of the first transistor is configured to receive a reference voltage, and a second transistor, the second The control end of the transistor is configured to receive the touch enable signal, the first end of the second transistor is electrically coupled to the output end of the drive signal generating circuit, and the second end of the second transistor is configured to receive And the control unit is configured to pull the voltage level of the operating node to an operating voltage level according to a first control signal after the touch enable signal is released. The display device of claim 10, wherein the control unit of each of the stages of the shift register circuit further comprises: a third transistor, the first end of the third transistor is configured to receive the first a control signal, the second end of the third transistor is electrically coupled to the operating node. The display device of claim 11, wherein the control unit of each of the stages of the shift register circuit further comprises: a fourth transistor, wherein the control end of the fourth transistor is electrically coupled to the front The output end of the driving signal generating circuit in the first-stage shift register circuit, the first end of the fourth transistor is configured to receive a second control signal, and the second end of the fourth transistor is electrically coupled to the a control terminal of the third transistor; a fifth transistor, the control terminal of the fifth transistor is electrically coupled to the output end of the driving signal generating circuit, and the first end of the fifth transistor is electrically coupled to the a control terminal of the third transistor, the second end of the fifth transistor is configured to receive the reference voltage; and a capacitor, the first end of the capacitor is electrically coupled to the control end of the third transistor, the capacitor The second end is configured to receive the reference voltage.