TW202036793A - Semiconducotr structure and method for fabricating the same - Google Patents

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the semiconductor structure. The method includes providing a substrate; forming a silicon layer on the substrate, wherein an edge region of a top surface of the substrate is exposed from the silicon layer; epitaxially growing a GaN-based semiconductor material on the silicon layer and the substrate to form a GaN-based semiconductor layer on the silicon layer and a plurality of GaN-based nodules on the edge region of the top surface of the substrate; and performing a first dry etch step to remove the GaN-based nodules, wherein performing the first dry etch step includes applying a first bias power that is equal to or higher than 1500 W.

Description

Semiconductor structure and manufacturing method thereof

The content of this disclosure is related to semiconductor manufacturing technology, and in particular to semiconductor structures with gallium nitride-based semiconductor materials and manufacturing methods thereof.

GaN-based semiconductor materials have many excellent material properties, such as high heat resistance, wide band-gap, and high electron saturation rate. Therefore, GaN-based semiconductor materials are suitable for high-speed and high-temperature operating environments. In recent years, GaN-based semiconductor materials have been widely used in light emitting diode (LED) devices and high-frequency devices, such as high electron mobility transistors (HEMTs) with heterogeneous interface structures. ).

With the development of gallium nitride-based semiconductor materials, these semiconductor structures using gallium nitride-based semiconductor materials are used in more severe working environments, such as higher frequency, higher temperature or higher voltage working environments. Therefore, the process conditions for semiconductor structures with gallium nitride-based semiconductor materials are also facing many new challenges.

Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure. The method includes providing a substrate; forming a silicon layer on the substrate, wherein the edge region of the upper surface of the substrate is exposed from the silicon layer; and gallium nitride (GaN- based) The semiconductor material is epitaxially grown on the silicon layer and the substrate to form a gallium nitride semiconductor layer on the silicon layer and a plurality of gallium nitride particles on the edge area of the upper surface of the substrate; and perform a first dry etching A step to remove these gallium nitride particles, wherein performing the first dry etching step includes applying a first bias power, and the first bias power is equal to or greater than 1500 watts.

Some embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes an aluminum nitride substrate, a silicon layer, and a gallium nitride semiconductor layer. The silicon layer is formed on the aluminum nitride substrate. The upper surface of the edge area of the aluminum nitride substrate is exposed from the silicon layer. The gallium nitride semiconductor layer is formed on the silicon layer. The angle between the sidewall and the bottom surface of the gallium nitride-based semiconductor layer is less than 90 degrees.

The semiconductor structure of the present disclosure can be applied to various types of semiconductor devices. In order to make the features and advantages of the present disclosure more obvious and understandable, the following examples are applied to high electron mobility transistors, together with the attached The diagram is described in detail as follows.

The following disclosure provides many embodiments or examples for implementing different elements of the provided semiconductor structure. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are only examples and are not intended to limit the embodiments of the disclosure. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the same or similar component numbers may be used repeatedly in different examples of the embodiments of the present disclosure. Such repetition is for conciseness and clarity, and is not used to express the relationship between the different embodiments discussed.

Some changes of the embodiment are described below. In the embodiments of different drawings and descriptions, similar component symbols are used to denote similar components. It is understood that additional steps may be provided before, during, and after the method, and some of the described steps may be substituted or deleted in other embodiments of the method.

The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. When GaN-based semiconductor materials are epitaxially grown on a silicon layer, GaN-based particles (nodule) attached to the substrate will also be formed, and these GaN-based particles are likely to be used in subsequent processes Falling off, thereby contaminating the subsequent manufacturing process, causes the gallium nitride-based particles to become a possible defect source in the manufacturing process of the semiconductor structure, but the gallium nitride-based particles cannot be effectively removed by wet etching. According to the embodiment of the present disclosure, the first dry etching step is performed with a bias power equal to or greater than 1500 watts, which can effectively remove the gallium nitride particles and prevent the gallium nitride particles from becoming a semiconductor structure during the process Therefore, the yield of the semiconductor structure can be improved.

FIGS. 1A to 1F are schematic cross-sectional views illustrating various stages of forming the semiconductor structure 100 shown in FIG. 1F according to some embodiments of the present disclosure. Please refer to Figure 1A to provide a base 102. The substrate 102 may be circular, and the diameter P of the substrate 102 may be 4 inches or more, such as 6 inches, 8 inches, or 12 inches, to be suitable for manufacturing equipment in the semiconductor industry.

In some embodiments, the substrate 102 is a ceramic substrate, and is formed by high temperature sintering of ceramic powder through powder metallurgy. For example, the substrate 102 is an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, a sapphire (Sapphire) substrate, a suitable similar substrate, or any combination of the foregoing. In one embodiment, the substrate 102 is an aluminum nitride substrate. In some embodiments, the substrate 102 is used to manufacture a semiconductor device containing a GaN-based semiconductor layer, such as a light-emitting diode (LED), a high-frequency device, or a high-voltage device. The high-frequency device or the high-voltage device can be, for example, a high electron mobility transistor (HEMT), a Schottky bipolar diode (SBD), a bipolar junction transistor (BJT), a junction field effect Junction field effect transistor (JFET) or insulated gate bipolar transistor (IGBT).

As shown in FIG. 1A, a silicon layer 104 is formed on the substrate 102, and the edge region 102P of the upper surface 102a of the substrate 102 is exposed from the silicon layer 104. In some embodiments, from the top view, the edge region 102P surrounds the silicon layer 104 (not shown). In some embodiments, as shown in FIG. 1A, the edge of the silicon layer 104 is separated from the edge of the substrate 102 by a distance D1, which is the width of the edge region 102P. In some embodiments, the distance D1 may be about 1.5 millimeters (mm) to about 3 millimeters, for example, about 2 millimeters. In some embodiments, the thickness of the silicon layer 104 is, for example, about 300 nanometers (nm) to about 600 nanometers.

As shown in FIG. 1B, a GaN-based semiconductor material is epitaxially grown on the silicon layer 104 and the substrate 102 to form a GaN-based semiconductor layer 106 on the silicon layer 140, and a plurality of nitrogen Gallium-based particles (nodules) 107 are on the edge region 102P of the upper surface 102a of the substrate 102. In some embodiments, the GaN-based semiconductor material includes, for example, gallium nitride (GaN), aluminum gallium nitride (AlGaN), other applicable similar GaN-based semiconductor materials, or any of the foregoing combination. In some embodiments, the thickness of the gallium nitride-based semiconductor layer 106 is about 5 microns to about 15 microns. In some embodiments, the size of the gallium nitride-based particles 107 is about 1 micrometer to about 50 micrometers.

In some embodiments of the present disclosure, the gallium nitride-based semiconductor layer 106 is epitaxially grown on the (111) plane of the silicon layer 140. In other words, the gallium nitride-based semiconductor layer 106 is, for example, a gallium nitride-based epitaxial layer , And directly formed on the (111) crystal plane of the silicon layer 104. In some embodiments, the epitaxially grown gallium nitride-based semiconductor layer 106 has substantially vertical sidewalls, for example, between the extension line of the sidewall of the gallium nitride-based semiconductor layer 106 and the upper surface 102a of the substrate 102 The included angle θ is, for example, about 85° to about 95°, for example, about 90°. In addition, the edge region 102P of the upper surface 102a of the substrate 102 does not have a silicon (111) crystal plane, which is not conducive to epitaxial growth of the gallium nitride semiconductor layer, so gallium nitride particles 107 with irregular shapes and sizes are formed, and The gallium nitride-based particles 107 are not stably attached to the substrate 102 like the gallium nitride-based semiconductor layer 106.

Next, in some embodiments, as shown in FIGS. 1C to 1D, a mask layer 112 is formed on the gallium nitride-based semiconductor layer 106, so that the upper surface 106a of the edge portion of the gallium nitride-based semiconductor layer 106 and The edge area 102P of the upper surface 102 a of the substrate 102 is exposed from the mask layer 112. In some embodiments, the mask layer 112 may be a photoresist layer, a hard mask layer (such as a nitride layer), or a combination thereof. In some embodiments of the present disclosure, the formation of the mask layer 112 is performed before the first dry etching step 160, and the related details of the first dry etching step 160 will be described in detail later in this article.

In some embodiments, as shown in FIG. 1C, a mask material layer 110 is formed on the GaN-based semiconductor layer 106 and the substrate 102. In some embodiments, the mask material layer 110 may include a photoresist material, a hard mask material (for example, nitride), or a combination thereof. In some embodiments, the mask material layer 110 may be formed by spin-on coating, chemical vapor deposition (CVD), applicable similar methods, or any combination of the foregoing. As shown in FIG. 1C, the mask material layer 110 can cover the GaN-based semiconductor layer 106, the silicon layer 104, the GaN-based particles 107, and the upper surface 102a of the substrate 102. In some embodiments, as shown in FIG. 1C, the outer periphery 110P of the mask material layer 110 covers the sidewalls of the gallium nitride-based semiconductor layer 106, the sidewalls of the silicon layer 104, the gallium nitride-based particles 107, And the edge area 102P of the upper surface 102a of the substrate 102.

Next, as shown in FIG. 1D, an edge bevel removal (EBR) step 150 is performed on the outer peripheral portion 110P of the mask material layer 110 to partially remove the mask material layer 110 and form a mask layer 112 . In some embodiments, as shown in FIG. 1D, the mask layer 112 covers the device area A, and the device area A is defined as an effective area of the substrate 102 for subsequent fabrication of semiconductor devices. In some embodiments, the boundary E of the device region A is separated from the edge of the GaN-based semiconductor layer 106 by a distance D2, which is less than the distance D1 (that is, the width of the edge region 102P). In some embodiments, the distance D2 is about 0.3 mm to 1 mm, for example, about 0.5 mm. In some embodiments, the sum of the distance D1 and the distance D2 is equal to or greater than 2.5 mm, for example, about 2.5 mm to about 3.5 mm.

In some embodiments, as shown in FIG. 1D, performing the edge removal (EBR) step 150 may include spraying a cleaning solution from the side surface of the mask material layer 110 to the outer peripheral portion 110P to remove the outer peripheral portion 110P of the mask material layer 110 Melt and remove, thereby exposing the upper surface 106a of the edge portion of the gallium nitride-based semiconductor layer 106. In some embodiments, the scavenging solution may include an organic solvent, for example, propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether ester (PGMEA), ethylene glycol monomethyl ether ester (EGMEA), ethyl lactate , Cyclohexanone, or any combination of the above.

In some embodiments, the structure shown in FIG. 1D may be disposed on the base (not shown) of the crystal edge removal device, and the nozzle (not shown) of the crystal edge removal device is disposed on the mask material layer 110 The side surface is not arranged above the mask material layer 110. Then, the base of the crystal edge removing device can drive the structure as shown in Figure 1D to rotate relative to the nozzle, so that the cleaning liquid sprayed from the nozzle can surround and be completely sprayed on the entire outer circumference 110P of the mask material layer 110 Thus, the outer peripheral portion 110P is melted and removed, and the upper surface 106a of the edge portion of the gallium nitride-based semiconductor layer 106 is exposed.

In some embodiments, as shown in FIGS. 1C to 1D, the spray direction R1 of the cleaning liquid is substantially parallel to the upper surface 110a of the mask material layer 110 (that is, the upper surface 112a of the mask layer 112), in other words , The spray direction R1 of the cleaning liquid is substantially perpendicular to the sidewall of the gallium nitride-based semiconductor layer 106 previously covered by the outer peripheral portion 110P. For example, in some embodiments, the angle θ1 between the spray direction R1 of the cleaning liquid and the upper surface 110a of the mask material layer 110 (that is, the upper surface 112a of the mask layer 112) is, for example, about 0° to Within a range of about 30°, the cleaning liquid is generally sprayed only on the outer peripheral portion 110P of the mask material layer 110, and not sprayed on the upper surface 110a of the mask material layer 110. In this way, the cleaning liquid can only remove the outer peripheral portion 110P of the mask material layer 110, and only expose the gallium nitride-based particles 107 that are scheduled to be removed later, and will not attack the mask from above the mask material layer 110. The thickness of the material layer 110 causes impairment. Therefore, the formed mask layer 112 can be used in the subsequent dry etching step to protect the GaN-based semiconductor layer 106 located below the device region A from being damaged by the dry etching step, for example, it may not be subjected to the dry etching step. Damage to the plasma.

Next, referring to FIG. 1E, perform a first dry etching step 160 to remove the gallium nitride particles 107. In an embodiment, performing the first dry etching step 160 includes applying a first bias power, and the first bias power is, for example, equal to or greater than 1500 watts (W).

When the gallium nitride-based semiconductor material is epitaxially grown on the silicon layer 104, the gallium nitride-based semiconductor material will also be epitaxially grown on the substrate 102. Since the gallium nitride-based particles 107 attached to the substrate 102 are likely to fall off during the subsequent manufacturing process, the subsequent manufacturing process will be contaminated, which causes the gallium nitride-based particles 107 to become a possible source of defects in the manufacturing process of the semiconductor structure. source). On the other hand, the gallium nitride particles 107 still have a certain degree of adhesion to the substrate 102. Not only the wet etching method cannot effectively remove the gallium nitride particles 107, but the dry etching process with insufficient energy is also not effective. Ground the gallium nitride-based particles 107 are removed. According to the embodiment of the present disclosure, the first dry etching step 160 is performed with a bias power equal to or greater than 1500 watts, which can effectively remove the gallium nitride particles 107 and prevent the gallium nitride particles 107 from becoming a semiconductor structure The source of defects in the process can improve the yield of the semiconductor structure.

In some embodiments, the first bias power is, for example, equal to or greater than 1800 watts. In some embodiments, the first bias power is, for example, about 1800 watts to about 2000 watts.

According to an embodiment of the present disclosure, when the first bias power is equal to or greater than 1800 watts, the bias power of the first dry etching step 160 is substantially greater than the bias power used in all subsequent dry processes of the semiconductor structure. Therefore, using a bias power equal to or greater than 1800 watts to perform the first dry etching step 160 can effectively ensure that even at this stage, some of the gallium nitride particles 107 have not been removed, and they cannot be removed in the subsequent process. The lower energy of other dry etching processes lower than 1800 watts is used to remove, so the gallium nitride-based particles 107 can be effectively prevented from becoming a source of defects in the process of semiconductor structure, and the yield of the process of semiconductor structure can be improved.

In some embodiments, the first dry etching step 160 may include using a fluorine-containing etchant, a chlorine-containing etchant, or a combination of the foregoing etchant. In some embodiments, the etchant may include SF ₆ , CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, Cl ₂ , or any combination of the foregoing. In one embodiment, the etchant used in the first dry etching step 160 may include SF ₆ , CF ₄ , Cl ₂ , or a combination thereof.

According to the embodiments of the present disclosure, the use of a fluorine-containing etchant and/or a chlorine-containing etchant can more effectively remove the gallium nitride particles 107 and the contaminants remaining on the surface.

In some embodiments, the first dry etching step 160 is, for example, a dry plasma etching process and is performed for about 100 seconds to about 400 seconds. In one embodiment, the first dry etching step 160 is performed for about 200 seconds, for example.

According to the embodiment of the present disclosure, the dry plasma etching process takes more than 100 seconds but within 400 seconds, so it can last enough time to accumulate enough energy to remove the gallium nitride particles 107, and at the same time can To avoid possible damage to the upper surface 102a of the substrate 102 caused by excessive plasma etching caused by too long, therefore, the gallium nitride-based particles 107 can be effectively removed and the structure of the upper surface 102a of the substrate 102 is kept intact.

In some embodiments, the structure shown in FIG. 1D can be placed on a stage (not shown) in the etching chamber (not shown) of the etching equipment, through the spray head (not shown) of the etching equipment ) Disperse the etchant evenly into the etching chamber, and then apply bias power to the etching chamber through a bias power generation source (not shown) of the etching equipment to generate a bias voltage field on the upper electrode ( Not shown, usually set at the top of the etching chamber) and the bottom electrode (not shown, usually set inside the carrier of the etching chamber). The etchant is accelerated by the bias electric field in the etching chamber, and in the direction of the stage, an anisotrpic dry etching process is performed on the structure shown in Figure 1D from above the mask layer 112 . In some embodiments, referring to Figure 1D, an anisotropic dry etching process is applied, for example, on the upper surface 106a of the edge portion of the gallium nitride semiconductor layer 106 exposed from the mask layer 112 and on the substrate 102 On the edge area 102P of the upper surface 102a.

In some embodiments, as shown in FIG. 1E, the first dry etching step 160 removes the gallium nitride-based particles 107 on the edge region 102P of the upper surface 102a of the substrate 102. In some embodiments, as shown in FIG. 1E, the first dry etching step 160 also partially removes the gallium nitride semiconductor layer 106 and the silicon layer 104 exposed from the mask layer 112, so that the formed gallium nitride The semiconductor layer 106 ′ has inclined sidewalls in the areas not protected by the mask layer 112, and the formed silicon layer 104 ′ has inclined sidewalls in the areas not protected by the mask layer 112.

In some embodiments, as shown in FIG. 1E, the sidewalls of the gallium nitride-based semiconductor layer 106' and the sidewalls of the silicon layer 104' form a continuous sloped sidewall, and the gap between the continuous sloped sidewall and the upper surface 102a of the substrate 102 The included angle is, for example, less than 90 degrees. In some embodiments, the angle between the continuously inclined sidewall and the upper surface 102a of the base 102 is, for example, about 50 degrees to about 85 degrees.

In some embodiments, as shown in FIG. 1E, the angle θ2 between the sidewall of the gallium nitride-based semiconductor layer 106' and the bottom surface 106b is, for example, less than 90 degrees. In some embodiments, as shown in FIG. 1E, the angle θ2 between the sidewall of the gallium nitride-based semiconductor layer 106' and the bottom surface 106b is, for example, about 50 degrees to about 85 degrees.

In some embodiments, as shown in FIG. 1E, the angle θ3 between the sidewall of the silicon layer 104' and the bottom surface 104b is, for example, less than 90 degrees. In some embodiments, as shown in FIG. 1E, the angle θ3 between the sidewall of the silicon layer 104' and the bottom surface 104b is, for example, about 50 degrees to about 85 degrees. In some embodiments, the included angle θ2 and the included angle θ3 may be the same or different.

Please refer to FIG. 1F. After performing the first dry etching step 160, the mask layer 112 is removed. In some embodiments, for example, an ash process may be used to remove the mask layer 112.

In some embodiments, after the mask layer 112 is removed, a cleaning step 170 may be further performed to clean the gallium nitride-based semiconductor layer 106 ′ and the edge region 102P of the upper surface 102 a of the substrate 102 with a cleaning solution. In some embodiments, the cleaning solution may include ammonia (NH ₄ OH), sulfuric acid (H ₂ SO ₄ ), hydrogen peroxide (H ₂ O ₂ ), water, or any combination of the foregoing.

In some embodiments, a mixture of sulfuric acid and hydrogen peroxide (volume ratio of about 2~4:1) can be used to wash away the mask material that may remain after removing the mask layer 112 at a temperature of about 130°C, and Use a mixed solution of ammonia, hydrogen peroxide and water (volume ratio of about 0.05-1:1:1) to wash away metal particles that may remain after removing the gallium nitride particles 107 at a temperature of about 70°C.

According to the embodiments of the present disclosure, using a cleaning solution to clean the GaN-based semiconductor layer 106' and the edge area 102P of the upper surface 102a of the substrate 102 can further clean the remaining mask material and/or remaining metal particles. So far, the semiconductor structure 100 as shown in FIG. 1F is formed.

Next, according to an embodiment of the present disclosure, a semiconductor material layer may be formed on the gallium nitride-based semiconductor layer 106', and a dry etching process may be performed to form at least one recess in the semiconductor material layer, and the dry etching process may be performed The applied bias power is less than the first bias power of the first dry etching step 160. In some embodiments, the semiconductor material layer formed on the gallium nitride-based semiconductor layer 106' includes, for example, a gallium nitride semiconductor layer and aluminum gallium nitride (Al _x Ga _1-x N, where 0<x<1) Semiconductor layer, other applicable similar GaN-based semiconductor layers, or any combination of the above.

In the embodiments of the present disclosure, in addition to forming a semiconductor material layer on the gallium nitride-based semiconductor layer 106' to form semiconductor structures of different embodiments, other devices and/or other devices including gallium nitride-based semiconductor materials can also be further used. The device is formed on the semiconductor structure 100 as shown in FIG. 1F to form a semiconductor structure according to other further embodiments of the disclosure. For example, a semiconductor device containing a gallium nitride-based semiconductor material may be, for example, a light emitting diode (LED), a high electron mobility transistor (HEMT), a Schottky diode (SBD), a dual carrier transistor ( BJT), junction field effect transistor (JFET), insulated gate bipolar transistor (IGBT), or other similar devices. Hereinafter, a high electron mobility transistor (HEMT) is taken as an example to describe an embodiment in which a semiconductor device is formed on the semiconductor structure 100 in FIG. 1F.

FIGS. 2A to 2E are cross-sectional schematic diagrams illustrating the use of the semiconductor structure of FIG. 1F to further form a high electron mobility transistor at various stages according to some embodiments of the present disclosure. In this embodiment, the same or similar component numbers are used for the same or similar components in the previous embodiments, and the related description of the same or similar components please refer to the foregoing description, which will not be repeated here.

In the following embodiments as shown in FIG. 2A to FIG. 2E, only the device area A of the semiconductor structure of the embodiment of the present disclosure is shown to illustrate that other devices and/or elements are further formed on the semiconductor of FIG. 1F Structurally, to form other further embodiments of semiconductor structures with high electron mobility transistors. In the following embodiments as shown in FIGS. 2A to 2E, the gallium nitride (GaN) semiconductor layer 204 in FIGS. 2A to 2E is, for example, an example of the aforementioned gallium nitride semiconductor layer 106'. The aluminum gallium nitride semiconductor layer 206 in FIGS. 2A to 2E is, for example, an example of the aforementioned semiconductor material layer, but the embodiments of the disclosure are not limited thereto.

Referring to FIG. 2A, an aluminum gallium nitride semiconductor layer 206 (for example, the aforementioned semiconductor material layer) is formed on the gallium nitride semiconductor layer 204 (for example, the aforementioned gallium nitride-based semiconductor layer 106'). There is a heterogeneous interface between the gallium nitride semiconductor layer 204 and the aluminum gallium nitride semiconductor layer 206, so that two-dimensional electron gas (2DEG) (not shown) can be formed on this heterogeneous interface. The high electron mobility transistor 200 shown in Fig. 2E can use two-dimensional electron gas as conductive carriers. In some embodiments, the aluminum gallium nitride semiconductor layer 206 may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE) , Applicable similar methods, or any combination of the above. In some embodiments, the gallium nitride semiconductor layer 204 and the gallium aluminum nitride semiconductor layer 206 may have dopants, such as n-type dopants or p-type dopants.

Next, an insulating layer 208 containing silicon is formed on the gallium nitride semiconductor layer 204 (for example, the aforementioned gallium nitride-based semiconductor layer 106'). In some embodiments, the silicon-containing insulating layer 208 can be a high-quality thin film formed by atomic layer deposition (ALD), thermal oxidation process or similar deposition process, and its material can be silicon oxide, silicon nitride, silicon oxynitride, suitable Similar materials or any combination of the above. Forming a high-quality thin silicon-containing insulating layer 208 on the gallium aluminum nitride semiconductor layer 206 can prevent the subsequent formation of source contacts (first contact 220), drain contacts (second contact 222), and gate The leakage current of the pole contact (third contact 228) (shown in Figure 2E).

As shown in FIG. 2A, a material layer of the mask layer 210 is formed on the silicon-containing insulating layer 208, and a first opening 212 and a second opening 214 are formed in the material layer of the mask layer 210 using photolithography technology. An opening 212 and a second opening 214 expose a part of the upper surface of the silicon-containing insulating layer 208.

Next, referring to FIG. 2B, a second dry etching step 510 is performed through the first opening 212 and the second opening 214 of the mask layer 210 to form a first recess 216' and a second recess 218 in the silicon-containing insulating layer 208 '. In some embodiments, performing the second dry etching step 510 includes applying a second bias power, and the second bias power is less than the first bias power. According to the embodiment of the present disclosure, because the second bias power is less than the first bias power, even if some of the gallium nitride particles 107 are not removed by the first dry etching step 160, the second dry etching step 510 is still It will not cause the gallium nitride particles 107 to fall off, so it can prevent the process yield from being adversely affected. In some embodiments, the second bias power is, for example, about 100 watts to about 500 watts.

Next, referring to FIG. 2C, perform a third dry etching step 520 to etch the gallium nitride semiconductor layer 204 (for example, the aforementioned gallium nitride semiconductor layer 106') to align the first recess 216' and the second recess 218' Extending into the aluminum gallium nitride semiconductor layer 206, a first recess 216 and a second recess 218 are generated. In some embodiments, performing the third dry etching step 520 includes applying a third bias power, and the third bias power is less than the first bias power. According to the embodiment of the present disclosure, because the third bias power is less than the first bias power, even if some of the gallium nitride particles 107 are not removed by the first dry etching step 160, the third dry etching step 520 is still It will not cause the gallium nitride particles 107 to fall off, so it can prevent the process yield from being adversely affected. In some embodiments, the third bias power is, for example, about 1000 watts to about 1350 watts.

Next, referring to FIG. 2D, after the third dry etching step 520, an ashing process may be performed to remove the mask layer 210 on the silicon-containing insulating layer 208.

Next, referring to FIG. 2D, a first contact 220 and a second contact 222 are formed in the first recess 216 and the second recess 218, respectively. In some embodiments, the first contact 220 is, for example, a source contact, and the second contact 222 is, for example, a drain contact. The first contact 220 and the second contact 222 are located on the aluminum gallium nitride semiconductor layer 206 and are in electrical contact with the aluminum gallium nitride semiconductor layer 206. In some embodiments, the first contact member 220 and the second contact member 222 may not fill the first recess 216 and the second recess 218, but are formed along the sidewall and bottom surface of the first recess 216 and the second recess 218, and Extend to part of the surface of the silicon-containing insulating layer 208. In some embodiments, the material of the first contact 220 and the second contact 222 may be conductive materials, such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi _2. Applicable similar materials, or any combination of the above, and the first contact 220 and the second contact 222 can be made by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (physical vapor deposition, PVD), sputtering, or applicable similar processes. In some embodiments, the first contact 220 and the second contact 222 may be formed together in the same deposition process.

Next, in some embodiments, as shown in FIG. 2E, a passivation layer 224 is formed on the first contact 220 and the second contact 222, and the passivation layer 224 covers the first contact 220 and the second contact 222. In some embodiments, the material of the passivation layer 224 may be silicon nitride, silicon oxide, silicon oxynitride, suitable similar materials, or any combination of the foregoing. In some embodiments, the passivation layer 224 may be formed by chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), or a suitable similar method.

Next, in some embodiments, as shown in FIG. 2E, a third recess 226 is formed in the passivation layer 224 using photolithography technology and an etching process, and the third recess 226 is located in the first contact 220 and the second contact 222 between. Next, a third contact 228 is formed in the third recess 226 between the first contact 220 and the second contact 222. In some embodiments, the third contact 228 is, for example, a gate contact, and the high electron mobility transistor 200 is formed so far. In some embodiments, the third contact 228 is located on the silicon-containing insulating layer 208 and between the first contact 220 and the second contact 222. In some embodiments, the third contact 228 may not fill the third recess 226 but is formed along the sidewall and bottom surface of the third recess 226 and extends to a part of the surface of the passivation layer 224. In some embodiments, the material of the third contact 228 may be a conductive material, such as Au, Ni, Pt, Pd, Ir, Ti, Cr, W, Al, Cu, TaN, TiN, WSi ₂ , suitable similar materials , Or any combination of the above, and the third contact 228 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or a suitable similar process. The first contact 220 and the second contact 222 can finally be electrically connected to an external circuit through a metal layer (not shown) passing through the passivation layer 224.

Several embodiments are summarized above so that those with ordinary knowledge in the technical field of the present invention can better understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field to which the present invention pertains should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can, without departing from the spirit and scope of the present invention, Make all kinds of changes, substitutions and replacements.

100: semiconductor structure 102: substrate 102a, 106a, 110a, 112a: upper surface 102P: edge area 104, 104': silicon layer 104b, 106b: bottom surface 106, 106': gallium nitride semiconductor layer 107: gallium nitride System particles 110: mask material layer 110P: outer peripheral portion 112, 210: mask layer 150: crystal edge removal step 160: first dry etching step 170: cleaning step 200: high electron mobility transistor 204: gallium nitride semiconductor Layer 206: aluminum gallium nitride semiconductor layer 208: silicon-containing insulating layer 212: first opening 214: second opening 216, 216': first recess 218, 218': second recess 220: first contact 222: first Second contact 224: passivation layer 226: third recess 228: third contact 510: second dry etching step 520: third dry etching step A: device area D1, D2: distance E: boundary P: diameter R1: spraying Direction θ, θ1, θ2, θ3: included angle

In order to make the features and advantages of this disclosure more comprehensible, different embodiments are specifically cited below, together with the accompanying drawings, for detailed descriptions as follows: Figures 1A to 1F are based on some embodiments of the disclosure, illustrating the formation Cross-sectional schematic diagrams of the semiconductor structure at various stages. FIGS. 2A to 2E are cross-sectional schematic diagrams illustrating the use of the semiconductor structure of FIG. 1F to further form a high electron mobility transistor at various stages according to some embodiments of the present disclosure.

100: semiconductor structure

102: Base

104’: Silicon layer

106’: Gallium nitride semiconductor layer

170: Cleaning steps

A: Device area

E: boundary

P: diameter

Claims (20)

A method for manufacturing a semiconductor structure includes: providing a substrate; forming a silicon layer on the substrate, wherein an edge region of an upper surface of the substrate is exposed from the silicon layer; and applying a GaN-based ) A semiconductor material is epitaxially grown on the silicon layer and the substrate to form a gallium nitride semiconductor layer on the silicon layer and a plurality of gallium nitride particles on the edge region of the upper surface of the substrate; And performing a first dry etching step to remove the gallium nitride particles, wherein performing the first dry etching step includes applying a first bias power, and the first bias power is equal to or greater than 1500 watts . According to the manufacturing method of the semiconductor structure described in the first item of the scope of patent application, the first bias power is 1800 watts to 2000 watts. According to the manufacturing method of the semiconductor structure described in claim 1, wherein performing the first dry etching step includes using a fluorine-containing etchant, a chlorine-containing etchant, or a combination thereof. According to the manufacturing method of the semiconductor structure described in the first item of the scope of patent application, the first dry etching step is a dry plasma etching process and is performed for 100 seconds to 400 seconds. The method for manufacturing a semiconductor structure as described in claim 1 further includes: before performing the first dry etching step, forming a mask layer on the gallium nitride semiconductor layer, wherein the gallium nitride semiconductor layer An upper surface of an edge portion of the semiconductor layer and the edge area of the upper surface of the substrate are exposed from the mask layer. According to the manufacturing method of the semiconductor structure described in claim 5, forming the mask layer includes: forming a mask material layer on the gallium nitride semiconductor layer and the substrate; and the mask material layer An outer periphery of an outer periphery undergoes an edge bevel removal (EBR) step to partially remove the mask material layer and form the mask layer. According to the manufacturing method of the semiconductor structure described in item 6 of the scope of patent application, the step of performing the edge removal (EBR) includes: spraying a cleaning liquid on the outer periphery from the side of the mask material layer. According to the method of manufacturing a semiconductor structure described in claim 5, the first dry etching step is an anisotropic dry etching process, and is performed from above the mask layer, the anisotropic dry etching The process is applied on the upper surface of the edge portion of the gallium nitride-based semiconductor layer exposed from the mask layer and on the edge area of the upper surface of the substrate. According to the method of manufacturing a semiconductor structure described in claim 5, wherein the first dry etching step partially removes the gallium nitride-based semiconductor layer and the silicon layer exposed from the mask layer, so that the nitrogen A sidewall of the gallium sulfide semiconductor layer and a sidewall of the silicon layer form a continuous inclined sidewall. The manufacturing method of the semiconductor structure as described in item 5 of the scope of the patent application further includes: after performing the first dry etching step, removing the mask layer; and using a cleaning solution to clean the gallium nitride semiconductor layer And the edge area of the upper surface of the substrate, wherein the cleaning liquid includes ammonia, sulfuric acid, hydrogen peroxide, water, or any combination of the foregoing. The method for manufacturing a semiconductor structure as described in item 1 of the scope of the patent application further comprises: forming a semiconductor material layer on the gallium nitride semiconductor layer; and performing a dry etching process to form at least A recess, wherein a bias power applied to the dry etching process is less than the first bias power of the first dry etching step. The manufacturing method of the semiconductor structure described in the first item of the patent application further includes: forming a silicon-containing insulating layer on the gallium nitride-based semiconductor layer; and performing a second dry etching step on the silicon-containing insulating layer A first recess and a second recess are formed, wherein performing the second dry etching step includes applying a second bias power, and the second bias power is less than the first bias power. The method for manufacturing a semiconductor structure as described in claim 12 further includes: performing a third dry etching step to etch the gallium nitride-based semiconductor layer to extend the first recess and the second recess to the nitrogen In the gallium aluminum semiconductor layer, performing the third dry etching step includes applying a third bias power, and the third bias power is less than the first bias power. The method for manufacturing a semiconductor structure as described in item 13 of the scope of the patent application further includes: forming a first contact and a second contact in the first recess and the second recess, respectively; and in the first contact A third contact member is formed between the second contact member and the second contact member. A semiconductor structure includes: an aluminum nitride substrate; a silicon layer formed on the aluminum nitride substrate, wherein an upper surface of an edge region of the aluminum nitride substrate is exposed from the silicon layer; and a gallium nitride The semiconductor layer is formed on the silicon layer, wherein the angle between a sidewall and a bottom surface of the gallium nitride semiconductor layer is less than 90 degrees. In the semiconductor structure described in claim 15, wherein the angle between the sidewall and the bottom surface of the GaN-based semiconductor layer is 50 degrees to 85 degrees. In the semiconductor structure described in claim 15, wherein the angle between a sidewall and a bottom surface of the silicon layer is less than 90 degrees. The semiconductor structure according to claim 15, wherein the sidewall of the gallium nitride-based semiconductor layer and a sidewall of the silicon layer form a continuous inclined sidewall, and the continuous inclined sidewall and the upper side of the aluminum nitride substrate The angle between the surfaces is 50 degrees to 85 degrees. According to the semiconductor structure described in item 15 of the scope of patent application, the GaN-based semiconductor layer is a GaN-based epitaxial layer directly formed on the (111) crystal plane of the silicon layer. The semiconductor structure described in claim 15, wherein the edge region surrounds the silicon layer.

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