TW202032730A - 半導體封裝及其製造方法 - Google Patents

半導體封裝及其製造方法 Download PDF

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TW202032730A
TW202032730A TW108130258A TW108130258A TW202032730A TW 202032730 A TW202032730 A TW 202032730A TW 108130258 A TW108130258 A TW 108130258A TW 108130258 A TW108130258 A TW 108130258A TW 202032730 A TW202032730 A TW 202032730A
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Taiwan
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die
active
fine
pitch
active die
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TW108130258A
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TWI717813B (zh
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徐宏欣
林南君
張簡上煜
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力成科技股份有限公司
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Abstract

提供一種半導體封裝及其製造方法。半導體封裝包括分別佈置的第一和第二主動晶粒、至少橫向密封第一和第二主動晶粒的絕緣包封體、設置在絕緣包封體及第一和第二主動晶粒上的重佈線層、以及設置在重佈線層上並延伸超過第一和第二主動晶粒之間的間隙的細間距晶粒。細間距晶粒具有與第一和第二主動晶粒不同的功能。細間距晶粒的晶粒連接件藉由重佈線層的第一導電路徑連接到第一主動晶粒的導電特徵。第一導電路徑的第一連接長度基本上等於細間距晶粒的晶粒連接件與第一主動晶粒的導電特徵之間的最短距離。

Description

半導體封裝及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種扇出（fan-out）半導體封裝及其製造方法。
近年來，電子設備對人類生活更為重要。為了使電子設備設計實現輕薄短小，半導體封裝技術不斷發展，試圖開發體積更小、重量更輕、整合度更高以及市場競爭更激烈的產品。由於晶片封裝技術受到積體電路發展的高度影響，故隨著電子裝置尺寸的變化，封裝技術的需求也變得越來越苛刻。因此，在保持製程簡單性的同時使半導體封裝微型化已成為該領域的研究人員的一大挑戰。
本發明提供一種半導體封裝及其製造方法，其可提供電氣性能的改善以及更高的可製造性。
本發明提供了一種半導體封裝。半導體封裝包括分別佈置的第一主動晶粒和第二主動晶粒、至少橫向密封第一主動晶粒和第二主動晶粒的絕緣包封體、設置在絕緣包封體及第一主動晶粒和第二主動晶粒上的重佈線層、以及設置在重佈線層上並延伸超過第一主動晶粒和第二主動晶粒之間的間隙的細間距晶粒。細間距晶粒具有與第一主動晶粒和第二主動晶粒不同的功能。細間距晶粒的晶粒連接件藉由重佈線層的第一導電路徑連接到第一主動晶粒的導電特徵，其中重佈線層的第一導電路徑的第一連接長度基本上等於細間距晶粒的晶粒連接件和第一主動晶粒的導電特徵之間的最短距離。
在本發明的一實施例中，絕緣包封體的厚度大於第一主動晶粒和第二主動晶粒的厚度。在本發明的一實施例中，第一主動晶粒包括第一主動面和分佈在第一主動面上的多個導電特徵，細間距晶粒包括第二主動面和分佈在第二主動面上的多個晶粒連接件，第一主動晶粒的導電特徵中的第一群組連接到細間距晶粒的多個晶粒連接件，並且第一主動晶粒的導電特徵中的第二群組不連接到細間距晶粒，以及分佈在細間距晶粒的第二主動面上的晶粒連接件的分佈密度比分佈在第一主動晶粒的第一主動面上的導電特徵中的第二群組的分佈密度更密集。在本發明的一實施例中，導電特徵中的一群組設置在第一主動面的周邊並對應於重佈線層的晶粒安裝區，其中細間距晶粒設置在晶粒安裝區，以及群組中的相鄰的導電特徵的間距基本上與對應於群組設置的細間距晶粒的相鄰的晶粒連接件的間距相匹配。
本發明提供一種半導體封裝的製造方法。製造方法至少包括以下步驟。多個主動晶粒用絕緣包封體密裝，其中相鄰的主動晶粒在空間上被絕緣包封體的一部分隔開。在主動晶粒和絕緣包封體上形成重佈線層。細間距的晶粒設置在重佈線層上並在絕緣包封體的一部分的上方，其中細間距晶粒的晶粒連接件接合到重佈線層的導電路徑。晶粒連接件中的任一者與主動晶粒中的任一者之間的導電路徑的連接長度基本上等於晶粒連接件中的所述一者與主動晶粒中的所述一者之間的最短距離。
在本發明的一實施例中，用絕緣包封體密封主動晶粒包括將主動晶粒分開地設置在臨時載體上，其中主動晶粒的主動面朝向所述臨時載體，以及在形成重佈線層之前，將臨時載體從主動晶粒上釋出以暴露出主動晶粒的主動面。在本發明的一實施例中，用絕緣包封體密封主動晶粒包括形成絕緣包封體以覆蓋主動晶粒中的每一者的側壁和背面，其中背面與重佈線層相對並且側壁連接到背面。在本發明的一實施例中，形成重佈線層還包括在圖案化導電層上形成圖案化介電層以部分地覆蓋圖案化導電層，其中在設置細間距晶粒之後，細間距晶粒的晶粒連接件的底部被圖案化介電層橫向覆蓋，以與圖案化導電層接觸。在本發明的一實施例中，半導體封裝的製造方法還包括形成導電端子於重佈線層上並在細間距晶粒旁，其中導電端子藉由重佈線層電性耦合到至少一個主動晶粒。在本發明的一實施例中，半導體封裝的製造方法還包括在細間距晶粒和重佈線層之間形成底膠以至少橫向覆蓋未被重佈線層掩蓋的細間距晶粒的晶粒連接件。在本發明的一實施例中，半導體封裝的製造方法還包括設置被動元件在重佈線層上並在細間距晶粒旁，其中被動元件藉由重佈線層電性耦合到至少一個主動晶粒。在本發明的一實施例中，當在重佈線層上設置細間距晶粒時，對細間距晶粒的晶粒連接件執行回焊製程。
基於上述，由於半導體封裝包括以面對面配置設置的主動晶粒和細間距晶粒，以縮短它們之間的互連距離，並可實現半導體封裝的較低功耗和高頻寬。細間距晶粒可用於提供高密度輸入/輸出（input/output，I/O）通訊以互連相鄰的主動晶粒。藉由使用上述製造方法，可以將均質晶粒（homogeneous die）和異質晶粒（heterogeneous die）整合在單一的扇出封裝中。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1F是示出根據本公開的實施例的半導體封裝的製造方法的示意性剖視圖。參考圖1A，第一主動晶粒110和第二主動晶粒120並排佈置在臨時載體50上方。在說明書中，用語“主動晶粒”可以是指具有電氣功能的半導體晶粒（或半導體晶片），其可對所製得的半導體封裝的電氣操作做出貢獻。臨時載體50可以是由玻璃、塑料、金屬或其他合適材料製成的晶圓級或面板級基板，只要該材料能承載後續製程同時承載形成於其上的結構。在一些實施例中，多個第一主動晶粒110和多個第二主動晶粒120以陣列（例如交替設置）佈置在臨時載體50上方。在一些實施例中，第一主動晶粒110及/或第二主動晶粒120從裝置晶圓（未示出）中分割出來，然後單獨地佈置在臨時載體50上。
第一主動晶粒110可包括主動面110a、與主動面110a相對的背面110b、以及連接到主動面110a和背面110b的側壁110c。類似地，第二主動晶粒120可包括主動面120a、背面120b和側壁120c。在一些實施例中，在設置第一主動晶粒110和第二主動晶粒120之後，在第一主動晶粒110和第二主動晶粒120之間形成間隙G，舉例來說，間隙G是第一主動晶粒110的側壁110c和第二主動晶粒120的側壁120c之間的最短距離。在一些實施例中，間隙G在約50μm至約300μm的範圍內。
在一些實施例中，當設置第一主動晶粒110和第二主動晶粒120時，第一主動晶粒110的主動面110a和第二主動晶粒120的主動面120a面向臨時載體50。舉例來說，第一主動晶粒110的主動面110a和第二主動晶粒120的主動面120a藉由離型層51接合到臨時載體50。舉例來說，離型層51包括光熱轉換（light to heat conversion，LTHC）離型層或其他合適的剝離層，其可以在後續製程中增強第一主動晶粒110和第二主動晶粒120從臨時載體50的可剝離性。做為另一種選擇，離型層51可被省略。
在一些實施例中，第一主動晶粒110包括半導體基板112，半導體基板112包括形成在其中的半導體裝置（例如電晶體、電容器、電感器、電阻器等；未示出）、設置在半導體基板112上並電性耦合到半導體裝置的多個接觸墊114、以及設置在半導體基板112上方並部分覆蓋接觸墊114的鈍化層116。半導體基板112可由半導體材料製成，並可包括摻雜或未摻雜的塊狀矽（bulk silicon）或絕緣體上矽基板（silicon-on-insulator substrate）的主動層等。接觸墊114可包括鋁，但可替代地使用其他導電材料（例如銅）。鈍化層116可以是聚合物層，以便為下面的結構提供保護和隔離。接觸墊114的至少一部分可被鈍化層116暴露出來以進一步電性連接。
在一些實施例中，第一主動晶粒110是無凸塊晶粒（bumpless die），並且表面（例如接觸墊114分佈和被暴露出來的地方）可被視為用於連接到外部元件的主動面110a。“無凸塊”（bumpless）可以指當最初提供第一主動晶粒110時在接觸墊114上不存在導電凸塊。做為另一種選擇，第一主動晶粒包括在接觸墊上形成的導電凸塊。在這樣的實施例中，第一主動晶粒的主動面可以是指導電凸塊分佈於其上的表面以用於連接到外部元件。在一些實施例中，接觸墊114的第一群組GP1分佈在第一主動晶粒110的主動面110a的外圍區域，其中主動面110a的外圍區域是靠近第二主動晶粒120的區域。接觸墊114的第二群組GP2可分佈在除了主動面110a的外圍區域之外的其餘區域。在一些實施例中，第一群組GP1中的兩個相鄰的接觸墊114的間距比第二群組GP2中的兩個相鄰的接觸墊114的間距更為精細。
第二主動晶粒120可具有與第一主動晶粒110類似的元件及/或配置方式。舉例來說，接觸墊124的第三群組GP3分佈在第二主動晶粒120的主動面120a的外圍區域，其中主動面120a的外圍區域是接近第一主動晶粒110的區域。第一主動晶粒110的第一群組GP1和第二主動晶粒120的第三群組GP3可彼此接近，並且第一群組GP1中的接觸墊114和第三群組GP3中的接觸墊124可具有相同或相似的精細間距（fine pitch）。接觸墊124的第四群組GP4可分佈在除了主動面120a的外圍區域之外的其餘區域，並且第二群組GP2中的接觸墊114和第四群組GP4中的接觸墊124可具有相同或相似的間距。
第一主動晶粒110和第二主動晶粒120可以是均質晶粒（即相同的晶粒）或異質晶粒（即不同的晶粒）。舉例來說，第一主動晶粒110和第二主動晶粒120包括記憶體晶粒、邏輯晶粒、中央處理單元（central processing unit，CPU）晶粒、其組合等。取決於所製得的半導體封裝的所需功能，可採用其他類型或功能的晶粒，並不限於此。
參照圖1B，在臨時載體50上形成絕緣包封體130以密封第一主動晶粒110和第二主動晶粒120。在一些實施例中，絕緣包封體130的厚度T1大於第一主動晶粒110和第二主動晶粒120的厚度。舉例來說，第一主動晶粒110的側壁110c和背面110b以及第二主動晶粒120的側壁120c和背面120b被絕緣包封體130覆蓋。絕緣包封體130可具有足夠的剛性以保護第一主動晶粒110和第二主動晶粒120。在一些實施例中，絕緣包封體130包括環氧樹脂、模塑化合物、模塑底膠或其他合適的電性絕緣材料。絕緣包封體130可藉由模塑製程或其他合適的成型製程形成。
舉例來說，在形成之後，第一主動晶粒110和第二主動晶粒120被絕緣包封體130包圍，並且絕緣包封體130的一部分形成在第一主動晶粒110和第二主動晶粒120之間的間隙G中，以在空間上將第一主動晶粒110與第二主動晶粒120分開。在其他實施例中，藉由使用例如研磨、化學機械拋光（chemical-mechanical polishing，CMP）、蝕刻、其組合等方式將絕緣包封體130薄化，以使第一主動晶粒110的背面110b和第二主動晶粒120的背面120b基本上平整。
參考圖1C，從第一主動晶粒110，第二主動晶粒120和絕緣包封體130移除臨時載體50。舉例來說，在移除臨時載體50之後，絕緣包封體130的底面130b、第一主動晶粒110的接觸墊114和第二主動晶粒120的接觸墊124被暴露出來，以進行進一步處理。舉例來說，可將外部能量（例如UV雷射、可見光或熱）施加到離型層51，使第一主動晶粒110、第二主動晶粒120和絕緣包封體130可從臨時載體50剝離。可採用其他合適的去除製程（例如機械剝離、蝕刻等）來移除臨時載體50。
臨時載體60接合到與臨時載體50相對的絕緣包封體130。在一些實施例中，絕緣包封體130的頂面130t藉由離型層61與臨時載體60接合。臨時載體60和離型層61的材料可類似於臨時載體50和離型層51的材料。在移除臨時載體50之前，臨時載體60接合到絕緣包封體130。在其他實施例中，臨時載體60的接合過程是在移除臨時載體50之後才執行。做為另一種選擇，絕緣包封體130具有足夠的剛性以在後續製程期間保護第一主動晶粒110和第二主動晶粒120，故可省略臨時載體60的接合製程。
參考圖1D，在絕緣包封體130、第一主動晶粒110和第二主動晶粒120上形成重佈線層（redistribution layer，RDL）140。在一些實施例中，在移除臨時載體50之後，可將結構上下翻轉以在主動晶粒的主動面上形成RDL140。RDL140可包括晶粒安裝區DR以及圍繞晶粒安裝區DR的端子安裝區TR。舉例來說，晶粒安裝區DR重疊於第一主動晶粒110的第一群組GP1、形成在間隙G中的絕緣包封體130的部分、以及第二主動晶粒120的第三群組GP3。在一些實施例中，RDL140包括交替堆疊在彼此上的至少一個圖案化介電層和至少一個圖案化導電層。
在示例性的實施例中，形成RDL140至少包括以下步驟。介電材料可形成在絕緣包封體130的底面130b上並藉由使用例如旋塗或其他合適的沉積製程在絕緣包封體130的底面130b上延伸以覆蓋第一主動晶粒110和第二主動晶粒120。接下來，藉由使用例如微影和蝕刻製程或其他合適的去除技術，去除一部分的介電材料以形成具有第一開口OP1和第二開口OP2的第一圖案化介電層142a。第一開口OP1可形成在晶粒安裝區DR內，而第二開口OP2可形成在端子安裝區TR內。舉例來說，第一主動晶粒110的第一群組GP1中的接觸墊114的至少一部分和第二主動晶粒120的第三群組GP3中的接觸墊124的至少一部分可由第一開口OP1被暴露出來，並可藉由第二開口OP2暴露出第一主動晶粒110的第二群組GP2中的接觸墊114的至少一部分和第二主動晶粒120的第四群組GP4中的接觸墊124的至少一部分。
接下來，在第一圖案化介電層142a上及第一開口OP1和第二開口OP2的內部形成導電材料並且圖案化導電材料，以藉由使用例如旋塗光阻、微影和蝕刻光阻、電鍍導電材料和去除光阻或任何其他合適的製程來形成第一圖案化導電層144a。應注意的是，在其他實施例中，可在形成第一圖案化介電層142a之前先形成第一圖案化導電層144a。
舉例來說，第一圖案化導電層144a包括分別形成在第一圖案化介電層142a的第一開口OP1和第二開口OP2中的導通孔CV1和CV2、分別連接到導通孔CV1和CV2的導電接墊CP1和CP2、連接到導通孔CV2並在第一圖案化介電層142a上延伸以重新佈線的導線CL。第一圖案化導電層144a可選擇性地包括連接到導線CL的導電接墊CP3，其中下一層形成的導通孔（例如第二導電層144b）可著落在導電接墊CP3上。導通孔CV1和於其上形成的導電接墊CP1可在晶粒安裝區DR內形成。導通孔CV2、形成在導通孔CV2上的導電接墊CP2、連接到導電接墊CP2的導線CL、以及選擇性形成的導電接墊CP3可形成在端子安裝區TR內。舉例來說，導通孔CV1和CV2被佈置成垂直地在垂直堆疊的相鄰層之間路由電訊號，並且導線CL被佈置為水平地路由電訊號以將電訊號傳遞延伸超出給定區域外或縮小到給定區域內。
在一些實施例中，第一圖案化導電層144a的導通孔CV2的部分被第一圖案化介電層142a橫向覆蓋並物理性連接到第二群組GP2中的接觸墊114。第一主動晶粒110的電訊號藉由直接形成在第二群組GP2中的接觸墊114上的導通孔CV2傳輸到外部電氣元件（例如隨後安裝的晶粒）或從外部電氣元件傳輸。藉由導電接墊CP2、導線CL、以及選擇性形成的導電接墊CP3，通過導通孔CV2的電訊號可橫向傳遞延伸超過第一主動晶粒110的遠離第二主動晶粒120的側壁110c（或者可橫向朝第二主動晶粒120延伸），其中導通孔CV2是著落在第二群組GP2中的接觸墊114上。在一些實施例中，第一圖案化導電層144a的導通孔CV1被第一圖案化介電層142a橫向覆蓋並物理性連接到第一群組GP1中的接觸墊114。第一主動晶粒110的電訊號藉由形成在第一群組GP1中的接觸墊114上的導通孔CV1傳輸到外部電氣元件或從外部電氣元件傳輸。通過導通孔CV1的電訊號可藉由物理性地連接到相應於導通孔CV1的導電接墊CP1垂直傳輸到外部電子元件或從外部電子元件傳輸，其中導通孔CV1是著落在第一群組GP1中的接觸墊114上，並且通過導電接墊CP1的電訊號可以不藉由任何導線且不橫向擴展。
類似地，第一圖案化導電層144a的導通孔CV2的部分被第一圖案化介電層142a橫向覆蓋並且導通孔CV2的部分物理性地著落在第四群組GP4中的接觸墊124上。第二主動晶粒120的電訊號藉由直接形成在第四群組GP4中的接觸墊124上的導通孔CV2傳輸到外部電氣元件或從外部電氣元件傳輸。藉由導電接墊CP2、導線CL、以及選擇性形成的導電接墊CP3，通過導通孔CV2的電訊號可橫向延伸超過第二主動晶粒120的遠離第一主動晶粒110的側壁120c（或者可橫向朝向第一主動晶粒110延伸），其中導通孔CV2是著落在第四群組GP4中的接觸墊124上。第一圖案化導電層144a的導通孔CV1被第一圖案化介電層142a橫向覆蓋且物理性地連接到第三群組GP3中的接觸墊124。第二主動晶粒120的電訊號藉由形成在第三群組GP3中的接觸墊124上的導通孔CV1傳輸到外部電氣部件或從外部電氣元件傳輸。通過導通孔CV1的電訊號可藉由物理性地連接到相應於導通孔CV1的導電接墊CP1垂直傳輸到外部電子元件或從外部電子元件傳輸，其中導通孔CV1是著落在第三群組GP3中的接觸墊124上，並且通過導電接墊CP1的電訊號可以不藉由任何導線且不橫向擴展。
隨後，可在第一圖案化介電層142a上形成第二圖案化介電層142b，以覆蓋第一圖案化導電層144a。第二圖案化介電層142b可包括第三開口OP3和第四開口OP4，第三開口OP3可形成在晶粒安裝區DR內，而第四開口OP4可形成在端子安裝區TR內。舉例來說，導電接墊CP1的至少一部分可藉由第三開口OP3被暴露出來，而導電接墊CP3的至少一部分可藉由第四開口OP4被暴露出來。在一些實施例中，如特定功能所需，第三開口OP3的開口尺寸小於第四開口OP4的開口尺寸。兩個相鄰的第三開口OP3的間距可比兩個相鄰的第四開口OP4的間距更精細。應當理解的是，可依設計需求而調節開口尺寸和第三開口OP3與第四開口OP4的間距。
在第二圖案化介電層142b上和第四開口OP4內形成第二圖案化導電層144b，以電性連接到第一圖案化導電層144a。第二圖案化介電層142b和第二圖案化導電層144b的形成過程可類似於第一圖案化介電層142a和第一圖案化導電層144a的形成過程。可將第一圖案化介電層142a和第二圖案化介電層142b統稱為RDL140的圖案化介電層142，亦可將第一圖案化導電層144a和第二圖案化導電層144b一併視為RDL140的圖案化導電層144。做為另一種選擇，可省略第二圖案化導電層144b。須說明的是，圖1D所示的圖案化介電層和圖案化導電層的數量僅為示例，在一些實施例中，可多次執行上述步驟以獲得電路設計所需的多層重佈線結構。應當理解的是，藉由形成更少的圖案化介電層和圖案化的導電層來實現更好的翹曲控制並且可降低製造成本。
在一些實施例中，第二圖案化導電層144b不形成在晶粒安裝區DR內，而是形成在端子安裝區TR內。舉例來說，第二圖案化導電層144b包括物理性地和電性地連接到第一圖案化導電層144a的導電接墊CP3的導通孔CV3，以及連接到導通孔CV3並在第二圖案化介電層142b上延伸的接合墊BP。接合墊BP可以是用於植球製程的凸塊下金屬（under-ball metallurgy，UBM）接墊。在省略第二圖案化導電層144b的其他實施例中，第一圖案化導電層144a的導電接墊CP3可以是用於植球製程的UBM接墊。在一些實施例中，第二圖案化導電層144b未形成在第二圖案化介電層142b的第三開口OP3中，使得第一圖案化導電層144a的導電接墊CP1保持被第三開口OP3暴露出來。
繼續參考圖1D，在臨時載體60接合到絕緣包封體130的一些實施例中，在形成RDL140之後，臨時載體60從絕緣包封體130剝離。臨時載體60的剝離過程可類似於圖1C中描述的臨時載體50的剝離過程，因此為了簡潔起見，不再重複詳細描述。
參照圖1E，細間距晶粒150設置在與第一主動晶粒110和第二主動晶粒120相對的RDL140上。細間距晶粒150可包括主動面150a和以高密度分佈在主動面150a上的多個晶粒連接件154。舉例來說，分佈在主動面150a上的晶粒連接件154的分佈密度比分佈在第一主動晶粒110的主動面110a上的第二群組GP2中的接觸墊114的分佈密度更密集，或者比分佈在在第二主動晶粒120的主動面120a上的第四群組GP4中的接觸墊124的分佈密度更密集。細間距晶粒150設置在RDL140上並且在晶粒安裝區DR內，細間距晶粒150的主動面150a面向第一主動晶粒110的主動面110a和第二主動晶粒120的主動面120a。舉例來說，細間距晶粒150包括半導體基板152、形成在半導體基板152上的互連層（未示出）、以及形成在互連層上的多個晶粒連接件154。半導體基板152的材料可類似於第一主動晶粒110的半導體基板的材料。可形成互連層以提供晶粒連接件154中不同的連接層之間的連接路徑。
舉例來說，晶粒連接件154可以是細間距接觸凸塊（fine-pitched contact bump），例如銅凸塊、焊料凸塊等。晶粒連接件154可包括導電材料，例如銅、金、錫、銀、焊料、金屬合金、其組合或其他合適的材料。在一些實施例中，兩個相鄰的晶粒連接件154的間距154P在約20μm至約60μm的範圍內。舉例來說，間距154P基本上等於第一主動晶粒110的第一群組GP1中的兩個相鄰的接觸墊114的間距或第二主動晶粒120的第一群組GP3中的兩個相鄰的接觸墊124的間距。第一主動晶粒110設置在足夠靠近第二主動晶粒120的位置以便允許第一主動晶粒110的第一群組GP1中的接觸墊114和第二主動晶粒120的第一群組GP3中的接觸墊124藉由位在晶粒安裝區DR內的第一圖案化導電層144a和細間距晶粒150的晶粒連接件154的電性互連，從而實現更好的訊號完整性和更低的傳輸損耗。
細間距晶粒150可藉由覆晶接合（flip chip bonding）製程或其他合適的接合製程安裝在RDL140上。舉例來說，細間距晶粒150的晶粒連接件154接合到第一圖案化導電層144a。在晶粒連接件154包括焊蓋（solder cap）或焊料凸塊（solder bump）的一些實施例中，對焊料材料執行回焊（reflow）製程，以增強晶粒連接件154和第一圖案化導電層144a的導電接墊CP1之間的黏著性。在進行回焊之後，晶粒連接件154的底部154b被第二圖案化介電層142b橫向覆蓋並且物理性地連接到第一圖案化導電層144a的導電接墊CP1。在焊料材料最初未形成在晶粒連接件154上的其他實施例中，焊料材料可沉積在第一圖案化導電層144a的導電接墊CP1上並位在第二圖案化介電層142b的第三開口OP3內，然後對焊料材料執行回焊製程。可採用其他導電膏來代替焊料材料。
在一些實施例中，在將細間距晶粒150接合到RDL140之後，晶粒連接件154的底部（如焊料材料部分）嵌入第二圖案化介電層142b中，並且晶粒連接件154的其餘部分被第二圖案化介電層142b暴露出來。可在RDL140上形成底膠UF，以藉由使用例如點膠（dispensing）、針射（injecting）或其他合適的製程來至少橫向覆蓋未被第二圖案化介電層142b掩蓋的晶粒連接件154的其餘部分。在細間距晶粒150和RDL140之間形成的底膠UF可增強接合製程的可靠性。做為另一種選擇，可省略底膠UF。
細間距晶粒150可以不是主動晶粒。在一些實施例中，包括細間距的晶粒連接件154的細間距晶粒150附接到RDL140，藉此提供高密度互連路徑以與第一主動晶粒110和第二主動晶粒120互連。舉例來說，細間距晶粒150是用於互連第一主動晶粒110和第二主動晶粒120的橋接晶粒（bridge die），其可作為第一主動晶粒110和第二主動晶粒120的電氣訊號溝通。在其他實施例中，細間距晶粒150包括內置在半導體基板152中的被動裝置（如電阻器、電感器和電容器）。連接第一主動晶粒110和第二主動晶粒120的最短電連接路徑可藉由使用細節距晶粒150來實現。
繼續參考圖1E，在RDL140上且在細間距晶粒150旁邊形成多個導電端子160。舉例來說，導電端子160形成在接合墊BP上並在RDL140的端子安裝區TR內。在一些實施例中，細間距晶粒150被導電端子160圍繞。導電端子160可藉由RDL140電性耦合到第一主動晶粒110和第二主動晶粒120。導電端子160可藉由RDL140而電性耦合到提供特定功能的細間距晶粒150。做為另一種選擇，導電端子160可以不電性耦合到細間距晶粒150。
舉例來說，導電端子160藉由使用植球製程、電鍍製程或其他合適的製程形成。在一些實施例中，導電端子160是藉由植球製程所形成的焊球，從而降低製造成本並提高製造效率。導電端子160可依設計需求而使用其他可能的形式和形狀。舉例來說，可執行焊接製程並選擇性地執行回焊製程以增強導電端子160和RDL140的接合墊BP之間的黏附性。可在設置細間距晶粒150之後形成導電端子160。做為另一種選擇，可在設置細間距晶粒150之前形成導電端子160。
參照圖1E和圖1F，在設置細間距晶粒150並形成導電端子160之後，執行單體化（singulation）製程以形成多個半導體封裝SP1。舉例來說，切割工具（未示出）可沿著切割道SL切穿RDL140和下面的絕緣包封體130，以將結構彼此分開。至此便基本完成半導體封裝SP1的製程。在一些實施例中，半導體封裝SP1被稱為扇出（fan-out）半導體封裝，而RDL140可被稱為扇出型重佈線層。
如圖1F所示，半導體封裝SP1包括細間距晶粒150，其提供高密度互連路徑以與第一主動晶粒110和第二主動晶粒120互連。半導體封裝SP1可具有整合在其中的均勻和異質晶粒（例如細間距晶粒150、第一主動晶粒110和第二主動晶粒120）。具有高密度晶粒連接件154並耦合到第一主動晶粒110和第二主動晶粒120的細間距晶粒150可以在操作期間為半導體封裝SP1提供更好的電氣性能。細間距晶粒150的晶粒連接件154藉由RDL140的第一圖案化導電層144a的導通孔CV1和導電接墊CP1（即第一導電路徑）耦合到第一主動晶粒110。導電端子160藉由RDL140的第二導電路徑（例如導通孔CV2、導電接墊CP2、導線CL、導電接墊CP3、導通孔CV3、接合墊BP）耦合到第一主動晶粒110。第一導電路徑的第一連接長度L1短於第二導電路徑的第二連接長度L2。
由於導通孔CV1直接連接到第一主動晶粒110的接觸墊114，並且細間距晶粒150的晶粒連接件154直接連接到導電接墊CP1，因此第一導電路徑的第一連接長度L1基本上等於細間距晶粒150的晶粒連接件154與第一主動晶粒110的接觸墊114（即導電特徵）之間的最短距離。這種配置可以保持短訊號長度，以便最小化操作之間的雜訊並改善訊號性能。應當注意的是，雖然在圖1F中示出了兩個主動晶粒和單一的細間距晶粒，但半導體封裝可包括更多的主動晶粒和對應於主動晶粒的更多的細間距晶粒，本發明並不限制主動晶粒和細間距晶粒的數量和配置方式。
圖2是示出根據本公開的實施例的半導體封裝的示意性剖視圖。參考圖2，提供半導體封裝SP2。除了半導體封裝SP2進一步包括被動元件170之外，半導體封裝SP2類似於上述半導體封裝SP1。
被動元件170可設置在RDL140'上並放置在細間距晶粒150旁邊。在一些實施例中，被動元件170設置在細間距晶粒150和導電端子160之間。被動元件170可藉由RDL140'電性耦合到第一主動晶粒110和第二主動晶粒120。舉例來說，RDL140'的圖案化導電層144'可依被動元件170的電路需求而進行調整。舉例來說，被動元件170可以是或可包括電阻器、電感器、電容器、其組合或者依特定功能所需的其他電氣元件。在一些實施例中，被動元件170是薄型電容器（low-profile capacitor），其設置在與第一主動晶粒110或第二主動晶粒120相對的RDL140'上，以獲得更佳的去耦合（decoupling）性能。應當注意的是，儘管在圖2中僅示出一個被動元件170，但具有相同功能或不同功能的多個被動元件可被包含在半導體封裝SP2內，而被動元件的數量取決於半導體封裝SP2所需的功能。
本發明中敘述的半導體封裝SP1或SP2可安裝到包括封裝基板、印刷電路板、系統板、母板等的外部裝置。舉例來說，半導體封裝SP1或SP2的第一主動晶粒110和第二主動晶粒120的電訊號藉由導電端子160傳輸到外部裝置。半導體封裝SP1或SP2也可具有其他的應用方式。
基於上述，由於半導體封裝包括以面對面配置設置的主動晶粒和細間距晶粒，藉以縮短晶粒之間的互連距離並可實現半導體封裝的較低功耗和高頻寬。細間距晶粒可用於提供高密度輸入/輸出（input/output）通訊以互連相鄰的主動晶粒。藉由上述製造方法，可將均質晶粒和異質晶粒整合在單一的扇出型封裝中。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
50、60:臨時載板 51、61:離型層 110:第一主動晶粒 110a、120a、150a:主動面 110b、120b:背面 110c、120c:側壁 112:半導體基板 114、124:接觸墊 116:鈍化層 120:第二主動晶粒 130:絕緣包封體 130b:底面 130t:頂面 140:重佈線層 142:圖案化介電層 142a:第一圖案化介電層 142b:第二圖案化介電層 144:圖案化導電層 144a:第一圖案化導電層 144b:第二圖案化導電層 144’:圖案化導電層 150:細間距晶粒 152:半導體基板 154:晶粒連接件 154P:間距 154b:底部 160:導電端子 170:被動元件 BP:接合墊 CL:導線 CP1、CP2、CP3:導電接墊 CV1、CV2、CV3:導通孔 DR:晶粒安裝區 GP1:第一群組 GP2:第二群組 GP3:第三群組 GP4:第四群組 L1:第一連接長度 L2:第二連接長度 OP1:第一開口 OP2:第二開口 OP3:第三開口 OP4:第四開口 SL:切割道 SP1、SP2:半導體封裝 T1:厚度 TR:端子安裝區 UF:底膠
圖1A至圖1F是示出根據本發明的實施例的半導體封裝的製造方法的示意性剖視圖。 圖2是示出根據本發明的實施例的半導體封裝的示意性剖視圖。
110:第一主動晶粒
114:接觸墊
120:第二主動晶粒
130:絕緣包封體
140:重佈線層
150:細間距晶粒
154:晶粒連接件
160:導電端子
CP1:導電接墊
CV1:導通孔
L1:第一連接長度
L2:第二連接長度
SP1:半導體封裝
UF:底膠

Claims (10)

  1. 一種半導體封裝，包括： 第一主動晶粒和第二主動晶粒，分開地排列； 絕緣包封體，至少橫向密封所述第一主動晶粒和所述第二主動晶粒； 重佈線層，設置在所述絕緣包封體、所述第一主動晶粒和所述第二主動晶粒上；以及 細間距晶粒，設置在所述重佈線層上並延伸超過所述第一主動晶粒和所述第二主動晶粒之間的間隙，所述細間距晶粒具有不同於所述第一主動晶粒和所述第二主動晶粒的功能，所述細間距晶粒的晶粒連接件藉由所述重佈線層的第一導電路徑連接到所述第一主動晶粒的導電特徵，其中所述重佈線層的所述第一導電路徑的第一連接長度基本上等於所述細間距晶粒的所述晶粒連接件與所述第一主動晶粒的所述導電特徵之間的最短距離。
  2. 如申請專利範圍第1項所述的半導體封裝，還包括： 導電端子，設置在所述重佈線層上並在所述細間距晶粒旁，所述導電端子藉由所述重佈線層電性連接到所述第一主動晶粒和所述第二主動晶粒。
  3. 如申請專利範圍第2項所述的半導體封裝，其中所述重佈線層的第二導電路徑連接到所述導電端子和所述第一主動晶粒和所述第二主動晶粒中的任一者，並且所述第一導電路徑的所述第一連接長度短於所述第二導電路徑的第二連接長度。
  4. 如申請專利範圍第1項所述的半導體封裝，還包括： 被動元件，設置在所述重佈線層並在所述細間距晶粒旁，所述被動元件藉由所述重佈線層電性連接到所述第一主動晶粒和所述第二主動晶粒。
  5. 如申請專利範圍第1項所述的半導體封裝，還包括： 底膠，設置在所述細間距晶粒和所述重佈線層之間，以橫向覆蓋所述細間距晶粒的所述晶粒連接件。
  6. 如申請專利範圍第1項所述的半導體封裝，其中所述第一主動晶粒的所述導電特徵是接觸墊，並且所述重佈線層的所述第一導電路徑與所述接觸墊直接接觸。
  7. 如申請專利範圍第1項所述的半導體封裝，其中所述細間距晶粒的所述晶粒連接件部分地嵌入所述重佈線層中以與所述第一導電路徑直接接觸。
  8. 一種半導體封裝的製造方法，包括： 用絕緣包封體密封多個主動晶粒，其中相鄰的所述主動晶粒在空間上被所述絕緣包封體的一部分隔開； 在所述主動晶粒和所述絕緣包封體上形成重佈線層；以及 在所述重佈線層和所述絕緣包封體的所述部分上設置細間距晶粒，其中所述細間距晶粒的多個晶粒連接件與所述重佈線層的導電路徑結合，在所述細間距晶粒的所述晶粒連接件中的任一者與所述主動晶粒中的任一者之間的所述導電路徑的連接長度基本上等於所述晶粒連接件中的所述一者和所述主動晶粒中的所述一者之間的最短距離。
  9. 如申請專利範圍第8項所述的半導體封裝的製造方法，其中形成所述重佈線層包括： 在所述主動晶粒的主動面上形成圖案化導電層，其中所述圖案化導電層的導通孔直接連接到分佈在所述主動面上的所述主動晶粒的接觸墊。
  10. 如申請專利範圍第8項所述的半導體封裝的製造方法，其中所述主動晶粒中的任一者設置有至少兩個接觸墊，所述接觸墊具有間距，所述間距基本上匹配於所述細間距晶粒的兩個相鄰的所述晶粒連接件之間的間距，並且所述接觸墊設置在所述主動晶粒的外圍和靠近所述絕緣包封體的所述部分。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI730917B (zh) * 2020-10-27 2021-06-11 矽品精密工業股份有限公司 電子封裝件及其製法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102450570B1 (ko) 2018-10-02 2022-10-07 삼성전자주식회사 반도체 패키지
US11854984B2 (en) * 2019-09-25 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
CN111554676B (zh) * 2020-05-19 2022-03-29 上海先方半导体有限公司 一种局部带宽增强的转接板封装结构及制作方法
US11735554B2 (en) * 2020-08-14 2023-08-22 Sj Semiconductor (Jiangyin) Corporation Wafer-level chip scale packaging structure having a rewiring layer and method for manufacturing the wafer-level chip scale packaging structure
US20220375866A1 (en) * 2021-05-21 2022-11-24 Intel Corporation Hybrid conductive vias for electronic substrates
US11616003B2 (en) * 2021-07-01 2023-03-28 Deca Technologies Usa, Inc. Stackable fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
US11728248B2 (en) 2021-07-01 2023-08-15 Deca Technologies Usa, Inc. Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects
US20230207523A1 (en) * 2021-12-28 2023-06-29 International Business Machines Corporation Wafer to wafer high density interconnects

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7034391B2 (en) * 2003-11-08 2006-04-25 Chippac, Inc. Flip chip interconnection pad layout
US20080136002A1 (en) 2006-12-07 2008-06-12 Advanced Chip Engineering Technology Inc. Multi-chips package and method of forming the same
US8492203B2 (en) 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US9831170B2 (en) * 2011-12-30 2017-11-28 Deca Technologies, Inc. Fully molded miniaturized semiconductor module
US8901748B2 (en) * 2013-03-14 2014-12-02 Intel Corporation Direct external interconnect for embedded interconnect bridge package
US9165885B2 (en) 2013-12-30 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Staggered via redistribution layer (RDL) for a package and a method for forming the same
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9640521B2 (en) * 2014-09-30 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die package with bridge layer and method for making the same
US9595496B2 (en) 2014-11-07 2017-03-14 Qualcomm Incorporated Integrated device package comprising silicon bridge in an encapsulation layer
US9443824B1 (en) * 2015-03-30 2016-09-13 Qualcomm Incorporated Cavity bridge connection for die split architecture
US20170098589A1 (en) 2015-10-05 2017-04-06 Mediatek Inc. Fan-out wafer level package structure
CN105261611B (zh) * 2015-10-15 2018-06-26 矽力杰半导体技术(杭州)有限公司 芯片的叠层封装结构及叠层封装方法
US10163856B2 (en) * 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9627365B1 (en) * 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
KR20170075125A (ko) * 2015-12-22 2017-07-03 에스케이하이닉스 주식회사 반도체 패키지 및 제조 방법
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US10032722B2 (en) 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US20180076179A1 (en) 2016-09-09 2018-03-15 Powertech Technology Inc. Stacked type chip package structure and manufacturing method thereof
US10410969B2 (en) 2017-02-15 2019-09-10 Mediatek Inc. Semiconductor package assembly
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10727198B2 (en) * 2017-06-30 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
KR102077455B1 (ko) 2017-07-04 2020-02-14 삼성전자주식회사 반도체 장치
US10290610B2 (en) * 2017-08-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. PoP device and method of forming the same
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
US11251157B2 (en) * 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
TWI652788B (zh) * 2017-11-09 2019-03-01 大陸商上海兆芯集成電路有限公司 晶片封裝結構及晶片封裝結構陣列
US20190244943A1 (en) * 2018-02-08 2019-08-08 Powertech Technology Inc. Semiconductor package and manufacturing method thereof
US10777531B2 (en) * 2018-12-28 2020-09-15 Taiwan Semiconductor Manufacturing Co., Ltd. Package contact structure, semiconductor package and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI730917B (zh) * 2020-10-27 2021-06-11 矽品精密工業股份有限公司 電子封裝件及其製法

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