TW202029452A - 封裝裝置 - Google Patents
封裝裝置 Download PDFInfo
- Publication number
- TW202029452A TW202029452A TW108137632A TW108137632A TW202029452A TW 202029452 A TW202029452 A TW 202029452A TW 108137632 A TW108137632 A TW 108137632A TW 108137632 A TW108137632 A TW 108137632A TW 202029452 A TW202029452 A TW 202029452A
- Authority
- TW
- Taiwan
- Prior art keywords
- interposer
- integrated circuit
- dielectric layer
- module
- die
- Prior art date
Links
- 238000004806 packaging method and process Methods 0.000 claims description 22
- 238000005538 encapsulation Methods 0.000 claims description 17
- 230000008878 coupling Effects 0.000 abstract description 14
- 238000010168 coupling process Methods 0.000 abstract description 14
- 238000005859 coupling reaction Methods 0.000 abstract description 14
- 239000008393 encapsulating agent Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 150
- 238000001465 metallisation Methods 0.000 description 78
- 238000000034 method Methods 0.000 description 41
- 239000000758 substrate Substances 0.000 description 34
- 239000000463 material Substances 0.000 description 31
- 230000008569 process Effects 0.000 description 27
- 229910052751 metal Inorganic materials 0.000 description 21
- 239000002184 metal Substances 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 18
- 239000004065 semiconductor Substances 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 15
- 238000004364 calculation method Methods 0.000 description 14
- 239000004020 conductor Substances 0.000 description 13
- 238000012545 processing Methods 0.000 description 10
- 238000012360 testing method Methods 0.000 description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 7
- 238000005476 soldering Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000005553 drilling Methods 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 229920002577 polybenzoxazole Polymers 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000013473 artificial intelligence Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000009434 installation Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000000523 sample Substances 0.000 description 3
- 238000012795 verification Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000013135 deep learning Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000010801 machine learning Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- -1 silicon nitride Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/40—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs
- H01L23/4006—Mountings or securing means for detachable cooling or heating arrangements ; fixed by friction, plugs or springs with bolts or screws
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
在實施例中,一種封裝裝置包括封裝組件,所述封裝組件包括:第一積體電路管芯;包封體,至少局部地環繞第一積體電路管芯;重佈線結構,位於包封體上,所述重佈線結構與第一積體電路管芯進行實體耦合及電耦合;第一模塊插座,貼合到重佈線結構;中介層,與第一模塊插座相鄰地貼合到重佈線結構,所述中介層的最外界限延伸超出重佈線結構的最外界限;以及外部連接件,貼合到中介層。
Description
本發明的實施例是有關於一種封裝裝置。
隨著半導體技術持續演化,積體電路管芯(integrated circuit dies)變得越來越小。此外,越來越多的功能被積體到管芯中。因此,管芯所需要的輸入/輸出(input/output,I/O)焊盤的數目增加,同時輸入/輸出焊盤可用的面積減小。輸入/輸出焊盤的密度隨著時間迅速上升,從而增加了進行管芯封裝的難度。
在一些封裝技術中,積體電路管芯在被封裝之前從晶片單體化。此種封裝技術的有利特徵是可形成扇出型封裝(fan-out packages),所述扇出型封裝使得管芯上的輸入/輸出焊盤能夠被重佈線到更大的面積。因此管芯的表面上的輸入/輸出焊盤的數目可增加。
本發明實施例提供一種封裝裝置,包括封裝組件。封裝組件包括第一積體電路管芯、包封體、重佈線結構、第一模塊插座、中介層以及外部連接件。包封體至少局部地環繞第一積體電路管芯。重佈線結構與第一積體電路管芯進行實體耦合及電耦合。第一模塊插座貼合到重佈線結構。中介層與第一模塊插座相鄰地貼合到重佈線結構。中介層的最外界限延伸超出重佈線結構的最外界限。外部連接件貼合到中介層。
本發明實施例提供一種封裝方法,包括提供封裝組件,封裝組件包括第一積體電路管芯、重佈線結構及導電連接件,重佈線結構實體耦合到及電耦合到第一積體電路管芯,導電連接件實體耦合到及電耦合到重佈線結構。在封裝組件周圍組裝夾具。將中介層放置在封裝組件及夾具之上。調整夾具以減小夾具與中介層的第一部分之間的間隙。對導電連接件進行回流焊,以將中介層實體耦合到及電耦合到重佈線結構。以及,移除夾具。
本發明實施例提供一種封裝方法,包括將積體電路管芯放置在載體基底上。使用包封體包封積體電路管芯。在包封體及積體電路管芯之上形成重佈線結構,重佈線結構的最外界限被設置成與重佈線結構的中心相距第一距離。將模塊插座貼合到重佈線結構。將中介層相鄰於模塊插座貼合到重佈線結構,中介層的內邊緣被設置成與重佈線結構的中心相距第二距離,中介層的外邊緣被設置成與重佈線結構的中心相距第三距離,第二距離小於第一距離,第三距離大於第一距離。以及,將外部連接件貼合到中介層。
以下公開提供用於實施本發明的不同特徵的許多不同實施例或實例。以下闡述組件及排列的具體實例以簡化本公開。當然,這些僅為實例且並非旨在進行限制。例如,以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成有附加特徵從而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外,本公開可能在各種實例中重複使用參考編號和/或字母。這種重複使用是出於簡潔及清晰的目的,而不是自身表示所論述的各種實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如“在...之下(beneath)”、“在...下方(below)”、“下部的(lower)”、“在...上方(above)”、“上部的(upper)”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。設備可具有其他取向(旋轉90度或處於其他取向),且本文中使用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例,將扇出型中介層整合在系統晶片(例如超大扇出型晶片級封裝(fan-out wafer-level package,FOWLP))上,從而使得系統晶片可用的輸入/輸出引腳數得到擴大。扇出型中介層被貼合在晶片的邊緣處且延伸超出晶片的邊緣。接著將外部連接件貼合到中介層。因此外部連接件可延伸超出晶片的最外界限,從而增大外部連接件可用的表面積。因此更多的外部連接件可包括在系統晶片內。
圖1示出根據一些實施例的積體電路管芯50的剖視圖。積體電路管芯50將在後續的處理中被封裝以形成積體電路封裝組件。積體電路管芯50可為邏輯管芯(例如,中央處理器(central processing unit,CPU)、圖形處理單元(graphics processing unit,GPU)、系統芯片(system-on-a-chip,SoC)、應用處理器(application processor,AP)、微控制器等)、存儲器管芯(例如,動態隨機存取存儲器(dynamic random access memory,DRAM)管芯、靜態隨機存取存儲器(static random access memory,SRAM)管芯等)、電源管理管芯(例如,電源管理積體電路(power management integrated circuit,PMIC)管芯)、射頻(radio frequency,RF)管芯、傳感器管芯、微機電系統(micro-electro-mechanical-system,MEMS)管芯、信號處理管芯(例如,數字信號處理(digital signal processing,DSP)管芯)、前端管芯(例如,模擬前端(analog front-end,AFE)管芯)、應用專用管芯(例如,應用專用積體電路(application-specific integrated circuit,ASIC)、現場可編程門陣列(field-programmable gate array,FPGA)等)、類似管芯或其組合。
積體電路管芯50可形成在晶片中,所述晶片可包括不同的裝置區,這些裝置區在後續步驟中被單體化以形成多個積體電路管芯。可根據適用的製造工藝對積體電路管芯50進行處理以形成積體電路。舉例來說,積體電路管芯50包括半導體基底52,例如經摻雜的或未經摻雜的矽、或者絕緣體上半導體(semiconductor-on-insulator,SOI)基底的有源層。半導體基底52可包含其他半導體材料,例如鍺;化合物半導體,包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦;合金半導體,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或其組合。也可使用其他基底,例如多層式基底或梯度基底(gradient substrate)。半導體基底52具有有時被稱為前側的有效表面(例如,圖1中的面朝上的表面)以及有時被稱為背側的非有效表面(例如,圖1中的面朝下的表面)。可在半導體基底52的前表面處形成裝置。所述裝置可為有源裝置(例如,晶體管、二極管等)或無源裝置(例如,電容器、電阻器、電感器等)。
內連結構54位於半導體基底52之上,且對所述裝置進行內連以形成積體電路。內連結構54可通過例如半導體基底52上的介電層中的金屬化圖案形成。金屬化圖案包括形成在一個或多個低介電常數(low-k)介電層中的金屬線及通孔。內連結構54的金屬化圖案電耦合到半導體基底52的裝置。積體電路管芯50還包括進行外部連接的焊盤(例如,鋁焊盤)。焊盤位於積體電路管芯50的有效側上,例如位於內連結構54中和/或內連結構54上。積體電路管芯50上(例如內連結構54的一些部分上)可具有一個或多個鈍化膜。管芯連接件56(例如導電支柱(例如由例如銅等金屬形成的導電支柱))實體耦合到及電耦合到內連結構54。管芯連接件56可通過例如鍍覆(plating)等形成。管芯連接件56與積體電路管芯50的相應的積體電路進行電耦合。
可選地,可在內連結構54的焊盤上設置焊料區(例如,焊料球或焊料凸塊)。焊料球可用于對積體電路管芯50執行芯片探針(chip probe,CP)測試。可對積體電路管芯50執行CP測試以確定積體電路管芯50是否是已知良好管芯(known good die,KGD)。因此,只有作為KGD的積體電路管芯50會經受後續處理及封裝,而未通過CP測試的管芯不會被封裝。在測試之後,焊料區可在後續的處理步驟中被移除。
介電層58可位於(或可不位於)積體電路管芯50的有效側上,例如鈍化膜及管芯連接件56上。介電層58在橫向上包封管芯連接件56,且介電層58在橫向上與積體電路管芯50共端(coterminous)。在開始時,介電層58可掩埋管芯連接件56,使得介電層58的最頂表面位於管芯連接件56的最頂表面上方。在管芯連接件56上設置有焊料區的一些實施例中,介電層58也可掩埋焊料區。作為另外一種選擇,焊料區可在形成介電層58之前被移除。
介電層58可為聚合物,例如聚苯並噁唑(polybenzoxazole,PBO)、聚醯亞胺(polyimide)、苯並環丁烯(benzocyclobutene,BCB)等;氮化物,例如氮化矽等;氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)等;類似材料或其組合。介電層58可例如通過旋轉塗布(spin coating)、疊層(lamination)、化學氣相沉積(chemical vapor deposition,CVD)等形成。在一些實施例中,管芯連接件56在積體電路管芯50的形成期間通過介電層58被暴露出。在一些實施例中,管芯連接件56保持被掩埋且在用於封裝積體電路管芯50的後續工藝期間被暴露出。暴露出管芯連接件56可移除管芯連接件56上可能存在的任何焊料區。
在一些實施例中,積體電路管芯50是包括多個半導體基底52的堆疊裝置。舉例來說,積體電路管芯50可為存儲器裝置,例如混合存儲器立方體(hybrid memory cube,HMC)裝置、高帶寬存儲器(high bandwidth memory,HBM)裝置或包括多個存儲器管芯的類似裝置。在此種實施例中,積體電路管芯50包括由基底穿孔(through-substrate via,TSV)進行內連的多個半導體基底52。半導體基底52中的每一者可具有(或可不具有)內連結構54。
圖2到圖11示出根據一些實施例的用於形成封裝組件100的工藝期間的中間步驟的剖視圖。封裝組件100是具有多個封裝區的重構晶片(reconstructed wafer),其中積體電路管芯50中的一者或多者被封裝在封裝區中的每一者中。封裝區包括計算部位102及連接部位104。計算部位102中的每一者可具有例如邏輯功能、存儲器功能等,且封裝組件100可為包括計算部位102及連接部位104的單個計算裝置,例如系統晶片總成。舉例來說,封裝組件100可為人工智能(artificial intelligence,AI)、機器學習(machine learning,ML)或深度學習(deep learning,DL)加速器,且每一計算部位102可為加速器的神經網絡節點。連接部位104中的每一者可具有例如外部連接件(在以下進一步論述),且封裝組件100的計算部位102可通過連接部位104連接到外部系統。封裝組件100的示例性系統包括AI服務器、高性能計算(high-performance computing,HPC)系統、高功率計算裝置、雲計算系統、邊緣計算系統等。
如上所述,封裝組件100將是系統晶片總成的部件。如此一來,封裝組件100是大的。舉例來說,封裝組件100可具有超過10,000 mm2
的表面積。大的表面積使得能夠具有大數量的計算部位102及連接部位104。圖2到圖11中示出兩個計算部位102(例如,計算部位102A及計算部位102B)及兩個連接部位104(例如,連接部位104A及連接部位104B),但應理解,封裝組件100可包括許多計算部位102及連接部位104,且所述部位可以各種方式佈置。
在圖2中,提供載體基底106,且在載體基底106上形成粘合層108。載體基底106可為玻璃載體基底、陶瓷載體基底等。載體基底106可為晶片,使得可在載體基底106上同時形成多個封裝。粘合層108可與載體基底106一起從將在後續步驟中形成的上覆結構被移除。在一些實施例中,粘合層108是任何合適的粘合劑、環氧樹脂、管芯貼合膜(die attach film,DAF)等,且粘合層108被施加在載體基底106的表面之上。
在圖3中,將積體電路管芯50貼合到粘合層108。在計算部位102A及計算部位102B以及連接部位104A及連接部位104B中的每一者中貼合期望類型及數量的積體電路管芯50。在一些實施例中,在計算部位102A及計算部位102B中貼合第一類型的積體電路管芯,例如SoC管芯50A,且在連接部位104A及連接部位104B中貼合第二類型的積體電路管芯,例如輸入/輸出接口管芯50B。儘管在一些部位中示出單個積體電路管芯50,然而應理解,在一些或所有的部位中可彼此相鄰地貼合多個積體電路管芯。當在每一部位中貼合有多個積體電路管芯時,所述多個積體電路管芯可具有相同的技術節點(technology node)或不同的技術節點。舉例來說,積體電路管芯50可包括形成在10 nm技術節點處的管芯、形成在7 nm技術節點處的管芯、類似管芯或其組合。
在圖4中,在各個組件上及各個組件周圍形成包封體110。在形成之後,包封體110包封積體電路管芯50。包封體110可為模塑化合物、環氧樹脂等,且可通過壓縮模塑(compression molding)、傳遞模塑(transfer molding)等施加。包封體110可以液體或半液體形式施加且然後被固化。在一些實施例中,包封體110形成在載體基底106之上,使得積體電路管芯50被掩埋或被覆蓋,且接著對包封體110執行平坦化工藝以暴露出積體電路管芯50的管芯連接件56。在平坦化工藝之後,包封體110的最頂表面、管芯連接件56的最頂表面及介電層58的最頂表面共面。所述平坦化工藝可為例如化學機械拋光(chemical-mechanical polish,CMP)。
在圖5到圖7中,在包封體110及積體電路管芯50之上形成具有精細特徵部分112A及粗特徵部分112B的重佈線結構112(參見圖7)。重佈線結構112包括金屬化圖案、介電層及凸塊下金屬(under-bump metallurgy,UBM)。金屬化圖案也可被稱作重佈線層或重佈線(redistribution line)。重佈線結構112被示出為具有六層金屬化圖案的實例。可在重佈線結構112中形成更多或更少的介電層及金屬化圖案。如果要形成更少的介電層及金屬化圖案,則可省略以下所論述的步驟及工藝。如果要形成更多的介電層及金屬化圖案,則可重複以下所論述的步驟及工藝。重佈線結構112的精細特徵部分112A及粗特徵部分112B包括不同大小的金屬化圖案及介電層。
在圖5中,形成重佈線結構112的精細特徵部分112A。重佈線結構112的精細特徵部分112A包括介電層114、介電層118、介電層122及介電層126;以及金屬化圖案116、金屬化圖案120及金屬化圖案124。在一些實施例中,介電層118、介電層122及介電層126由相同的介電材料形成,且被形成為相同的厚度。同樣地,在一些實施例中,金屬化圖案116、金屬化圖案120及金屬化圖案124的導電特徵由相同的導電材料形成,且被形成為相同的厚度。具體來說,介電層118、介電層122及介電層126具有小的第一厚度T1
,例如處於約7 µm到約50 µm範圍內的第一厚度T1
,且金屬化圖案116、金屬化圖案120及金屬化圖案124的導電特徵具有小的第二厚度T2
,例如處於約2 µm到約20 µm範圍內的第二厚度T2
。
作為形成重佈線結構112的精細特徵部分112A的實例,在包封體110、介電層58及管芯連接件56上沉積介電層114。在一些實施例中,介電層114是由可使用光刻掩模進行圖案化的感光性材料(例如PBO、聚醯亞胺、BCB等)形成。介電層114可通過旋轉塗布、疊層、CVD、類似工藝或其組合來形成。接著將介電層114圖案化。所述圖案化會形成暴露出管芯連接件56的一些部分的開口。所述圖案化可通過可接受的工藝來進行,例如通過當介電層114是感光性材料時將介電層114暴露到光或通過使用例如各向異性刻蝕(anisotropic etch)進行刻蝕來進行。如果介電層114是感光性材料,則可在曝光之後將介電層114顯影。
接著形成金屬化圖案116。金屬化圖案116具有線部分(也被稱作導電線或跡線)且具有通孔部分(也被稱作導通孔),線部分位於介電層114的主表面上且沿介電層114的主表面延伸,通孔部分延伸穿過介電層114以與積體電路管芯50的管芯連接件56進行實體耦合及電耦合。作為形成金屬化圖案116的實例,在介電層114之上及在延伸穿過介電層114的開口中形成晶種層。在一些實施例中,晶種層是金屬層,所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層以及位於所述鈦層之上的銅層。晶種層可使用例如物理氣相沉積(physical vapor deposition,PVD)等來形成。接著在晶種層上形成光刻膠並將所述光刻膠圖案化。光刻膠可通過旋轉塗布等形成且可被暴露到光以進行圖案化。光刻膠的圖案對應於金屬化圖案116。所述圖案化會形成穿過光刻膠的開口以暴露出晶種層。接著在光刻膠的開口中及在晶種層的被暴露出的部分上形成導電材料。所述導電材料可通過鍍覆(例如電鍍或無電鍍覆)等來形成。所述導電材料可包括金屬,如銅、鈦、鎢、鋁等。所述導電材料與晶種層的下伏部分的組合會形成金屬化圖案116。移除光刻膠及晶種層的上面未形成有導電材料的部分。光刻膠可通過例如使用氧等離子體等可接受的灰化工藝(ashing process)或剝除工藝(stripping process)來移除。一旦光刻膠被移除,便例如使用可接受的刻蝕工藝(例如通過濕式刻蝕或幹式刻蝕)來移除晶種層的被暴露出的部分。
接著在金屬化圖案116及介電層114上沉積介電層118。介電層118可採用與介電層114相似的方式以及由與介電層114相似的材料形成。接著形成金屬化圖案120。金屬化圖案120具有線部分且具有通孔部分,線部分位於介電層118的主表面上且沿介電層118的主表面延伸,通孔部分延伸穿過介電層118以與金屬化圖案116進行實體耦合及電耦合。金屬化圖案120可採用與金屬化圖案116相似的方式以及由與金屬化圖案116相似的材料形成。
接著在金屬化圖案120及介電層118上沉積介電層122。介電層122可採用與介電層114相似的方式以及由與介電層114相似的材料形成。接著形成金屬化圖案124。金屬化圖案124具有線部分且具有通孔部分,線部分位於介電層122的主表面上且沿介電層122的主表面延伸,通孔部分延伸穿過介電層122以與金屬化圖案120進行實體耦合及電耦合。金屬化圖案124可採用與金屬化圖案116相似的方式以及由與金屬化圖案116相似的材料形成。
在金屬化圖案124及介電層122上沉積介電層126。介電層126可採用與介電層114相似的方式以及由與介電層114相似的材料形成。
在圖6中,形成重佈線結構112的粗特徵部分112B。重佈線結構112的粗特徵部分112B包括介電層130、介電層134及介電層138;以及金屬化圖案128、金屬化圖案132及金屬化圖案136。在一些實施例中,介電層130、介電層134及介電層138由相同的介電材料形成,且被形成為相同的厚度。同樣地,在一些實施例中,金屬化圖案128、金屬化圖案132及金屬化圖案136的導電特徵由相同的導電材料形成,且被形成為相同的厚度。具體來說,介電層130、介電層134及介電層138具有大的第三厚度T3
,例如處於約7 µm到約50 µm範圍內的第三厚度T3
,且金屬化圖案128、金屬化圖案132及金屬化圖案136的導電特徵具有大的第四厚度T4
,例如處於約2 µm到約20 µm範圍內的第四厚度T4
。第三厚度T3
大於第一厚度T1
(參見圖5),且第四厚度T4
大於第二厚度T2
(參見圖5)。
作為形成重佈線結構112的粗特徵部分112B的實例,形成金屬化圖案128。金屬化圖案128具有線部分且具有通孔部分,線部分位於介電層126的主表面上且沿介電層126的主表面延伸,通孔部分延伸穿過介電層126以與金屬化圖案124進行實體耦合及電耦合。作為形成金屬化圖案128的實例,在介電層126之上及在延伸穿過介電層126的開口中形成晶種層。在一些實施例中,晶種層是金屬層,所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層以及位於所述鈦層之上的銅層。晶種層可使用例如PVD等來形成。接著在晶種層上形成光刻膠並將所述光刻膠圖案化。光刻膠可通過旋轉塗布等形成且可被暴露到光以進行圖案化。光刻膠的圖案對應於金屬化圖案128。所述圖案化會形成穿過光刻膠的開口以暴露出晶種層。接著在光刻膠的開口中及在晶種層的被暴露出的部分上形成導電材料。所述導電材料可通過鍍覆(例如電鍍或無電鍍覆)等來形成。所述導電材料可包括金屬,如銅、鈦、鎢、鋁等。導電材料與晶種層的下伏部分的組合會形成金屬化圖案128。移除光刻膠及晶種層的上面未形成有導電材料的部分。光刻膠可通過例如使用氧等離子體等可接受的灰化工藝或剝除工藝來移除。一旦光刻膠被移除,便例如使用可接受的刻蝕工藝(例如通過濕式刻蝕或幹式刻蝕)來移除晶種層的被暴露出的部分。
接著在金屬化圖案128及介電層126上沉積介電層130。在一些實施例中,介電層130是由可使用光刻掩模進行圖案化的感光性材料(例如PBO、聚醯亞胺、BCB等)形成。介電層130可通過旋轉塗布、疊層、CVD、類似工藝或其組合來形成。接著形成金屬化圖案132。金屬化圖案132具有線部分且具有通孔部分,線部分位於介電層130的主表面上且沿介電層130的主表面延伸,通孔部分延伸穿過介電層130以與金屬化圖案128進行實體耦合及電耦合。金屬化圖案132可採用與金屬化圖案128相似的方式以及由與金屬化圖案128相似的材料形成。
接著在金屬化圖案132及介電層130上沉積介電層134。介電層134可採用與介電層130相似的方式以及由與介電層130相似的材料形成。接著形成金屬化圖案136。金屬化圖案136具有線部分且具有通孔部分,線部分位於介電層134的主表面上且沿介電層134的主表面延伸,通孔部分延伸穿過介電層134以與金屬化圖案132進行實體耦合及電耦合。金屬化圖案136可採用與金屬化圖案128相似的方式以及由與金屬化圖案128相似的材料形成。
在金屬化圖案136及介電層134上沉積介電層138。介電層138可採用與介電層130相似的方式以及由與介電層130相似的材料形成。
在圖7中,形成凸塊下金屬(UBM)140以用於對重佈線結構112進行外部連接。UBM 140具有凸塊部分且具有通孔部分,凸塊部分位於介電層138的主表面上且沿介電層138的主表面延伸,通孔部分延伸穿過介電層138以與金屬化圖案136進行實體耦合及電耦合。因此,UBM 140電耦合到積體電路管芯50。UBM 140可採用與金屬化圖案136相似的方式以及由與金屬化圖案136相似的材料形成。在一些實施例中,UBM 140具有與金屬化圖案116、金屬化圖案120、金屬化圖案124、金屬化圖案128、金屬化圖案132及金屬化圖案136不同的大小。
在形成之後,重佈線結構112的最外界限從封裝組件100的中心延伸距離D1
。如上所述,封裝組件100是大的。因此距離D1
也是大的。舉例來說,距離D1
可處於約50 mm到約200 mm範圍內。
在圖8中,執行載體基底剝離(carrier substrate debonding)以將載體基底106從包封體110及積體電路管芯50分離(或“剝離”)。在一些實施例中,所述剝離包括通過例如研磨工藝或平坦化工藝(例如,CMP)將載體基底106及粘合層108移除。在移除之後,積體電路管芯50的背側表面被暴露出,且包封體110的背側表面與積體電路管芯50的背側表面是齊平的。接著將所述結構放置在條帶142上。
在圖9中,穿過封裝組件100形成螺栓(bolt)孔144。螺栓孔144可通過鑽孔工藝(例如雷射鑽孔(laser drilling)、機械鑽孔(mechanical drilling)等)形成。螺栓孔144可通過利用鑽孔工藝鑽制螺栓孔144的輪廓且接著移除由所述輪廓分離的材料來形成。
在圖10中,在UBM 140上形成導電連接件146。導電連接件146可為球柵陣列(ball grid array,BGA)連接件、焊料球、金屬支柱、受控塌陷芯片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊等。導電連接件146可包含導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合。在一些實施例中,導電連接件146通過以下方法來形成:在開始時通過蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等形成焊料或焊料膏層。一旦已在所述結構上形成焊料層,便可執行回流焊(reflow)以將材料塑形成期望的凸塊形狀。
在圖11中,將模塊插座(module socket)148及中介層150貼合到重佈線結構112。模塊插座148及中介層150是用於對封裝組件100(在以下進一步論述)進行外部連接的接口。模塊插座148及中介層150包括用於對重佈線結構112進行實體連接及電連接的焊盤152(例如鋁焊盤)。模塊插座148的焊盤152與中介層150的焊盤152可具有(或可不具有)相同的節距P1
。舉例來說,節距P1
可為小的節距,例如處於約0.1 mm到約1 mm範圍內的節距P1
。貼合模塊插座148及中介層150可包括使用例如拾取及放置(pick-and-place)技術將模塊插座148及中介層150放置在重佈線結構112上,且接著對導電連接件146進行回流焊,以將焊盤152實體耦合到及電耦合到UBM 140。可對導電連接件146執行回流焊,使得模塊插座148與中介層150同時貼合到重佈線結構112。在所示出的實施例中,模塊插座148貼合在計算部位102A及計算部位102B處,且中介層150貼合在連接部位104A及連接部位104B處。可形成底部填充膠154以填充模塊插座148與重佈線結構112之間的間隙。底部填充膠154可在模塊插座148及中介層150被貼合之後通過毛細管流動工藝(capillary flow process)形成,或可在模塊插座148及中介層150被貼合之前通過合適的沉積方法形成。
模塊插座148是模塊(在以下進一步論述)的電接口及實體接口,所述模塊可在製造封裝組件100之後被安裝在計算部位102A及計算部位102B處。舉例來說,封裝組件100的用戶可在模塊插座148中安裝模塊以在計算部位102A及計算部位102B處形成完整的功能系統。選擇用於安裝的模塊的類型取決於計算部位102A及計算部位102B處的期望的功能系統的類型。可安裝在模塊插座148中的模塊的實例包括存儲器模塊、電壓調節器(voltage regulator)模塊、電源供應器模塊、積體無源裝置(integrated passive device,IPD)模塊等。模塊插座148可包括可包含不同材料的不同組件,例如基座(chassis)、焊盤152及接觸引腳(contact pin)。
中介層150是附加的外部連接件(在以下進一步論述)到連接部位104A及連接部位104B的電接口及實體接口。中介層150可包括例如芯體及設置在芯體的相對的側上的一個或多個金屬化層以用於對電連接進行扇入及扇出。可在中介層150中形成任何數量的金屬化層。舉例來說,中介層150中的金屬化層的數量可處於2到20範圍內。除了具有位於與重佈線結構112面對的第一側處的焊盤152,中介層150還具有位於與第一側相對的第二側處的焊盤156。焊盤156具有節距P2
,節距P2
大於焊盤152的節距P1
。舉例來說,節距P2
可為大的節距,例如處於約0.5 mm到約3 mm範圍內(例如約0.8 mm)的節距P2
。
中介層150沿封裝組件100的周邊放置,其中中介層150的最外界限延伸超出重佈線結構112的最外界限。具體來說,將中介層150放置成使得中介層150的內邊緣被設置成與封裝組件100的中心相距距離D2
且中介層150的外邊緣被設置成與封裝組件100的中心相距距離D3
,其中距離D2
小於距離D1
(參見圖6),且距離D3
大於距離D1
。舉例來說,距離D2
可處於約35 mm到約140 mm範圍內,且距離D3
可處於約65 mm到約260 mm範圍內。在一些實施例中,距離D2
可為距離D1
的至少一半。重佈線結構112的大多數面積可被中介層150佔用,從而增大模塊插座148可用的面積。
此外,將外部連接件158貼合到中介層150。外部連接件158是封裝組件100到外部系統的電接口及實體接口。舉例來說,當封裝組件100被安裝以作為更大的外部系統(例如數據中心)的部件時,外部連接件158可用于將封裝組件100耦合到所述外部系統。外部連接件158的實例包括帶狀線纜(ribbon cable)、柔性印刷電路(flexible printed circuit)等的接受件(receptor)。外部連接件158包括焊盤160,焊盤160可相似於焊盤156(且具有與焊盤156相同的節距P2
)。外部連接件158可包括可包含不同材料的不同組件,例如基座、焊盤160及外部連接引腳。外部連接件158還包括位於焊盤160上的導電連接件162,導電連接件162可相似於導電連接件146。焊盤160及導電連接件162用於對中介層150進行實體連接及電連接。貼合外部連接件158可包括使用例如拾取及放置技術將外部連接件158放置在中介層150上,且接著對導電連接件162進行回流焊,以與焊盤156及焊盤160進行實體耦合及電耦合。由於外部連接件158堆疊在中介層150上,因此在貼合之後外部連接件158在垂直方向上相對於模塊插座148偏移。因此外部連接件158的最外界限延伸超出重佈線結構112的最外界限。在一些實施例中,外部連接件158僅局部地在橫向上與重佈線結構112交疊。在一些實施例中,外部連接件158不在橫向上與重佈線結構112交疊。
一些HPC系統可能需要與外部系統進行大量的外部連接。舉例來說,當封裝組件100是AI加速器時,連接部位104可包括數千或數萬的外部連接。然而,如上所述,外部連接件158的焊盤160具有大的節距P2
。使用中介層150使得外部連接件158能夠延伸超出封裝組件100的最外界限,從而增大外部連接件158可用的表面積。因此更多的外部連接件158可被包括在封裝組件100內,從而增大可用的外部連接的量。
模塊插座148及外部連接件158可以各種佈局貼合到重佈線結構112。圖2到圖11所示剖視圖示出一個示例性佈局。圖12是根據一些實施例的封裝組件100的俯視圖。在此實施例中,計算部位102排列成包括二十五個計算部位102的柵格(grid),且所述柵格的側的周圍設置有四個連接部位104。模塊插座148中的每一者直接上覆在對應的計算部位102的SoC管芯50A之上且電耦合到SoC管芯50A。中介層150中的每一者直接上覆在一個或多個連接部位104的輸入/輸出接口管芯50B之上且電耦合到輸入/輸出接口管芯50B。中介層150及外部連接件158延伸超出封裝組件100的最外界限。
中介層150在俯視圖中具有寬度W1
及長度L1
。舉例來說,寬度W1
可處於約15 mm到約45.5 mm範圍內,且長度L1
可處於約30 mm到約250 mm範圍內。同樣地,外部連接件158在俯視圖中具有寬度W2
及長度L2
,其中寬度W2
小於寬度W1
,且長度L2
小於長度L1
。舉例來說,寬度W2
可處於約10 mm到約32 mm範圍內,且長度L2
可處於約20 mm到約245 mm範圍內。此外,外部連接件158在俯視圖中彼此間隔開距離D4
,且在俯視圖中與中介層150的邊緣間隔開距離D5
。舉例來說,距離D4
可處於約0.2 mm到約2 mm範圍內,且距離D5
可處於約0.2 mm到約2 mm範圍內。此外,計算部位102在俯視圖中可具有寬度W3
及長度L3
。舉例來說,寬度W3
可處於約15 mm到約36.67 mm範圍內,且長度L3
可處於約15 mm到約36.67 mm範圍內。此外,計算部位102在俯視圖中彼此間隔開距離D6
,且在俯視圖中與連接部位104間隔開距離D7
。舉例來說,距離D6
可處於約0.1 mm到約0.5 mm範圍內,且距離D7
可處於約0.1 mm到約0.5 mm範圍內。
可利用若干技術將模塊插座148、中介層150及外部連接件158貼合到重佈線結構112。如以下所進一步論述,在一些實施例中,模塊插座148、中介層150及外部連接件158通過使用可調整的夾具(jig)進行貼合,在將中介層150實體耦合到重佈線結構112之前,可調整的夾具能夠支撐中介層150。也可使用其他技術對模塊插座148、中介層150及外部連接件158進行貼合。
圖13示出根據一些實施例的系統晶片總成的剖視圖。系統晶片總成是通過將封裝組件100固定在熱模塊200與機械支架300之間形成。熱模塊200可為散熱器(heat sink)、熱散佈器(heat spreader)、冷板等。機械支架300是可由具有高剛度的材料(例如金屬(例如,鋼、鈦、鈷等))形成的剛性支撐件。機械支架300實體抵靠重佈線結構112的一些部分。通過將封裝組件100夾持在熱模塊200與機械支架300之間,可減小封裝組件100的翹曲(例如由載體基底剝離引起的翹曲)。機械支架300是柵格,所述柵格具有暴露出模塊插座148的一些部分的開口,以易於模塊安裝。
將封裝組件100從條帶142移除並使用螺栓202緊固在熱模塊200與機械支架300之間。螺栓202螺紋穿過封裝組件100的螺栓孔144、穿過熱模塊200中對應的螺栓孔且穿過機械支架300中對應的螺栓孔。將緊固件204螺旋到螺栓202上並進行旋緊以將封裝組件100夾持在熱模塊200與機械支架300之間。緊固件204可為例如螺旋到螺栓202的螺母(nut)。緊固件204貼合到系統晶片總成的兩側處(例如,具有熱模塊200的一側(有時被稱作背側)處以及具有機械支架300的一側(有時被稱作前側)處)的螺栓202。在貼合之後,機械支架300的一些部分設置在模塊插座148之間以及模塊插座148與中介層150之間。
在將各個組件緊固在一起之前,可在封裝組件100的背側上分配熱界面材料(thermal interface material,TIM)208,以將熱模塊200實體耦合到及熱耦合到積體電路管芯50。在一些實施例中,TIM 208由包含銦及HM03類型的材料的膜形成。在緊固期間,對緊固件204進行旋緊,從而增大由熱模塊200及機械支架300施加到封裝組件100的機械力。對緊固件204進行旋緊直到熱模塊200對TIM 208施加期望大小的壓力。
圖14示出在模塊插座148中安裝模塊400之後系統晶片總成的剖視圖。如上所述,模塊400可為存儲器模塊、電壓調節器模塊、電源供應器模塊、積體無源裝置(IPD)模塊等。模塊400包括導電連接件402,導電連接件402插置在對應的接受件中以與模塊插座148的接觸引腳進行實體耦合及電耦合。因此模塊400被固定在模塊插座148中,以在計算部位102A及計算部位102B處形成完整的功能系統。
圖15A、圖15B、圖15C及圖15D示出根據其他實施例的系統晶片總成的剖視圖。在這些實施例中,將除了外部連接件158之外的其他特徵貼合到中介層150。在圖15A中,裝置模塊164與外部連接件158相鄰地貼合到中介層150。在圖15B中,無源裝置166與外部連接件158相鄰地貼合到中介層150。在圖15C中,模塊400(參見圖14)的附加的模塊插座148與外部連接件158相鄰地貼合到中介層150。在圖15D中,裝置模塊164、無源裝置166及模塊插座148的組合與外部連接件158相鄰地貼合到中介層150。可將任何期望的連接件及模塊的組合貼合到中介層150。
裝置模塊164可包括若干類型的裝置。裝置模塊164可包括有源裝置。舉例來說,裝置模塊164可為邏輯裝置、存儲器裝置、電源管理裝置、射頻(RF)裝置、信號處理裝置、前端裝置、應用專用裝置、輸入/輸出裝置、類似裝置或其組合。裝置模塊164可為管芯、多芯片模塊(multi-chip module,MCM)、扇出型封裝、芯片尺寸封裝(chip-scale package)等,且可通過倒裝芯片(flip-chip)連接、打線結合(wire bond)等連接到中介層150。
無源裝置166可包括若干類型的裝置。舉例來說,無源裝置166可為電阻器(例如膜電阻器(film resistor))、電感器(例如線圈電感器(coil inductor))、電容器(例如金屬電極多層式陶瓷芯片(multilayered ceramic chip,MLCC))電容器等。無源裝置166可為離散無源裝置,或可為積體無源裝置(IPD)。
圖16A到圖19B是根據一些實施例的在用於將模塊插座148、中介層150及外部連接件158貼合到封裝組件100的工藝期間的中間步驟的各種視圖。可在例如以上針對圖11所述的中間步驟期間執行所示的工藝。圖16A、圖17A、圖18A及圖19A是示出封裝組件100的邊緣處的單個計算部位102A及單個連接部位104A的剖視圖。圖16B、圖17B、圖18B及圖19B是與封裝組件100的相應的剖視圖對應的俯視圖。
在圖16A及圖16B中,在封裝組件100周圍組裝可調整的夾具。可調整的夾具將封裝組件100固定在適當位置,並將封裝組件100夾合在一起,以減小回流焊操作(在以下進一步論述)期間的晶片翹曲。可調整的夾具包括底部夾具部分502、中間夾具部分504及頂部夾具部分506。底部夾具部分502、中間夾具部分504及頂部夾具部分506可由金屬(例如鋼、鈦、鈷等)形成。底部夾具部分502放置在條帶142下方,且可用於在後續處理中支撐封裝組件100。中間夾具部分504放置在封裝組件100周圍,且在後續處理中在橫向上固定封裝組件100。頂部夾具部分506放置在封裝組件100之上,且在後續處理中夾持封裝組件100以減小晶片翹曲。底部夾具部分502與頂部夾具部分506一同包括一對磁體508。磁體508將底部夾具部分502與頂部夾具部分506保持在一起,且還用於在貼合中介層150(在以下進一步論述)期間對中間夾具部分504進行調整。磁體508可為耦合到電流源(未示出)且由電流源控制的電磁體。中間夾具部分504由被磁體508產生的磁場磁性吸引的材料形成。因此,可通過調整流經底部夾具部分502和/或頂部夾具部分506中的磁體508的電流量來改變中間夾具部分504的位置。頂部夾具部分506還包括開口510。在組裝可調整的夾具之後,頂部夾具部分506中的開口510暴露出封裝組件100的計算部位102及連接部位104。
在圖17A及圖17B中,將模塊插座148及中介層150貼合到重佈線結構112。如上所述,貼合模塊插座148及中介層150可包括將模塊插座148及中介層150放置在重佈線結構112上,且接著對導電連接件146進行回流焊。模塊插座148及中介層150被放置在頂部夾具部分506的開口510中、重佈線結構112的被開口510暴露出的部分上。應注意,可將中介層150放置在重佈線結構112及中間夾具部分504之上。在放置之後,中介層150的一些部分在橫向上延伸超出重佈線結構112的最外界限且在中間夾具部分504之上延伸,且中介層150的其他部分在橫向上局限於重佈線結構112的最外界限內。
在放置期間,可對中間夾具部分504進行調整以減小中間夾具部分504與中介層150之間的間隙G1
。具體來說,可對中間夾具部分504進行調整以消除或至少減小間隙G1
,使得中介層150實質上是齊平的且接觸所有期望的導電連接件146。在一些實施例中,中間夾具部分504具有充足的推力(throw)使間隙G1
能夠在每一方向上調整高達10 µm。對中間夾具部分504的調整可通過改變供應到磁體508的電流量而使用磁體508來完成。因此在放置中介層150之後以及進行回流焊之前,中介層150可由中間夾具部分504支撐。在對導電連接件146進行回流焊之後,模塊插座148與中介層150同時貼合到重佈線結構112。底部填充膠154可在模塊插座148及中介層150被貼合之前或之後形成。
在圖18A及圖18B中,將外部連接件158貼合到中介層150。此外,也可將模塊插座148、裝置模塊164和/或無源裝置166貼合到中介層150。如上所述,貼合外部連接件158、模塊插座148、裝置模塊164和/或無源裝置166可包括將外部連接件158、模塊插座148、裝置模塊164和/或無源裝置166放置在中介層150上,且接著對導電連接件162進行回流焊。
在圖19A及圖19B中,移除包括底部夾具部分502、中間夾具部分504及頂部夾具部分506的可調整的夾具。由於可調整的夾具的組件由磁體508保持在一起,因此可通過將底部夾具部分502與頂部夾具部分506拉開直到磁體508的力被克服來完成移除。
當模塊插座148、裝置模塊164和/或無源裝置166被貼合到中介層150時,模塊插座148、裝置模塊164和/或無源裝置166在俯視圖中可具有寬度W4
及長度L4
。舉例來說,寬度W4
可處於約3 mm到約9.5 mm範圍內,且長度L4
可處於約10 mm到約30.8 mm範圍內。寬度W4
可小於寬度W2
(參見圖12),且長度L4
可小於長度L2
(參見圖12)。此外,中介層150上的模塊插座148、裝置模塊164和/或無源裝置166在俯視圖中彼此間隔開距離D8
,且在俯視圖中與中介層150的邊緣間隔開距離D9
。舉例來說,距離D8
可處於約0.1 mm到約0.5 mm範圍內,且距離D9
可處於約0.2 mm到約2 mm範圍內。
實施例可實現各種優點。如上所述,連接部位104可依據實施封裝組件100的系統的類型而包括數千或數萬的外部連接。使用中介層150使外部連接件158能夠延伸超出封裝組件100的最外界限,從而增大外部連接件158可用的表面積。因此可包括更多的外部連接件158,從而使更多的外部連接包括在封裝組件100內。
還可包括其他特徵及工藝。舉例來說,可包括測試結構以幫助對三維(three-dimensional,3D)封裝或三維積體電路(three-dimensional integrated circuit,3DIC)裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基底上形成的測試焊盤(test pad),以便能夠對3D封裝或3DIC進行測試、使用探針和/或探針卡(probe card)等。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可與包含對已知良好管芯進行中間驗證的測試方法結合使用以提高良率並降低成本。
在實施例中,一種封裝裝置包括封裝組件,所述封裝組件包括:第一積體電路管芯;包封體,至少局部地環繞所述第一積體電路管芯;重佈線結構,位於所述包封體上,所述重佈線結構與所述第一積體電路管芯進行實體耦合及電耦合;第一模塊插座,貼合到所述重佈線結構;中介層,與所述第一模塊插座相鄰地貼合到所述重佈線結構,所述中介層的最外界限延伸超出所述重佈線結構的最外界限;以及外部連接件,貼合到所述中介層。
在所述裝置的一些實施例中,所述中介層包括位於所述中介層的第一側上的第一焊盤及位於所述中介層的第二側上的第二焊盤,所述第一焊盤與所述重佈線結構進行實體耦合及電耦合,所述第二焊盤與所述外部連接件進行實體耦合及電耦合,所述第一焊盤具有第一節距,所述第二焊盤具有第二節距,所述第二節距大於所述第一節距。在所述裝置的一些實施例中,所述第一節距處於0.1 mm到1 mm範圍內,且所述第二節距處於0.5 mm到3 mm範圍內。在所述裝置的一些實施例中,所述中介層包括金屬化層,所述金屬化層的數量處於2到20範圍內。在所述裝置的一些實施例中,所述重佈線結構的所述最外界限被設置成與所述封裝組件的中心相距第一距離,所述中介層的內邊緣被設置成與所述封裝組件的所述中心相距第二距離,且所述中介層的外邊緣被設置成與所述封裝組件的所述中心相距第三距離,所述第二距離小於所述第一距離,所述第三距離大於所述第一距離。在所述裝置的一些實施例中,所述第二距離為所述第一距離的至少一半。在所述裝置的一些實施例中,所述封裝組件還包括第二積體電路管芯,所述第二積體電路管芯與所述外部連接件相鄰地貼合到所述中介層。在所述裝置的一些實施例中,所述封裝組件還包括無源裝置,所述無源裝置與所述外部連接件相鄰地貼合到所述中介層。在所述裝置的一些實施例中,所述封裝組件還包括第二模塊插座,所述第二模塊插座與所述外部連接件相鄰地貼合到所述中介層。在所述裝置的一些實施例中,所述中介層是貼合到所述重佈線結構的多個中介層中的一者,所述中介層中的每一者具有延伸超出所述重佈線結構的所述最外界限的最外界限。在一些實施例中,所述裝置還包括:熱界面材料,位於所述第一積體電路管芯的背側表面上;以及熱模塊,通過所述熱界面材料熱耦合到及實體耦合到所述第一積體電路管芯的所述背側表面。在一些實施例中,所述裝置還包括:機械支架,所述封裝組件設置在所述熱模塊與所述機械支架之間;以及螺栓,延伸穿過所述機械支架、所述封裝組件及所述熱模塊。在所述裝置的一些實施例中,所述封裝組件還包括底部填充膠,所述底部填充膠設置在所述中介層與所述重佈線結構之間。
在實施例中,一種封裝方法包括:提供封裝組件,所述封裝組件包括第一積體電路管芯、重佈線結構及導電連接件,所述重佈線結構實體耦合到及電耦合到所述第一積體電路管芯,所述導電連接件實體耦合到及電耦合到所述重佈線結構;在所述封裝組件周圍組裝夾具;將中介層放置在所述封裝組件及所述夾具之上,所述夾具支撐所述中介層的第一部分;調整所述夾具以減小所述夾具與所述中介層的所述第一部分之間的間隙;對所述導電連接件進行回流焊,以將所述中介層實體耦合到及電耦合到所述重佈線結構;以及移除所述夾具。
在所述方法的一些實施例中,在移除所述夾具之後,所述中介層的所述第一部分在橫向上延伸超出所述重佈線結構的最外界限,且所述中介層的第二部分在橫向上局限於所述重佈線結構的所述最外界限內。在所述方法的一些實施例中,所述夾具包括底部部分、頂部部分及中間部分,所述底部部分支撐所述封裝組件,所述頂部部分具有暴露出所述封裝組件的開口,所述中間部分設置在所述頂部部分與所述底部部分之間。在所述方法的一些實施例中,調整所述夾具包括通過調整磁場來移動所述中間部分。在所述方法的一些實施例中,將所述中介層放置在所述封裝組件及所述夾具之上包括將所述中介層放置在所述夾具的所述頂部部分的所述開口中。
在實施例中,一種封裝方法包括:將積體電路管芯放置在載體基底上;使用包封體包封所述積體電路管芯;在所述包封體及所述積體電路管芯之上形成重佈線結構,所述重佈線結構的最外界限被設置成與所述重佈線結構的中心相距第一距離;將模塊插座貼合到所述重佈線結構;將中介層相鄰於所述模塊插座貼合到所述重佈線結構,所述中介層的內邊緣被設置成與所述重佈線結構的所述中心相距第二距離,所述中介層的外邊緣被設置成與所述重佈線結構的所述中心相距第三距離,所述第二距離小於所述第一距離,所述第三距離大於所述第一距離;以及將外部連接件貼合到所述中介層。
在所述方法的一些實施例中,所述第二距離為所述第一距離的至少一半。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解,他們可容易地使用本公開作為設計或修改其他工藝及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到,這些等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
50:積體電路管芯
50A:系統芯片(SoC)管芯
50B:輸入/輸出(I/O)接口管芯
52:半導體基底
54:內連結構
56:管芯連接件
58、114、118、122、126、130、134、138:介電層
100:封裝組件
102、102A、102B:計算部位
104、104A、104B:連接部位
106:載體基底
108:粘合層
110:包封體
112:重佈線結構
112A:精細特徵部分
112B:粗特徵部分
116、120、124、128、132、136:金屬化圖案
140:凸塊下金屬(UBM)
142:條帶
144:螺栓孔
146、162、402:導電連接件
148:模塊插座
150:中介層
152、156、160:焊盤
154:底部填充膠
158:外部連接件
164:裝置模塊
166:無源裝置
200:熱模塊
202:螺栓
204:緊固件
208:熱界面材料(TIM)
300:機械支架
400:模塊
502:底部夾具部分
504:中間夾具部分
506:頂部夾具部分
508:磁體
510:開口
D1、D2、D3、D4、D5、D6、D7、D8、D9:距離
G1:間隙
L1、L2、L3、L4:長度
P1、P2:節距
T1:第一厚度
T2:第二厚度
T3:第三厚度
T4:第四厚度
W1、W2、W3、W4:寬度
結合附圖閱讀以下詳細說明,會最好地理解本公開的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為使論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1示出根據一些實施例的積體電路管芯的剖視圖。
圖2到圖11示出根據一些實施例的用於形成封裝組件的工藝期間的中間步驟的剖視圖。
圖12是根據一些實施例的封裝組件的俯視圖。
圖13示出根據一些實施例的系統晶片(system-on-wafer)總成的剖視圖。
圖14示出根據一些實施例的系統晶片總成中的模塊安裝的剖視圖。
圖15A、圖15B、圖15C及圖15D示出根據其他實施例的系統晶片總成的剖視圖。
圖16A到圖19B是根據一些實施例的用於將中介層貼合到封裝組件的工藝期間的中間步驟的各種視圖。
50:積體電路管芯
100:封裝組件
102、102A、102B:計算部位
104、104A、104B:連接部位
110:包封體
112:重佈線結構
112A:精細特徵部分
112B:粗特徵部分
140:凸塊下金屬(UBM)
142:條帶
144:螺栓孔
146、162:導電連接件
148:模塊插座
150:中介層
152、156、160:焊盤
154:底部填充膠
158:外部連接件
D2、D3:距離
P1、P2:節距
Claims (1)
- 一種封裝裝置,包括: 封裝組件,包括: 第一積體電路管芯; 包封體,至少局部地環繞所述第一積體電路管芯; 重佈線結構,位於所述包封體上,所述重佈線結構與所述第一積體電路管芯進行實體耦合及電耦合; 第一模塊插座,貼合到所述重佈線結構; 中介層,與所述第一模塊插座相鄰地貼合到所述重佈線結構,所述中介層的最外界限延伸超出所述重佈線結構的最外界限;以及 外部連接件,貼合到所述中介層。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962798600P | 2019-01-30 | 2019-01-30 | |
US62/798,600 | 2019-01-30 | ||
US16/529,119 US10978382B2 (en) | 2019-01-30 | 2019-08-01 | Integrated circuit package and method |
US16/529,119 | 2019-08-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW202029452A true TW202029452A (zh) | 2020-08-01 |
Family
ID=71732611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108137632A TW202029452A (zh) | 2019-01-30 | 2019-10-18 | 封裝裝置 |
Country Status (3)
Country | Link |
---|---|
US (3) | US10978382B2 (zh) |
CN (1) | CN111508920A (zh) |
TW (1) | TW202029452A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI747582B (zh) * | 2020-10-29 | 2021-11-21 | 創意電子股份有限公司 | 檢測裝置 |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11011451B2 (en) * | 2018-12-05 | 2021-05-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and method |
TWI791881B (zh) * | 2019-08-16 | 2023-02-11 | 矽品精密工業股份有限公司 | 電子封裝件及其組合式基板與製法 |
US11404316B2 (en) * | 2019-12-27 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | System, device and methods of manufacture |
CN113053802A (zh) | 2019-12-27 | 2021-06-29 | 台湾积体电路制造股份有限公司 | 半导体器件的形成方法 |
KR20210087299A (ko) * | 2020-01-02 | 2021-07-12 | 삼성전기주식회사 | 고주파 모듈 및 이를 포함하는 전자기기 |
US11393807B2 (en) | 2020-03-11 | 2022-07-19 | Peter C. Salmon | Densely packed electronic systems |
US11546991B2 (en) | 2020-03-11 | 2023-01-03 | Peter C. Salmon | Densely packed electronic systems |
US10966338B1 (en) * | 2020-03-11 | 2021-03-30 | Peter C. Salmon | Densely packed electronic systems |
US20230088049A1 (en) * | 2020-03-11 | 2023-03-23 | Peter C. Salmon | Densely packed electronic systems |
US11726784B2 (en) | 2020-04-09 | 2023-08-15 | Micron Technology, Inc. | Patient monitoring using edge servers having deep learning accelerator and random access memory |
US11355175B2 (en) | 2020-04-09 | 2022-06-07 | Micron Technology, Inc. | Deep learning accelerator and random access memory with a camera interface |
US11887647B2 (en) | 2020-04-09 | 2024-01-30 | Micron Technology, Inc. | Deep learning accelerator and random access memory with separate memory access connections |
US11461651B2 (en) * | 2020-04-09 | 2022-10-04 | Micron Technology, Inc. | System on a chip with deep learning accelerator and random access memory |
US11874897B2 (en) | 2020-04-09 | 2024-01-16 | Micron Technology, Inc. | Integrated circuit device with deep learning accelerator and random access memory |
US20200303291A1 (en) * | 2020-06-08 | 2020-09-24 | Intel Corporation | Integrated circuit (ic) package with substrate having validation connectors |
US11508665B2 (en) | 2020-06-23 | 2022-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packages with thick RDLs and thin RDLs stacked alternatingly |
US11444002B2 (en) * | 2020-07-29 | 2022-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure |
WO2022187053A1 (en) * | 2021-03-01 | 2022-09-09 | Tesla, Inc. | Wafer alignment structure |
KR20230122825A (ko) * | 2022-02-15 | 2023-08-22 | 삼성전자주식회사 | 반도체 패키지 |
US11445640B1 (en) | 2022-02-25 | 2022-09-13 | Peter C. Salmon | Water cooled server |
US11523543B1 (en) | 2022-02-25 | 2022-12-06 | Peter C. Salmon | Water cooled server |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8759964B2 (en) | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
CN102859691B (zh) | 2010-04-07 | 2015-06-10 | 株式会社岛津制作所 | 放射线检测器及其制造方法 |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US8361842B2 (en) | 2010-07-30 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded wafer-level bonding approaches |
US8884431B2 (en) | 2011-09-09 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures for semiconductor devices |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8829676B2 (en) | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
WO2013100995A1 (en) * | 2011-12-28 | 2013-07-04 | Intel Corporation | Photonic package architecture |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US8680647B2 (en) | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
US8703542B2 (en) | 2012-05-18 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level packaging mechanisms |
US9991190B2 (en) | 2012-05-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with interposer frame |
US8809996B2 (en) | 2012-06-29 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with passive devices and method of forming the same |
US8785299B2 (en) | 2012-11-30 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with a fan-out structure and method of forming the same |
US8803306B1 (en) | 2013-01-18 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package structure and methods for forming the same |
US8778738B1 (en) | 2013-02-19 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices and packaging devices and methods |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US8877554B2 (en) | 2013-03-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US9768145B2 (en) * | 2015-08-31 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming multi-die package structures including redistribution layers |
US9829626B2 (en) * | 2016-01-13 | 2017-11-28 | Oracle International Corporation | Hybrid-integrated multi-chip module |
GB2587961B (en) * | 2018-04-12 | 2022-05-18 | Rockley Photonics Ltd | Electro-optical package and method of fabrication |
US10714462B2 (en) * | 2018-04-24 | 2020-07-14 | Advanced Micro Devices, Inc. | Multi-chip package with offset 3D structure |
KR20230122825A (ko) * | 2022-02-15 | 2023-08-22 | 삼성전자주식회사 | 반도체 패키지 |
CN117594579A (zh) * | 2022-08-19 | 2024-02-23 | 谷歌有限责任公司 | 支撑高性能多晶粒asic的插座 |
-
2019
- 2019-08-01 US US16/529,119 patent/US10978382B2/en active Active
- 2019-10-18 TW TW108137632A patent/TW202029452A/zh unknown
- 2019-10-24 CN CN201911015739.9A patent/CN111508920A/zh active Pending
-
2021
- 2021-04-12 US US17/227,608 patent/US11488897B2/en active Active
-
2022
- 2022-10-31 US US17/977,301 patent/US20230053190A1/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI747582B (zh) * | 2020-10-29 | 2021-11-21 | 創意電子股份有限公司 | 檢測裝置 |
US11852470B2 (en) | 2020-10-29 | 2023-12-26 | Global Unichip Corporation | Inspecting device |
Also Published As
Publication number | Publication date |
---|---|
US20210233835A1 (en) | 2021-07-29 |
US20230053190A1 (en) | 2023-02-16 |
US11488897B2 (en) | 2022-11-01 |
CN111508920A (zh) | 2020-08-07 |
US10978382B2 (en) | 2021-04-13 |
US20200243429A1 (en) | 2020-07-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11488897B2 (en) | Integrated circuit package and method | |
TWI724706B (zh) | 經封裝裝置及其形成方法 | |
TWI709204B (zh) | 積體電路封裝及其製造方法 | |
TWI793373B (zh) | 半導體裝置及其製造方法 | |
US11764171B2 (en) | Integrated circuit structure and method | |
US11293974B2 (en) | System and method for semiconductor device testing | |
CN111276453B (zh) | 半导体装置及其形成方法 | |
TWI719678B (zh) | 半導體結構及其形成方法 | |
US12074143B2 (en) | Integrated circuit package and method | |
TW202243048A (zh) | 半導體元件及其製造方法 | |
US12057407B2 (en) | Semiconductor package and method | |
US20220359344A1 (en) | Integrated Circuit Package and Method | |
KR20200081231A (ko) | 집적 회로 패키지 및 방법 | |
US12125798B2 (en) | Semiconductor package and method |