TW202022827A - Gate driving apparatus - Google Patents

Abstract

A gate driving apparatus is provided. A plurality of gate driving circuit respectively generates a plurality of gate driving signals according to a plurality of external clock signals. A M-th gate driving circuit includes a control signal generator. An output stage circuit is based on a first internal clock signal and generates an M-th control signal at an output terminal in accordance with a first bias voltage and a second internal clock signal. A charge and discharge circuit adjusts the first bias voltage according to a M-2th control signal and the M+2th control signal to provide a first power voltage or a second power voltage to an input terminal. The pull-down circuit adjusts the first bias voltage and the M-th control signal according to the second bias voltage. The anti-noise circuit adjusts the second bias voltage according to the first internal clock signal and the M-th control signal. Where M is a positive integer greater than one.

Description

Gate drive device

The present invention relates to a gate driving device, and more particularly to a gate driving device of a display device.

In recent years, many products have integrated the gate driver in the display driver circuit on the glass, which is the gate-driver-on-array (GOA) circuit. The gate driving circuit on the array has many advantages, which can reduce the width of the frame of the display panel to achieve the effect of a narrow frame, thereby effectively reducing the design area of the internal circuit of the display. It should be noted that the conventional gate drive circuit may be affected by too many components and it is difficult to achieve the effect of a narrow frame.

In the conventional gate drive device, the designer usually generates a control signal through the control signal generator in the gate drive circuit, and uses the control signal to control a plurality of output transistors (such as thin film). The state of the transistor), and based on the clock signal, generates multiple gate drive signals to the display panel. However, in the prior art, the control signal generator usually does not have the function of bidirectional scanning, and cannot effectively achieve the effect of noise suppression. In addition, in the prior art, each gate driving signal transmitted to the display panel usually has a delay between the corresponding clock signal, and thus each gate driving signal cannot be synchronized with the corresponding clock signal. Switch actions.

Therefore, how to design a control signal generator with a bidirectional scanning function and a full-time anti-noise mechanism, and make each gate drive signal and the corresponding clock signal achieve the effect of timing overlap, so as to improve the gate drive device Work efficiency will be an important topic for those skilled in the art.

The present invention provides a gate driving device, which can enable the control signal generator in each gate driving circuit to have the function of bidirectional scanning, and can achieve the effect of anti-noise at all times, thereby improving the working efficiency of the gate driving device.

The gate drive device of the present invention includes a multi-stage gate drive circuit. The multi-stage gate driving circuit respectively generates a plurality of gate driving signals according to a plurality of external clock signals, wherein the M-th gate driving circuit includes a control signal generator. The control signal generator includes an output stage circuit, a charging and discharging circuit, a pull-down circuit and an anti-noise circuit. The output stage circuit is coupled to the input terminal and the reference potential to receive the first bias voltage. The output stage circuit generates the first bias voltage at the output terminal based on the first internal clock signal and according to the first bias voltage and the second internal clock signal. M-level control signal. The charging and discharging circuit is coupled to the input terminal, and provides a first power voltage or a second power voltage to the input terminal to adjust the first bias voltage according to the M-2th level control signal and the M+2th level control signal. The pull-down circuit is coupled to the control terminal and the reference potential to receive the second bias voltage, and adjust the first bias voltage and the M-th level control signal according to the second bias voltage. The anti-noise circuit is coupled between the control terminal and the reference potential, and adjusts the second bias voltage according to the first internal clock signal and the M-th level control signal. Where M is a positive integer greater than 1.

Based on the above, the control signal generator of the gate driving device of the present invention can set the voltage levels of the first power supply voltage and the second power supply voltage so that the control signal generator can have a bidirectional scanning function. In addition, the control signal generator can use the pull-down circuit and the anti-noise circuit to activate the anti-noise mechanism, so that the corresponding bias voltage and control signal can be maintained at a low voltage level to prevent the input terminal from being floating. The generated noise affects the performance of the control signal generator, so as to achieve the effect of anti-noise at all times.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

FIG. 1 is a circuit diagram of a control signal generator of an M-th gate driving circuit of a gate driving device according to an embodiment of the present invention. Please refer to FIG. 1, in this embodiment, the control signal generator 100 includes an output stage circuit 110, a charging and discharging circuit 120, a pull-down circuit 130 and an anti-noise circuit 140. Among them, the output stage circuit 110 includes transistors M3 to M4 and a capacitor C1. The first terminal of the transistor M3 is coupled to the output terminal OUT, the second terminal of the transistor M3 receives the internal clock signal CK1 (or the internal clock signal CK4), and the control terminal of the transistor M3 is coupled to the input terminal IN to receive Bias voltage A[n]. The first terminal of the transistor M4 is coupled to the reference potential VSS, the second terminal of the transistor M4 is coupled to the output terminal OUT, and the control terminal of the transistor M4 receives the internal clock signal CK3 (or the internal clock signal CK2). The first terminal of the capacitor C1 is coupled to the input terminal IN, and the second terminal of the capacitor C2 is coupled to the output terminal OUT.

It should be noted that in this embodiment, when the control signal generator 100 is operating in the forward scan phase, the second end of the transistor M3 can receive the internal clock signal CK1, and the control end of the transistor M4 can receive Internal clock signal CK3. In contrast, when the control signal generator 100 is operating in the reverse scan phase, the second terminal of the transistor M3 can receive the internal clock signal CK4, and the control terminal of the transistor M4 can receive the internal clock signal CK2.

The charging and discharging circuit 120 is coupled to the output stage circuit 110. The charging and discharging circuit 120 includes transistors M1 to M2. The first terminal of the transistor M1 is coupled to the input terminal IN, the second terminal of the transistor M1 is coupled to the power supply voltage VDDF, and the control terminal of the transistor M1 receives the M-2 level control signal. The first terminal of the transistor M2 is coupled to the power supply voltage VDDB, the second terminal of the transistor M2 is coupled to the input terminal IN, and the control terminal of the transistor M2 receives the M+2 level control signal. It is worth mentioning that, in this embodiment, when the control signal generator 100 is operating in the forward scanning phase, the voltage level of the power supply voltage VDDF may be higher than the voltage level of the power supply voltage VDDB (for example, the power supply voltage VDDF is set to a high voltage level, and the power supply voltage VDDB is set to a low voltage level). In contrast, when the control signal generator 100 is operating in the reverse scan phase, the voltage level of the power supply voltage VDDF may be lower than the voltage level of the power supply voltage VDDB (for example, the power supply voltage VDDF is set to a low voltage level, The power supply voltage VDDB is set to a high voltage level), but the embodiment of the present invention is not limited to this.

On the other hand, the pull-down circuit 130 is coupled between the control terminal CT and the reference voltage VSS. The pull-down circuit 130 includes transistors M5 to M6. The first terminal of the transistor M5 is coupled to the reference voltage VSS, the second terminal of the transistor M5 receives the bias voltage A[n], and the control terminal of the transistor M5 is coupled to the control terminal CT. The first terminal of the transistor M6 is coupled to the reference voltage VSS, the second terminal of the transistor M6 receives the M-th level control signal G[M], and the control terminal of the transistor M6 is coupled to the control terminal CT.

The anti-noise circuit 140 is coupled between the pull-down circuit 130 and the reference voltage VSS. The anti-noise circuit 140 includes transistors M7 to M10. The second end of the transistor M7 and the control end jointly receive the internal clock signal CK1 (or the internal clock signal CK4). The first terminal of the transistor M8 is coupled to the control terminal CT, the second terminal of the transistor M8 receives the internal clock signal CK1 (or the internal clock signal CK4), and the control terminal of the transistor M8 is coupled to the second terminal of the transistor M7. One end. The first terminal of the transistor M9 is coupled to the reference voltage VSS, the second terminal of the transistor M9 is coupled to the first terminal of the transistor M7, and the control terminal of the transistor M9 receives the M-th level control signal G[M]. The first terminal of the transistor M10 is coupled to the reference voltage VSS, the second terminal of the transistor M10 is coupled to the control terminal CT, and the control terminal of the transistor M10 receives the M-th level control signal G[M].

It should be noted that, in this embodiment, when the control signal generator 100 is operating in the forward scan phase, the second terminal and the control terminal of the transistor M7 and the second terminal of the transistor M8 can receive the internal clock signal CK1. In contrast, when the control signal generator 100 is operating in the reverse scan phase, the second terminal and the control terminal of the transistor M7 and the second terminal of the transistor M8 can receive the internal clock signal CK4.

Specifically, in this embodiment, when the control signal generator 100 is operating in the forward scanning phase (that is, the scanning sequence is sequentially scanned from the internal clock signal CK1 to the internal clock signal CK4), the charging and discharging circuit 120 can provide the power supply voltage VDDF to the input terminal IN according to the M-2th level control signal and the M+2th level control signal to charge the bias voltage A[n]. Then, the output stage circuit 110 can receive the bias voltage A[n] through the input terminal IN, and based on the timing state of the internal clock signal CK1, and according to the bias voltage A[n] and the internal clock signal CK3 to output The terminal OUT generates the M-th level control signal G[M] correspondingly.

In addition, in the forward scanning phase, the anti-noise circuit 140 can generate and adjust the bias voltage B[n] according to the internal clock signal CK1 and the M-th level control signal G[M]. In addition, the pull-down circuit 130 can determine whether to pull down the bias voltage A[n] and the M-th level control signal G[M] according to the bias voltage B[n], so as to avoid noise generated by the floating state of the input terminal IN. Affect the performance of the control signal generator 100.

On the other hand, when the control signal generator 100 is operating in the reverse scanning phase (that is, the scanning sequence is sequentially scanned from the internal clock signal CK4 to the internal clock signal CK1), the charging and discharging circuit 120 can perform according to the M-th The 2-level control signal and the M+2-th level control signal provide the power supply voltage VDDB to the input terminal IN to charge the bias voltage A[n]. Then, the output stage circuit 110 can receive the bias voltage A[n] through the input terminal IN, and based on the timing state of the internal clock signal CK4, and according to the bias voltage A[n] and the internal clock signal CK2 to output The terminal OUT generates the M-th level control signal G[M] correspondingly.

In addition, in the reverse scanning phase, the anti-noise circuit 140 can generate and adjust the bias voltage B[n] according to the internal clock signal CK4 and the M-th level control signal G[M]. Moreover, the pull-down circuit 130 can also determine whether to pull down the bias voltage A[n] and the M-th control signal G[M] at the same time according to the bias voltage B[n], so as to avoid the floating state of the input terminal IN. The noise affects the performance of the control signal generator 100. Wherein, the aforementioned M is a positive integer greater than 1.

2 is a timing diagram of the control signal generator of the M-th gate driving circuit of the gate driving device according to an embodiment of the present invention operating in the forward scanning phase. Please refer to FIG. 1 and FIG. 2 for the operation details of the control signal generator 100 when operating in the forward scanning phase TFS. In detail, in the sub-stage TF1 of the forward scanning stage TFS, the charging and discharging circuit 120 can turn on the transistor M1 according to the M-2th level control signal G[M-2] with a high voltage level, and will have The high-voltage power supply voltage VDDF is provided to the input terminal IN, so that the bias voltage A[n] is pulled up to the voltage level V2.

Then, in the sub-phase TF2 of the forward scanning phase TFS, the output stage circuit 110 can turn on the transistor M3 according to the bias voltage A[n]. In addition, the output stage circuit 110 can charge the output terminal OUT according to the internal clock signal CK1 having a high voltage level, so that the M-th control signal G[M] is synchronously pulled up to the high voltage level. At the same time, the bias voltage A[n] can be further pulled up to the voltage level V3 through the coupling effect of the capacitor C1. Among them, the voltage value of the voltage level V3 is greater than the voltage value of the voltage level V2.

It is worth mentioning that in the sub-stage TF2, since the M-th level control signal G[M] is at a high voltage level at this time, the anti-noise circuit 140 can be adjusted according to the M-th level control signal G[M] Make the transistor M9 and the transistor M10 conduct. Thereby, the anti-noise circuit 140 can pull down the bias voltage B[n] to the reference potential VSS according to the conduction path of the transistor M9 and the transistor M10. In other words, in the sub-phase TF2, the pull-down circuit 130 can disconnect the transistor M5 and the transistor M6 according to the pulled-down bias voltage B[n], so that the anti-noise mechanism of the anti-noise circuit 140 is not It is started during the subphase TF2.

Then, in the sub-phase TF3 of the forward scanning phase TFS, the charging and discharging circuit 120 can turn on the transistor M2 according to the M+2th level control signal G[M+2] with a high voltage level, and will have a low voltage The level of the power supply voltage VDDB is provided to the input terminal IN, so that the bias voltage A[n] is pulled down to the voltage level V1. Among them, the voltage value of the voltage level V1 is less than the voltage value of the voltage level V2.

It is worth mentioning that, in the sub-stage TF3, since the transistor M4 can be turned on according to the internal clock signal CK3 with a high voltage level at this time, the output stage circuit 110 can pull down the first according to the internal clock signal CK3. The voltage level of the M-level control signal G[M]. In other words, in the sub-phase TF3, the bias voltage A[n] and the voltage level of the M-th control signal G[M] are all pulled down to a low voltage level.

Then, in the sub-stage TF4 of the forward scanning stage TFS, the control signal generator 100 has completed the output waveform of the forward scanning at this time, and the internal clock signal CK1 can be reset to the high voltage level, and the Mth The level control signal G[M] can still be maintained at a low voltage level. In this case, the anti-noise circuit 140 can disconnect the transistor M9 and the transistor M10 according to the M-th level control signal G[M] with a low voltage level. Moreover, the anti-noise circuit 140 can turn on the transistor M7 and the transistor M8 according to the internal clock signal CK1 having a high voltage level.

Furthermore, the anti-noise circuit 140 can pull up the bias voltage B[n] to a high voltage level according to the conduction path of the transistor M7 and the transistor M8, so that the pull-down circuit 130 can be based on the bias voltage being pulled up The voltage B[n] turns on the transistor M5 and the transistor M6, so that the corresponding bias voltage A[n] and the M-th level control signal G[M] are simultaneously pulled down to the reference potential VSS, thereby making the anti-noise The signal circuit 140 can activate the anti-noise mechanism in the sub-stage TF4.

3 is a timing diagram of the control signal generator of the M-th gate driving circuit of the gate driving device according to an embodiment of the present invention operating in the reverse scanning phase. Please refer to FIG. 1 and FIG. 3 for the operation details of the control signal generator 100 when operating in the reverse scanning phase TRS. In detail, in the sub-stage TR1 of the reverse scan stage TRS, the charging and discharging circuit 120 can turn on the transistor M2 according to the M+2 level control signal G[M+2] with a high voltage level, and will have The high-voltage power supply voltage VDDB is provided to the input terminal IN, so that the bias voltage A[n] is pulled up to the voltage level V2.

Then, in the sub-phase TR2 of the reverse scan phase TRS, the output stage circuit 110 can turn on the transistor M3 according to the bias voltage A[n]. In addition, the output stage circuit 110 can charge the output terminal OUT according to the internal clock signal CK4 having a high voltage level, so that the M-th control signal G[M] is synchronously pulled up to the high voltage level. At the same time, the bias voltage A[n] can be further pulled up to the voltage level V3 through the coupling effect of the capacitor C1. Among them, the voltage value of the voltage level V3 is greater than the voltage value of the voltage level V2.

It is worth mentioning that in the sub-stage TR2, since the M-th level control signal G[M] is at a high voltage level at this time, the anti-noise circuit 140 can be adjusted according to the M-th level control signal G[M] Make the transistor M9 and the transistor M10 conduct. Thereby, the anti-noise circuit 140 can pull down the bias voltage B[n] to the reference potential VSS according to the conduction path of the transistor M9 and the transistor M10. In other words, in the sub-stage TR2, the pull-down circuit 130 can disconnect the transistor M5 and the transistor M6 according to the pulled-down bias voltage B[n], so that the anti-noise mechanism of the anti-noise circuit 140 is not It is started during the subphase TF2.

Then, in the sub-phase TR3 of the reverse scan phase TRS, the charging and discharging circuit 120 can turn on the transistor M1 according to the M-2th level control signal G[M-2] with a high voltage level, and will have a low voltage The level of the power supply voltage VDDF is provided to the input terminal IN, so that the bias voltage A[n] is pulled down to the voltage level V1. Among them, the voltage value of the voltage level V1 is less than the voltage value of the voltage level V2.

It is worth mentioning that, in the sub-phase TR3, since the transistor M4 can be turned on according to the internal clock signal CK2 with a high voltage level at this time, the output stage circuit 110 can pull down the first clock signal according to the internal clock signal CK2. The voltage level of the M-level control signal G[M]. In other words, in the sub-stage TR3, the bias voltage A[n] and the voltage level of the M-th control signal G[M] are all pulled down to a low voltage level.

Then, in the sub-stage TR4 of the reverse scan stage TRS, the control signal generator 100 has completed the output waveform of the reverse scan at this time, and the internal clock signal CK4 can be reset to the high voltage level, and the Mth The level control signal G[M] can still be maintained at a low voltage level. In this case, the anti-noise circuit 140 can disconnect the transistor M9 and the transistor M10 according to the M-th level control signal G[M] with a low voltage level. Moreover, the anti-noise circuit 140 can turn on the transistor M7 and the transistor M8 according to the internal clock signal CK4 having a high voltage level.

Furthermore, the anti-noise circuit 140 can pull up the bias voltage B[n] to a high voltage level according to the conduction path of the transistor M7 and the transistor M8, so that the pull-down circuit 130 can be based on the bias voltage being pulled up The voltage B[n] turns on the transistor M5 and the transistor M6, so that the corresponding bias voltage A[n] and the M-th level control signal G[M] are simultaneously pulled down to the reference potential VSS, thereby making the anti-noise The signal circuit 140 can activate the anti-noise mechanism in the sub-phase TR4.

According to the above content, in this embodiment, the control signal generator 100 can set the voltage level of the power supply voltage VDDF and the voltage level of the power supply voltage VDDB (for example, during the forward scanning phase TFS, Set the power supply voltage VDDF to a high voltage level and set the power supply voltage VDDB to a low voltage level; in the reverse scan phase TRS, set the power supply voltage VDDF to a low voltage level, and set the power supply voltage VDDB to a high voltage level) , So that the control signal generator 100 can have a bidirectional scanning function. In addition, when the control signal generator 100 operates in the forward scan stage TFS and the reverse scan stage TRS, and the M-th level control signal G[M] output by the output stage circuit 110 is in a low-voltage level state, either The pull-down circuit 130 and the anti-noise circuit 140 are used to activate the anti-noise mechanism, so that the corresponding bias voltage A[n] and the M-th level control signal G[M] can be maintained at a low voltage level. In order to avoid the noise generated by the floating state of the input terminal IN from affecting the performance of the control signal generator 100, the effect of anti-noise at all times is achieved.

4 is a schematic diagram of a gate driving device according to an embodiment of the invention. 1 and FIG. 4 at the same time, in this embodiment, the gate driving device 400 includes a multi-level gate driving circuit (eg, gate driving circuits 410-420). It should be noted that those skilled in the art can determine the number of gate drive circuits according to the design requirements of the gate drive device 400. For the convenience of description, FIG. 4 is based on the two-level gate drive circuits 410-420. It appears, but the number of gate drive circuits of the present invention is not limited to this.

Taking the gate driving circuit 410 as an example, the gate driving circuit 410 includes a control signal generator SR1, a clock signal transmitter 411, and a compensation circuit 412. Wherein, the control signal generator SR1 of this embodiment can be implemented through the control signal generator 100 in FIG. 1.

In the gate driving circuit 410, the clock signal transmitter 411 may be composed of a plurality of transistors TA1 to TA4, wherein the first ends of the respective transistors TA1 to TA4 can respectively receive the corresponding external clock signals CLK1 to CLK4 , The second end of each transistor TA1 to TA4 can be respectively coupled to the corresponding gate line G1 to G4, and the control end of each transistor TA1 to TA4 can be commonly coupled to the output terminal OUT of the control signal generator SR1 for receiving Control signal G[1].

Specifically, please refer to FIG. 1, FIG. 4, and FIG. 5 at the same time. FIG. 5 is a timing diagram of a gate driving device according to an embodiment of the present invention. In the gate driving circuit 410, the clock signal transmitter 411 can sequentially generate the gate driving signals GS1 to GS4 based on the timing state of the external clock signals CLK1 to CLK4 and according to the control signal G[1]. For example, when the clock signal transmitter 411 receives the control signal G[1] with a high voltage level, the transistors TA1 to TA4 can be turned on. At the same time, the clock signal transmitter 411 can sequentially generate the gate driving signals GS1 to GS4 with high voltage levels to the display panel 500 according to the timing state of the external clock signals CLK1 to CLK4.

On the other hand, in the gate driving circuit 410, the compensation circuit 412 is coupled to the control terminal CT of the control signal generator SR1, the reference potential VSS, and the clock signal transmitter 411. The compensation circuit 412 can be composed of a plurality of transistors T111 to T124, wherein the first end of each transistor T111 to T114 can be coupled to the corresponding gate line G1 to G4, and the second end of each transistor T111 to T114 The terminals can be commonly coupled to the reference potential VSS, and the control terminals of the respective transistors T111 to T114 can be commonly coupled to the control terminal CT of the control signal generator SR1 to receive the bias voltage B[1]. In addition, the first end of each transistor T121 to T124 can be respectively coupled to the corresponding gate line G1 to G4, the second end of each transistor T121 to T124 can be commonly coupled to the reference potential VSS, and each transistor T121 to The control terminals of T124 can be commonly coupled to the internal clock signal CK3.

Specifically, the compensation circuit 412 can pull down the voltage levels of the gate driving signals GS1 to GS4 according to the bias voltage B[1] and the state of the internal clock signal CK3. For example, when the transistors T111 to T114 of the compensation circuit 412 receive the bias voltage B[1] with a high voltage level, the transistors T111 to T114 can be turned on. At the same time, the compensation circuit 412 can pull down the gate driving signals GS1 to GS4 to the reference potential VSS according to the bias voltage B[1]. In addition, when the transistors T121 to T124 of the compensation circuit 412 receive the internal clock signal CK3 with a high voltage level, the transistors T121 to T124 can be turned on. At the same time, the compensation circuit 412 can also pull down the gate driving signals GS1 to GS4 to the reference potential VSS according to the internal clock signal CK3.

On the other hand, taking the gate driving circuit 420 as an example, the gate driving circuit 420 includes a control signal generator SR2, a clock signal transmitter 413, and a compensation circuit 414. Among them, the control signal generator SR2 of this embodiment can also be implemented by the control signal generator 100 in FIG. 1, and the components in the clock signal transmitter 413 and the compensation circuit 414 and their coupling methods are the same or similar. The clock signal transmitter 411 and the compensation circuit 412 are not detailed here. Wherein, the same or similar elements use the same or similar reference numerals.

Please refer to FIG. 1, FIG. 4, and FIG. 5 at the same time. The difference from the gate drive circuit 410 is that in the gate drive circuit 420, the clock signal transmitter 413 can be based on the received external clock signals CLK5 to CLK8. The timing state, and according to the control signal G[2] generated by the control signal generator SR2, to sequentially generate the gate drive signals GS5 to GS8. For example, when the timing signal transmitter 413 receives the control signal G[2] with a high voltage level, the transistors TA1 to TA4 can be turned on. At the same time, the clock signal transmitter 413 can sequentially generate gate drive signals GS5 to GS8 with high voltage levels to the display panel 500 according to the timing state of the external clock signals CLK5 to CLK8.

On the other hand, the compensation circuit 414 can pull down the voltage levels of the gate driving signals GS5 to GS8 according to the bias voltage B[2] and the state of the internal clock signal CK4. For example, when the transistors T211 to T214 of the compensation circuit 414 receive the bias voltage B[2] with a high voltage level, the transistors T211 to T214 can be turned on. At the same time, the compensation circuit 414 can pull down the gate driving signals GS5 to GS8 to the reference potential VSS according to the bias voltage B[2]. In addition, when the transistors T221 to T224 of the compensation circuit 414 receive the internal clock signal CK4 with a high voltage level, the transistors T221 to T224 can be turned on. At the same time, the compensation circuit 414 can also pull down the gate driving signals GS5 to GS6 to the reference potential VSS according to the internal clock signal CK4.

In particular, according to the description of FIG. 4 and FIG. 5, it can be known that the gate driving device 400 of the present invention can make the gate driving signals GS1 to GS8 be able to communicate with each other through a clock signal transmitter and a compensation circuit. The corresponding external clock signals CLK1 to CLK8 are switched synchronously, so that each gate drive signal and the corresponding external clock signal achieve the effect of overlapping in time sequence.

It should be noted that those skilled in the art can determine the transistors TA1 to TA4 in the clock signal transmitters 411 and 413 and the transistors T111 to T124 in the compensation circuit 412 according to the design requirements of the gate driving device 400. The number of transistors T211 to T224 and the external clock signal in the compensation circuit 414 is not limited to the number in FIG. 4 in the embodiment of the present invention. In addition, in the gate driving device 400, the operation modes of the remaining odd-numbered stages of gate driving circuits may be the same or similar to those of the gate driving circuit 410, and the remaining even-numbered stages of gate driving circuits may be operated in the same manner. The operation mode is the same or similar to that of the gate driving circuit 420, and will not be repeated here.

According to the above description, for the gate driving circuit 410, when the bias voltage B[1] or the internal clock signal CK3 is in a high voltage level state, the gate driving device 400 of the present invention can compensate The circuit 412 pulls down the gate driving signals GS1 to GS4 on the gate lines G1 to G4 to the reference potential VSS. In this way, the compensation circuit 412 can release the charges in the gate lines G1 to G4 to the reference potential VSS, thereby reducing the noise generated by the mutual coupling between the gate lines, thereby improving the performance of the gate driving device 400 .

In summary, based on the above, the control signal generator of the gate driving device of the present invention can set the voltage levels of the first power supply voltage and the second power supply voltage so that the control signal generator can have a bidirectional scanning Features. In addition, the control signal generator can use the pull-down circuit and the anti-noise circuit to activate the anti-noise mechanism, so that the corresponding bias voltage and control signal can be maintained at a low voltage level to prevent the input terminal from being floating. The generated noise affects the performance of the control signal generator, so as to achieve the effect of anti-noise at all times.

Although the present invention has been disclosed as above by the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, SR1, SR2: control signal generator 110: output stage circuit 120: charging and discharging circuit 130: pull-down circuit 140: anti-noise circuit 400: gate driving device 410, 420: gate driving circuit 411, 413: clock Signal transmitter 412, 414: Compensation circuit 500: Display panel A[n], B[n]: Bias voltage C1: Capacitor CT: Control terminal CK1～CK4: Internal clock signal CLK1～CLK8: External clock signal G [M], G[M+2], G[M-2]: Control signal G1～G8: Gate line GS1～GS8: Gate drive signal IN: Input terminal M1～M10, TA1～TA4, T111～T114 , T121～T124, T211～T214, T221～T224: Transistor OUT: Output TFS: Forward scanning phase TRS: Reverse scanning phase TF1～TF4, TR1～TR4: Sub-phase VDDF, VDDB: Power supply voltage VSS: Reference Potential V1～V3: voltage level

FIG. 1 is a circuit diagram of a control signal generator of an M-th gate driving circuit of a gate driving device according to an embodiment of the present invention. 2 is a timing diagram of the control signal generator of the M-th gate driving circuit of the gate driving device according to an embodiment of the present invention operating in the forward scanning phase. 3 is a timing diagram of the control signal generator of the M-th gate driving circuit of the gate driving device according to an embodiment of the present invention operating in the reverse scanning phase. 4 is a schematic diagram of a gate driving device according to an embodiment of the invention. FIG. 5 is a timing diagram of a gate driving device according to an embodiment of the invention.

100: Control signal generator

110: output stage circuit

120: charge and discharge circuit

130: pull-down circuit

140: Anti-noise circuit

A[n], B[n]: Bias voltage

C1: Capacitance

CT: control terminal

CK1~CK4: Internal clock signal

G[M], G[M+2], G[M-2]: control signal

IN: input

M1~M10: Transistor

OUT: output terminal

VDDF, VDDB: power supply voltage

VSS: Reference potential

Claims (15)

A gate driving device includes: a multi-level gate driving circuit, which generates a plurality of gate driving signals corresponding to a plurality of external clock signals, wherein the M-th gate driving circuit includes: a control signal generator, the The control signal generator includes: an output stage circuit coupled to an input terminal and a reference potential to receive a first bias voltage, the output stage circuit based on a first internal clock signal, and based on the first bias voltage Voltage and a second internal clock signal to generate an M-th level control signal at an output terminal; a charging and discharging circuit, coupled to the input terminal, according to an M-2th level control signal and an M+2th level Control signal to provide a first power supply voltage or a second power supply voltage to the input terminal to adjust the first bias voltage; a pull-down circuit coupled to a control terminal and the reference potential to receive a second bias voltage , Adjust the first bias voltage and the M-th level control signal according to the second bias voltage; and an anti-noise circuit, coupled between the control terminal and the reference potential, according to the first internal time The pulse signal and the M-th level control signal are used to adjust the second bias voltage, where M is a positive integer greater than 1. For the gate drive device described in item 1 of the scope of patent application, the M-th stage gate drive circuit further includes: a clock signal transmitter coupled to the output terminal to receive the M-th stage control signal, and The pulse signal transmitter generates the corresponding gate drive signals based on the external clock signals and the M-th level control signal; and a compensation circuit coupled to the control terminal, the reference potential, and the clock signal The transmitter pulls down the gate driving signals according to the second bias voltage and the second internal clock signal. The gate driving device described in the first item of the scope of patent application, wherein in a forward scanning phase, the voltage level of the first power supply voltage is higher than the voltage level of the second power supply voltage, and a reverse scanning phase , The voltage level of the first power supply voltage is lower than the voltage level of the second power supply voltage. According to the gate driving device described in item 3 of the scope of patent application, in a first sub-stage of the forward scanning stage, the charging and discharging circuit provides the first power supply voltage to The input terminal pulls up the first bias voltage. The gate driving device according to claim 4, wherein in a second sub-stage of the forward scanning stage, the pull-down circuit is turned off according to the pulled-down second bias voltage. According to the gate driving device described in item 5 of the scope of patent application, in a third sub-stage of the forward scanning stage, the charging and discharging circuit provides the second power supply voltage to the M+2 level control signal according to the The input terminal pulls down the first bias voltage, and the output stage circuit pulls down the M-th level control signal according to the second internal clock signal. According to the gate driving device described in item 6 of the scope of patent application, in a fourth sub-stage of the forward scanning stage, the pull-down circuit is turned on according to the pulled-up second bias voltage. The gate driving device according to item 3 of the scope of patent application, wherein in a first sub-stage of the reverse scan stage, the charge and discharge circuit provides the second power supply voltage to The input terminal pulls up the first bias voltage. In the gate driving device described in item 8 of the scope of patent application, in a second sub-stage of the reverse scanning stage, the pull-down circuit is turned off according to the pulled-down second bias voltage. The gate drive device according to claim 9, wherein in a third sub-stage of the reverse scan stage, the charge and discharge circuit provides the first power supply voltage to The input terminal pulls down the first bias voltage, and the output stage circuit pulls down the M-th level control signal according to the second internal clock signal. The gate driving device according to claim 10, wherein in a fourth sub-stage of the reverse scan stage, the pull-down circuit is turned on according to the pulled-up second bias voltage. For the gate drive device described in the first item of the patent application, the output stage circuit includes: a first transistor, the first terminal of which is coupled to the output terminal, and the second terminal of which receives the first internal clock Signal, its control terminal receives the first bias voltage; a second transistor, its first terminal is coupled to the reference potential, its second terminal is coupled to the output terminal, and its control terminal receives the second internal timing Pulse signal; and a capacitor, the first terminal of which is coupled to the input terminal, and the second terminal of which is coupled to the output terminal. For the gate drive device described in the first item of the patent application, the charging and discharging circuit includes: a first transistor, the first terminal of which is coupled to the input terminal, and the second terminal of which is coupled to the first power supply voltage , Its control terminal receives the M-2th level control signal; and a second transistor, the first terminal of which is coupled to the second power supply voltage, the second terminal of which is coupled to the input terminal, and the control terminal of which receives the first M+2 level control signal. For the gate driving device described in claim 1, wherein the pull-down circuit includes: a first transistor, the first terminal of which is coupled to the reference potential, and the second terminal of which receives the first bias voltage, Its control terminal receives the second bias voltage; and a second transistor whose first terminal is coupled to the reference potential, its second terminal receives the M-th level control signal, and its control terminal receives the second bias voltage Voltage. For example, the gate drive device described in item 1 of the scope of patent application, wherein the anti-noise circuit includes: a first transistor, the second end and the control end of which jointly receive the first internal clock signal; A crystal, the first end of which is coupled to the control end, the second end of which receives the first internal clock signal, and the control end of which is coupled to the first end of the first transistor; a third transistor, the second end of which is One end is coupled to the reference potential, the second end is coupled to the first end of the first transistor, and the control end receives the M-th level control signal; and a fourth transistor, and the first end is coupled To the reference potential, the second terminal is coupled to the control terminal, and the control terminal receives the M-th level control signal.

Images