TWI413970B - Gate driver - Google Patents

Gate driver Download PDF

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Publication number
TWI413970B
TWI413970B TW98137241A TW98137241A TWI413970B TW I413970 B TWI413970 B TW I413970B TW 98137241 A TW98137241 A TW 98137241A TW 98137241 A TW98137241 A TW 98137241A TW I413970 B TWI413970 B TW I413970B
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Taiwan
Prior art keywords
signal
output
coupled
width
input
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TW98137241A
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Chinese (zh)
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TW201117174A (en
Inventor
Yan Jou Chen
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Hannstar Display Corp
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Abstract

A gate driver is provided. The gate driver comprises a plurality of stages, each stage receiving an input signal and outputting an output signal or a carrier signal to the next stage as the input signal of the next stage. The output signal of each stage is employed for driving a row of pixels. According to the gate driver of the present invention, the driving period of each row of pixels is extended from one-pulse width to two-pulse width, and, the power consumption can be saved by lowering down the number of the clock lines and the frequency of the clock signals.

Description

Gate drive circuit

The present invention relates to a gate drive circuit, and more particularly to a gate drive circuit for a liquid crystal display.

The liquid crystal display usually comprises an array substrate, which is mainly composed of a pixel array divided by m data lines (D1-Dm) and n data lines (G1-Gn), wherein the m data lines are driven by a plurality of data lines. Driven, n gate lines are driven by a plurality of gate drive chips. In addition, a timing controller controls the gate drive wafer and the data drive wafer.

For the resolution requirement, the number of pixels, gate lines, data lines, data driving chips, and gate driving chips of the pixel array must be increased, resulting in an excessive manufacturing cost of the liquid crystal display. In order to reduce the cost, an integrated gate driver (IGD) replaces the gate driving chip, and the integrated gate driver integrates the gate driving circuit and the array substrate, that is, the system and drawing The array of atoms is simultaneously fabricated on the array substrate, which saves the cost of parts for the gate drive wafer.

The design of the integrated gate driver is usually a driving unit including a plurality of stages, each driving unit drives a column of pixel switching elements, and each driving unit is designed through the circuit layout to make the input of the nth stage. The signal is equal to the output signal of the n-1th stage, The output signal of the nth stage is equal to the input signal of the n+1th stage, and the concept of a shift register is such that the number of output signals of the control gate line is greatly reduced.

With the increase in resolution requirements, a pre-charged integrated gate drive circuit has been proposed. The difference between the precharged integrated gate drive circuit and the conventional integrated gate drive circuit is that The output signal of each stage of the driving unit is maintained for a long time, so that the switching elements of the column of pixels driven by the driving unit of the stage have a long opening time to ensure sufficient charging time of the column of pixels. .

A conventional pre-charged integrated gate driving circuit is shown in FIG. 1A and FIG. BB, wherein the first A-picture is a block diagram of a pre-charged integrated gate driving circuit, and the first B-picture is Timing diagram of the first A picture. As shown, the precharged integrated gate drive circuit is divided into two groups, an odd group containing odd-numbered drive units and an even group containing even-numbered drive units. Each group must utilize two clock signals, the odd group utilizes clock signals CK1 and CKB1, and the even group utilizes clock signals CK2 and CKB2 for circuit driving. The output signal of each stage of the drive unit is transmitted through a gate line (such as G1-G5) to drive a column of pixel switching elements. As shown in FIG. B, the high-level pulse of the output signal of each stage of the driving unit has an overlapping portion with the high-level pulse of the driving unit of the previous stage, that is, when the driving unit of the previous stage has not returned to the low level. Each stage of the drive unit begins to output a high level pulse, that is, performs a precharge operation, and during the second half of the pulse (ie, during the period when the pulse does not overlap with the previous stage drive unit pulse), it is the data driver output (source). Driver output) The time at which the pixel voltage is written.

Although the above circuit achieves the purpose of pre-filling the driving circuit, its design needs to divide the circuit into two groups, the design is too complicated, and a total of four clock signals are required, and the design is difficult to change and the power consumption is high. In addition, the conventional gate drive circuit of the prior art There is still room for improvement in stability and reliability.

Therefore, there is a need to provide a new gate drive circuit to improve the above-mentioned lack.

It is an object of the present invention to provide a novel gate driving circuit which has good stability and reliability, a simple circuit design, and a small footprint, and which consumes less power than conventional techniques.

According to the above object, an embodiment of the present invention provides a gate driving circuit including a plurality of serially connected driving units, each driving unit comprising: a signal input terminal for receiving an input signal; and a feedback signal input terminal for receiving a feedback signal. a carrier signal output end, outputting a carrier signal; a signal output end, outputting an output signal to drive a column of pixels; a first switch having a first end and a control end coupled to the signal input end for receiving input The second switch is coupled to a first node, and the second switch has a first end coupled to a clock signal, a second end coupled to a second node and a carrier signal output terminal for outputting a carrier signal, The control end is coupled to the first node; the third switch has a first end coupled to the first node, the second end coupled to a low voltage source, and a control end coupled to the feedback signal input end to receive the feedback signal; The fourth switch has a first end coupled to a high voltage source, a second end coupled to the signal output end, and a control end coupled to the first node; and a fifth switch having a first end coupled to the fourth switch The second end is coupled to the signal output end, the second end is coupled to the low voltage source, and the second end is coupled to the feedback signal input end; and a sixth switch having a first end coupled to the second node and a second end coupled a low voltage source, a control end coupled to the feedback signal input end; wherein each of the drive units The signal signal output end is coupled to the signal input end of the next-stage driving unit, and the feedback signal input end is coupled to the output signal end of the lower two-stage driving unit.

According to the above object, an embodiment of the present invention provides a gate driving circuit including a plurality of serially connected driving units, each driving unit comprising: a signal input terminal for receiving an input signal; and a feedback signal input terminal for receiving a feedback signal. a carrier signal output terminal outputs a carrier signal; a signal output terminal outputs an output signal to drive a column of pixels; and a first switch has a first terminal coupling. According to the above objective, the embodiment of the present invention provides a a first clock signal, a second end coupled to the first node and the signal output end, and a control end coupled to the signal input end; a second switch having a first end coupled to a second clock signal, The second end is coupled to the second node and the carrier signal output end, and the control end is coupled to the first node; the third switch has a first end coupled to the first node and a second end coupled to the low voltage source a control terminal is coupled to the feedback signal input end; a fourth switch having a first end coupled to the second node and the feedback signal output end, a second end coupled to the low voltage source, and a control end coupled to the feedback signal input ; Wherein each carrier signal is coupled to the output terminal of the driving unit to take over a drive signal input unit, the feedback signal input terminal coupled to the signal output to take over the two drive units.

According to the above object, an embodiment of the present invention provides a gate driving circuit including a plurality of serially connected driving units, each driving unit comprising: a signal input terminal for receiving an input signal; and a feedback signal input terminal for receiving a feedback signal. a signal output end, outputting an output signal to drive a column of pixels; a first switch having a first end coupled to a clock signal, a second end coupled to a node and a signal output end, and a control end coupling Connected to the signal input end; a second switch having a first end coupling node and a signal output end, a second end coupled to a low voltage source, and a control end coupled to the feedback signal input end; wherein each of the driving units The signal output end is coupled to the signal input end of the next-stage driving unit and the feedback signal input end is coupled The output signal terminal of the lower two-stage drive unit.

According to the above object, an embodiment of the present invention provides a gate driving circuit including a plurality of serially connected driving units, each driving unit comprising: a signal input terminal for receiving an input signal; and a feedback signal input terminal for receiving a feedback signal. a signal output end, outputting an output signal to drive a column of pixels; a first switch having a first end coupled to a control end of the input signal end, a second end coupled to a node; a second switch a first end coupled to a clock signal, a second end coupled to the signal output end, and a control end coupled node; and a third switch having a first end coupling node and a second end coupling A low voltage source and a control end are coupled to the feedback signal input end; wherein the signal output end of each drive unit is coupled to the signal input end of the next stage drive unit, and the feedback signal input end is coupled to the output signal end of the lower three stage drive unit .

According to the above object, an embodiment of the present invention provides a gate driving circuit, which includes a plurality of serially connected driving units, each driving unit includes: a signal input terminal that receives an input signal; a signal output terminal that outputs an output signal. Driving a column of pixels; a first switch having a first end coupled to the signal input end, a second end coupled to a node, a control end coupled to the first clock signal; and a second switch having a first switch The first end is coupled to a second clock signal, a second end coupled to the signal output end, and a control end coupled to the node; wherein the signal output end of each of the drive units is coupled to the signal input end of the next stage drive unit.

10‧‧‧ gate drive circuit

11-15‧‧‧ drive unit

20‧‧‧ clock generator

30‧‧‧ gate drive circuit

40‧‧‧ gate drive circuit

50‧‧‧ gate drive circuit

60‧‧‧ gate drive circuit

G1-G5‧‧‧ gate line

IP‧‧‧ signal input

OP‧‧‧ signal output

RP‧‧‧ feedback signal input

CP‧‧‧carrier signal output

CKV‧‧‧ clock signal

CKB1-CKB2‧‧‧ clock signal

M1-M6‧‧‧ switch

CK1-CK6‧‧‧ clock signal

VSS‧‧‧low voltage source

Vdd‧‧‧High voltage source

X‧‧‧ node

Z‧‧‧ node

Input‧‧‧ input signal

Output‧‧‧Output signal

Carrier‧‧‧Carrier Signal

W‧‧‧first width

1A and 1B show a conventional precharge gate drive circuit and its timing diagram; FIG. 2A shows a block diagram of the gate drive circuit 10 of the embodiment of the present invention; FIG. 2B is a timing diagram showing a clock signal received by the gate driving circuit 10 of the embodiment of the present invention; and FIG. 3 is a circuit diagram showing a driving unit of the gate driving circuit 10 of the embodiment of the present invention; 4B is a block diagram showing the gate driving circuit 10 of the embodiment of the present invention; FIG. 5B is a block diagram showing the gate driving circuit 30 of the embodiment of the present invention; and FIG. 5B is a diagram showing the gate driving of the embodiment of the present invention. A timing diagram of a clock signal received by the circuit 30; a sixth diagram showing a circuit diagram of a driving unit of the gate driving circuit 30 of the embodiment of the present invention; and FIGS. 7A and 7B are diagrams showing a gate driving circuit of an embodiment of the present invention; FIG. 8 is a block diagram showing a gate driving circuit 40 according to an embodiment of the present invention; and FIG. 8B is a timing chart showing a clock signal received by the gate driving circuit 40 according to the embodiment of the present invention; 9 is a circuit diagram showing two driving units of the gate driving circuit 40 of the embodiment of the present invention; FIGS. 10A and 10B are diagrams showing a driving method of the gate driving circuit 40 according to the embodiment of the present invention; Gate of the embodiment of the invention Block diagram of the driving circuit 50; FIG. 11B shows a timing chart of the clock signal received by the gate driving circuit 50 of the embodiment of the present invention; and FIG. 12 shows one of the gate driving circuits 50 of the embodiment of the present invention. FIG. 13A and FIG. 13B are diagrams showing a driving method of a gate driving circuit 50 according to an embodiment of the present invention; and FIG. 14A is a block diagram showing a gate driving circuit 60 according to an embodiment of the present invention; FIG. 14B is a timing diagram showing clock signals received by the gate driving circuit 60 of the embodiment of the present invention; Fig. 15 is a circuit diagram showing a driving unit of the gate driving circuit 60 of the embodiment of the present invention; and Figs. 16A and 16B are diagrams showing a driving method of the gate driving circuit 60 of the embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the drawings. In addition to the detailed description, the present invention may be widely practiced in other embodiments, and any alternatives, modifications, and equivalent variations of the described embodiments are included in the scope of the present invention, and the scope of the following patents is quasi. In the description of the specification, numerous specific details are set forth in the description of the invention. In addition, well-known steps or elements are not described in detail to avoid unnecessarily limiting the invention.

Figure 2A shows a block diagram of a gate drive circuit 10 in accordance with an embodiment of the present invention. The gate driving circuit 10 includes a plurality of serially connected driving units 11, such as a first driving unit S1, a second driving unit S2, a third driving unit S3, a fourth driving unit S4, and the like shown in the drawings, each of which The driving unit 11 receives an input signal, a feedback signal, and a clock signal, wherein the clock signals CK1 and CK2 are provided by a clock generator 20, and the pulse generator 20 may or may not be included in the gate. In the drive circuit 10.

Each of the driving units 11 includes a signal input terminal IP to receive an input signal Input, a feedback signal input terminal RP to receive a feedback signal, a signal output terminal OP to output an output signal, and a carrier signal output terminal CP to output a signal. Carrier signal carrier.

The carrier signal output terminal CP of each driving unit 11 is coupled to the next-level driving list. The signal input terminal IP and the feedback signal input terminal RP of the element are coupled to the output signal terminal OP of the lower two-stage driving unit; therefore, the input signal Input of each stage of the driving unit 11 is the carrier signal carrier and the feedback signal output by the driving unit of the previous stage. The output signal Output of the lower two-stage driving unit, however, since the first driving unit S1 is the first-stage driving unit of the serial-connected driving unit, the difference from the other driving units is that the signal input terminal IP receives, for example, together The start pulse is used as the input signal (Input) of the first driving unit S1, and the pulse width of the start signal is set to a first width W.

FIG. 2B is a timing diagram showing clock signals received by the gate driving circuit 10 of the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2, and the duty cycle thereof is 1/2, the pulse width is also the first width (W), and the two clock signals have a phase difference from each other, such as a time difference of the first width (W). In addition, as shown in FIG. 2A, in this embodiment, each driving unit will receive one of the two clock signals as its respective clock signal, and any two adjacent driving units receive different times. Pulse signal.

The third figure shows a circuit diagram of a driving unit of the gate driving circuit 10 of the embodiment of the present invention. This embodiment is described by taking the second driving unit S2 as an example, and is assumed to be an nth-level driving unit.

The nth stage driving unit 11 has a signal input terminal IP, a feedback signal input terminal RP, a signal output terminal OP, a carrier signal output terminal CP, and a switch M1 to a switch M6, wherein the switches M1 to M6 may be thin film transistors (TFTs) or any Semiconductor switching elements, such as NMOS transistors, PMOS transistors, BJT transistors, and the like. As described above, the nth stage driving driving unit 11 receives an input signal Input(n) via the signal input terminal IP, receives a feedback signal Output(n+2) via the feedback signal input terminal RP, and outputs a feedback signal output terminal OP via the signal output terminal OP. lose The output signal Output(n) is used to drive a column of pixels in the pixel array (for example, the nth column of pixels), and a carrier signal carrier(n) is outputted via the carrier signal output terminal CP to the N+1th stage driving unit as the nth The input signal Input(n+1) of the +1 stage drive unit. Each switch has a control end, a first end, and a second end. The first end of the switch M1 and the control end are coupled to the signal input end IP to receive the input signal Input(n), and the second end is coupled to the node X. The first end of the switch M2 is coupled to the clock signal CK2, the second end is coupled to the node Z and the carrier signal output terminal CP to output the carrier signal carrier(n), and the control end is coupled to the node X. The first end of the switch M3 is coupled to the node X, the second end is coupled to a low voltage source VSS (having a low potential, for example, -10V), and the control end is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+2). . The first end of the switch M4 is coupled to a high voltage source Vdd (having a high potential, for example, 15V), the second end is coupled to the signal output end OP and the first end of the switch M5, and the control end is coupled to the node X. The first end of the switch M5 is coupled to the signal output terminal OP, the second end is coupled to the low voltage source VSS, and the control end is coupled to the feedback signal input terminal RP. The first end of the switch M6 is coupled to the node Z, the second end is coupled to the low voltage source VSS, and the control end is coupled to the feedback signal input end RP.

The sizes of the above-mentioned switches M4 and M5 are larger than the sizes of the switches M2 and M6. For example, preferably, the sizes of the switches M10 and M5 may be different by several tens or even hundreds of times, because the switches M4 and M5 are coupled to the signal output terminal OP. For a switching element that drives a column of pixels, a larger capacitive load requires a larger switching element to be driven, and switches M2 and M6 are coupled to the carrier signal output terminal CP to output a carrier signal as an input signal of the next-stage driving unit. Large size switching elements are not required.

4A and 4B are diagrams showing a driving method of the gate driving circuit 10 according to the embodiment of the present invention, wherein the fourth A diagram shows that the gate driving circuit 10 drives the unit according to one of the third figures. For example, the input signal Input(n), the clock signal CK2, the feedback signal Output(n+2), the potential of the node X, and the carrier signal carrier (n) in the second-stage driving unit S2 (assumed to be the n-th driving unit) ), the timing diagram of the output signal Output(n), the output signal Output(n+1), and the fourth B diagram is the operational state of the switch M1 to the switch M6 with respect to the fourth A diagram. Moreover, in the following description, the high level may be, for example, 15 volts; the low level may be, for example, -10 volts, but it is not intended to limit the invention.

During T1, the input signal Input(n) received by the signal input terminal IP is at a high level, and the feedback signal Output(n+2) is at a low level. Therefore, the switch M1 is turned on, and the switches M3, M5, and M6 are turned off. The input signal Input(n) is coupled to node X and charges the potential of the node X to a high level. The high-level potential conduction switch M2 of the node X causes the low-level potential of the clock signal CK2 to be coupled to the node Z to output the low-level carrier signal carrier(n), and the high-level potential of the node X is also turned on. Switch M4 causes the high level potential of high voltage source Vdd to be coupled to signal output OP to output a high level output signal Output(n).

During T2, the input signal Input(n) and the feedback signal Output(n+2) are at a low level, so the switches M1, M3, M5, M6 are turned off. The potential of node X remains at a high level because there is no discharge path, causing switches M2, M4 to conduct. At this time, the clock signal CK2 is at a high level, and the high-level potential of the clock signal CK2 is coupled to the node Z via the switch M2 to output a carrier signal carrier(n) of a high level, and the high voltage source Vdd is high. The level potential is coupled to the signal output OP via switch M4 and outputs a high level output signal Output(n).

During T3, the input signal Input is at a low level and the switch M1 is turned off. The feedback signal Output(n+2) is at a high level, and the switches M3, M5, M6 are turned on, so that the potential of the node X is discharged to the low level via the switch M3, and the potential of the node Z is discharged to the potential via the switch M6. The low level, the potential of the signal output terminal OP is discharged to the low level via the switch M5, so the carrier signal output terminal CP outputs a low level carrier signal Carrier(n), and the signal output terminal OP outputs a low level output signal Output. (n).

During T4, the input signal Input is at a low level, the switch M1 is turned off, the potential of the node X is maintained at a low level, so that the switches M2 and M4 are turned off, and the potentials of the node Z and the signal output terminal OP are maintained due to the non-conduction of the charging path. Low level. On the other hand, the feedback signal Output(n+2) is at a high level, and the switches M3, M5, and M6 are turned on, so that the potentials of the node X, the node Z, and the signal output terminal OP are ensured at a low level, so the carrier signal output terminal CP A low-level carrier signal carrier(n) is output, and the signal output terminal OP outputs a low-level output signal output(n).

The output signals Output(n+1) and Output(n+2) are the output signals of the next-stage and lower-level driving units, and the timing chart can be deduced according to the above description. According to the gate driving circuit and the driving method of the second to fourth embodiments of the present invention, if the pulse width W of the starting signal is used as a reference, the carrier signal carrier outputted by each stage of the driving unit will be behind the received signal. The input signal Input has a time difference of the first width (W); the output signal Output of each stage of the driving unit has a pulse width of twice the pulse width W of the start signal, that is, the pulse width of the output signal Output is 2W. And, except for the first-stage driving unit, the output signal of each driving unit is behind the output signal of the previous-stage driving unit by a time difference of the first width (W), that is, the output signals of the adjacent two-stage driving units partially overlap each other. And the overlap period is one of the first widths (W), whereby the switching element for driving the column of pixels can be extended in opening time to achieve the effect of pre-charging. In addition, it can be seen from the fourth A picture that the output signal of the nth stage driving unit will overlap with the input signal Input portion thereof, and the overlap width is The degree is also the first width (W). In addition, the input signal received by each stage of the driving unit is the carrier signal output by the upper stage driving unit, instead of the output signal, so that the accumulated resistance-capacitance effect of the output signal of each stage of the driving unit is not coupled to the next-stage driving unit. In addition, each stage of the drive unit requires only one clock signal. In other words, the entire gate drive circuit requires only two clock signals and does not need to be divided into two groups, which is more power-saving and designed than the prior art. Easier advantage. In addition, when a switching element of the prior art is coupled to a clock signal at the first end or the second end thereof, the circuit stability may be affected by a coupling effect of the parasitic capacitance of the switch and the control end of the switch. In the embodiment of the present invention, since the size of the switch M2 can be tens or even hundreds of times smaller than the size of the switch M4, the coupling effect is almost negligible. In addition, in the embodiment of the present invention, no DC power source (such as a high voltage source Vdd) or a clock signal is coupled to the control end of any switching element, so the threshold voltage of each switching element after long-term use. It does not shift and the reliability is better.

Figure 5A shows a block diagram of a gate drive circuit 30 in accordance with an embodiment of the present invention. The gate driving circuit 30 includes a plurality of serially connected driving units 12, such as a first driving unit S1 to a fourth driving unit S4, etc., wherein each driving unit 12 receives an input signal, a feedback signal, and two clock signals. The clock signals CK1, CK2 are provided by a clock generator 20, and the pulse generator 20 may or may not be included in the gate driving circuit 30.

Each of the driving units 12 includes a signal input terminal IP for receiving an input signal Input, a feedback signal input terminal RP for receiving a feedback signal, a signal output terminal OP for outputting an output signal Output, and a carrier signal output terminal CP for output. A carrier signal carrier.

The signal output terminal OP of the two-stage driving unit and the signal signal output terminal CP of the two-stage driving unit are coupled to the signal input terminal IP of the next-stage driving unit; therefore, the driving unit 12 of each stage is received by the driving signal input terminal RP. The input signal Input is the carrier signal carrier output by the previous stage driving unit, and the received feedback signal is the output signal Output of the latter two-stage driving unit, but since the first driving unit S1 is the first stage of the serially connected driving unit The driving unit has a signal input terminal IP receiving an input signal received by the gate driving circuit 30, for example, a start signal, and the pulse width of the starting signal is a first width W.

FIG. 5B is a timing diagram showing clock signals received by the gate driving circuit 30 according to the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2, and the pulse width is also equal to the first width. (W), the duty cycle is 1/2, and the clock signals have a phase difference from each other, such as a time difference of the first width (W). In addition, the pulse waveforms of the two clock signals do not overlap each other and are cycled with each other. In addition, as shown in FIG. 5A, in this embodiment, each driving unit will receive the two clock signals (CK1 and CK2) to drive the unit circuit.

The sixth figure shows a circuit diagram of a driving unit of the gate driving circuit 30 of the embodiment of the present invention. This embodiment is described by taking the second driving unit S2 as an example, and is assumed to be an nth-level driving unit.

The nth stage driving unit 12 has a signal input terminal IP, a feedback signal input terminal RP, a signal output terminal OP, a carrier signal output terminal CP, and a switch M1 to a switch M4, wherein the switches M1 to M4 may be thin film transistors or any semiconductor switching elements. For example, NMOS transistors, PMOS transistors, BJT transistors, and the like. As described above, the nth stage driving unit 12 receives an input signal Input(n) via the signal input terminal IP, and is connected via the feedback signal input terminal RP. Receiving a feedback signal Output(n+2), outputting an output signal Output(n) via the signal output terminal OP to drive the nth column of pixels in the pixel array, and outputting a carrier signal carrier (carrier) via the carrier signal output terminal CP ) to the n+1th stage driving unit as the input signal Input(n+1) of the n+1th stage driving unit.

Each switch has a control end, a first end, and a second end. The first end of the switch M1 is coupled to the clock signal CK1, the second end is coupled to the node X and the signal output end OP to output the output signal Output(n), and the control end is coupled to the signal input end IP to receive the input signal Input(n). ). The first end of the switch M2 is coupled to the clock signal CK2, the second end is coupled to the node z and the carrier signal output terminal CP to output the carrier signal carrier (n), and the control end is coupled to the node X. The first end of the switch M3 is coupled to the node X, the second end is coupled to a low voltage source VSS (having a low potential, for example, -30V), and the control end is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+2). . The first end of the switch M4 is coupled to the node Z and the feedback signal output terminal CP, the second end is coupled to the low voltage source Vss, and the control end is coupled to the feedback signal input terminal RP. The sizes of the switches M1 and M3 may be larger than the sizes of the switches M2 and M4. For example, the size of the switches M1 and M3 may be different by tens or even hundreds of times. The reason is the same as before, and will not be described again.

7A and 7B are diagrams showing a driving method of the gate driving circuit 30 of the embodiment of the present invention, wherein FIG. 7A shows the driving circuit 30 of the gate driving circuit 30 according to the sixth figure, for example, the second stage driving unit S2 ( It is assumed that it is the input signal Input(n) in the nth stage driving unit, the clock signal CK1, the clock signal CK2, the potential of the node X, the potential of the node Z, the carrier signal Carrier(n), and the output signal Output(n). ), the timing diagram of the output signal Output(n+1), the feedback signal Output(n+2), and the seventh B diagram is the operational state of the switch M1 to the switch M4 with respect to the seventh A diagram.

During T1, the input signal Input(n) is a high level and feedback signal. No. Output(n+2) is low level, so switch M1 is turned on and switches M3 and M4 are turned off. The high level of the clock signal CK1 is coupled to the node X via the switch M1 and charges the potential of the node X to a high level to output a high-level output signal Output(n), and the high-level potential conduction switch of the node X M2 causes the low level potential of the clock signal CK2 to be coupled to the node Z to output the carrier signal Carrier(n) of the low level.

During T2, the input signal Input and the feedback signal Output(n+2) are at a low level, so the switches M1, M3, M4 are turned off. The potential of the node X is maintained at a high level because there is no discharge path, and the output signal Output(n) of the high level is output via the signal output terminal OP, and the high level of the node X causes the switch M2 to be turned on. At this time, the clock signal CK2 is at a high level, and the high level potential of the clock signal CK2 is coupled to the node Z via the switch M2 to output the carrier signal carrier(n) of the high level.

During T3, the input signal Input is at a low level and the switch M1 is turned off. The feedback signal Output(n+2) is at a high level, and the switches M3 and M4 are turned on, so that the potential of the node X is discharged to the low level via the switch M3, and the potential of the node Z is discharged to the low level via the switch M4, so the carrier The signal output terminal CP outputs a low-level carrier signal carrier (n), and the signal output terminal OP outputs a low-level output signal Output(n).

During T4, the input signal Input is at a low level, the switch M1 is turned off, the potential of the node X is maintained at a low level, so that the switch M2 is turned off, and the node Z potential is maintained at a low level because the charging path is not conducting. On the other hand, the feedback signal Output(n+2) is at a high level, and the switches M3 and M4 are turned on, so that the potentials of the node X and the node Z are ensured at a low level, so the carrier signal output terminal CP outputs a low-level carrier signal. Carrier(n) and signal output OP output a low level output signal output(n).

The output signals Output(n+1) and Output(n+2) are the output signals of the next-stage and lower-level driving units, respectively, and the timing chart can be deduced according to the above description. According to the gate driving circuit and the driving method of the fifth embodiment to the seventh embodiment of the present invention, if the pulse width of the start signal is a first width W, the carrier of each stage driving unit is output. The signal carrier lags behind the received input signal Input by a time difference of the first width (W); the output signal Output of each stage of the driving unit has a pulse width of twice the first width, that is, 2W, and the first stage driving unit The output signal of each stage of the driving unit is behind the output signal of the previous stage driving unit by a time difference of the first width (W), that is, the pulses of the output signals of the two adjacent driving units will partially overlap, and the overlapping width is The first width (W), by which the switching elements of the column of pixels are driven, can be extended to achieve a precharge effect. In addition, it can also be seen from the seventh A diagram that the output signal Output(n) of the nth stage driving unit will partially overlap with the input signal Input(n), and the overlap width is also the first width (W). In addition, the first clock signal CK1 is synchronized with the input signal or the start signal, that is, the pulse of the input signal and the pulse of the first clock signal CK1 are simultaneously generated.

In addition, the advantages of the fifth A to seventh embodiment are the same as those of the second A to fourth embodiment, the difference being that each of the latter driving units requires two clock signals, while the former only needs One, but the latter drive unit has two fewer switching elements than the former, and the required layout area is smaller, so the design is easier.

Figure 8A shows a block diagram of a gate drive circuit 40 in accordance with an embodiment of the present invention. The gate driving circuit 40 includes a plurality of serially connected driving units 13, such as a first driving unit S1 to a fourth driving unit S4, etc., wherein each driving unit 13 receives an input signal, a feedback signal, and a clock signal. The clock signals CK1 and CK2 are provided by a clock generator 20, and the pulse generator 20 may or may not be included in the gate driving power. Road 40.

Each of the driving units 13 includes a signal input terminal IP to receive an input signal Input, a feedback signal input terminal RP to receive a feedback signal, and a signal output terminal OP to output an output signal Output. The signal output terminal OP of each of the first-level driving units is coupled to the signal input terminal IP of the next-stage driving unit, and the signal input terminal RP of the two-stage driving unit is coupled to the signal output terminal OP of the two-stage driving unit; therefore, the driving unit of each stage is received by the driving unit 13 The input signal Input is the output signal Output of the previous stage driving unit, and the received feedback signal is the output signal Output of the latter two stages of driving units, but since the first driving unit S1 is the first stage driving of the serially connected driving units The signal input terminal IP receives the input signal received by the gate driving circuit 40, for example, a start signal, and the pulse width of the start signal is a first width W.

FIG. 8B is a timing diagram showing clock signals received by the gate driving circuit 40 according to the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2, and the pulse width is equal to the first. The width (W) and the duty cycle are both 1/2, and the two clock signals have a phase difference from each other, for example, a time difference of the first width (W). In addition, the pulse waveforms of the two clock signals do not overlap each other. In addition, as shown in FIG. 8A, in this embodiment, each driving unit will receive one of the two clock signals as its respective clock signal, and any two adjacent driving units receive different time. Pulse signal. FIG. 9 is a circuit diagram showing two driving units of the gate driving circuit 40 according to the embodiment of the present invention. The first driving unit S1 and the second driving unit S2 are taken as an example for the description, and assumed to be the n-th. Level 1 drive unit and stage n drive unit.

The n-1th driving unit and the nth driving unit each have a signal input terminal IP, Feedback signal input terminal RP, signal output terminal OP, two switches - the former has switches M1 and M2 and the latter has switches M3 and M4, wherein the switches M1 to M4 can be thin film transistors or any semiconductor switching elements, such as NMOS transistors , PMOS transistors, BJT transistors and so on.

The n-1th driving unit receives an input signal Input(n-1) via the signal input terminal IP, receives a feedback signal Output(n+1) via the feedback signal input terminal RP, and outputs an output signal Output via the signal output terminal OP. (n-1) driving the n-1th column pixel in the pixel array, and outputting the output signal Output(n-1) to the signal input terminal IP of the nth stage driving unit via the signal output terminal OP as its input Signal Input(n). The nth stage driving unit receives a feedback signal Output(n+2) via the feedback signal input terminal RP, and outputs an output signal Output(n) via the signal output terminal OP to drive the nth column of pixels in the pixel array.

Each switch has a control end, a first end, and a second end. For the n-1th stage driving unit, the first end of the switch M1 is coupled to the clock signal CK1, the second end is coupled to the node X and the signal output end OP to output the output signal Output(n-1), and the control end coupling Connect to the signal input IP to receive the input signal Input(n-1). The first end of the switch M2 is coupled to the node X and the signal output terminal OP, the second end is coupled to a low voltage source VSS (having a low potential, for example, -10V), and the control end is coupled to the feedback signal input terminal RP to receive the feedback signal Output. (n+1).

For the nth stage driving unit, the first end of the switch M3 is coupled to the clock signal CK2, the second end is coupled to the node Y and the signal output end OP to output the output signal Output(n), and the control end is coupled to the signal input. End IP to receive the input signal Input(n). The first end of the switch M4 is coupled to the node Y and the signal output terminal OP, the second end is coupled to the low voltage source VSS, and the control end is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+2).

10A and 10B show the driving of the gate driving circuit 40 of the embodiment of the present invention. The method of the tenth A shows the input signal Input(n-1), the clock signal CK1, the clock signal CK2, the potential of the node X, and the node in the two driving units of the gate driving circuit 40 according to the ninth figure. Timing diagram of potential of Y, output signal Output(n-1), output signal Output(n), feedback signal Output(n+1), feedback signal Output(n+2), and the tenth B-picture is relative to The operation state of the switch M1 to the switch M4 of the tenth A diagram.

During T1, the input signal Input(n-1) is at a high level, and the feedback signals Output(n+1) and Output(n+2) are at a low level. Therefore, the switch M1 is turned on, and the switches M2 and M4 are turned off. The high level of the clock signal CK1 is coupled to the node X via the switch M1 and charges the potential of the node X to a high level to output a high level output signal Output(n-1), and the high level potential of the node X The turn-on switch M3 causes the low-level potential of the clock signal CK2 to be coupled to the node Y to output the low-level output signal Output(n).

During T2, the input signal Input(n-1) and the feedback signals Output(n+1) and Output(n+2) are at a low level, so the switches M1, M2, and M4 are turned off. The potential of the node X is maintained at a high level because there is no discharge path, and the output signal Output(n-1) of the high level is output via the signal output terminal OP, and the high level of the node X causes the switch M3 to be turned on. At this time, the clock signal CK2 is at a high level, and the high level potential of the clock signal CK2 is coupled to the node Y via the switch M3 to output a high level output signal Output(n).

During T3, the input signal Input(n-1) is at a low level and the switch M1 is turned off. The feedback signal Output(n+1) is at a high level, and the switch M2 is turned on, so that the potential of the node X is discharged to a low level via the switch M2, so the signal output terminal OP outputs a low level output signal Output(n-1). . For the nth stage driving unit, the node X is at a low level, the switch M3 is turned off, and the feedback signal Output(n+2) is at a low level, so the potential of the node Y is due to no discharge path. Maintaining at a high level, the output signal Output(n) of the high level is output via the signal output terminal OP.

During T4, the input signal Input(n-1) is at a low level, the switch M1 is turned off, the potential of the node X is maintained at a low level, the output signal Output(n-1) is maintained at a low level, and the node X is low. The potential of the bit causes the switch M3 to be turned off. The feedback signal Output(n+2) is at a high level, so that the switch M4 is turned on, the potential of the node Y is discharged to a low level, and the low-level output signal Output(n) is output via the signal output terminal OP.

According to the gate driving circuit and the driving method of the eighth embodiment to the tenth embodiment of the present invention, if the pulse width of the start signal is a first width w as a reference, the output signal of each stage of the driving unit Output, the pulse width is 2W, and the output signal of each stage of the driving unit is behind the output signal of the previous stage driving unit by a time difference of the first width (W), that is, the overlapping width of the pulses of two adjacent driving units will be the first A width (W), whereby the switching element that drives the column of pixels can be extended in opening time to achieve the effect of pre-charging. In addition, it can also be seen from the tenth A diagram that the output signal Output(n-1) of the n-1th stage driving unit will partially overlap with the input signal Input(n-1), and the overlap width is also the first width. (W).

In addition, the advantages of the eighth to tenth embodiment are the same as those of the second to fourth embodiments, the difference being that the former drive unit requires only two switching elements, and the required layout area is more Less, so design is easier. In addition, in each of the above embodiments, the clock generator only needs to generate a set of time signals (each of which includes two corresponding clock signals CK1 and CK2) to drive all the driving in the gate driver. The unit does not need to divide all the driving units in the gate driver into odd group driving units and even group driving units as in the prior art (for example, as shown in FIG. A), and two sets of clock signals are required (four times in total) Pulse signal) to drive the odd group drive unit and the even group drive unit respectively. In addition, in the above embodiment, the output signal of each driving unit has a pulse width of a start signal pulse or a time pulse signal. In the prior art, the pulse width of the output signal of each driving unit is the same as the pulse width of the clock signal.

Fig. 11A is a block diagram showing the gate driving circuit 50 of the embodiment of the present invention. The gate driving circuit 50 includes a plurality of serially connected driving units 14, such as a first driving unit S1 to a fourth driving unit S4, etc., wherein each driving unit 14 receives an input signal, a feedback signal, and a clock signal. The clock signals CK1 and CK2 are provided by a clock generator 20, and the pulse generator 20 may or may not be included in the gate driving circuit 50.

Each of the driving units 14 includes a signal input terminal IP to receive an input signal Input, a feedback signal input terminal RP to receive a feedback signal, and a signal output terminal OP to output an output signal Output. The signal output terminal OP of each of the first-level driving units 14 is coupled to the signal input terminal IP of the next-stage driving unit, and the signal input terminal RP of the third-level driving unit is coupled to the signal output terminal OP of the third-level driving unit; therefore, the driving output of each of the driving units 14 is The input signal Input is the output signal Output of the previous stage driving unit, and the received feedback signal is the output signal of the last three stages of driving units, but since the first driving unit 14 is the first stage driving unit of the series driving unit The signal input terminal IP receives the input signal received by the gate driving circuit 50, for example, a start signal, and sets the pulse width of the start signal to a first width W.

FIG. 11B is a timing diagram showing clock signals received by the gate driving circuit 50 according to the embodiment of the present invention. The clock generator 20 generates two clock signals CK1 and CK2, and the duty cycle of each clock signal. The duty cycle is 2/3, the pulse width is twice the first width (W), that is, 2W, and the clock signal CK2 lags behind the clock signal CK1 by a time difference of the first width (W). The immediate pulse signals CK1 and CK2 partially overlap, and the overlap width is The first width (W). In addition, as shown in FIG. 11A, in this embodiment, only two clock signals are needed, and each driving unit receives one of the two clock signals as its respective clock signal, and Two adjacent drive units receive different clock signals.

FIG. 12 is a circuit diagram showing a driving unit of the gate driving circuit 50 of the embodiment of the present invention. The second driving unit S2 is taken as an example for the description, and is assumed to be an nth-level driving unit.

The nth stage driving unit has a signal input terminal IP, a feedback signal input terminal RP, a signal output terminal OP, and switches M1 to M3, wherein the switches M1 to M3 may be a thin film transistor or any semiconductor switching element, such as an NMOS transistor, a PMOS battery. Crystals, BJT transistors, etc.

As described above, the nth stage driving unit receives an input signal Input(n) via the signal input terminal IP, receives a feedback signal Output(n+3) via the feedback signal input terminal RP, and outputs an output signal via the signal output terminal OP. Output(n) drives a list of pixels in the pixel array, such as the nth column of pixels.

Each switch has a control end, a first end, and a second end. The first end of the switch M1 and the control end are coupled to the input signal terminal IP to receive the input signal Input(n), and the second end is coupled to the node X. The first end of the switch M2 is coupled to the clock signal CK1, the second end is coupled to the signal output end OP to output the output signal Output(n), and the control end is coupled to the node X. The first end of the switch M3 is coupled to the node X, the second end is coupled to a low voltage source VSS (having a low potential, for example, -10V), and the control end is coupled to the feedback signal input terminal RP to receive the feedback signal Output(n+3). .

13A and 13B show a driving method of the gate driving circuit 50 according to the embodiment of the present invention, wherein FIG. 13A shows the input signal Input in the driving unit of the gate driving circuit 50 according to the twelfth figure. (n), the clock signal CK1, the potential of the node X, The timing diagram of the output signal Output(n) and the feedback signal Output(n+3), and the thirteenth Bth diagram is the operational state of the switch M1 to the switch M2 with respect to the thirteenth A diagram.

During T1, the input signal Input(n) is at a high level and the feedback signal Output(n+3) is at a low level, so the switch M1 is turned on and the switch M3 is turned off. The high level of the input signal Input(n) is coupled to the node X via the switch M1 and charges the potential of the node X to a high level, and the high level potential of the node X turns on the switch M2 to make the high level potential of the clock signal CK1 An output signal Output(n) that is coupled to the signal output OP and outputs a high level.

During T2, the input signal Input(n) and the feedback signal Output(n+3) are at a low level, so the switches M1, M3 are turned off. The potential of the node X is maintained at a high level because there is no discharge path, so that the switch M2 is turned on, and the high level of the clock signal CK1 is coupled to the signal output terminal OP via the switch M2 to output a high-level output signal Output(n) .

During T3, the input signal Input(n) and the feedback signal Output(n+3) are at a low level, so the switches M1, M3 are turned off. The potential of the node X is maintained at a high level because there is no discharge path, so that the switch M2 is turned on, at which time the clock signal CK1 is at a low level, and the low level of the clock signal CK1 is coupled to the signal output terminal OP via the switch M2. Output low output signal Output(n).

During T4 and T5, the input signal Input(n) is at a low level, so the switch M1 is turned off. The feedback signal Output(n+3) is at a high level, and the potential of the node X is discharged to a low level via the switch M3, so the switch M2 is turned off, and the output signal Output(n) is maintained at a low level.

During T6, T7, and T8, the input signal Input(n) is at a low level, so the switch M1 is turned off, so the potential of the node X is maintained at a low level, so the switch M2 is turned off, and the input is turned off. The potential of the output signal terminal OP is maintained at a low level to output a low level output signal Output(n).

The output signals Output(n+1), output(n+2), and output(n+3) are the output signals of the next, lower, and lower three-level driving units, and the timing chart can be based on the above description and so on. . According to the gate driving circuit and the driving method of the eleventh to thirteenthth embodiment of the present invention, if the pulse width of the start signal is a first width W as a reference, the output of each stage of the driving unit a signal whose pulse width is twice the first width (W), that is, 2W, and the output signal of each stage of the driving unit is behind the output signal of the previous stage driving unit by a time difference of the first width (W), thereby The switching element that drives the column of pixels can be extended in opening time to achieve the effect of pre-charging. In addition, it can be seen from the 13th A picture that the output signal Output(n) of the nth stage driving unit partially overlaps with the input signal Input(n), and the overlap width is also the first width (W); The clock signal CK1 is synchronized with the input signal or the start signal, that is, the pulse of the input signal and the pulse of the clock signal CK1 are simultaneously generated. In addition, the signal pulse of node X is three times the first width (W).

In addition, the advantages of the eleventh to thirteenthth embodiment are substantially the same as those of the previous embodiment, and the difference is that the clock signal used in the embodiment has a duty cycle of 2/3, whereas the previous embodiment is 1/2, but since each stage of the drive unit requires only one clock signal, it still has a power saving effect. In addition, in this embodiment, only three switching elements are required for each stage of the driving unit, and the required layout area is small, and the design is easy.

Fig. 14A is a block diagram showing the gate driving circuit 60 of the embodiment of the present invention. The gate driving circuit 60 includes a plurality of serially connected driving units 15, such as a first driving unit S1 to a fourth driving unit S4, etc., wherein each driving unit 15 receives an input signal, two clock signals, wherein the clock Signals CK1 through CK6 are provided by a clock generator 20, and at this time pulse generator 20 may or may not be included in the gate drive circuit 60.

Each driving unit 15 includes a signal input terminal IP to receive an input signal Input and a signal output terminal OP to output an output signal Output. The signal output terminal OP of each stage of the driving unit 15 is coupled to the signal input terminal IP of the next stage driving unit; therefore, the input signal Input received by each stage of the driving unit 15 is the output signal Output of the previous stage driving unit, but A driving unit 15 is a first-stage driving unit of the serial driving unit, and the signal input terminal IP receives an input signal received by the gate driving circuit 60, for example, a start signal, and sets a pulse width of the start signal. Is a first width W.

FIG. 14B is a timing diagram showing clock signals received by the gate driving circuit 60 of the embodiment of the present invention. The clock generator 20 generates a total of six clock signals CK1 to CK6, wherein the clock signals CK1 to CK3 The duty cycle is 1/3, the pulse width is also the first width (W), and has a phase difference between each other, for example, a time difference of the first width (W), and does not overlap each other; the clock signal CK4 to The duty cycle of CK6 is 2/3, the pulse width is twice the first width (W), that is, 2W, and there is a phase difference between each other, for example, a time difference of the first width (W), in other words, CK4 To CK6, the pulses of the adjacent two clock signals partially overlap each other, and the overlap width is the first width (W). That is, the embodiment includes a total of two sets of clock signals, a first group and a second group of clock signals, wherein the first group of clock signals includes three clock signals of CK1 to CK3, and the first group of clock signals The pulse width is the first width, and the second set of clock signals includes three clock signals of CK4 to CK6, and the second group of clock signals has a pulse width of twice the first width. In addition, as shown in FIG. 14A, each driving unit receives only one of the first group of clock signals and one of the second group of clock signals to drive the unit circuit, and two adjacent driving units. Receive different clock signals.

Figure 15 shows a drive of the gate drive circuit 60 of the embodiment of the present invention. The circuit diagram of the unit is described by taking the second driving unit S2 as an example, and is assumed to be the nth stage driving unit.

The nth stage driving unit has a signal input terminal IP, a signal output terminal OP, and switches M1 to M2, wherein the switches M1 to M2 may be thin film transistors or any semiconductor switching elements, such as NMOS transistors, PMOS transistors, BJT transistors, etc. Wait. As described above, the nth stage driving unit receives an input signal Input(n) via the signal input terminal IP, and outputs an output signal Output(n) via the signal output terminal OP to drive a column of pixels in the pixel array, for example, n columns of pixels.

Each switch has a control end, a first end, and a second end. The first end of the switch M1 is coupled to the signal input terminal IP to receive the input signal Input(n), the second end is coupled to the node X, and the control terminal is coupled to the clock signal CK1. The first end of the switch M2 is coupled to the clock signal CK4, the second end is coupled to the signal output end OP to output the output signal Output(n), and the control end is coupled to the node X.

16A and 16B show a driving method of the gate driving circuit 60 according to the embodiment of the present invention, wherein FIG. 16A shows the input signal Input in the driving unit of the gate driving circuit 60 according to the fifteenth figure. n), clock signal CK1, clock signal CK4, potential of node X, output signal Output(n), output signal Output(n+1), output signal Output(n+2) timing diagram, and the sixteenth The B diagram is an operational state of the switch M1 to the switch M2 with respect to the sixteenth A diagram.

During T1, the clock signal CK1 and the input signal Input(n) are at a high level, so the switch M1 is turned on, and the high level of the input signal Input(n) is coupled to the node X via the switch M1 and the potential of the node X Charging to a high level, the high-level potential conduction switch M2 of the node X causes the high-level potential of the clock signal CK4 to be coupled to the signal output terminal OP for output High level output signal Output(n).

During T2, the clock signal CK1 is at a low level, so the switch M1 is turned off. The potential of the node X is maintained at a high level because there is no discharge path, so that the switch M2 is turned on, and the high level of the clock signal CK4 is coupled to the signal output terminal OP via the switch M2 to output a high-level output signal Output(n) .

During T3, the clock signal CK1 is at a low level, so the switch M1 is turned off. The potential of the node X is maintained at a high level because there is no discharge path, so that the switch M2 is turned on, and the low level of the clock signal CK4 is coupled to the signal output terminal OP via the switch M2 to output a low-level output signal Output(n) .

During T4, the clock signal CK1 is at a high level, so the switch M1 is turned on. At this time, the low level of the input signal Input(n) is coupled to the node X, so that the potential of the node X is at a low level, and the switch M2 is turned off. The signal output terminal OP is maintained at a low level and outputs a low level output signal Output(n).

During T5 and T6, the clock signal CK1 is at a low level, so the switch M1 is turned off, the node X is maintained at the low level, the switch M2 is kept off, and the signal output terminal OP is maintained at the low level to output the output signal of the low level. Output(n).

During T7, the clock signal CK1 is at a high level, so the switch M1 is turned on, at which time the low level of the input signal Input(n) is coupled to the node X such that the potential of the node X is at a low level and the switch M2 is turned off. The signal output terminal OP is maintained at a low level and outputs a low level output signal Output(n).

During T8, the clock signal CK1 is at a low level, so the switch M1 is turned off, the node X is maintained at the low level, the switch M2 is kept off, and the signal output terminal OP is maintained at the low level. And output the low level output signal Output(n).

The output signal (n+1) and the output signal (n+2) are output signals of the next-stage and lower-level driving units, and the timing chart thereof can be deduced according to the above description. According to the gate driving circuit and the driving method of the fourteenth to sixteenth embodiments of the present invention, if the pulse width of the input signal or the clock signal CK1 is the first width W as a reference, each stage is driven. The output signal of the unit has a pulse width of 2W, and the output signal of each stage of the driving unit is behind the output signal of the previous stage driving unit by one W, that is, the pulses of the adjacent output signals partially overlap each other by a first width (W), The switching element that drives the column of pixels can be extended in time to achieve the effect of pre-charging. In addition, it can be seen from the sixteenth A diagram that the output signal Output(n) of the nth stage driving unit partially overlaps with the input signal Input(n), and the overlap width is also the first width (W). In addition, the signal pulse of the node X is three times the first width (W), and the clock signals CK1, CLK4 and the input signal (or the start signal) are generated in synchronization with each other.

In addition, the advantages of the fourteenth embodiment to the sixteenth embodiment are substantially the same as those of the previous embodiment, and the difference is that the clock signal used in the embodiment has a duty cycle of 2/3, and the previous embodiment is 1/2, but since each stage of the drive unit requires only one clock signal, it still has a power saving effect. In addition, in this embodiment, only two switching elements are required for each stage of the driving unit, and the required layout area is small, and the design is easy.

In the above, the gate driving circuit and the driving method according to the embodiment of the present invention not only increase the stability and reliability of operation, but also reduce the power consumption of the overall driving circuit by reducing the number of clock signals and the duty cycle of the clock signal. The power can be greatly reduced.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention; Changes or modifications are intended to be included in the scope of the claims below.

10‧‧‧ gate drive circuit

11‧‧‧Drive unit

20‧‧‧ clock generator

CK1-CK2‧‧‧ clock signal

IP‧‧‧ signal input

OP‧‧‧ signal output

RP‧‧‧ feedback signal input

CP‧‧‧carrier signal output

Input‧‧‧ input signal

Output‧‧‧Output signal

Carrier‧‧‧Carrier Signal

Claims (33)

  1. A gate driving circuit comprises a plurality of serially connected driving units, each driving unit comprises: a signal input end, receiving an input signal; a feedback signal input end receiving a feedback signal; a carrier signal output end, outputting a a signal signal outputting an output signal to drive a column of pixels; a first switch having a first end coupled to a control terminal for receiving the input signal and a second end coupling Connected to a first node; a second switch having a first end coupled to a clock signal, a second end coupled to a second node and the carrier signal output end for outputting the carrier signal, and a control terminal coupled to the second node a first switch; a third switch having a first end coupled to the first node, a second end coupled to a low voltage source, and a control end coupled to the feedback signal input end for receiving the feedback signal; The switch has a first end coupled to the high voltage source, a second end coupled to the signal output end, and a control end coupled to the first node; a fifth switch having a first end coupled to the fourth The second end of the switch a signal output end, a second end coupled to the low voltage source, a control end coupled to the feedback signal input end; and a sixth switch having a first end coupled to the second node and a second end coupled The low voltage source and a control end are coupled to the feedback signal input end; wherein the carrier signal output end of each drive unit is coupled to the signal input end of the next stage drive unit, and the feedback signal input end is coupled to the output of the lower two stage drive unit Signal side.
  2. a gate drive circuit according to item 1 of the patent application scope, wherein the plurality of strings The signal input end of the first stage driving unit of the driving unit receives the start signal as the input signal of the first stage driving unit, and the pulse width of the starting signal is a first width (W). The pulse width of the pulse signal is also the first width (W), the duty cycle is 1/2, and the clock signal is behind the start signal to have a time difference of the first width (W).
  3. According to the gate driving circuit of claim 2, wherein the output signal of each driving unit has a pulse width of a second width (2W), and the second width is twice the first width (W) And the pulses of the output signals of the adjacent two driving units partially overlap each other.
  4. According to the gate driving circuit of claim 3, wherein the width of the overlapping portion is the first width (W).
  5. According to the gate driving circuit of claim 3, the output signal of the first driving unit and the pulse of the starting signal partially overlap each other, and the width of the overlapping portion is the first width.
  6. According to the second aspect of the patent application, the gate driving circuit includes only two clock signals, which have a time difference of the first width (W), and each driving unit receives the two clock signals. One of them is the respective clock signal, and two adjacent driving units receive different clock signals.
  7. According to the gate driving circuit of claim 2, wherein the size of the fourth switch and the fifth switch is larger than the size of the second switch and the sixth switch, the sizes of the two switches are several tens to hundreds of times.
  8. According to the gate driving circuit of claim 2, wherein the carrier signal output by each driving unit is behind the input signal received by the driving unit by a time difference of the first width (W), and the output signal of each driving unit , the pulse width is the first width It is twice the degree and is behind the output signal of the previous driving unit by a time difference of the first width.
  9. A gate driving circuit comprises a plurality of serially connected driving units, each driving unit comprises: a signal input end, receiving an input signal; a feedback signal input end receiving a feedback signal; a carrier signal output end, outputting a a signal signal outputting an output signal to drive a column of pixels; a first switch having a first end coupled to a first clock signal and a second end coupled to a first node and the a signal output end, a control end coupled to the signal input end; a second switch having a first end coupled to a second clock signal, a second end coupled to a second node and the carrier signal output end, a control terminal is coupled to the first node; a third switch has a first end coupled to the first node, a second end coupled to a low voltage source, and a control end coupled to the feedback signal input end; The fourth switch has a first end coupled to the second node and the feedback signal output end, a second end coupled to the low voltage source, and a control end coupled to the feedback signal input end; wherein each of the driving units Carrier signal output terminal coupled A signal input terminal of the driving unit, feedback signal output coupled to a signal input terminal took two drive units.
  10. According to the gate drive circuit of claim 9, wherein the signal input end of the first stage drive unit of the plurality of serially connected drive units receives a start signal as the input signal of the first stage drive unit, The pulse width of the start signal is a first width (W), the duty cycle of the first clock signal and the second clock signal are both 1/2, and the pulse width is also the first width (W). The second clock signal lags behind the first clock signal by the first A time difference of width (W), and the first clock signal is synchronized with the start signal.
  11. The gate driving circuit according to item 9 of the patent application scope includes only the first clock signal and the second clock signal.
  12. The gate driving circuit of claim 10, wherein a pulse width of the output signal of each driving unit is a second width (2W), and the second width is twice the first width (W) And the pulses of the output signals of the adjacent two driving units overlap each other.
  13. According to the gate driving circuit of claim 10, the width of the overlapping portion of the output signal of the first driving unit and the pulse of the starting signal is the first width.
  14. According to the gate driving circuit of claim 9, wherein the size of the first switch and the third switch is larger than the size of the second switch and the fourth switch, and the size is different by several tens to 100 times.
  15. According to the gate driving circuit of claim 10, wherein the carrier signal output by each driving unit is behind the input signal received by the driving unit by a time difference of the first width (W), and the output signal of each driving unit The pulse width is twice the first width (W) and is behind the output signal of the previous driving unit by a time difference of the first width (W).
  16. A gate driving circuit comprises a plurality of serially connected driving units, each driving unit comprises: a signal input end receiving an input signal; a feedback signal input end receiving a feedback signal; a signal output end, an output output a signal to drive a column of pixels; a first switch having a first end coupled to a clock signal and a second end coupled to a node The signal output end and a control end are coupled to the signal input end; a second switch having a first end coupled to the node and the signal output end and a second end coupled to a low voltage source and a control end coupling The signal output end of each driving unit is coupled to the signal input end of the next-stage driving unit, and the feedback signal input end is coupled to the output signal end of the lower two-stage driving unit.
  17. According to the gate drive circuit of claim 16, wherein the signal input end of the first stage drive unit of the plurality of serially connected drive units receives a start signal as the input signal of the first stage drive unit, The pulse width of the start signal is a first width (W), the duty cycle of the clock signal is 1/2, the pulse width is also the first width (W), and the clock signal is synchronized with the start signal. .
  18. The gate driving circuit according to claim 17 of the patent application includes only two clock signals having a time difference of the first width (W) with each other, and each driving unit receives the two clock signals. One of them is the respective clock signal, and the adjacent two driving units receive different clock signals.
  19. According to the gate driving circuit of claim 17, wherein the pulse width of the output signal of each driving unit is a second width (2W), and the second width is twice the first width (W). The pulses of the output signals of any two adjacent driving units overlap each other, and the output signals of the first driving unit and the pulse of the starting signal overlap with each other.
  20. According to the gate driving circuit of claim 17, wherein the output signal of each driving unit has a pulse width of twice the first width (W) and is lower than the output signal of the previous driving unit. The time difference of width (W).
  21. A gate driving circuit comprises a plurality of serially connected driving units, each driving unit comprises: a signal input end receiving an input signal; a feedback signal input end receiving a feedback signal; a signal output end, an output output a signal for driving a column of pixels; a first switch having a first end coupled to the control terminal and the second terminal coupled to the node; and a second switch having a first end coupling Connected to a clock signal, a second end coupled to the signal output end, a control end coupled to the node; and a third switch having a first end coupled to the node and a second end coupled to a low voltage source The control end is coupled to the feedback signal input end; wherein the signal output end of each drive unit is coupled to the signal input end of the next-stage drive unit, and the feedback signal input end is coupled to the output signal end of the lower three-stage drive unit.
  22. According to the gate drive circuit of claim 21, the signal input end of the first stage drive unit of the plurality of serially connected drive units receives a start signal as the input signal of the first drive unit, and the The pulse width of the start signal is a first width (W), the duty cycle of the clock signal is 2/3, the pulse width is twice the first width (W), and the start signal and the clock signal are Synchronize.
  23. According to the gate drive circuit of claim 22, wherein the output signal of each drive unit has a pulse width of twice the first width (W), and the output signals of any two adjacent drive units are pulsed with each other. Partially overlapping, and the width of the overlapping portion of the output signal of the first driving unit and the pulse of the starting signal is the first width.
  24. The gate drive circuit according to item 22 of the patent application scope contains only two a clock signal having a time difference of the first width (W) with each other, and each driving unit receives one of the two clock signals as a respective one of the clock signals, and the two adjacent driving units receive Different clock signals.
  25. According to the gate driving circuit of claim 22, wherein the output signal of each driving unit has a pulse width of twice the first width (W) and is lower than the output signal of the previous driving unit. The time difference of width (W).
  26. According to the gate driving circuit of claim 22, the pulse width of the signal of the node is three times the first width.
  27. A gate driving circuit comprises a plurality of serially connected driving units, each driving unit comprises: a signal input end receiving an input signal; a signal output end outputting an output signal to drive a column of pixels; The switch has a first end coupled to the input end, a second end coupled to a node, a control end coupled to the first clock signal, and a second switch having a first end coupled to the first The second clock signal, a second end coupled to the signal output end, and a control end coupled to the node; wherein the signal output end of each drive unit is coupled to the signal input end of the next stage drive unit.
  28. According to the gate drive circuit of claim 27, wherein the signal input end of the first stage drive unit of the plurality of serially connected drive units receives a start signal as the input signal of the first stage drive unit, The pulse width of the start signal is a first width (W), the duty cycle of the first clock signal is 1/3, and the pulse width is also the first width (W), and the second clock signal works. The period is 2/3, and the pulse width is the first width. The start signal is synchronized with the first clock signal and the second clock signal by twice the degree (W).
  29. According to the gate driving circuit of claim 28, the first clock signal and the pulse of the second clock signal partially overlap each other, and the width of the overlapping portion is the first width.
  30. According to the gate driving circuit of claim 28, wherein the output signal of each driving unit has a pulse width of twice a first width (W), and the pulse of the output signals of any two adjacent driving units has a pulse The portions overlap each other, and a width of an overlapping portion of the output signal of the first driving unit and a pulse of the start signal is the first width.
  31. According to the gate driving circuit of claim 28, the pulse width of the signal of the node is three times the first width.
  32. The gate driving circuit according to item 27 of the patent application scope includes a first group and a second group of clock signals, wherein each group of clock signals respectively includes three clock signals, and the first group of clock signals thereof The pulse width is the first width, and the pulse width of the second group of clock signals is twice the first width, and each driving unit receives only one of the first set of clock signals and the second One of the group clock signals is used as the respective first and second clock signals, and the two adjacent driving units receive different clock signals.
  33. According to the gate drive circuit of claim 28, wherein the output signal of each drive unit has a pulse width of twice the first width (W) and is lower than the output signal of the previous drive unit. The time difference of width (W).
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TWI455094B (en) * 2012-06-07 2014-10-01 Au Optronics Corp Gate driver of display device and operating method thereof
TWI664614B (en) * 2018-12-13 2019-07-01 凌巨科技股份有限公司 Gate driving apparatus

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TW200521949A (en) * 2003-12-30 2005-07-01 Boe Hydis Technology Co Ltd Driving circuit of liquid crystal display
US20070001953A1 (en) * 2005-06-30 2007-01-04 Jang Yong H Display apparatus
US20070038909A1 (en) * 2005-07-28 2007-02-15 Kim Sung-Man Scan driver, display device having the same and method of driving a display device
US20070195053A1 (en) * 2006-02-23 2007-08-23 Mitsubishi Electric Corporation Shift register circuit and image display apparatus containing the same
TW200826052A (en) * 2006-08-31 2008-06-16 Semiconductor Energy Lab Liquid crystal display device
TW200912878A (en) * 2007-07-06 2009-03-16 Samsung Electronics Co Ltd Liquid crystal display and method of driving the same
TW200926137A (en) * 2007-12-12 2009-06-16 Hannstar Display Corp Driving signal generating circuit and signal generatiing method thereof
TW200931427A (en) * 2008-01-09 2009-07-16 Au Optronics Corp Shift register

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200521949A (en) * 2003-12-30 2005-07-01 Boe Hydis Technology Co Ltd Driving circuit of liquid crystal display
US20070001953A1 (en) * 2005-06-30 2007-01-04 Jang Yong H Display apparatus
US20070038909A1 (en) * 2005-07-28 2007-02-15 Kim Sung-Man Scan driver, display device having the same and method of driving a display device
US20070195053A1 (en) * 2006-02-23 2007-08-23 Mitsubishi Electric Corporation Shift register circuit and image display apparatus containing the same
TW200826052A (en) * 2006-08-31 2008-06-16 Semiconductor Energy Lab Liquid crystal display device
TW200912878A (en) * 2007-07-06 2009-03-16 Samsung Electronics Co Ltd Liquid crystal display and method of driving the same
TW200926137A (en) * 2007-12-12 2009-06-16 Hannstar Display Corp Driving signal generating circuit and signal generatiing method thereof
TW200931427A (en) * 2008-01-09 2009-07-16 Au Optronics Corp Shift register

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