TW202020842A - Display panel - Google Patents

Abstract

A display panel includes multiple pixel circuits and a compensation circuit. The multiple pixel circuits locate at a display area. The compensation circuit locates at a non-display area, and couples with some of the multiple pixel circuits. The compensation circuit includes a first switch, a second switch, and a dummy transistor. A first node of the first switch is configured to receive a predetermined high voltage, a second node of the first switch couples with a first nodal point, and the control node of the first switch is configured to receive a first control signal. A first node of the second switch couples with a second nodal point, a second node of the second switch couples with the first nodal point, and the control node of the second switch is configured to receive a second control signal. A first node of the dummy transistor is configured to receive a predetermined low voltage, a second node of the dummy transistor couples with the second nodal point, and a control node of the dummy transistor is configured to receive a reference voltage. The compensation circuit is configured to selectively output the predetermined high voltage or a threshold voltage of the dummy transistor to the some of the multiple pixel circuits.

Description

Display panel

This disclosure relates to a display panel, in particular to a display panel having a compensation circuit coupled to multiple pixel circuits.

Low temperature poly-silicon thin-film transistor (low temperature poly-silicon thin-film transistor) has the characteristics of high carrier mobility and small size, suitable for high resolution, narrow frame and low power consumption display panel. At present, the industry widely uses excimer laser annealing (excimer laser annealing) technology to form polysilicon thin films of low-temperature polysilicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, in different areas of the display panel, the characteristics of the low-temperature polysilicon thin film transistor will be different. For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages.

At present, the industry widely uses the technical solution of intra-pixel compensation to overcome the above-mentioned critical voltage variation problem. However, the pixel circuit with the internal pixel compensation function has a complicated circuit structure, so that the aperture ratio of the related display panel is low.

In view of this, how to provide high aperture ratio and can compensate for thin film The display panel with the variation of the critical voltage of the crystal is really a problem to be solved in the industry.

The present disclosure provides a display panel. The display panel includes a plurality of pixel circuits and a compensation circuit. Multiple pixel circuits are located in a display area. The compensation circuit is located in a non-display area and is coupled to a part of the pixel circuits among the plurality of pixel circuits. The compensation circuit includes a first switch, a second switch, and a matching transistor. The first switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the first switch is used to receive a predetermined high voltage. The second terminal of the first switch is coupled to a first node. The control end of a switch is used to receive a first control signal. The second switch includes a first terminal, a second terminal and a control terminal, the first terminal of the second switch is coupled to a second node, the second terminal of the second switch is coupled to the first node, and the second switch The control end of is used to receive a second control signal. The matching transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor is used to receive a predetermined low voltage. The second terminal of the matching transistor is coupled to the second node. The control terminal of the crystal is used to receive a reference voltage. The compensation circuit is used to selectively output a predetermined high voltage or a threshold voltage matching the transistor to some pixel circuits through the first node.

This disclosure provides another display panel. The display panel includes a plurality of pixel circuits and a compensation circuit. Multiple pixel circuits are located in a display area. The compensation circuit is located in a non-display area and is coupled to a part of the pixel circuits among the plurality of pixel circuits. The compensation circuit includes a current source circuit and a matching transistor. The current source circuit is used to output a reference current to a sixth node. Matching The crystal includes a first terminal, a second terminal and a control terminal. The first terminal of the matching transistor is coupled to the sixth node. The second terminal and the control terminal of the matching transistor are used to receive a reference voltage. Wherein, when the matching transistor receives the reference current, the compensation circuit outputs a critical voltage of the matching transistor to the partial pixel circuit through the sixth node.

The present disclosure provides yet another display panel. The display panel includes a plurality of pixel circuits and a compensation circuit. Multiple pixel circuits are located in a display area. The compensation circuit is located in a non-display area and is coupled to a part of the pixel circuits among the plurality of pixel circuits. The compensation circuit includes a matching transistor and a current source circuit. The matching transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor is used to receive a reference voltage. The second terminal and the control terminal of the matching transistor are coupled to a tenth node. The current source circuit is coupled to the tenth node and used to extract a reference current from the matched transistor. Wherein, when the reference current flows through the matching transistor, the compensation circuit outputs a critical voltage of the matching transistor to the partial pixel circuit through the tenth node.

The above-mentioned display panel can still provide a uniform display picture even when the driving transistor has a critical voltage variation.

100, 500, 900 ‧‧‧ display panel

110, 510, 910‧‧‧ pixel circuit

120‧‧‧ source driver

130‧‧‧Gate driver

140, 540, 940‧‧‧ Compensation circuit

150‧‧‧Display area

160‧‧‧non-display area

210, 610, 1010‧‧‧ matching transistor

220, 620, 1020‧‧‧ drive transistor

230, 630, 1030‧‧‧ light unit

CS‧‧‧Current source circuit

C1~C5‧‧‧First capacitor~Fifth capacitor

CT1~CT3‧‧‧‧ First control signal~ Third control signal

SW1~SW10‧‧‧First switch~Tenth switch

N1~N13‧‧‧First node~Thirteenth node

VDD‧‧‧ preset high voltage

VSS‧‧‧ preset low voltage

Vref‧‧‧Reference voltage

Vdata‧‧‧Data voltage

VE‧‧‧Enable level

VS‧‧‧Enable level

Idri‧‧‧Drive current

Iref‧‧‧Reference current

T1‧‧‧ compensation stage

T2‧‧‧ Writing stage

T3‧‧‧Lighting stage

In order to make the above and other objects, features, advantages and embodiments of the disclosed document more obvious and understandable, the drawings are described as follows: FIG. 1 is a simplified functional block diagram of a display panel according to an embodiment of the disclosed document .

FIG. 2 is a partial schematic view of the display panel of FIG. 1 after being enlarged.

FIG. 3 is a timing chart of an operation example of the display panel of FIG. 1.

4A to 4C are schematic diagrams of partial equivalent circuits of the display panel of FIG. 1.

FIG. 5 is a simplified functional block diagram of a display panel according to another embodiment of the present disclosure.

FIG. 6 is a partial schematic diagram of the display panel of FIG. 5 after being enlarged.

FIG. 7 is a timing chart of an operation example of the display panel of FIG. 5.

8A to 8C are schematic diagrams of partial equivalent circuits of the display panel of FIG. 5.

FIG. 9 is a simplified functional block diagram of a display panel according to another embodiment of the present disclosure.

FIG. 10 is a partial schematic view of the display panel of FIG. 9 after being enlarged.

FIG. 11 is a timing chart of an operation example of the display panel of FIG. 9.

12A-12B are partial equivalent circuit diagrams of the display panel of FIG. 9.

The following will describe embodiments of the disclosed document in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

Figure 1 is a display panel according to an embodiment of the present disclosure 100 simplified functional block diagram. The display panel 100 includes a plurality of pixel circuits 110, a source driver 120, a gate driver 130, and a plurality of compensation circuits 140. The display panel 100 further includes a display area 150 and a non-display area 160, wherein a plurality of pixel circuits 110 are located in the display area 150, and a plurality of compensation circuits 140 are located in the non-display area 160.

As shown in FIG. 1, each compensation circuit 140 corresponds to a row of pixel circuits 110 coupled to the display panel 100. That is, each compensation circuit 140 is coupled to a part of the pixel circuits 110 in the aforementioned plurality of pixel circuits 110. In order to make the drawing simple and easy to explain, the other components and the connection relationship in the display panel 100 are not shown in FIG. 1.

FIG. 2 is a partial schematic view of the display panel 100 of FIG. 1 after being enlarged. As shown in FIG. 2, the compensation circuit 140 includes a first switch SW1, a second switch SW2, and a matching transistor 210. The first switch SW1 includes a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first switch SW1 is used to receive a preset high voltage VDD, and the second terminal of the first switch SW1 is coupled to the first node N1, The control terminal of the first switch SW1 is used to receive the first control signal CT1. The second switch SW2 includes a first end, a second end, and a control end. The first end of the second switch SW2 is coupled to the second node N2, and the second end of the second switch SW2 is coupled to the first node N1, the second The control terminal of the switch SW2 is used to receive the second control signal CT2.

The matching transistor 210 includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor 210 is used to receive a preset low voltage VSS. The second terminal of the matching transistor 210 is coupled to the second node N2. The control terminal of the transistor 210 is used to receive the reference voltage Vref.

The pixel circuit 110 includes a driving transistor 220, a third switch SW3, a fourth switch SW4, a first capacitor C1, a second capacitor C2, and a light emitting unit 230. The driving transistor 220 includes a first end, a second end, and a control end. The first end of the driving transistor 220 is coupled to the first node N1, and the second end of the driving transistor 220 is coupled to the third node N3. The control terminal of the crystal 220 is coupled to the fourth node N4.

The third switch SW3 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third switch SW3 is used to receive the data voltage Vdata. The second terminal of the third switch SW3 is coupled to the fourth node N4. The control terminal of the switch SW3 is used to receive the third control signal CT3. The fourth switch SW4 includes a first terminal, a second terminal, and a control terminal. The first terminal of the fourth switch SW4 is used to receive a preset low voltage VSS, and the second terminal of the fourth switch SW4 is coupled to the fifth node N5. The control terminal of the four switches SW4 is used to receive the second control signal CT2.

The first capacitor C1 is coupled between the first node N1 and the fifth node N5, and the second capacitor C2 is coupled between the fourth node N4 and the fifth node N5. The light emitting unit 230 includes a cathode terminal and an anode terminal, wherein the cathode terminal is used to receive a preset low voltage VSS, and the anode terminal is coupled to the third node N3.

In this embodiment, the compensation circuit 140 and a row of pixel circuits 110 coupled to the compensation circuit 140 are located in the polycrystalline silicon thin film region formed by the same or similar multi-channel excimer lasers. Therefore, the threshold voltage of the matching transistor 210 of the compensation circuit 140 will be the same or almost the same as the threshold voltage of the driving transistor 220 of the column of pixel circuits 110 to which the compensation circuit 140 is coupled.

In addition, the matching transistor 210, the driving transistor 220, the first The switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 may be implemented by P-type transistors. The light-emitting unit 230 can be implemented with a light-emitting material such as an organic light-emitting diode or a micro LED.

The compensation circuit 140 selectively outputs the threshold voltage of the matching transistor 210 or the preset high voltage VDD to the pixel circuit 110 to which the compensation circuit 140 is coupled through the first node N1 to compensate the driving power of different pixel circuits 110 The critical voltage of the crystal 220 varies. The cooperative operation of the compensation circuit 140 and the pixel circuit 110 will be further described below with reference to FIG. 2 and FIG. 3.

In the compensation phase T1, the first control signal CT1 and the third control signal CT3 are the disable level VS (for example, high voltage level), and the second control signal CT2 is the enable level VE (for example, low Voltage level). Therefore, the second switch SW2 and the fourth switch SW4 are in the on state, the first switch SW1 and the third switch SW3 are in the off state, and the voltage level of the reference voltage Vref makes the matching transistor 210 in the on state.

In this way, the compensation circuit 140 and the pixel circuit 110 form an equivalent circuit as shown in FIG. 4A. As shown in FIG. 4A, the voltage level of the fifth node N5 is set to the preset low voltage VSS, and the charge of the first node N1 is discharged to the preset low voltage VSS through the second switch SW2 and the matching transistor 210 Flow until the voltage level of the first node N1 is equal to the sum of the reference voltage Vref and the absolute value of the critical voltage of the matching transistor 210.

That is, in the compensation stage T1, the voltage level of the first node can be expressed by the following "Formula 1": V1=Vref+|Vth1| "Formula 1" Where, V1 represents the voltage level of the first node, and Vth1 represents the threshold voltage of the matching transistor 210. In addition, the voltage level of the first node N1 shown in "Formula 1" will be lower than the preset low voltage VSS to ensure that the light emitting unit 230 is in the off state.

In the writing phase T2, the first control signal CT1 is the disable level VS, and the second control signal CT2 and the third control signal CT3 are the enable level VE. Therefore, the first switch SW1 is maintained in the off state, and the second switch SW2, the third switch SW3, and the fourth switch SW4 are in the on state.

In this way, the compensation circuit 140 and the pixel circuit 110 form an equivalent circuit as shown in FIG. 4B. As shown in FIG. 4B, the voltage level of the fourth node N4 is set to the data voltage Vdata, and the voltage level of the fifth node N5 is maintained at the preset low voltage VSS. In addition, the voltage level of the first node N1 is maintained at the voltage value described in the above “Formula 1”, so that the light emitting unit 230 is maintained in the off state.

Therefore, in the writing phase T2, the voltage difference between the first node N1 and the fourth node N4 can be expressed by the following "Formula 2": V1-V4=Vref+|Vth1|-Vdata "Formula 2", where V4 represents the first The voltage level of the four node N4.

Next, in the lighting phase T3, the first control signal CT1 is the enable level VE, and the second control signal CT2 and the third control signal CT3 are the disable level VS. Therefore, the first switch SW1 is in the on state, and the second switch SW2, the third switch SW3, and the fourth switch SW4 are in the off state.

In this way, the compensation circuit 140 and the pixel circuit 110 form an equivalent circuit as shown in FIG. 4C. As shown in Figure 4C, the first node N1 The voltage level of will be set to the preset high voltage VDD. Moreover, since the fourth node N4 and the fifth node N5 are in a floating state, the voltage difference between the first node N1 and the fourth node N4 will be the same as the voltage difference shown in the above "Formula 2".

其中，Vth2代表驅動電晶體220的臨界電壓，k1代表驅動電晶體220的載子遷移率(carrier mobility)、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。 Therefore, in the light-emitting phase T3, the driving transistor 220 of the pixel circuit 110 provides the driving current Idri to the third node N3 (ie, the anode end of the light-emitting unit 230) to control the light-emitting unit 230 to generate a specific gray-scale brightness . Among them, the magnitude of the drive current Idri can be expressed by the following "Formula 4":

Where, Vth2 represents the threshold voltage of the driving transistor 220, and k1 represents the product of the carrier mobility of the driving transistor 220, the unit capacitance of the gate oxide layer, and the gate width-to-length ratio.

As mentioned above, the critical voltage of the matching transistor 210 and the driving transistor 220 will be the same or almost the same, so "Formula 4" can be further simplified to the following "Formula 5":

It can be seen from the above "Formula 5" that even if the driving transistors 220 of the pixel circuits 110 in different regions of the display panel 100 have different threshold voltages, the driving current Idri of each pixel circuit 110 will still have the same magnitude as the data voltage Vdata Fixed correspondence. Therefore, the display panel 100 can provide a uniform display screen.

In some embodiments, the first switch of the display panel 100 SW1, second switch SW2, third switch SW3 and fourth switch SW4 are implemented by N-type transistors. In this case, the enable level VE of the first control signal CT1, the second control signal CT2, and the third control signal CT3 of the display panel 100 is a high voltage level, and the disable level VS is a low voltage level .

FIG. 5 is a simplified functional block diagram of a display panel 500 according to another embodiment of the present disclosure. The display panel 500 is similar to the display panel 100 except that the display panel 500 includes a plurality of pixel circuits 510 and a plurality of compensation circuits 540, wherein each compensation circuit 540 corresponds to a row of pixel circuits 510 of the display panel 500.

FIG. 6 is a partial schematic diagram of the display panel 500 of FIG. 5 after being enlarged. As shown in FIG. 6, the compensation circuit 540 includes a current source circuit CS and a matching transistor 610. The current source circuit CS is used to output the reference current Iref to the sixth node N6. The matching transistor 610 includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor 610 is coupled to the sixth node N6, and both the second terminal and the control terminal of the matching transistor 610 are used to receive the reference voltage. Vref.

The pixel circuit 510 includes a driving transistor 620, a light emitting unit 630, a writing circuit 640, a reset circuit 650, a third capacitor C3, and a fourth capacitor C4. The writing circuit 640 is used to transmit the data voltage Vdata to the seventh node N7 according to the first control signal CT1. The reset circuit 650 is coupled to the sixth node N6, the seventh node N7, and the eighth node N8, and is used to transfer the threshold voltage and the preset high voltage VDD of the matching transistor 610 to the seventh node according to the second control signal CT2. N7 and the eighth node N8.

Specifically, the write circuit 540 includes a fifth switch SW5. The fifth switch SW5 includes a first end, a second end, and a control end. The fifth switch SW5 The first terminal of is used to receive the data voltage Vdata, the second terminal of the fifth switch SW5 is coupled to the seventh node N7, and the control terminal of the fifth switch SW5 is used to receive the first control signal CT1.

The reset circuit 550 includes a sixth switch SW6 and a seventh switch SW7. The sixth switch SW6 includes a first end, a second end, and a control end. The first end of the sixth switch SW6 is used to receive the threshold voltage of the matching transistor 610 from the compensation circuit 540. The second end of the sixth switch SW6 is coupled to The seventh node N7 and the control terminal of the sixth switch SW6 are used to receive the second control signal CT2. The seventh switch SW7 includes a first terminal, a second terminal, and a control terminal. The first terminal of the seventh switch SW7 is coupled to the eighth node N8. The second terminal of the seventh switch SW7 is used to receive the preset high voltage VDD. The control terminal of the seven switches SW7 is used to receive the second control signal CT2.

The driving transistor 620 includes a first end, a second end and a control end. The first end of the driving transistor 620 is used to receive a preset high voltage VDD. The second end of the driving transistor 620 is coupled to the ninth node N9 to drive The control terminal of the transistor 620 is coupled to the eighth node N8.

In addition, the third capacitor C3 is coupled between the seventh node N7 and the eighth node N8. The fourth capacitor C4 includes a first terminal and a second terminal. The first terminal of the fourth capacitor C4 is coupled to the seventh node N7. The second terminal of the fourth capacitor C4 is used to receive a predetermined high voltage VDD. The light emitting unit 630 includes a cathode terminal and an anode terminal. The cathode terminal is used to receive a preset low voltage VSS, and the anode terminal is coupled to the ninth node N9.

In practice, the matching transistor 610, the driving transistor 620, the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7 may be P-type transistors To achieve. The light-emitting unit 230 may be implemented with light-emitting materials such as organic light-emitting diodes or micro-light-emitting diodes.

When the matching transistor 610 receives the reference current Iref, the compensation circuit 540 outputs the threshold voltage of the matching transistor 610 to the pixel circuit 510 to which the compensation circuit 540 is coupled through the sixth node N6 to compensate for different pixel circuits 510 The critical voltage of the driving transistor 620 varies. The cooperative operation of the compensation circuit 540 and the pixel circuit 510 will be further described below with reference to FIG. 6 and FIG. 7.

In the compensation stage T1, the first control signal CT1 is the disable level VS (for example, a high voltage level), and the second control signal CT2 is the enable level VE (for example, a low voltage level). Therefore, the fifth switch SW5 is in the off state, and the sixth switch SW6 and the seventh switch SW7 are in the on state. Moreover, the current source circuit CS provides the reference current Iref to the matching transistor 610.

其中，V6表示第六節點N6的電壓準位，Vth3表示匹配電晶體610的臨界電壓。另外，k2代表匹配電晶體610的載子遷移率、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。 In this way, the compensation circuit 540 and the pixel circuit 510 form an equivalent circuit as shown in FIG. 8A. As shown in FIG. 8A, since the matched transistor 610 is a diode-connected transistor, when the reference current Iref flows through the matched transistor 610, the voltage level of the sixth node N6 can be determined by The following "Formula 6" indicates:

Where, V6 represents the voltage level of the sixth node N6, and Vth3 represents the threshold voltage of the matched transistor 610. In addition, k2 represents the product of the carrier mobility of the matching transistor 610, the unit capacitance of the gate oxide layer, and the gate width to length ratio.

Since the sixth node N6 passes through the sixth switch SW6 and the seventh section The points N7 are turned on each other, and the voltage level of the seventh node N7 is set to the voltage value shown in "Formula 6". Moreover, the preset high voltage VDD is transmitted to the eighth node N8 through the seventh switch SW7, so that the voltage level of the eighth node N8 is set to the preset high voltage VDD.

In the writing phase T2, the first control signal CT1 is the enable level VE, and the second control signal CT2 is the disable level VS. Therefore, the fifth switch SW5 is in an on state, and the sixth switch SW6 and the seventh switch SW7 are in an off state.

其中，V8表示第八節點N8的電壓準位。 In this way, the compensation circuit 540 and the pixel circuit 510 form an equivalent circuit as shown in FIG. 8B. As shown in FIG. 8B, the voltage level of the seventh node N7 will change from the voltage value shown in “Formula 6” to the data voltage Vdata, and the voltage change amount of the seventh node N7 will be coupled through the capacitance of the fourth capacitor C4 The effect passes to the eighth node N8. Therefore, the voltage level of the eighth node N8 can be expressed by the following "Formula 7":

Where, V8 represents the voltage level of the eighth node N8.

In the lighting phase T3, both the first control signal CT1 and the second control signal CT2 are at the disabled level VS. Therefore, the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7 are all in the off state.

其中，Vth4表示驅動電晶體620的臨界電壓。k3代表驅動電晶體620的載子遷移率、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。 Therefore, the compensation circuit 540 and the pixel circuit 510 form an equivalent circuit as shown in FIG. 8C. As shown in FIG. 8C, the driving transistor 620 provides the driving current Idri to the ninth node N9 (that is, the anode end of the light emitting unit 630), and the magnitude of the driving current Idri can be expressed by the following "Formula 8":

Here, Vth4 represents the threshold voltage of the driving transistor 620. k3 represents the product of the carrier mobility of the driving transistor 620, the unit capacitance of the gate oxide layer, and the gate width-to-length ratio.

Since the critical voltages of the matching transistor 610 and the driving transistor 620 will be the same or almost the same, "Formula 8" can be further simplified to the following "Formula 9"

It can be known from the above-mentioned "Formula 9" that even if the driving transistors 620 of the pixel circuits 510 in different regions of the display panel 500 have different threshold voltages, the driving current Idri of each pixel circuit 510 still has the magnitude of the data voltage Vdata Fixed correspondence. Therefore, the display panel 500 can provide a uniform display screen.

In some embodiments, the fifth switch SW5, the sixth switch SW6, and the seventh switch SW7 of the display panel 500 are implemented by N-type transistors. In this case, the enable level VE of the first control signal CT1 and the second control signal CT2 of the display panel 500 is a high voltage level, and the disable level VS is a low voltage level.

FIG. 9 is a simplified functional block diagram of a display panel 900 according to another embodiment of the present disclosure. The display panel 900 is similar to the display panel 100, except that the display panel 900 includes a plurality of pixel circuits 910 and multiple A compensation circuit 940, wherein each compensation circuit 940 corresponds to a pixel circuit 910 coupled to a column of the display panel 900.

FIG. 10 is a partial schematic view of the display panel 900 of FIG. 9 after being enlarged. As shown in FIG. 10, the compensation circuit 940 includes a matching transistor 1010 and a current source circuit CS. The matching transistor 1010 includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor 1010 is used to receive the reference voltage Vref. The second terminal and the control terminal of the matching transistor 1010 are coupled to the tenth node N10. The current source circuit CS is coupled to the tenth node N10 and is used to extract the reference current Iref from the matched transistor 1010.

The pixel circuit 910 includes an eighth switch SW8, a ninth switch SW9, a tenth switch SW10, a fifth capacitor C5, a driving transistor 1020, and a light emitting unit 1030. The eighth switch SW8 includes a first terminal, a second terminal, and a control terminal. The first terminal of the eighth switch SW8 is coupled to the tenth node N10, and the second terminal of the eighth switch SW8 is coupled to the eleventh node N11. The control terminal of the eight switch SW8 is used to receive the first control signal CT1. The ninth switch SW9 includes a first end, a second end, and a control end. The first end of the ninth switch SW9 is used to receive a preset high voltage VDD, and the second end of the ninth switch SW9 is coupled to the twelfth node N12. The control terminal of the ninth switch SW9 is used to receive the second control signal CT2. The tenth switch SW10 includes a first terminal, a second terminal, and a control terminal. The first terminal of the tenth switch SW10 is coupled to the twelfth node N12. The second terminal of the tenth switch SW10 is used to receive the data voltage Vdata. The control terminal of the switch SW10 is used to receive the first control signal CT1.

The driving transistor 1020 includes a first end, a second end, and a control end. The first end of the driving transistor 1020 is coupled to the twelfth node N12. The second end of the dynamic transistor 1020 is coupled to the thirteenth node N13, and the control end of the driving transistor 1020 is coupled to the eleventh node N11.

In addition, the fifth capacitor C5 is coupled between the eleventh node N11 and the twelfth node N12. The light emitting unit 1030 includes a cathode terminal and an anode terminal. The cathode terminal is used to receive a preset low voltage VSS, and the anode terminal is coupled to the thirteenth node N13.

In practice, the matching transistor 1010, the driving transistor 1020, the eighth switch SW8, the ninth switch SW9, and the tenth switch SW10 may be implemented by P-type transistors. The light-emitting unit 1030 may be implemented with light-emitting materials such as organic light-emitting diodes or micro-light-emitting diodes.

When the reference current Iref flows through the matching transistor 1010, the compensation circuit 940 outputs the threshold voltage of the matching transistor 1010 to the pixel circuit 910 to which the compensation circuit 940 is coupled through the tenth node N10 to compensate for different pixel circuits 910 The critical voltage of the driving transistor 1020 varies. The operation of the compensation circuit 940 and the pixel circuit 910 will be further described below with reference to FIG. 10 and FIG. 11.

In the compensation stage T1, the first control signal CT1 is the enable level VE (for example, a low voltage level), and the second control signal CT2 is the disable level VS (for example, a high voltage level). Therefore, the eighth switch SW8 and the tenth switch SW10 are in the on state, and the ninth switch SW9 is in the off state. In addition, the current source circuit CS draws the reference current Iref from the matched transistor 1010.

其中，V10代表第十節點N10的電壓準位，Vth5代表匹配電晶體1010的臨界電壓。另外，k4代表匹配電晶體1010的載子遷移率、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。 Therefore, the compensation circuit 940 and the pixel circuit 910 form an equivalent circuit as shown in FIG. 12A. As shown in FIG. 12A, because the matched transistor 1010 is a diode-coupled transistor, when the reference current Iref flows through the matched transistor 1010, the voltage level of the tenth node N10 can be determined by the following formula 10" means:

Among them, V10 represents the voltage level of the tenth node N10, and Vth5 represents the threshold voltage of the matched transistor 1010. In addition, k4 represents the product of the carrier mobility of the matched transistor 1010, the unit capacitance of the gate oxide layer, and the gate width-to-length ratio.

其中，V11代表第十一節點N11的電壓準位。 Since the tenth node N10 and the eleventh node N11 are electrically connected to each other via the eighth switch SW8, the voltage level of the eleventh node N11 is set to the voltage value as shown in "Formula 10". In addition, the data voltage Vdata is transmitted to the twelfth node N12 via the tenth switch SW10, so that the voltage level of the twelfth node N12 is set to the data voltage Vdata. Therefore, the voltage difference between the eleventh node N11 and the twelfth node N12 can be expressed by the following "Formula 11":

Among them, V11 represents the voltage level of the eleventh node N11.

As can be seen from the above, the transistor threshold voltage compensation and data writing of the pixel circuit 910 are performed in the same operation stage. Therefore, the operation process of the pixel circuit 910 omits the aforementioned writing stage T2.

In the lighting phase T3, the first control signal CT1 is the disable level VS, and the second control signal CT2 is the enable level VE. Therefore, the eighth switch SW8 and the tenth switch SW10 are in the off state, and the ninth switch SW9 is in the on state.

In this way, the compensation circuit 940 and the pixel circuit 910 will form an equivalent circuit as shown in FIG. 12B. As shown in FIG. 12B, the driving transistor 1020 provides the driving current Idri to the thirteenth node N13 (that is, the anode end of the light emitting unit 1030). Since the eleventh node N11 is in a floating state, the voltage difference between the eleventh node N11 and the twelfth node N12 will be the same as the voltage difference shown in "Formula 11".

其中，Vth6代表驅動電晶體1020的臨界電壓。k5代表驅動電晶體1020的載子遷移率、閘極氧化層的單位電容大小以及閘極寬長比三者的乘積。 Therefore, the magnitude of the drive current Idri can be expressed by the following "Formula 12":

Among them, Vth6 represents the critical voltage of the driving transistor 1020. k5 represents the product of the carrier mobility of the driving transistor 1020, the unit capacitance of the gate oxide layer, and the gate width to length ratio.

Since the critical voltage of the matching transistor 1010 and the driving transistor 1020 will be the same or almost the same, the "Formula 12" can be further simplified to the following "Formula 13":

It can be known from the above-mentioned "Formula 13" that even if the driving transistors 1020 of the pixel circuits 910 in different regions of the display panel 900 have different threshold voltages, the driving current Idri of each pixel circuit 910 will still have the same magnitude as the data voltage Vdata Fixed correspondence. Therefore, the display panel 900 can provide a uniform display screen.

In some embodiments, the eighth switch SW8, the ninth switch SW9, and the tenth switch SW10 of the display panel 900 are implemented by N-type transistors. In this case, the enable level VE of the first control signal CT1 and the second control signal CT2 of the display panel 900 is a high voltage level, and the disable level VS is a low voltage level.

Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The specification and the scope of patent application do not use the difference in names as a way to distinguish the components, but the difference in the functions of the components as the basis for distinguishing. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.

In addition, unless otherwise specified in the specification, any singular case also includes the meaning of the plural case.

The above are only the preferred embodiments of the disclosed document, and any changes and modifications made in accordance with the requested items of the disclosed document shall fall within the scope of the disclosed document.

100‧‧‧Display panel

110‧‧‧Pixel circuit

120‧‧‧ source driver

130‧‧‧Gate driver

140‧‧‧ Compensation circuit

150‧‧‧Display area

160‧‧‧non-display area

Claims (10)

A display panel includes: a plurality of pixel circuits located in a display area; and a compensation circuit located in a non-display area and coupled to a portion of the pixel circuits in the pixel circuits. The compensation circuit includes : A first switch, including a first end, a second end and a control end, the first end of the first switch is used to receive a preset high voltage, the second end of the first switch is coupled At a first node, the control end of the first switch is used to receive a first control signal; a second switch includes a first end, a second end, and a control end, the second switch One end is coupled to a second node, the second end of the second switch is coupled to the first node, the control end of the second switch is used to receive a second control signal; and a matching transistor, It includes a first terminal, a second terminal, and a control terminal. The first terminal of the matching transistor is used to receive a predetermined low voltage. The second terminal of the matching transistor is coupled to the second node. The control terminal of the matched transistor is used to receive a reference voltage; wherein, the compensation circuit is used to selectively output the preset high voltage or a threshold voltage of the matched transistor to the partial pixels through the first node Circuit. The display panel of claim 1, wherein one of the pixel circuits includes: a driving transistor including a first terminal, a second terminal, and a control terminal, and the first terminal of the driving transistor One end is coupled to the first node, the driving transistor The second terminal of the body is coupled to a third node, the control terminal of the driving transistor is coupled to a fourth node; a third switch includes a first terminal, a second terminal and a control terminal, The first terminal of the third switch is used to receive a data voltage, the second terminal of the third switch is coupled to a fourth node, and the control terminal of the third switch is used to receive a third control signal; A fourth switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the fourth switch is used to receive the preset low voltage, and the second terminal of the fourth switch is coupled to A fifth node, the control terminal of the fourth switch is used to receive the second control signal; a first capacitor is coupled between the first node and the fifth node; a second capacitor is coupled to Between the fourth node and the fifth node; and a light-emitting unit including a cathode terminal and an anode terminal, the cathode terminal is used to receive the preset low voltage, and the anode terminal is coupled to the third node. The display panel according to claim 2, wherein, in a compensation stage, the first control signal and the third control signal are a disabling level, and the second control signal is a uniform level, in a writing stage In this, the first control signal is the disable level, the second control signal and the third control signal are the enable level, and in a lighting stage, the first control signal is the enable level, The second control signal and the third control signal are the disable level. A display panel, including: A plurality of pixel circuits are located in a display area; and a compensation circuit is located in a non-display area and is coupled to a part of the pixel circuits in the pixel circuits. The compensation circuit includes: a current source circuit, It is used to output a reference current to a sixth node; and a matching transistor including a first terminal, a second terminal and a control terminal, the first terminal of the matching transistor is coupled to the sixth node, The second terminal and the control terminal of the matched transistor are used to receive a reference voltage; wherein, when the matched transistor receives the reference current, the compensation circuit passes a critical point of the matched transistor through the sixth node The voltage is output to this part of the pixel circuit. The display panel of claim 4, wherein one of the pixel circuits includes: a write circuit for transmitting a data voltage to a seventh node according to a first control signal; a reset A circuit, coupled to the sixth node, the seventh node and an eighth node, for transmitting the critical voltage and a preset high voltage to the seventh node and an eighth node according to a second control signal A drive transistor, including a first end, a second end and a control end, the first end of the drive transistor is used to receive the preset high voltage, the second end of the drive transistor is coupled At a ninth node, the control terminal of the driving transistor is coupled to the eighth node; a third capacitor is coupled between the seventh node and the eighth node; and a fourth capacitor includes a first One end and one second end, the fourth capacitor The first terminal of the second node is coupled to the seventh node, the second terminal of the fourth capacitor is used to receive the preset high voltage; and a light emitting unit includes a cathode terminal and an anode terminal, the cathode terminal is used to receive In the preset low voltage, the anode terminal is coupled to the ninth node. The display panel according to claim 5, wherein the writing circuit includes: a fifth switch including a first terminal, a second terminal and a control terminal, and the first terminal of the fifth switch is used to receive the data Voltage, the second end of the fifth switch is coupled to the seventh node, the control end of the fifth switch is used to receive the first control signal; wherein, the reset circuit includes: a sixth switch, including A first terminal, a second terminal and a control terminal, the first terminal of the sixth switch is used to receive the threshold voltage, the second terminal of the sixth switch is coupled to the seventh node, the sixth The control end of the switch is used to receive the second control signal; and a seventh switch includes a first end, a second end and a control end, the first end of the seventh switch is coupled to the eighth Node, the second end of the seventh switch is used to receive the preset high voltage, and the control end of the seventh switch is used to receive the second control signal. The display panel of claim 6, wherein, in a compensation stage, the first control signal is a disabling level, and the second control signal is a uniform energy level, and in a writing stage, the first control The signal is the enabling level, the The second control signal is the disable level. In a light-emitting stage, the first control signal and the second control signal are the disable level. A display panel includes: a plurality of pixel circuits located in a display area; and a compensation circuit located in a non-display area and coupled to a portion of the pixel circuits in the pixel circuits. The compensation circuit includes : A matching transistor, including a first terminal, a second terminal and a control terminal, the first terminal of the matching transistor is used to receive a reference voltage, the second terminal and the control terminal of the matching transistor Coupled to a tenth node; and a current source circuit, coupled to the tenth node, for drawing a reference current from the matched transistor; wherein, when the reference current flows through the matched transistor, the compensation The circuit outputs a threshold voltage of the matched transistor to the partial pixel circuit through the tenth node. The display panel of claim 8, wherein a pixel circuit of the pixel circuits includes: an eighth switch, including a first terminal, a second terminal, and a control terminal, and the first One end is coupled to the tenth node, the second end of the eighth switch is coupled to an eleventh node, the control end of the eighth switch is used to receive a first control signal; a ninth switch, It includes a first terminal, a second terminal and a control terminal. The first terminal of the ninth switch is used to receive the preset high voltage. The ninth switch The second terminal of the switch is coupled to a twelfth node, the control terminal of the ninth switch is used to receive a second control signal; a tenth switch includes a first terminal, a second terminal and a control End, the first end of the tenth switch is coupled to the twelfth node, the second end of the tenth switch is used to receive a data voltage, and the control end of the tenth switch is used to receive the first Control signal; a fifth capacitor, coupled between the eleventh node and the twelfth node; a driving transistor, including a first end, a second end and a control end, the driving transistor The first end is coupled to the twelfth node, the second end of the driving transistor is coupled to a thirteenth node, and the control end of the driving transistor is coupled to the eleventh node; and one The light-emitting unit includes a cathode terminal and an anode terminal, the cathode terminal is used to receive the preset low voltage, and the anode terminal is coupled to the thirteenth node. The display panel of claim 9, wherein, in a compensation stage, the first control signal is a uniform energy level, and the second control signal is an energy-disable level, and in a light-emitting stage, the first control signal For the disabled level, the second control signal is the enabled level.

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