TW202020835A - Source driver and operating method thereof - Google Patents

Abstract

A source driver and an operating method are provided. In the source driver, a clock data recovery (CDR) circuit is configured to receive an original data signal from an external device and generate a clock signal and a first data signal according to the original data signal. A digital circuit receives the clock signal and the first data signal, and generates a power-down signal according to the first data signal. A signal detection circuit is configured to receive a control signal from the external device and generate a power-on signal according to the control signal. A power control circuit powers down the CDR circuit according to the power-down signal, and the power control circuit restores the CDR circuit to power on according to the power-on signal.

Description

Source driver and its operating method

The present invention relates to a display device, and in particular to a source driver and an operation method thereof.

With the advancement of electronic technology, consumer electronic products have become an essential tool in people's lives. In order to provide a good human-machine interface, it has become a trend to configure high-quality display devices on consumer electronic products. Reducing the power consumption of the display device during the non-display time period will be a problem for those skilled in the art.

The invention provides a source driver and an operation method thereof, which can effectively reduce the power consumption of the source driver during the non-display time interval.

The source driver of the present invention includes a clock data recovery (CDR) circuit, a digital circuit, a signal detection circuit, and a power control circuit. The clock data recovery circuit is used to receive an original data signal from an external device, and generate a clock signal and a first data signal according to the original data signal. The digital circuit is coupled to the clock data recovery circuit to receive the clock signal and the first data signal, and generate a power-off signal according to the first data signal. The signal detection circuit is used to receive a control signal from an external device and generate a power-on signal according to the control signal. The power control circuit is coupled to the digital circuit to receive the power-off signal, and is coupled to the signal detection circuit to receive the power-on signal, wherein the power control circuit powers off the clock data recovery circuit according to the power-off signal, and the power control The circuit restores the clock data to the circuit according to the power-on signal.

The operation method of the present invention includes: the clock data recovery circuit generates the clock signal and the data signal according to the original data signal; the digital circuit generates the power-off signal according to the first data signal; and the signal detection circuit based on the control signal Generate a power-on signal; the power control circuit powers off the clock data recovery circuit according to the power-off signal; the power control circuit restores the clock data recovery circuit based on the power-on signal.

Based on the above, the source driver described in the embodiments of the present invention can use the power control circuit to power off at least one or all of the clock data recovery circuit, the digital circuit, and the driving circuit according to the power-off signal. In addition, the power control circuit is used to restore at least one or all of the clock data recovery circuit, the digital circuit, and the driving circuit according to the power-on signal. In this way, the source driver of the present invention can further reduce the power consumption of the entire source driver when operating in the non-display time interval.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below and described in detail in conjunction with the accompanying drawings.

The term "coupling (or connection)" used in the entire specification of the case (including the scope of patent application) may refer to any direct or indirect connection means. For example, if it is described that the first device is coupled (or connected) to the second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to another device or a certain device. Connection means indirectly connected to the second device. In addition, wherever possible, elements/components/steps using the same reference numbers in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numbers or use the same terminology in different embodiments may refer to related descriptions with each other.

FIG. 1 is a schematic circuit block diagram of a source driver 100 according to an embodiment of the invention. The source driver 100 receives the raw data signal TX and the control signal CS from the external device 160, and drives the display panel 170 to display the image according to the received raw data signal TX and the control signal CS. Specifically, the external device 160 of this embodiment may include a timing controller (Timing Controller, TCON). In this embodiment, the external device 160 can generate a raw data signal TX and a control signal CS to the source driver 100, wherein the raw data signal TX includes the display data to be displayed by the display panel 170, and the control signal CS is It is used to indicate the period of valid data and the period of invalid data (for example, training pattern) in the original data signal TX. Generally speaking, an invalid data period will be arranged after a vertical blanking period (before the transmission period of valid frame data). Therefore, the control signal CS carries a phase (time point) message of "the vertical blanking period has ended".

Referring to FIG. 1, the source driver 100 includes a clock data recovery circuit 110, a digital circuit 120, a signal detection circuit 130, a power control circuit 140 and a driving circuit 150. The power control circuit 140 is configured with a power on/off reset (POFR) circuit. The clock data recovery circuit 110 can be used to parse out the clock signal CLK and the data signal DS1 mounted in the original data signal TX. Wherein, the data signal DS1 may include pixel data, vertical blanking start signal VBK, line latch signal and other control signals, but this embodiment is not limited to this. Generally speaking, the vertical blanking start signal VBK can indicate/define the starting phase (starting time point) of a vertical blanking period.

The digital circuit 120 of this embodiment may be, for example, a controller or a data processor, but the present invention is not limited thereto. The digital circuit 120 is coupled to the clock data recovery circuit 110 to receive the clock signal CLK and the data signal DS1. The digital circuit 120 can process the data signal DS1 to generate a processed data signal DS2, such as pixel data. In addition, the digital circuit 120 can also generate a power-off signal CPS according to the data signal DS1. For example, in this embodiment, the digital circuit 120 can detect the vertical blanking start signal VBK in the data signal DS1 and generate a power-off signal CPS according to the vertical blanking start signal VBK for power control Circuit 140. In other embodiments, the digital circuit 120 can detect other information in the data signal DS1 and generate a power-off signal CPS according to the other information.

The driving circuit 150 is coupled to the clock data recovery circuit 110 to receive the clock signal CLK. The driving circuit 150 is also coupled to the digital circuit 120 to receive the data signal DS2. The driving circuit 150 can generate the source driving signals S1-Sn according to the clock signal CLK and the data signal DS2, and the driving circuit 150 can use the source driving signals S1-Sn to drive the display panel 170. This embodiment does not limit the implementation of the driving circuit 150. For example, in some embodiments, the driving circuit 150 may include a shift register (Shift Register), a data register (Data Register), and a level shifter (Level Shifter), which are well known to those skilled in the art. ), digital-to-analog converter (Digital-to-Analog Converter, DAC) and output buffer (Output Buffer), the relevant operation actions in each component will not be repeated here.

On the other hand, the signal detection circuit 130 is coupled to the external device 160 to receive the control signal CS. The control signal CS carries a phase (time point) message of "the vertical blanking period has ended", so the signal detection circuit 130 can generate the start power signal SPS according to the control signal CS. For example, in some application scenarios, the control signal CS with a first logical level (eg, high level) may indicate that during a valid data period in the original data signal TX, it has a second logical level (eg, low level) Bit) of the control signal CS may indicate the period of invalid data (eg training patterns) in the original data signal TX. Based on this, the signal detection circuit 130 can detect the falling edge of the control signal CS and generate a power-on signal SPS to the power-on/power-off reset circuit of the power control circuit 140 according to the falling edge of the control signal CS. In other application scenarios, the control signal CS with a low level may indicate a valid data period in the original data signal TX, and the control signal CS with a high level may indicate invalid data in the original data signal TX (for example Training style). Based on this, the signal detection circuit 130 can detect the rising edge of the control signal CS and generate a power-on signal SPS to the power-on/power-off reset circuit of the power control circuit 140 according to the rising edge of the control signal CS.

The power-on/power-off reset circuit of the power control circuit 140 is coupled to the digital circuit 120 to receive the power-off signal CPS. The power-on/power-off reset circuit of the power control circuit 140 is coupled to the signal detection circuit 130 to receive the start power signal SPS. The power-on/power-off reset circuit of the power control circuit 140 can control the power supply of the clock data recovery circuit 110, the digital circuit 120, and/or the driving circuit 150. The power control circuit 140 can provide power control signals PCS1, PCS2, and PCS3 to the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 according to the power-off signal CPS and the start-up power signal SPS, respectively, to control the clock data recovery circuit 110. The digital circuit 120 and the driving circuit 150 operate in a power-off state or a power-on state. For example, the power control circuit 140 may power off the clock data recovery circuit 110 during the non-display time interval, and restore the power to the clock data recovery circuit 110 during the display time interval.

For details of the operation of the source driver 100, please refer to FIGS. 1 and 2 at the same time. FIG. 2 is a schematic diagram illustrating signal timing of the source driver 100 shown in FIG. 1 according to an embodiment of the present invention. According to design requirements, the non-display time interval TND includes a vertical blanking period and/or other times. The embodiment shown in FIG. 2 will use the vertical blanking period as an example of the non-display time interval TND. In detail, in this embodiment, the digital circuit 120 can detect the vertical blanking start signal VBK of the data signal DS1 during the vertical blanking time interval TBK. The vertical blanking start signal VBK means the beginning of the vertical blanking period (non-display time interval TND). Therefore, according to the vertical blanking start signal VBK, the digital circuit 120 can set the power-off signal CPS to an enabled (eg, high voltage level) state during the vertical blanking time interval TBK. At the same time, the signal detection circuit 130 can receive the control signal CS. Since the control signal CS remains at the high level during the vertical blanking period, the signal detection circuit 130 can keep the start power signal SPS disabled (for example, the low voltage level).

When the power-off signal CPS is in an enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that a power-off reset event has occurred. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide the power control signals PCS1 to PCS3 with a disabled (eg low voltage level) state according to the power-off signal CPS to the corresponding clock data recovery The circuit 110, the digital circuit 120, and the driving circuit 150, so that the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 are powered off.

On the other hand, in the embodiment shown in FIG. 2, the control signal CS with a high level may indicate a valid data period in the original data signal TX, and the control signal CS with a low level may indicate the original data signal TX During invalid data (such as training style) in. The falling edge of the control signal CS means the end of the vertical blanking period (non-display time interval TND). Therefore, the signal detection circuit 130 can detect the falling edge of the control signal CS and generate an enabled (eg high voltage level) state at the end time TEND of the non-display time interval TND according to the falling edge of the control signal CS The power supply signal SPS is activated to the power on/off reset circuit of the power control circuit 140.

When the start power signal SPS is in an enabled state, the power-on/power-off reset circuit of the power control circuit 140 can know that a power-on reset event has occurred. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can provide the power control signals PCS1~PCS3 with the enabled (eg high voltage level) state to the corresponding clock data recovery circuit according to the startup power signal SPS 110. The digital circuit 120 and the driving circuit 150, so that the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 are restored.

In other words, in this embodiment, the source driver 100 can determine the start and end of the vertical blanking period (non-display time interval TND) through the digital circuit 120 and the signal detection circuit 130. When the digital circuit 120 detects the start of the vertical blanking period (non-display time interval TND) according to the vertical blanking time interval TBK, the digital circuit 120 can trigger the power-on of the power control circuit 140 by cutting off the power signal CPS/ Power-off reset event of the power-off reset circuit. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can perform power-off operations on the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 to reduce the power consumption of the source driver 100. When the signal detection circuit 130 detects the end of the vertical blanking period (non-display time interval TND) according to the falling edge of the control signal CS, the signal detection circuit 130 can trigger the power control circuit 140 by activating the power signal SPS Power-on reset event of the power-on/power-off reset circuit. Therefore, the power-on/power-off reset circuit of the power control circuit 140 can restore the clock data recovery circuit 110, the digital circuit 120, and the drive circuit 150, thereby enabling the clock data recovery circuit 110, the digital circuit 120, and the drive The circuit 150 restarts the related circuit operation at the end time TEND.

Then, when the source driver 100 operates in the display time interval TD, since the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 all operate under the normal working state according to the corresponding power control signals PCS1~PCS3, Therefore, the driving circuit 150 can normally generate the source driving signals S1-Sn according to the clock signal CLK and the data signal DS2. With the source driving signals S1 to Sn, the driving circuit 150 can drive the display panel 170 so that the display panel 170 displays a picture in the display time interval TD.

It is worth mentioning that, in this embodiment, those skilled in the art can decide which internal components of the source driver 100 are to be powered off or reset according to the design requirements of the source driver 100. For example, when the source driver 100 operates in a non-display time interval TND (such as a vertical blanking period), the power control circuit 140 of this embodiment can restore the clock data recovery circuit 110 and the digits according to the power-off signal CPS At least one or all of the circuit 120 and the driving circuit 150 are powered off. On the contrary, when the non-display time interval TND ends, the power control circuit 140 can restore at least one or all of the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 according to the start power signal SPS .

According to the above, the power control circuit 140 of the source driver 100 according to this embodiment can cut off the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 according to the power-off signal CPS during the non-display time interval TND. Power supply to reduce power consumption of the source driver 100. On the other hand, when the non-display time interval TND ends, the power control circuit 140 of the source driver 100 can restore the power of the clock data recovery circuit 110, the digital circuit 120, and the driving circuit 150 according to the start power signal SPS, resulting in a clock The data recovery circuit 110, the digital circuit 120, and the driving circuit 150 can start related circuit operations again after the end time point TEND of the non-display time interval TND.

FIG. 3 is a flowchart of an operation method of the source driver 100 according to an embodiment of the invention. Please refer to FIGS. 1 and 3 at the same time. In step S310, the source driver 100 can generate the clock signal CLK and the data signal DS1 according to the original data signal TX by the clock data recovery circuit 110. In step S320, the source driver 100 can generate the power-off signal CPS according to the data signal DS1 by the digital circuit 120. In step S330, the source driver 100 can power off the clock data recovery circuit 110 according to the power-off signal CPS by the power control circuit 140.

Then, in step S340, the source driver 100 can generate the start power signal SPS according to the control signal CS by the signal detection circuit 130. In step S350, the source driver 100 can restore power to the clock data recovery circuit 110 by the power control circuit 140 according to the startup power signal SPS.

The implementation details of each step are described in detail in the foregoing embodiments and implementations, and will not be described in detail below.

In summary, the source drivers described in the embodiments of the present invention can use the power control circuit to power off at least one or all of the clock data recovery circuit, the digital circuit and the driving circuit according to the power off signal . In addition, the power control circuit is used to restore at least one or all of the clock data recovery circuit, the digital circuit, and the driving circuit according to the power-on signal. In this way, the source drivers described in the embodiments of the present invention can reduce the overall power consumption of the source driver during the non-display time interval, thereby achieving the effect of power saving.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100: source driver 110: clock data recovery circuit 120: digital circuit 130: signal detection circuit 140: power control circuit 150: drive circuit 160: external device 170: display panel CLK: clock signal CPS: power off signal CS: Control signal DS1, DS2: Data signal PCS1～PCS3: Power control signal SPS: Start power signal S1～Sn: Source drive signal S310～S350: Step TX: Original data signal TBK: Vertical blanking time interval TND: Non Display time interval TEND: End time TD: Display time interval VBK: Vertical blanking start signal

FIG. 1 is a schematic diagram of a circuit block of a source driver according to an embodiment of the invention. FIG. 2 is a schematic diagram illustrating signal timing of the source driver shown in FIG. 1 according to an embodiment of the present invention. FIG. 3 is a flowchart of a method of operating a source driver according to an embodiment of the invention.

100: source driver

110: Clock data recovery circuit

120: digital circuit

130: Signal detection circuit

140: power control circuit

150: drive circuit

160: external device

170: display panel

CLK: clock signal

CPS: cut off the power signal

CS: control signal

DS1, DS2: data signal

PCS1~PCS3: power control signal

SPS: Start power signal

S1~Sn: source drive signal

TX: raw data signal

VBK: vertical blanking start signal

Claims (16)

A source driver includes: a clock data recovery circuit for receiving an original data signal from an external device, and generating a clock signal and a first data signal according to the original data signal; a digital circuit, coupled to The clock data recovery circuit receives the clock signal and the first data signal, and generates a power-off signal according to the first data signal; a signal detection circuit for receiving a control signal from the external device, and Generating a power-on signal according to the control signal; and a power control circuit coupled to the digital circuit to receive the power-off signal and coupled to the signal detection circuit to receive the power-on signal, wherein the power The control circuit powers off the clock data recovery circuit according to the power-off signal, and the power control circuit re-energizes the clock data recovery circuit according to the startup power signal. The source driver as described in item 1 of the patent application scope, wherein the power control circuit powers off the clock data recovery circuit during a non-display time interval. The source driver as described in item 2 of the patent application scope, wherein the non-display time interval includes a vertical blanking period. The source driver as described in item 1 of the patent application scope, wherein the digital circuit detects a vertical blanking start signal in the first data signal, and generates the power-off according to the vertical blanking start signal Signal to the power control circuit. The source driver as claimed in item 1 of the patent application scope, wherein the signal detection circuit detects a falling edge of the control signal, and generates the starting power signal to the power control circuit according to the falling edge of the control signal. The source driver as described in item 1 of the patent application range, wherein the power control circuit further powers down the digital circuit according to the power-off signal, and the power control circuit further powers up the digital circuit according to the power-on signal . The source driver as described in item 1 of the patent application scope, wherein the digital circuit outputs a second data signal according to the first data signal, and the source driver further includes: a drive circuit coupled to the clock data The recovery circuit receives the clock signal, and is coupled to the digital circuit to receive the second data signal, wherein the driving circuit is used to drive a display panel according to the second data signal; wherein the power control circuit is based on the switching The power-off signal also powers off the drive circuit, and the power control circuit also powers up the drive circuit based on the power-on signal. The source driver as described in item 1 of the patent application scope, wherein the power control circuit includes a power-on/power-off reset circuit. An operation method of a source driver includes: a clock data recovery circuit generates a clock signal and a first data signal according to an original data signal; a digital circuit generates a power-off signal according to the first data signal; a The signal detection circuit generates a starting power signal according to a control signal; a power control circuit powers off the clock data recovery circuit according to the power off signal; and the power control circuit enables the time according to the starting power signal Pulse data recovery circuit is restored. The operation method as described in item 9 of the patent application scope, wherein the power control circuit powers off the clock data recovery circuit during a non-display time interval. The operation method as described in item 10 of the patent application scope, wherein the non-display time interval includes a vertical blanking period. The operation method as described in item 9 of the patent application scope, wherein the step of generating the power-off signal includes: detecting a vertical blanking start signal in the first data signal; and based on the vertical blanking The start signal generates the power-off signal to the power control circuit. The operation method as described in item 9 of the patent application scope, wherein the step of generating the start power signal includes: detecting a falling edge of the control signal; and generating the start power signal according to the falling edge of the control signal to The power control circuit. The operation method as described in item 9 of the patent application scope further includes: the power control circuit de-energizes the digital circuit according to the power-off signal; and the power control circuit causes the digital circuit to reset according to the start-up power signal Electricity. The operation method described in item 9 of the patent application scope further includes: outputting a second data signal according to the first data signal by the digital circuit; driving a display panel according to the second data signal by a driving circuit; by the The power control circuit powers off the driving circuit according to the power-off signal; and the power control circuit re-powers the driving circuit according to the starting power signal. The operation method as described in item 9 of the patent application scope, wherein the power control circuit includes a power-on/power-off reset circuit.

Images