TW202006845A - 形成半導體裝置的方法 - Google Patents

形成半導體裝置的方法 Download PDF

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TW202006845A
TW202006845A TW108113819A TW108113819A TW202006845A TW 202006845 A TW202006845 A TW 202006845A TW 108113819 A TW108113819 A TW 108113819A TW 108113819 A TW108113819 A TW 108113819A TW 202006845 A TW202006845 A TW 202006845A
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Taiwan
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wafer
forming
rewiring
semiconductor device
item
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TW108113819A
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TWI708297B (zh
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余振華
郭庭豪
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台灣積體電路製造股份有限公司
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Abstract

一種形成半導體裝置的方法，包括：在載板上放置多個封裝組件；在包封體中包封多個封裝組件；在多個封裝組件及包封體上形成感光介電層；使用微影罩幕暴露感光介電層；以及顯影感光介電層以形成多個開口。多個封裝組件的導電特徵藉由多個開口被暴露出。所述方法更包括形成延伸至開口中的重佈線。重佈線中的一者具有大於約26毫米的長度。重佈線、多個封裝組件以及包封體組合地形成重構晶圓。

Description

建構晶圓中的跨晶圓重佈線
隨著半導體技術的發展，半導體晶片/晶粒正變得愈來愈小。同時，更多功能需要整合至半導體晶粒中。因此，半導體晶粒需要具有塞在較小面積中的數目越來越大的I/O接墊，且I/O接墊的密度隨時間推移而快速升高。因此，半導體晶粒的封裝變得更困難，而此會不利地影響封裝的良率。
習知的封裝技術可劃分成兩個類別。在第一類別中，封裝晶圓上的晶粒，隨後進行鋸割。此封裝技術具有一些有利特徵，諸如較大生產率（throughput）及較低成本。另外，需要較少底部填充膠或模塑化合物。然而，此封裝技術亦有缺點。由於晶粒的大小正變得越來越小，且各別封裝可僅為扇入型封裝（fan-in type package），每一晶粒的I/O接墊會受限於在各別晶粒的表面正上方的區。隨著晶粒的面積受限，I/O接墊的數目因I/O接墊的間距限制而受限。若接墊的間距減小，則可出現焊橋（solder bridge）。另外，在固定球大小的要求下，焊球必須具特定大小，此舉又限制可塞在晶粒的表面上的焊球的數目。
在封裝的另一類別中，自晶圓鋸割晶粒，隨後進行封裝。此封裝技術的有利特徵為形成扇出型封裝（fan-out package）的可能性。此意謂可將晶粒上的I/O接墊重新分配至比晶粒大的面積，且因此可增大配置於晶粒的表面上的I/O接墊的數目。此封裝技術的另一有利特徵為封裝「已知良好晶粒（known-good-dies）」且拋棄有缺陷的晶粒，故可以不在有缺陷的晶粒上浪費成本及精力。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵形成於第二特徵上方或第二特徵上可包含第一特徵與第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可形成於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡單性及清晰的目的且本身不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，可在本文中使用諸如「下方（underlying）」、「在...下方（below）」、「下部（lower）」、「上覆（overlying）」、「上部（upper）」以及類似者的空間相對術語來描述如在圖式中所示出的一個器件或特徵與另一器件或特徵的關係。除圖式中所描繪的定向之外，空間相對術語還意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向）且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據一些實施例提供一種封裝以及其形成方法。根據一些實施例示出形成封裝的中間階段。論述一些實施例的一些變化。在本揭露的各種視圖及示例性實施例中，相似的標號用來標明相似的元件。根據本揭露的一些實施例，形成跨晶圓RDL以直接連接重構晶圓中的封裝組件，而非經由裝置晶粒、訊號加強器（repeater）及/或焊料區連接。
圖1至圖10是根據本揭露的一些實施例的封裝的形成的中間階段的剖視圖。圖1至圖10中所繪示的製程亦在圖35中所繪示的製程流程200中示意性地反映。
圖1繪示載板20及形成於載板20上的離型膜22。載板20可為玻璃載板、陶瓷載板或類似者。載板20可具有圓形頂視形狀，且可具有矽晶圓的大小。舉例而言，載板20可具有8吋直徑、12吋直徑或類似者。離型膜22可由聚合物系材料（諸如，光熱轉換（Light-To-Heat-Conversion；LTHC）材料）形成。所述聚合物系材料可連同載板20一起自將在後續製程中形成的上覆結構移除。根據本揭露的一些實施例，離型膜22由環氧基系熱釋放材料形成。晶粒貼合膜（Die-Attach Film；DAF）24形成於離型膜22上。DAF 24為黏著膜，且可經塗佈或疊層。
圖1進一步繪示載板20上的封裝組件26（包括封裝組件26A及封裝組件26B）的佈局。對應的製程在圖35所繪示的製程流程中被示出為製程202。根據本揭露的一些實施例，封裝組件26包括邏輯晶粒（諸如計算晶粒）、記憶體晶粒（諸如動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）晶粒或靜態隨機存取記憶體（Static Random Access Memory；SRAM）晶粒）、光子晶粒、封裝（包含已封裝的裝置晶粒）、輸入-輸出（Input-output；IO）晶粒、數位晶粒、類比晶粒、表面安裝被動元件（surface-mounted passive device）、諸如高頻寬記憶體（High-Bandwidth Memory；HBM）塊的晶粒堆疊、或類似者。封裝組件26可全部為具有同一結構的相同類型，或可包含作為實例示出為封裝組件26A及封裝組件26B的多個不同類型的封裝組件。根據一些實施例，封裝組件26A為邏輯晶粒，而封裝組件26B為記憶體晶粒、IO晶粒、積體被動元件（Integrated Passive Devices；IPDs）（諸如電容器（例如多層陶瓷電容器（multilayer ceramic capacitors；MLCCs））、電阻器、電感器）或類似者。封裝組件26的面積可在約20平方毫米與約900平方毫米之間的範圍內。面積的一些實例為在約100平方毫米與約400平方毫米之間的範圍內。
根據本揭露的一些實施例，封裝組件26包含半導體基板28。所述半導體基板可為矽基板、鍺基板，或由例如GaAs、InP、GaN、InGaAs、InAlAs等形成的III-V化合物半導體基板。可在基板28的表面處或所述基板上形成積體電路元件（未繪示），諸如電晶體、二極體、電阻器、電容器、電感器或類似者。諸如形成於介電層中的金屬線及通孔的內連線結構形成於積體電路元件上且電性耦接至所述積體電路元件。導電柱30形成於對應的封裝組件26的表面處，且經由內連線結構電性耦接至封裝組件26中的積體電路元件。根據本揭露的一些實施例，使用諸如焊料、鋁或類似者的軟導電材料來在導電柱30上形成導電層33。導電層33用於探測（probing）封裝組件26以確保封裝組件26無故障。可在自各別晶圓單體化封裝組件26之前執行探測。在導電層33比下方金屬柱30更軟的情況下，由於探測裝置的探測卡（probing card）與導電層33之間的接觸改良了，故探測更為容易。形成介電層32以覆蓋導電層33及金屬柱30。介電層32可由諸如聚醯亞胺、聚苯并噁唑（polybenzoxazole；PBO）或類似者的聚合物形成。
接下來，參照圖2，將包封體38包封（有時稱為模塑）於封裝組件26上。對應的製程在圖35所繪示的製程流程中被示出為製程204。包封體38填充相鄰封裝組件26之間的間隙，且進一步覆蓋封裝組件26。包封體38可包括模塑化合物、模塑底部填充膠或類似者。包封體38可包括基材（base material），所述基材可為聚合物、環氧樹脂及/或樹脂，以及混合於基材中的填充劑顆粒（filler particle）。填充劑顆粒可由二氧化矽（silica）、氧化鋁或類似者形成，且可具有球形形狀。
在後續步驟中，如亦在圖2中所繪示，執行諸如化學機械研磨（Chemical Mechanical Polish；CMP）製程或機械研磨（grinding）製程的平坦化製程。對應的製程在圖35所繪示的製程流程中被示出為製程206。藉由平坦化降低包封體38的頂表面直至暴露金屬柱30。歸因於平坦化，金屬柱30的頂表面與包封體38的頂表面實質上共面。可在平坦化製程中移除導電層33（在圖1中繪示），或導電層33的一些底部部分可被留下而繼續覆蓋金屬柱30。
圖3至圖8繪示正面重佈線（RDLs）及各別介電層的形成。參照圖3，形成介電層40。對應的製程在圖35所繪示的製程流程中被示出為製程208。根據本揭露的一些實施例，介電層40由諸如PBO、聚醯亞胺或類似者的感光聚合物形成。根據本揭露的替代性實施例，介電層40由諸如氮化矽、氧化矽或類似者的無機材料形成。
舉例而言，可使用例如微影製程圖案化介電層40以形成開口42。用包括不透明部分36A及透明部分36B的微影罩幕36在由感光材料形成介電層40時曝光介電層40。接著使曝光的介電層40顯影以形成開口42。由於開口42在介電層40曝光時尚未形成，故將開口42的邊緣繪示為虛線。實際上，開口42在介電層40顯影時形成。根據介電層40為非感光材料的替代性實施例，將光阻（未繪示）塗佈於介電層40上，且使用微影罩幕36對光阻進行曝光並接著使光阻顯影，並使用圖案化光阻作為蝕刻罩幕來蝕刻介電層40以形成開口42。封裝組件26的金屬柱30藉由開口42顯露出。
根據一些實施例，微影罩幕36具有實質上等於或大於載板20尺寸的晶圓尺寸。舉例而言，圖4繪示介電層40及對應的微影罩幕36及載板20。根據一些實施例，載板20及上覆介電層40具有圓形頂視形狀，且微影罩幕36亦可具有圓形頂視形狀。根據替代性實施例，載板20及上覆介電層40具有矩形形狀，且微影罩幕36亦可具有矩形頂視形狀。曝光亦以晶圓級執行，此意謂在相同曝光製程中對處於相同級的所有圖案（諸如開口42）進行曝光。此不同於習知曝光製程，其中對應的微影罩幕小於對應的晶圓。習知晶圓的面積被劃分成子區，每一子區藉由曝光製程曝光。舉例而言，在第一曝光製程中，微影罩幕位於第一子區正上方，且對第一子區進行曝光。微影罩幕接著移動至第二子區正上方，且對第二子區進行曝光。重複上述製程直至對所有子區進行曝光，且接著執行顯影步驟。習知曝光存在問題。在所得封裝中，一個子區中的特徵必須與其他子區中的特徵一致。若諸如RDL的特徵延伸超出微影罩幕的大小，則難以形成此特徵。根據本揭露的一些實施例，微影罩幕的大小能夠覆蓋整個晶圓/載板，且因此諸如RDL的特徵可具有跨晶圓長度（cross-wafer length）。
接著形成RDL以電性連接至金屬柱30。對應的製程在圖35所繪示的製程流程中被示出為製程208。根據本揭露的一些實施例，如圖5中所繪示，形成毯覆式金屬晶種層44，所述毯覆式金屬晶種層44包含延伸至開口42中的一些部分及位於介電層40上的一些其他部分。金屬晶種層44可由鈦、銅、鎳或類似者形成。根據本揭露的一些實施例，金屬晶種層44包括鈦層及鈦層上的銅層。接著在金屬晶種層44上形成鍍覆罩幕46，且接著使所述鍍覆罩幕46圖案化以形成開口48，並使得金屬晶種層44的一些部分被顯露出。此外，開口42亦在空間上與開口48接合。
根據一些實施例，以晶圓級執行鍍覆罩幕46的形成。因此會在相同曝光製程中曝光整個鍍覆罩幕46。使用晶圓級微影罩幕47以對鍍覆罩幕46進行曝光，且所述晶圓級微影罩幕足夠大以涵蓋待形成於鍍覆罩幕46中的所有圖案（諸如開口48）。微影罩幕47包括不透明部分47A及透明部分47B，且亦可具有圓形頂視形狀或矩形頂視形狀。對應的曝光製程亦類似於圖4中所繪示的曝光製程。
參照圖6，執行鍍覆製程以形成RDL 50A。鍍覆製程可包括電化學鍍覆、無電鍍覆或類似者。經鍍覆材料可包括金屬或金屬合金，且所述金屬或金屬合金包括鈦、銅、鎳、鋁、鎢、其多層及/或其合金。
在後續製程中，例如在灰化製程中移除鍍覆罩幕46。接著蝕刻先前由鍍覆罩幕46覆蓋的毯覆式金屬晶種層44的部分。圖7繪示所得到的結構。金屬晶種層44的剩餘部分被視為RDL 50A的部分。RDL 50A包括介電層40中的通孔部分以及介電層40上的跡線（線）部分。跡線部分可包括較窄部分及較寬部分，其中較寬部分可充當金屬接墊。
參照圖8，根據本揭露的一些實施例，形成額外介電層及對應的RDL層。對應的製程在圖35所繪示的製程流程中被示出為製程210。應瞭解的是，取決於設計要求，介電層及RDL層的數目可比所繪示的數目更多或更少。根據本揭露的一些實施例，使用由用於形成介電層40的候選材料的類似族群中選出的材料來形成介電層52。RDL 50B形成以延伸至介電層52中且電性耦接至封裝組件26。可使用用於形成RDL 50A的類似材料及方法形成RDL 50B。介電層40及介電層52以及RDL 50A及RDL 50B組合地形成內連線結構56。所述內連線結構56可將包封體38中的所有封裝組件26電性內連為積體系統。在下文中將RDL 50A及RDL 50B組合地稱為RDL 50。在RDL 50B的形成中，可使用足夠大以覆蓋整個載板20的微影罩幕，以使得可在相同微影製程中形成處於相同級的所有RDL 50B。
圖9繪示電性連接件57的形成。根據本揭露的一些實施例，電性連接件57為焊料區。根據替代性實施例，電性連接件57包括金屬柱及金屬柱上的焊料區。電性連接件57的形成可包括將焊料球放置於頂部RDL層中的RDL接墊被暴露出的部分上，且接著回焊焊料球以形成焊料區。根據本揭露的替代性實施例，電性連接件57的形成包括執行鍍覆步驟以形成金屬柱及金屬柱上的焊料區，且接著回焊被鍍覆的焊料區。在本揭露的描述中，將DAF 24上方的特徵組合地稱為封裝組件，所述封裝組件可為重構晶圓（reconstructed wafer）58。
根據其他實施例，封裝組件（重構晶圓58）可為重構面板（reconstructed panel）、重構基板（reconstructed substrate）或類似者。舉例而言，在封裝組件（重構晶圓58）的平面視圖中，封裝組件（重構晶圓58）可具有環形形狀、矩形形狀或類似者。封裝組件26可配置為重構面板或重構基板中的陣列。
在後續製程中，亦在圖9中所繪示，例如藉由將光投射於離型膜22上來自重構晶圓58卸下（剝離）載板20，且光（諸如雷射光束）穿過透明載板20。對應的製程在圖35所繪示的製程流程中被示出為製程212。離型膜22被分解，且重構晶圓58自載板20釋放。可在清潔製程或背側研磨製程中移除DAF 24。因而形成重構晶圓58。
圖10繪示封裝60的形成，其中併入重構晶圓58。對應的製程在圖35所繪示的製程流程中被示出為製程214。根據本揭露的一些實施例，在封裝60中使用未經鋸割的自載板20剝離的重構晶圓58，且如圖9中的所有封裝組件26仍在封裝60中。重構晶圓58亦可例如藉由移除脫離封裝組件26及RDL 50的一些外部部分來被削減（trimmed），或可未經削減。作為實例，圖10繪示封裝60包括兩個重構晶圓58。應瞭解的是，封裝60可包括一個或大於兩個重構晶圓58。此外，當具有大於一個重構晶圓58時，重構晶圓58可具有相同結構或不同結構。
根據本揭露的一些實施例，將多個封裝組件62接合或貼合至重構晶圓58。所述封裝組件包括且不限於封裝、電壓調節器模組（voltage regulator module）、電源供應模組（power supply module）、IPD、IO連接件（諸如用於封裝60的IO的插座（socket））或類似者。重構晶圓58可經由熱界面材料（Thermal Interface Material；TIM）66貼合至熱模組64。可使用螺絲68、螺栓69以及加強件/支架70以將重構晶圓58緊固至熱模組64上。可在重構晶圓58及熱模組64中鑽孔，以使得螺栓69可穿過重構晶圓58及熱模組64。熱模組64可包括散熱器（heat sink）、熱散播器（heat spreader）、冷板（cold plate）或類似者。當使用冷板時，在其之中的對應冷卻劑可為氣體或液體，諸如水、油或類似者。
圖11繪示封裝72的形成，其中併入重構晶圓58。根據本揭露的一些實施例，經由覆晶接合來接合重構晶圓58與封裝組件74。封裝組件74可為封裝基板、中介板（interposer）、印刷電路板或類似者。封裝組件62可接合至封裝組件74。可藉由螺絲68及螺栓69將熱模組64、重構晶圓58以及封裝組件74緊固在一起。
封裝60（如圖10所示）及封裝72（如圖11所示）可為高效能計算（High-Performance Computing；HPC）封裝、人工智慧（Artificial Intelligence；AI）伺服器的加速器、用於資料中心應用程式的其他效能要求計算封裝，或用於一些伺服器的封裝。
參照圖11A、圖11B、圖12A、圖12B以及圖13至圖23論述封裝組件26（如在先前實施例中所論述的）的佈局的細節。根據此等實施例的重構晶圓58可為面積可大於約10,000平方毫米的大晶圓，且所述大晶圓的面積亦可在約10,000平方毫米與約70,686平方毫米之間的範圍內。圖12及圖13繪示根據一些實施例的重構晶圓58中的跨晶圓RDL 50。可包括一個或多個RDL 50的連接線具有端點EP1及端點EP2。在本揭露的描述中，內連端點EP1及端點EP2的RDL 50統稱為跨晶圓RDL，且由於跨晶圓RDL為RDL 50的集合，其亦使用標號50指代。端點EP1及端點EP2可為封裝組件26的導電接墊（或柱）或對諸如電性連接件57（如圖9所示）的外部連接的導電接墊。內連端點EP1及端點EP2的跨晶圓RDL 50的跡線長度（tracing length）為TL1。跡線長度為在追蹤端點EP1與端點EP2之間的路線時的總長度。舉例而言，圖14及圖15繪示連接於端點EP1與端點EP2之間的跨晶圓RDL。跨晶圓RDL 50可包括多個（諸如所示出的四個）層的RDL（包括跡線及通孔），且跡線（標記為76）的總長度為如圖12及圖13）中的跡線長度TL1。替代性地陳述，跡線長度TL1為流動於端點EP1與端點EP2之間的電流流過的路線的長度。相較於在圖14中RDL跡線中的一者為長跡線，圖15繪示RDL跡線中的兩者為長跡線的實施例。
返回參照圖12，重構晶圓58具有矩形頂視形狀，且重構晶圓58的對角線長度為DL1。根據一些實施例，重構晶圓58具有矩形頂視形狀，跨晶圓RDL 50具有大於約0.25的TL1/DL1比，且所述比可在約0.25與約1.0之間的範圍內。TL1為內連端點EP1及端點EP2的跡線長度，且DL1為重構晶圓58的對角線長度。根據一些實施例，重構晶圓58具有如圖13中所繪示的圓形頂視形狀，跨晶圓RDL 50具有大於約0.25的TL1/DIA1比，且所述比可在約0.25與約1.0之間的範圍內。TL1為內連端點EP1及端點EP2的跨晶圓RDL 50的跡線長度，且DIA1為重構晶圓58的直徑。
根據一些實施例，重構晶圓58具有大於約10,000平方毫米的面積。跨晶圓RDL的跡線長度可大於約26毫米，其為可藉由使用習知微影罩幕（有難度地）達到的最大長度。跡線長度可在約26毫米與約100毫米之間的範圍內。跨晶圓RDL 50也可具有大於約1.5倍封裝組件26的邊緣長度SDL的長度，例如圖16中所繪示。
圖16至圖21繪示根據一些實施例的重構晶圓58中的封裝組件26及跨晶圓RDL 50的一些實例。參照圖16，重構晶圓58具有矩形頂視形狀。封裝組件26佈置為陣列。跨晶圓RDL 50將第一列中的封裝組件26連接至最末列中的封裝組件26。跨晶圓RDL 50以穿過封裝組件26之間的空間（在頂視圖中）佈線。圖17繪示重構晶圓58具有圓形頂視形狀，且跨晶圓RDL 50通過多個封裝組件26之間的空間。
參照圖18，重構晶圓58具有矩形頂視形狀，且封裝組件26佈置為陣列。多個跨晶圓RDL 50可連接相同的兩個封裝組件26。所述多個跨晶圓RDL 50可彼此平行，且穿過封裝組件26的兩個相鄰列及/或行之間的相同空間佈線。圖19繪示具有圓形頂視形狀的重構晶圓58，其中跨晶圓RDL 50穿過封裝組件26的陣列的外側佈線。跨晶圓RDL 50亦可連接實質上位於相同直徑的對置端上的兩個封裝組件26。
圖20至圖25繪示配置為組GD的封裝組件26。組GD可具有彼此一致的結構。每一組GD中可包括單個類型的封裝組件，諸如計算晶粒，或可包括多個封裝組件，諸如邏輯/計算晶粒、記憶體晶粒、被動元件、IO晶粒及/或類似者。相同組GD中的封裝組件26之間的組內間隔可等於或小於組GD之間的組間間隔。舉例而言，圖20及圖21繪示出組內間隔S1小於組間間隔S2。根據一些實施例，跨晶圓RDL 50可以多個組態佈線。舉例而言，一些跨晶圓RDL 50中可跨越（cross-over）一些封裝組件，而一些其他跨晶圓RDL 50可能未跨越任何封裝組件26（除連接至跨晶圓RDL 50的封裝組件26外）。一些跨晶圓RDL 50可包括不同介電層中的部分。舉例而言，跨晶圓RDL 50-1及跨晶圓RDL 50-2可在不同介電層中。在圖20中，重構晶圓58具有矩形頂視形狀，且在圖21中，重構晶圓58具有圓形頂視形狀。
圖22、圖23、圖24以及圖25繪示根據一些實施例的封裝組件組GD。跨晶圓RDL未繪示，而跨晶圓RDL可類似於圖16至圖21中所繪示的跨晶圓RDL。舉例而言，圖22繪示包括封裝組件組GD的矩形重構晶圓58，且每一組GD包括2×2的封裝組件26陣列。圖23繪示包括封裝組件組GD的圓形重構晶圓58，且每一組GD包括2×2的封裝組件26陣列。圖24繪示包括封裝組件組GD的矩形重構晶圓58，且每一組GD包括3×3的封裝組件26陣列。圖25繪示包括封裝組件組GD的圓形重構晶圓58，且每一組GD包括3×3的封裝組件26陣列。
圖26至圖33繪示跨晶圓RDL 50的剖視圖及其在多個介電層52及介電層40中的分佈方式。舉例而言，圖26繪示端點EP1為封裝組件26中的一者的導電接墊/柱且端點EP2為重構晶圓58的頂部導電特徵的跨晶圓RDL 50，其中所述頂部導電特徵可與最靠近重構晶圓58的邊緣的封裝組件交疊。端點EP1及端點EP2靠近重構晶圓58的相對的側邊緣（例如，左側邊緣及右側邊緣）。在介電層52的一者中的RDL 50自重構晶圓58的左側邊緣實質上延伸至右側邊緣。此外，底部介電層40及介電層40正上方的介電層52中的RDL 50中的一者（標記為50'）具有端點EP1’及端點EP2’，其中對應的RDL 50單獨為自重構晶圓58的左側邊緣實質上延伸至右側邊緣的跨晶圓RDL。
圖27繪示根據一些實施例的跨晶圓RDL。跨晶圓RDL 50具有靠近重構晶圓58的相對的側邊緣（例如，左側邊緣及右側邊緣）的端點EP1及端點EP2。根據一些實施例，各自在介電層中的兩個RDL自重構晶圓58的左側邊緣實質上組合地延伸至右側邊緣以形成跨晶圓RDL。
圖28繪示端點EP1及端點EP2兩者為封裝組件26的導電特徵的一些實施例。根據一些實施例，端點EP1及端點EP2兩者在最靠近重構晶圓58的各別邊緣的封裝組件26中。根據替代性實施例，端點EP1及端點EP2中的一或兩者在未最靠近重構晶圓58的任何邊緣的封裝組件26中。圖28繪示一個介電層52中的RDL 50自重構晶圓58的左側邊緣實質上延伸至右側邊緣。圖29繪示自重構晶圓58的左側邊緣至右側邊緣的距離實質上由多個介電層中的RDL同等地共用。
圖30至圖33繪示上部介電層52厚於下部介電層52及下部介電層40的一些實施例。因此，上部RDL 50厚於下部RDL 50。舉例而言，厚度T1至厚度T6標記於圖30中。厚度T4、厚度T5以及厚度T6大於厚度T1、厚度T2以及厚度T3。舉例而言，厚度T4/厚度T5/厚度T6與厚度T1/厚度T2/厚度T3的比可大於約1.5，且可在約1.5與3.0之間的範圍內。厚度T4、厚度T5以及厚度T6可在約8微米與約30微米之間的範圍內，其中厚度的實例為約15微米。為減小跨晶圓RDL的電阻，跨晶圓RDL的大部分長度可分佈於更厚的介電層中。舉例而言，圖30繪示頂部RDL 50自重構晶圓58的左側邊緣實質上延伸至右側邊緣。圖31繪示中間厚RDL 50自重構晶圓58的左側邊緣實質上延伸至右側邊緣。圖32及圖33繪示下部RDL延伸跨晶圓距離的較小部分，且跨晶圓距離的主要部分由更厚的介電層中的上部RDL覆蓋。根據一些實施例，下部薄RDL實質上用於連接至上部層，且並未顯著地用於橫向佈線，且上部厚層用於橫向佈線，如圖31至圖33中所繪示。根據一些實施例，圖31至圖33中的下部薄RDL為金屬接墊，其中上部金屬接墊與下部金屬接墊交疊，且用於內連金屬接墊的通孔未垂直對準。當金屬接墊佈線至厚金屬層時，佈線變成橫向。
圖34繪示根據本揭露的一些實施例的一些RDL 50的一部分的頂視圖。較厚RDL 50（如圖30至圖33所示的上部RDL）的寬度W可在約15微米與約200微米之間的範圍內，且作為實例可等於約15微米。較薄RDL 50（如圖30至圖33所示具有厚度T1、厚度T2以及厚度T3）的寬度W可在約5微米與約20微米之間的範圍內。相鄰厚RDL之間的間隔S可大於約20微米，且可在約20微米與約50微米之間的範圍內。厚度T1至厚度T6（如圖30至圖33所示，標記於圖30中）與寬度W（如圖34所示）的比可在約0.5與約2.0之間的範圍內。S/W的比可在約0.5與約3.0之間的範圍內。
應瞭解的是，已在圖14至圖34中示出各種實施例。在可應用時，這些實施例可併入至相同的重構晶圓58中。舉例而言，如圖26及圖33中的兩者或多於兩者（或所有者）中所繪示的佈線方式可以任何組合存在於相同的重構晶圓58中。另外，可形成跨晶圓RDL以將封裝組件26中的任一者連接至所有其他封裝組件26，使得可在重構晶圓58中的任何兩個封裝組件26之間建立一對一連接。此外，在可能時，所示出的頂視圖及示出的剖視圖可彼此對應。
在上文所示出的實施例中，一些製程及特徵根據本揭露的一些實施例來論述。亦可包括其他特徵及製程。舉例而言，可包括測試結構以輔助對3D封裝或3DIC元件的驗證測試。測試結構可包括例如形成於重佈線層中或基板上的測試接墊，且所述測試接墊允許測試3D封裝或3DIC、使用探針及/或探針卡，以及類似者。可對中間結構以及最終結構執行驗證測試。此外，本文中所揭露的結構及方法可結合併入對已知良好晶粒的中間驗證的測試方法來使用，以提高良率及降低成本。
本揭露的實施例具有一些有利的特徵。藉由形成跨晶圓RDL，相同重構晶圓中的任何兩個封裝組件均可經由跨晶圓RDL內連，而無需經過焊料區、晶粒、封裝、訊號加強器或類似者。RDL的電阻值因而減小，尤其對實質上在整個重構晶圓上延伸的跨晶圓RDL而言。因此，能夠提高高速計算的效能。另外，可提高信號完整性（signal integrity），可減小插入損耗（insertion loss），且可減少雜訊。
根據本揭露的一些實施例，一種形成半導體裝置的方法包括：在載板上放置多個封裝組件；在包封體中包封多個封裝組件；在多個封裝組件及包封體上形成感光介電層；使用第一微影罩幕暴露感光介電層；顯影感光介電層以形成多個開口，其中多個封裝組件的導電特徵藉由多個開口被暴露出；以及形成延伸至開口中的重佈線，其中重佈線中的一者具有大於約26毫米的長度，且重佈線、多個封裝組件以及包封體組合地形成重構晶圓。在實施例中，第一微影罩幕足夠大以覆蓋載板上的所有封裝組件。在實施例中，形成重佈線包括：塗佈鍍覆罩幕；使用足夠大以覆蓋載板上的所有封裝組件的第二微影罩幕來圖案化鍍覆罩幕；以及在鍍覆罩幕中的開口中鍍覆重佈線，其中具有大於約26毫米的長度的重佈線中的一者是藉由鍍覆形成。在實施例中，所述方法更包括：將重構晶圓從載板剝離；以及將重構晶圓接合至基本上由插入件、封裝基板、印刷電路板、熱模組及其組合所組成的族群中選出的封裝組件。在實施例中，已接合至封裝組件的重構晶圓具有圓形頂視形狀。在實施例中，重構晶圓在接合至封裝組件之前為未鋸割的。在實施例中，方法更包括藉由穿過重構晶圓的螺栓將重構晶圓緊固至封裝組件。在實施例中，多個封裝組件被放置為多個組，其中相同組中的封裝組件之間的組內間隔小於多個組中的相鄰者之間的組間間隔。在實施例中，重佈線在多個重佈線層中，且多個重佈線層的上部層厚於多個重佈線層的下部層。
根據本揭露的一些實施例，一種形成半導體裝置的方法包括：在包封體中包封多個裝置晶粒；以及在多個裝置晶粒上形成重佈線且所述重佈線電性耦接至多個裝置晶粒，其中多個裝置晶粒、包封體以及重佈線為重構晶圓的部分，且重構晶圓包括：第一側邊緣；第二側邊緣，其中第一側邊緣及第二側邊緣為重構晶圓的相對的側邊緣；第一裝置晶粒，靠近第一側邊緣；以及第二裝置晶粒，靠近第二側邊緣，其中形成跨晶圓重佈線以包括重佈線中的至少一者，且跨晶圓重佈線具有連接至第一裝置晶粒的第一末端以及連接至第二裝置晶粒或與第二裝置晶粒交疊的第二末端。在實施例中，使用相同的曝光製程形成相同層中的所有重佈線。在實施例中，使用足夠大以覆蓋所有包封體的微影罩幕來執行相同的曝光製程。在實施例中，第二末端處於重構晶圓的頂表面，且第二末端與第二裝置晶粒交疊。在實施例中，第二末端連接至第二裝置晶粒。在實施例中，跨晶圓重佈線具有大於約26毫米的長度。在實施例中，方法更包括，在不鋸割重構晶圓的情況下將重構晶圓接合至基本上由插入件、封裝基板、印刷電路板、熱模組及其組合所組成的族群中選出的封裝組件。
根據本揭露的一些實施例，一種形成半導體裝置的方法包括：形成重構晶圓，包括：在模塑化合物中模塑多個裝置晶粒；形成電性耦接至多個裝置晶粒的多個重佈線層，其中多個重佈線層形成多個跨晶圓重佈線，每一跨晶圓重佈線連接一對多個裝置晶粒，且每一跨晶圓重佈線包括多個重佈線層中的至少一者中的重佈線；以及將重構晶圓接合至熱模組。在實施例中，多個跨晶圓重佈線形成針對每一對多個裝置晶粒的一對一連接。在實施例中，方法更包括將重構晶圓緊固至熱模組。在實施例中，跨晶圓重佈線中的一者具有大於約26毫米的跡線長度。
前文概述若干實施例的特徵，以使所屬領域中具通常知識者可更好地理解本揭露的態樣。所屬領域中具通常知識者應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範圍，且所屬領域中具通常知識者可在不脫離本揭露的精神及範圍的情況下在本文中作出各種改變、替代以及更改。
20‧‧‧載板 22‧‧‧離型膜 24‧‧‧晶粒貼合膜 26、26A、26B、62、74‧‧‧封裝組件 30‧‧‧導電柱 32、40、52‧‧‧介電層 33‧‧‧導電層 36、47‧‧‧微影罩幕 36A、47A‧‧‧不透明部分 36B、47B‧‧‧透明部分 38‧‧‧包封體 42、48‧‧‧開口 44‧‧‧金屬晶種層 46‧‧‧鍍覆罩幕 47‧‧‧晶圓級微影罩幕 50、50-1、50-2、50A、50B、50'‧‧‧重佈線（RDL） 56‧‧‧內連線結構 57‧‧‧電性連接件 58‧‧‧重構晶圓 60、72‧‧‧封裝 64‧‧‧熱模組 66‧‧‧熱界面材料 68‧‧‧螺絲 69‧‧‧螺栓 70‧‧‧加強件/支架 76‧‧‧跡線 200‧‧‧製程流程 202、204、206、208、210、212、214‧‧‧製程 DL1‧‧‧對角線長度 EP1、EP1’、EP2、EP2’‧‧‧端點 GD‧‧‧組 S‧‧‧間隔 S1‧‧‧組內間隔 S2‧‧‧組間間隔 SDL‧‧‧邊緣長度 T1、T2、T3、T4、T5、T6‧‧‧厚度 TL1‧‧‧跡線長度 W‧‧‧寬度
圖1至圖10是根據一些實施例的封裝的形成的中間階段的剖視圖。 圖11是根據一些實施例的封裝的剖視圖。 圖12及圖13是根據一些實施例的重構晶圓中的重佈線（Redistribution Lines；RDLs）的跡線長度的頂視圖。 圖14及圖15是根據一些實施例的重構晶圓中的RDL的跡線長度的剖視圖。 圖16至圖21是根據一些實施例的重構晶圓中的一些RDL的頂視圖。 圖22至圖25繪示根據一些實施例的重構晶圓中的晶粒組。 圖26至圖33繪示根據一些實施例的重構晶圓中的RDL在不同介電層中的分佈。 圖34是根據一些實施例的一些RDL的頂視圖。 圖35繪示用於形成根據一些實施例的封裝的製程流程。
26‧‧‧封裝組件
38‧‧‧包封體
40‧‧‧介電層
50‧‧‧重佈線(RDL)
56‧‧‧內連線結構
58‧‧‧重構晶圓
76‧‧‧跡線
EP1、EP2‧‧‧端點

Claims (20)

  1. 一種形成半導體裝置的方法，所述方法包括： 在載板上放置多個封裝組件； 在包封體中包封所述多個封裝組件； 在所述多個封裝組件及所述包封體上形成感光介電層； 使用第一微影罩幕暴露所述感光介電層； 顯影所述感光介電層以形成多個開口，其中所述多個封裝組件的導電特徵藉由所述多個開口被暴露出；以及 形成延伸至所述開口中的重佈線，其中所述重佈線中的一者具有大於約26毫米的長度，且所述重佈線、所述多個封裝組件以及所述包封體組合地形成重構晶圓。
  2. 如申請專利範圍第1項所述的形成半導體裝置的方法，其中所述第一微影罩幕足夠大以覆蓋所述載板上的所有封裝組件。
  3. 如申請專利範圍第1項所述的形成半導體裝置的方法，其中形成所述重佈線包括： 塗佈鍍覆罩幕； 使用足夠大以覆蓋所述載板上的所有封裝組件的第二微影罩幕來圖案化所述鍍覆罩幕；以及 在所述鍍覆罩幕的開口中鍍覆所述重佈線，其中所述具有大於約26毫米的長度的所述重佈線中的一者是藉由鍍覆形成。
  4. 如申請專利範圍第1項所述的形成半導體裝置的方法，更包括： 將所述重構晶圓從所述載板剝離；以及 將所述重構晶圓接合至基本上由插入件、封裝基板、印刷電路板、熱模組及其組合所組成的族群中選出的封裝組件。
  5. 如申請專利範圍第4項所述的形成半導體裝置的方法，其中已接合至所述封裝組件的所述重構晶圓具有圓形頂視形狀。
  6. 如申請專利範圍第4項所述的形成半導體裝置的方法，其中所述重構晶圓在接合至所述封裝組件之前為未鋸割的。
  7. 如申請專利範圍第4項所述的形成半導體裝置的方法，更包括藉由穿過所述重構晶圓的螺栓將所述重構晶圓緊固至所述封裝組件。
  8. 如申請專利範圍第1項所述的形成半導體裝置的方法，其中所述多個封裝組件被放置為多個組，其中相同組中的封裝組件之間的組內間隔小於所述多個組中的相鄰者之間的組間間隔。
  9. 如申請專利範圍第1項所述的形成半導體裝置的方法，其中所述重佈線在多個重佈線層中，且所述多個重佈線層的上部層厚於所述多個重佈線層的下部層。
  10. 一種形成半導體裝置的方法，所述方法包括： 在包封體中包封多個裝置晶粒；以及 在所述多個裝置晶粒上形成重佈線且所述重佈線電性耦接至所述多個裝置晶粒，其中所述多個裝置晶粒、所述包封體以及所述重佈線為重構晶圓的部分，且所述重構晶圓包括： 第一側邊緣； 第二側邊緣，其中所述第一側邊緣及所述第二側邊緣為所述重構晶圓的相對的側邊緣； 第一裝置晶粒，靠近所述第一側邊緣；以及 第二裝置晶粒，靠近所述第二側邊緣，其中形成跨晶圓重佈線以包括所述重佈線中的至少一者，且所述跨晶圓重佈線具有連接至所述第一裝置晶粒的第一末端以及連接至所述第二裝置晶粒或與所述第二裝置晶粒交疊的第二末端。
  11. 如申請專利範圍第10項所述的形成半導體裝置的方法，其中使用相同的曝光製程形成相同層中的所有重佈線。
  12. 如申請專利範圍第11項所述的形成半導體裝置的方法，其中使用足夠大以覆蓋所有所述包封體的微影罩幕來執行所述相同的曝光製程。
  13. 如申請專利範圍第10項所述的形成半導體裝置的方法，其中所述第二末端處於所述重構晶圓的頂表面，且所述第二末端與所述第二裝置晶粒交疊。
  14. 如申請專利範圍第10項所述的形成半導體裝置的方法，其中所述第二末端連接至所述第二裝置晶粒。
  15. 如申請專利範圍第10項所述的形成半導體裝置的方法，其中所述跨晶圓重佈線具有大於約26毫米的長度。
  16. 如申請專利範圍第10項所述的形成半導體裝置的方法，更包括，在不鋸割所述重構晶圓的情況下將所述重構晶圓接合至基本上由插入件、封裝基板、印刷電路板、熱模組及其組合所組成的族群中選出的封裝組件。
  17. 一種形成半導體裝置的方法，包括： 形成重構晶圓，包括： 在模塑化合物中模塑多個裝置晶粒； 形成電性耦接至所述多個裝置晶粒的多個重佈線層，其中所述多個重佈線層形成多個跨晶圓重佈線，每一所述跨晶圓重佈線連接一對所述多個裝置晶粒，且每一所述跨晶圓重佈線包括所述多個重佈線層中的至少一者中的重佈線；以及 將所述重構晶圓接合至熱模組。
  18. 如申請專利範圍第17項所述的形成半導體裝置的方法，其中所述多個跨晶圓重佈線形成針對每一對所述多個裝置晶粒的一對一連接。
  19. 如申請專利範圍第17項所述的形成半導體裝置的方法，更包括將所述重構晶圓緊固至所述熱模組。
  20. 如申請專利範圍第17項所述的形成半導體裝置的方法，其中所述跨晶圓重佈線中的一者具有大於約26毫米的跡線長度（tracing length）。
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