TW202001844A - Pixel circuit - Google Patents

Abstract

A pixel circuit includes a driving transistor, a lighting unit, a writing circuit, a voltage regulating circuit, and a compensation circuit. A first node of the driving transistor is configured to receive a lighting control signal, a second node of the driving transistor couples with a first node, and a control node of the driving transistor couples with a second node. The lighting unit includes a cathode and an anode, the anode couples with the first node, and the cathode is configured to receive a reference voltage. The writing circuit couples with the second node and a third node, and is configured to determine a second node voltage according to a first control signal and a data voltage. The voltage regulating circuit couples with the third node, and is configured to determine a third node voltage according to a second control signal and the lighting control signal. The compensation circuit couples with the first node and the third node, and is configured to determine the third node voltage according to a third control signal and the lighting control signal.

Description

Pixel circuit

This disclosure relates to a pixel circuit, especially a pixel circuit that can compensate for the critical voltage variation of the driving transistor.

Low temperature poly-silicon thin-film transistor (low temperature poly-silicon thin-film transistor) has high carrier mobility and small size, suitable for high-resolution, narrow frame and low power consumption display panel. At present, the industry widely uses excimer laser annealing (excimer laser annealing) technology to form polycrystalline silicon thin films of low-temperature polycrystalline silicon thin film transistors. However, since the scanning power of each shot of the excimer laser is not stable, the polycrystalline silicon films in different regions will have differences in grain size and number. Therefore, the characteristics of the low-temperature polysilicon thin film transistor will be different in different areas of the display panel. For example, low-temperature polysilicon thin film transistors in different regions will have different threshold voltages. In addition, the power supply voltage provided by the display panel to the pixel circuits in different areas will have different voltage drops due to the equivalent impedance on the wires.

When the power voltage of the display panel or the threshold voltage of the driving transistor varies with the area, the display panel will face the problem of uneven display.

In view of this, how to provide a low-temperature polysilicon display panel with a uniform display screen is really a problem to be solved in the industry.

This disclosure provides a pixel circuit. The pixel circuit includes a driving transistor, a light emitting unit, a writing circuit, a voltage adjusting circuit and a compensation circuit. The driving transistor includes a first end, a second end, and a control end, wherein the first end of the driving transistor is used to receive a light-emitting control signal, and the second end of the driving transistor is coupled to a In the first node, the control terminal of the driving transistor is coupled to a second node. The light emitting unit includes an anode terminal and a cathode terminal, the anode terminal is coupled to the first node, and the cathode terminal is used to receive a reference voltage. The write circuit is coupled to the second node and a third node, and is used to determine a second node voltage of the second node according to a first control signal and a data voltage. The voltage regulating circuit is coupled to the third node, and is used to determine a third node voltage of the third node according to a second control signal and the light-emitting control signal. The compensation circuit is coupled to the first node and the third node, and is used to determine the voltage of the third node according to a third control signal and the light-emitting control signal.

By applying the above pixel circuit to a display panel, the display panel can have a uniform display screen.

100‧‧‧Pixel circuit

110‧‧‧Drive transistor

120‧‧‧Write circuit

122‧‧‧ First switch

124‧‧‧ First capacitor

130‧‧‧Voltage regulating circuit

132‧‧‧Second switch

140‧‧‧ Compensation circuit

142‧‧‧The third switch

144‧‧‧Second capacitor

150‧‧‧Lighting unit

201‧‧‧Display panel

203-1~203-n‧‧‧Column

205‧‧‧Source drive circuit

207‧‧‧ gate drive circuit

N1~N3‧‧‧First node to third node

S1[n-1]‧‧‧First control signal

S1[n]‧‧‧The first control signal of the adjacent line

S2‧‧‧Second control signal

S3‧‧‧ Third control signal

ELVDD‧‧‧luminescence control signal

VSS‧‧‧Reference voltage

Vn2‧‧‧second node voltage

Vn3‧‧‧third node voltage

Vdata‧‧‧Data voltage

Idri‧‧‧Drive current

PH1‧‧‧Highest level

PL1‧‧‧First lowest level

PH2‧‧‧Second highest level

PL2‧‧‧second lowest level

PX‧‧‧ preset level

In order to make the above and other objects, features, advantages and embodiments of the disclosed document more obvious and understandable, the drawings are described as follows: FIG. 1 is a simplified functional block of a pixel circuit according to an embodiment of the disclosed document Figure.

FIG. 2 is a simplified functional block diagram of a display panel according to an embodiment of the present disclosure.

FIG. 3 is an operation timing diagram of the pixel circuit of FIG. 1 according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 1 in the compensation stage.

FIG. 5 is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 1 at the writing stage.

FIG. 6 is a schematic diagram of the equivalent circuit operation of the pixel circuit of FIG. 1 during the light-emission phase.

The embodiments of the present invention will be described below in conjunction with related drawings. In the drawings, the same reference numerals indicate the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of the pixel circuit 100 according to an embodiment of the present disclosure. The pixel circuit 100 includes a driving transistor 110, a writing circuit 120, a voltage adjusting circuit 130, a compensation circuit 140, and a light emitting unit 150. The pixel circuit 100 can control the driving current Idri transmitted to the light-emitting unit 150, thereby controlling the light-emitting unit 150 to generate different gray-scale brightness.

In practice, the light-emitting unit 150 may be realized by light-emitting materials such as organic light-emitting diodes or micro light-emitting diodes.

The driving transistor 110 includes a first end, a second end, and a control end, wherein the first end of the driving transistor 110 is used to receive the light emission control signal ELVDD, and the second end of the driving transistor 110 is coupled to the first node N1 to drive The control terminal of the transistor is coupled to the second node N2.

The write circuit 120 is coupled to the second node N2 and the third node N3 and includes a first switch 122 and a first capacitor 124. The first switch 122 includes a first terminal, a second terminal, and a control terminal. The first terminal of the first switch 122 is used to receive the data voltage Vdata. The second terminal of the first switch 122 is coupled to the second node N2. The control terminal of the switch 122 is used to receive the first control signal S1[n-1]. The first capacitor 124 is coupled between the second node N2 and the third node N3. The write circuit 120 is used to determine the second node voltage Vn2 of the second node N2 according to the first control signal S1[n-1] and the data voltage Vdata.

The voltage regulating circuit 130 is coupled to the third node N3 and includes a second switch 132. The second switch 132 includes a first end, a second end, and a control end. The first end of the second switch 132 is coupled to the third node N3. The second end of the second switch 132 is used to receive the light emission control signal ELVDD. The control end of the two switches 132 is used to receive the second control signal S2. The voltage adjusting circuit 130 is used to determine the third node voltage Vn3 of the third node N3 according to the second control signal S2 and the light emission control signal ELVDD.

The compensation circuit 140 is coupled to the first node N1 and the third node N3, and includes a third switch 142 and a second capacitor 144. The third switch 142 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third switch 142 is coupled to the third node N3, and the second terminal of the third switch 142 is coupled to the first node N1. The control end of the three switches 142 is used to receive the third control signal S3. The second capacitor 144 includes a first terminal and a second terminal, wherein the first terminal of the second capacitor 144 is coupled to the third node N3, and the second terminal of the second capacitor 144 is used to receive the reference voltage VSS. The compensation circuit 140 is used to determine the third node voltage Vn3 according to the third control signal S3 and the light emission control signal ELVDD.

The light-emitting unit 150 includes an anode terminal and a cathode terminal. The anode terminal of the light-emitting unit 150 is coupled to the first node N1. The cathode terminal of the light-emitting unit 150 is used to receive the reference voltage VSS.

In practice, the first switch 122, the second switch 132, and the third switch 142 can be implemented with P-type low-temperature polysilicon thin film transistors, but this embodiment is not limited thereto. For example, the first switch 122, the second switch 132, and the third switch 142 may also be implemented with P-type amorphous silicon thin film transistors.

The operation of the pixel circuit 100 will be further described in conjunction with FIGS. 2 and 3. As shown in FIG. 2, the pixel circuit 100 is suitable for a display panel 201. A plurality of pixel circuits 100 are arranged in a matrix shape with a plurality of rows 203-1~203-n in the display panel 201, and each pixel circuit 100 is coupled to the source driving circuit 205 and the gate of the display panel 201 Driving circuit 207. In order to make the drawing simple and easy to explain, the other components and the connection relationship in the display panel 201 are not shown in FIG. 2.

The indexes 1 to n in the components and device numbers used in the specification and drawings of this case are just for convenience to refer to individual components and devices, and are not intended to limit the number of the foregoing components and devices to a specific number.

Please refer to FIG. 3, during the operation of the pixel circuit 100, the light emission control signal ELVDD switches between the first high level PH1 and the first low level PL1. The first control signal S1[n-1], the second control signal S2 and the third control signal S3 are switched between the second high level PH2 and the second low level PL2. The first high level PH1 and the second high level PH2 may be the same or different, and the first low level PL1 and the second low level PL2 may also be the same or different.

Please also refer to FIGS. 1~3. In the compensation stage T1, the light emission control signal ELVDD is switched from the first high level PH1 to the first low level PL1, so that the pixel circuit 100 no longer provides the driving current Idri to the light emitting unit 150 . The first control signal S1[n-1] and the third control signal S3 are the second low level PL2, and the second control signal S2 is the second high level PH2. Therefore, the first switch 122 and the third switch 142 are in an on state, and the second switch 132 is in an off state, so that the data voltage Vdata is transmitted to the second node N2, and the light emission control signal ELVDD is transmitted to the third node N3.

In other words, the pixel circuit 100 will be equivalent to the equivalent circuit shown in FIG. 4 during the compensation stage T1. The data voltage Vdata is maintained at the preset level PX during the compensation stage T1, so the second node voltage Vn2 is set by the write circuit 120 to the preset level PX during the compensation stage. In addition, the charge originally stored in the third node N3 will drain to the first end of the driving transistor 110, so that the third node voltage Vn3 starts to decrease. Because the driving transistor 110 in the compensation stage T1 is a diode-connected transistor, the third node voltage Vn3 will continue to drop until the third node voltage Vn3 is equal to the second low level PL2 plus The absolute value of the threshold voltage of the driving transistor 110. That is, the third node voltage Vn3 of the compensation stage T1 can be expressed by the following "Formula 1", where Vth represents the critical voltage of the driving transistor 110: Vn3=PL1+|Vth| "Formula 1"

It is worth mentioning that when the pixel circuit 100 of a certain column of the display panel 201 (eg, column 203-1) performs the compensation stage T1, other columns of the display panel 201 (eg, columns 201-2~201) -n) The pixel circuit 100 also performs a similar compensation operation. In this way, it can be ensured that each pixel circuit 100 of the display panel 201 has sufficient time to drain the charge stored in the third node N3, so that the respective third node voltage Vn3 can correctly reach the above in the compensation stage T1 The voltage level shown in "Formula 1".

In the compensation stage T1 of some embodiments, the light emission control signal ELVDD is switched from the first high level PH1 to the first low level PL1, and the second control signal S2 is then switched from the second low level PL2 to the second high level The level PH2 is to discharge the third node N3 charge stored in part through the second switch 132. Then, when the second control signal S2 is maintained at the second high level PH2, the third control signal S3 is switched from the second high level PH2 to the second low level PL2. In this way, it can be avoided that the third node voltage Vn3 is too high, so that the light-emitting unit 150 is unexpectedly turned on during the compensation stage T1, so as to improve the contrast of the display image.

In a writing phase T2, the second control signal S2 will be maintained at the second high level PH2, and the first control signal S1[n-1] and the third control signal S3 will be switched from the second low level PL2 to The second high level PH2 makes the first switch 122, the second switch 132, and the third switch 142 all off. Then, the first control signal S1[n-1] is switched from the second high level PH2 to the second low level PL2 to turn on the first switch 122. At this time, the pixel circuit 100 is equivalent to the equivalent circuit shown in FIG. As shown in FIG. 5, the data voltage Vdata is transmitted to the second node N2 through the first switch 122, so that the second node voltage Vn2 changes from the preset level PX to a specific data voltage Vdata corresponding to a certain gray-scale brightness.

At this time, the change amount of the second node voltage Vn2 is transferred to the third node N3 via the capacitive coupling effect of the first capacitor 124 and the second capacitor 144. Therefore, in the writing phase T2, the third node voltage Vn3 can be expressed by the following "Formula 2", where C1 and C2 represent the capacitance values of the first capacitor 124 and the second capacitor 144, respectively:

Also in the writing phase T2, the first control signal S1[n-1] is switched from the second low level PL2 to the second high level PH2 to turn off the first switch 122 again. That is, when the second control signal S2 and the third control signal S3 are maintained at the second high level PH2, the first control signal S1[n-1] will be switched from the second high level PH2 to the second low level first Bit PL2, and then switch from the second low level PL2 to the second high level PH2. At this time, in the display panel 201, the first control signal S1[n] that controls the pixel circuit 100 in the adjacent next row will turn on the first switch 122 of the pixel circuit 100 in the next row to perform a similar data voltage Vdata Until the pixel circuit 100 of each column in the display panel 201 completes the writing operation of the data voltage Vdata.

For example, in the writing phase T2, when the pixel circuit 100 of the column 203-1 of the display panel 201 completes the writing operation of the data voltage Vdata, the pixel circuit 100 of the row 203-2 will start writing the data voltage Vdata Into operation. When the pixel circuit 100 of the column 203-2 completes the writing operation of the data voltage Vdata, the pixel circuit 100 of the column 203-3 starts the writing operation of the data voltage Vdata, and so on.

In the lighting phase T3, the lighting control signal ELVDD is the first high level PH1, the first control signal S1[n-1] and the third control signal S3 are the second high level PH2, and the second control signal S2 is the second Low level PL2. At this time, the first switch 122 and the third switch 142 are in the off state, and the second switch 132 is in the on state.

Therefore, the pixel circuit 100 in the light-emitting phase T3 is equivalent to the equivalent circuit shown in FIG. 6. As shown in FIG. 6, the second switch 132 transmits the light emission control signal ELVDD to the third node N3, so that the third node voltage Vn3 changes from the voltage level described in "Formula 2" to the first high level PH1. At this time, the change amount of the third node voltage Vn3 is transmitted to the second node N2 through the capacitive coupling effect of the first capacitor 124 and the second capacitor 144. Therefore, in the light-emission phase T3, the second node voltage Vn2 can be expressed by the following "Formula 3":

At this time, the driving transistor 110 generates the driving current Idri according to the voltage difference between the first terminal and the control terminal of the driving transistor 110. Therefore, in the lighting phase T3, the driving current Idri can be expressed by the following "Formula 4":

In "Formula 4," k represents the product of the carrier mobility of the driving transistor 110, the unit capacitance of the gate oxide layer, and the gate width-to-length ratio.

It can be seen from "Formula 4" that the driving current dri has nothing to do with the critical voltage of the driving transistor. Therefore, even if the driving transistors 110 in different regions of the display panel 201 have different characteristics (for example, different threshold voltages), the driving current Idri generated by the driving transistors 110 in different regions will still have a fixed correspondence with the data voltage Vdata .

In addition, the driving current dri is also independent of the first high level PH1 of the light emission control signal ELVDD. Therefore, in the light-emitting phase T3, even if the light-emitting control signals ELVDD in different areas of the display panel 201 generate different levels of voltage drop due to wire impedance, the drive current Idri in different areas can still have a fixed correspondence with the data voltage Vdata.

In some embodiments, the first switch 122, the second switch 132, and/or the third switch 142 may also be implemented with N-type transistors. In this case, the first control signal S1[n-1], the second control signal S2, and/or the third control signal S3 and the corresponding control signals in the embodiment of FIG. 3 are opposite to each other.

In summary, applying the pixel circuit 100 to a display panel can not only make the display panel have a uniform display screen, but also increase the contrast of the display screen.

Certain words are used in the specification and patent application scope to refer to specific elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The description and the scope of patent application do not use the difference in names as the way to distinguish the components, but the difference in the functions of the components as the basis for the distinction. "Inclusion" mentioned in the description and the scope of patent application is an open term, so it should be interpreted as "including but not limited to." In addition, "coupling" here includes any direct and indirect connection means. Therefore, if it is described that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection, wireless transmission, optical transmission, or other signal connection, or through other elements or connections The means is indirectly electrically or signally connected to the second element.

The description method of "and/or" used herein includes any combination of one or more of the listed items. In addition, unless otherwise specified in the description, any singular case also includes the meaning of the plural case.

The above are only preferred embodiments of the present invention, and any equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

100‧‧‧Pixel circuit

110‧‧‧Drive transistor

120‧‧‧Write circuit

122‧‧‧ First switch

124‧‧‧ First capacitor

130‧‧‧Voltage regulating circuit

132‧‧‧Second switch

140‧‧‧ Compensation circuit

142‧‧‧The third switch

144‧‧‧Second capacitor

150‧‧‧Lighting unit

N1~N3‧‧‧First node to third node

S1[n-1]‧‧‧First control signal

S2‧‧‧Second control signal

S3‧‧‧ Third control signal

ELVDD‧‧‧luminescence control signal

VSS‧‧‧Reference voltage

Vn2‧‧‧second node voltage

Vn3‧‧‧third node voltage

Vdata‧‧‧Data voltage

Idri‧‧‧Drive current

Claims (10)

A pixel circuit includes: a driving transistor, including a first end, a second end, and a control end, wherein the first end of the driving transistor is used to receive a light-emitting control signal, and the driving transistor The second terminal is coupled to a first node, the control terminal of the driving transistor is coupled to a second node; a light emitting unit includes an anode terminal and a cathode terminal, the anode terminal is coupled to the first node , The cathode terminal is used to receive a reference voltage; a write circuit, coupled to the second node and a third node, is used to determine a second of the second node according to a first control signal and a data voltage Node voltage; a voltage regulation circuit, coupled to the third node, for determining a third node voltage of the third node based on a second control signal and the light-emitting control signal; and a compensation circuit, coupled to the The first node and the third node are used to determine the voltage of the third node according to a third control signal and the light emission control signal. The pixel circuit of claim 1, wherein the light emission control signal is switched between a first high level and a first low level, the first control signal, the second control signal and the third control signal Switching between a second high level and a second low level, in a compensation stage, the first control signal and the third control signal are the second low level, and the second control signal is the The second high level, and the light emission control signal is the first low level. The pixel circuit of claim 2, wherein, in the compensation stage, the light emission control signal is switched from the first high level to the first low level first, and the second control signal is then switched from the second low level The bit is switched to the second high level, and when the second control signal is maintained at the second high level, the third control signal is switched from the second high level to the second low level. The pixel circuit of claim 2, wherein in the compensation stage, the writing circuit sets the second node voltage to a predetermined level according to the data voltage, the driving transistor has a threshold voltage, and the compensation The circuit transmits the light emission control signal to the third node so that the voltage of the third node is the sum of the absolute value of the first low level and the threshold voltage. The pixel circuit of claim 2, wherein, in a writing stage, when the second control signal and the third control signal are maintained at the second high level, the first control signal is first determined by the second The high level is switched to the second low level, and then the second low level is switched to the second high level, and the light emission control signal is maintained at the first low level. The pixel circuit of claim 2, wherein, in a light-emitting stage, the first control signal and the third control signal are the second high level, and the second control signal is the second low level, and The light emission control signal is the first high level. The pixel circuit of claim 6, wherein in the light-emission phase, the voltage adjustment circuit transmits the light-emission control signal to the third node, and the write circuit transmits a variation of the third node voltage to The second node determines the voltage of the second node. The pixel circuit of claim 1, wherein the write circuit includes: a first switch including a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is used for receiving The data voltage, the second end of the first switch is coupled to the second node, the control end of the first switch is used to receive the first control signal; and a first capacitor is coupled to the second Between the node and the third node. The pixel circuit of claim 8, wherein the voltage regulating circuit comprises: a second switch including a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is coupled to In the third node, the second terminal of the second switch is used to receive the light-emitting control signal, and the control terminal of the second switch is used to receive the second control signal. The pixel circuit of claim 9, wherein the compensation circuit includes: a third switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third switch is coupled to the A third node, the second end of the third switch is coupled to the first node, the control end of the third switch is used to receive the third control signal; and a second capacitor includes a first end and A second terminal, the first terminal of the second capacitor is coupled to the third node, and the second terminal of the second capacitor is used to receive the reference voltage.

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