TWI652661B - Pixel circuit - Google Patents

Abstract

A pixel circuit includes a driving transistor, a light emitting unit, a reset circuit, a rectifier circuit, and a write circuit. The first terminal of the driving transistor is used to receive the power supply voltage, and the control terminal of the driving transistor is coupled to the first node. The anode terminal of the light-emitting unit is coupled to the second terminal of the driving transistor, and the cathode terminal of the light-emitting unit is used to receive a light-emitting control signal. The reset circuit is configured to determine a first node voltage of the first node according to the first control signal and the first reference voltage. The rectifier circuit is coupled between the first node and the second node, and is configured to receive a second reference voltage from the second node, wherein when the second reference voltage is greater than the voltage of the first node, the rectifier circuit turns on the first node and the second node When the second reference voltage is less than or equal to the first node voltage, the rectifier circuit disconnects the first node and the second node. The writing circuit is used for determining the first node voltage according to the second control signal and the data voltage.

Description

Pixel circuit

The present disclosure relates to a pixel circuit, and more particularly to a pixel circuit capable of compensating a threshold voltage variation of a driving transistor.

Low temperature poly-silicon thin-film transistors have the characteristics of high carrier mobility and small size, and are suitable for high-resolution, narrow-frame, and low-power display panels. At present, the industry widely uses excimer laser annealing technology to form polycrystalline silicon thin films of low-temperature polycrystalline silicon thin film transistors. However, because the scanning power of each shot of an excimer laser is not stable, polycrystalline silicon thin films in different regions will have differences in grain size and number. Therefore, the characteristics of the low temperature polycrystalline silicon thin film transistor will be different in different regions of the display panel. For example, low-temperature polycrystalline silicon thin film transistors in different regions may have different threshold voltages. In this case, the display panel will face the problem of uneven display.

In view of this, how to provide a display panel with uniform brightness is a problem to be solved in the industry.

This disclosure provides a pixel circuit. The pixel circuit includes a driving transistor, a light emitting unit, a reset circuit, a rectifier circuit, and a write circuit. The driving transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the driving transistor is used to receive a power voltage. The control terminal of the driving transistor is coupled to a first terminal. node. The light-emitting unit includes an anode terminal and a cathode terminal. The anode terminal is coupled to the second terminal of the driving transistor. The cathode terminal is used to receive a light-emitting control signal. When the light-emitting control signal is a first Micro Motion Position, the anode terminal and the cathode terminal are not conductive with each other. When the light emission control signal is at a first low level, the anode terminal and the cathode terminal are conductive with each other. The reset circuit is used to determine a first node voltage of the first node according to a first control signal and a first reference voltage. The rectifying circuit is coupled between the first node and a second node, and is configured to receive a second reference voltage from the second node. When the second reference voltage is greater than the voltage of the first node, the rectifying circuit The first node and the second node are turned on. When the second reference voltage is less than or equal to the voltage of the first node, the rectifier circuit disconnects the first node and the second node. The writing circuit is used for determining the first node voltage according to a second control signal and a data voltage.

The above pixel circuit is applied to a display panel, which can ensure that the display panel has a uniform display screen.

100‧‧‧pixel circuit

110‧‧‧Drive transistor

120‧‧‧Reset circuit

122‧‧‧The first switch

124‧‧‧first capacitor

130‧‧‧Rectifier circuit

132‧‧‧Second switch

140‧‧‧write circuit

142‧‧‧Third switch

144‧‧‧Second capacitor

150‧‧‧light-emitting unit

201‧‧‧Display Panel

203-1 ~ 203-n‧‧‧columns

205‧‧‧Source driving circuit

207‧‧‧Gate driving circuit

N1 ~ N3‧‧‧ first node ~ third node

S1‧‧‧first control signal

S2 [n] ‧‧‧Second control signal

S2 [n + 1] ‧‧‧Second control signal of adjacent column

ELVSS‧‧‧Light control signal

Vn1‧‧‧ first node voltage

Vn3‧‧‧ third node voltage

VDD‧‧‧ supply voltage

VSS‧‧‧first reference voltage

Vref‧‧‧second reference voltage

Vdata‧‧‧Data voltage

Idri‧‧‧Drive current

PH1‧‧‧The highest level

PL1‧‧‧First Low

PH2‧‧‧The second highest level

PL2‧‧‧ the second lowest level

PX‧‧‧ preset level

T1‧‧‧ Reset Phase

T2‧‧‧Compensation stage

T3‧‧‧writing stage

T4‧‧‧light-emitting stage

In order to make the above and other objects, features, advantages, and embodiments of the disclosure document more comprehensible, the description of the drawings is as follows: FIG. 1 is a functional block diagram of a pixel circuit according to an embodiment of the present disclosure.

FIG. 2 is a simplified functional block diagram of a display panel according to an embodiment of the present disclosure.

FIG. 3 is an operation timing diagram of a pixel circuit according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of an equivalent circuit of the pixel circuit of FIG. 1 in a reset phase.

FIG. 5 is an equivalent circuit driving diagram of the pixel circuit of FIG. 1 in a reset compensation phase.

FIG. 6 is an equivalent circuit driving schematic diagram of the pixel circuit of FIG. 1 in a writing stage.

FIG. 7 is an equivalent circuit driving schematic diagram of the pixel circuit of FIG. 1 in a light emitting stage.

Hereinafter, embodiments of the present invention will be described with reference to related drawings. In the drawings, the same reference numerals represent the same or similar elements or method flows.

FIG. 1 is a functional block diagram of a pixel circuit 100 according to an embodiment of the present disclosure. The pixel circuit 100 includes a driving transistor 110, a reset circuit 120, a rectifying circuit 130, a writing circuit 140, and a light emitting unit 150. The pixel circuit 100 can control the magnitude of the driving current Idri flowing through the light-emitting unit 150, so that the light-emitting unit 150 generates different gray-scale brightness.

In practice, the light-emitting unit 150 may be an organic light-emitting diode. (organic light-emitting diode) or micro light-emitting diode (micro light-emitting diode) and other light-emitting materials.

The driving transistor 110 is used for generating a driving current Idri, and includes a first terminal, a second terminal, and a control terminal. The first terminal of the driving transistor 110 is used to receive the power supply voltage VDD, and the control terminal is coupled to the first node N1. The light-emitting unit 150 includes an anode terminal and a cathode terminal. The anode terminal is coupled to the second terminal of the driving transistor 110 to receive the driving current Idri from the driving transistor 110, and the cathode terminal is used to receive a light-emitting control signal ELVSS. The light emission control signal ELVSS can be used to control the on and off states of the light emitting unit 150.

The reset circuit 120 includes a first switch 122 and a first capacitor 124. The first switch 122 includes a first terminal, a second terminal, and a control terminal. The first terminal of the first switch 122 is used to receive a first reference voltage VSS, the second terminal is coupled to the first node N1, and the control terminal is used to Receive a first control signal S1. The first capacitor 124 includes a first terminal and a second terminal. The first terminal of the first capacitor 124 is coupled to the first node N1, and the second terminal is used to receive the power supply voltage VDD. The reset circuit 120 is configured to determine the first node voltage Vn1 of the first node N1 according to the power supply voltage VDD, the first control signal S1, and the first reference voltage VSS.

The rectifier circuit 130 includes a second switch 132. The second switch 132 includes a first terminal, a second terminal, and a control terminal. The first terminal of the second switch 132 is coupled to the second node N2 and configured to receive the second reference voltage Vref from the second node N2. The second terminal and the control terminal of 132 are coupled to the first node N1. When the second reference voltage Vref is greater than the first node voltage Vn1, the rectification The circuit 130 turns on the first node N1 and the second node N2. On the other hand, when the second reference voltage Vref is less than or equal to the first node voltage Vn1, the rectifier circuit 130 turns off the first node N1 and the second node N2.

The write circuit 140 includes a third switch 142 and a second capacitor 144. The third switch 142 includes a first terminal, a second terminal, and a control terminal. The first terminal of the third switch 142 is coupled to the third node N3, the second terminal is used to receive the data voltage Vdata, and the control terminal is used to receive the first voltage. Second control signal S2 [n]. The second capacitor 144 is coupled between the first node N1 and the third node N3. The writing circuit 140 is configured to determine the first node voltage Vn1 according to the second control signal S2 [n] and the data voltage Vdata.

In practice, the first switch 122, the second switch 132, and the third switch 142 can be implemented by a P-type low-temperature polycrystalline silicon thin film transistor, but this embodiment is not limited thereto. For example, the first switch 122, the second switch 132, and the third switch 142 can also be implemented by a P-type amorphous silicon thin film transistor.

The operation of the pixel circuit 100 will be further described below with reference to FIGS. 2 and 3. As shown in FIG. 2, the pixel circuit 100 is suitable for a display panel 201. A plurality of pixel circuits 100 are arranged in a matrix shape with multiple columns 203-1 to 203-n in the display panel 201, and each pixel circuit 100 is coupled to a source driving circuit 205 and a gate of the display panel 201 Driving circuit 207. In order to make the drawing simple and easy to explain, other components and connection relationships in the display panel 201 are not shown in FIG. 2.

The indexes 1 ~ n in the components and device numbers used in the description and drawings of this case are only for the convenience of referring to individual components and devices. The number of the aforementioned elements and devices is intended to be limited to a specific number.

Please refer to FIG. 3. During the operation of the pixel circuit 100, the light emitting control signal ELVSS is switched between the first high level PH1 and the first low level PL1, and the first control signal S1 and the second control signal S2 [n] will switch between the second high level PH2 and the second low level PL2. The first high level PH1 and the second high level PH2 may be the same or different, and the first low level PL1 and the second low level PL2 may be the same or different.

Please refer to FIGS. 1 to 3 at the same time. In the reset phase T1, the light emission control signal ELVSS is the first high level PH1, so that the cathode terminal voltage of the light emitting unit 150 is higher than the anode terminal voltage. Therefore, the light emitting unit 150 will be in an off state to prevent the light emitting unit 150 from generating an unintended grayscale brightness that is not related to the data voltage Vdata during the reset phase T1. On the other hand, the first control signal S1 and the second control signal S2 [n] are both at the second low level PL2, so that the first switch 122, the second switch 132, and the third switch 142 are all in an on state.

Therefore, the pixel circuit 100 is equivalent to the equivalent circuit shown in FIG. 4 during the reset phase. As shown in FIG. 4, the reset circuit 120 transmits the first reference voltage VSS to the first node N1, and the rectifier circuit 130 transmits the second reference voltage Vref to the first node N1. In this embodiment, since the first reference voltage VSS is smaller than the second reference voltage Vref, the first node voltage Vn1 will be greater than the first reference voltage VSS during the reset phase, but will be smaller than the second reference voltage Vref, that is, the first A node voltage Vn1 is between the first reference voltage VSS and the second reference voltage Vref. Write circuit 140

It is worth mentioning that during the reset phase, the data voltage will be maintained at a preset level PX, where the preset level PX may be the same as the second reference The voltage level of the voltage Vref. Therefore, in the reset stage, when the data voltage Vdata is transmitted to the third node N3 through the third switch 142, the third node voltage Vn3 of the third node N3 is set to have a preset level PX.

In addition, when the pixel circuit 100 of one column (for example, column 203-1) of the display panel 201 performs the reset phase, the picture of other columns (for example, columns 203-2 to 203-n) of the display panel 201 is operated. The element circuit 100 also performs the operation in the reset phase.

Then, in a compensation phase T2, the light-emitting control signal ELVSS is maintained at the first high level PH1 to avoid the light-emitting unit 150 from generating unintended gray-scale brightness unrelated to the data voltage Vdata during the compensation phase T2. On the other hand, the first control signal S1 is the second high level PH2, and the second control signal S2 [n] is maintained at the second low level PL2, so that the first switch 122 is turned off, and the second switch 132 and The third switch 142 is maintained in an on state.

Therefore, the pixel circuit 100 is equivalent to the equivalent circuit shown in FIG. 5 during the compensation phase. As shown in FIG. 5, the rectifier circuit 130 transmits the second reference voltage to the first node N1, and further charges the first node N1. The data voltage is also transmitted to the third node N3 through the third switch 142. Because the data voltage Vdata is maintained at the preset level PX, the third node voltage Vn3 is also maintained at the preset level PX in the compensation phase T2.

In this embodiment, both the driving transistor 110 and the second switch 132 are implemented by a P-type low temperature polycrystalline silicon thin film transistor. Since the distance between the driving transistor 110 and the second switch 132 is similar, the driving transistor 110 and the second switch 132 have almost the same characteristics. For example, driving transistor 110 And the second switch 132 will have approximately the same threshold voltage. In this case, during the compensation phase, since the second switch 132 is a diode-connected transistor, the rectifier circuit 130 sets the first node voltage Vn1 to the second reference voltage Vref and the threshold voltage. The absolute value of the difference. Therefore, in the compensation phase, the first node voltage Vn1 can be expressed by the following "Formula 1", where Vth represents the threshold voltage for driving the transistor 110 or the second switch 132: Vn1 = Vref- | Vth | "Formula 1"

It is worth mentioning that when the pixel circuit 100 of one column (for example, column 203-1) of the display panel 201 is performing the compensation phase, other columns (for example, columns 203-2 to 203-n) of the display panel 201 The pixel circuit 100) also performs the operation of the compensation phase. In this way, regardless of the resolution of the display panel 201, each pixel circuit 100 can have sufficient time to perform the operation in the compensation phase.

Then, in the writing phase T3, the light emission control signal ELVSS is maintained at the first high level PH1, and the first control signal S1 is maintained at the second high level PH2. Therefore, the light emitting unit 150 and the first switch 122 are maintained in an off state. Since the voltage difference between the first node N1 and the second node N2 is a threshold voltage for driving the transistor 110 or the second switch 132, the second switch 132 is also in an off state. On the other hand, in the writing phase T3, the third switches 142 of all the pixel circuits 100 in the display panel 201 are first switched from the on state to the off state, and then sequentially turned on to sequentially write the corresponding specific gray. The specific data voltage Vdata of the step brightness.

Therefore, please refer to Figures 3 and 6 at the same time. For the pixel circuit 100 (for example, a pixel circuit 100 in column 203-1), when the first control signal S1 is maintained at the second high level PH2, the second control signal S2 [n] is first changed by the first The second high level PH2 is switched to the second low level PL2 to turn on the third switch 142 and transfer a specific data voltage Vdata to the third node N3. In this case, the pixel circuit 100 is equivalent to the equivalent circuit shown in FIG. 6.

Then, the second control signal S2 [n] is switched from the second low level PL2 to the second high level PH2 to turn off the third switch 142 again. In this case, the third node voltage Vn3 will change from the preset level PX to a specific data voltage Vdata, and the voltage change amount of the third node voltage Vn3 will be coupled by the capacitance of the first capacitor 124 and the second capacitor 144 The effect is passed to the first node N1. Therefore, in the writing phase T3, the first node voltage Vn1 is as shown in the following “Formula 2”, where C1 and C2 represent the capacitance values of the first capacitor 124 and the second capacitor 144, respectively:

It is worth mentioning that the first node voltage Vn1 in the above “Formula 2” will be greater than or equal to the second reference voltage Vref, so the second switch 132 will be maintained in the off state.

In addition, referring to FIG. 3, when the pixel circuit 100 of one column (for example, column 203-1) of the display panel 201 is controlled by the second control signal S2 [n], the specific data voltage Vdata is written into the third When the node N3 operates, the pixel circuit 100 of the next adjacent column (for example, column 203-2) is controlled according to the corresponding second control signal S2 [n + 1], and then the corresponding data voltage Vdata is written Enter the third node N3 in the next column, and so on.

Next, in the light emitting phase T4, the light emitting control signal ELVSS is switched from the first high level PH1 to the first low level PL1, so that the light emitting unit 150 is switched from the off state to the on state. On the other hand, the first control signal S1 and the second control signal S2 [n] are both at the second high level PH2, so that the first switch 122, the second switch 132, and the third switch 142 are all turned off.

Therefore, the pixel circuit 100 is equivalent to the equivalent circuit shown in FIG. 7 in the light emitting stage. At this time, the first node voltage Vn1 will still have a voltage value as shown in "Formula 2", so that the driving current Idri generated by the driving transistor 110 is as shown in the following "Formula 3": Among them, k represents the product of the carrier mobility of the driving transistor 110, the unit capacitance of the gate oxide layer, and the gate width-to-length ratio.

According to "Formula 3", the driving current Idri is independent of the threshold voltage writing circuit 140 of the driving transistor 110. Therefore, even if the driving transistors 110 in different regions of the display panel 201 have different characteristics (for example, different threshold voltages), the driving current Idri and the data voltage Vdata still maintain a fixed correspondence relationship.

In summary, applying the pixel circuit 100 to a display panel can not only ensure that the display panel has a uniform display screen, but also avoid The display panel generates unintended grayscale brightness that is unrelated to the data voltage Vdata, thereby increasing the contrast of the display screen.

In some embodiments, the first switch 122, the second switch 132, and / or the third switch 142 may also be implemented by an N-type transistor. In this case, the pulse direction of the first control signal S1, the second control signal S2, and / or the third control signal S3 is opposite to the pulse direction of the corresponding control signal in the embodiment of FIG. 3.

Certain terms are used in the description and the scope of patent applications to refer to specific elements. However, it should be understood by those with ordinary knowledge in the technical field that the same elements may be referred to by different names. The scope of the specification and patent application does not take the difference in names as a way to distinguish components, but rather uses the difference in functions of components as a basis for distinguishing. "Inclusion" mentioned in the specification and the scope of patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupled" includes any direct or indirect means of connection. Therefore, if the first element is described as being coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or through other elements or connections. Means are indirectly electrically or signally connected to the second element.

As used herein, the description of "and / or" includes any combination of one or more of the listed items. In addition, unless otherwise specified in the description, the terms of any singular number also include the meaning of the plural number.

The above are only preferred embodiments of the present invention. All equal changes and modifications made by the terms should fall within the scope of the present invention.

Claims (10)

A pixel circuit includes: a driving transistor including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the driving transistor is used to receive a power voltage, and the driving transistor is The control terminal is coupled to a first node; a light-emitting unit includes an anode terminal and a cathode terminal, the anode terminal is coupled to the second terminal of the driving transistor, and the cathode terminal is used to receive a light-emitting control signal, wherein When the light emission control signal is at a first high level, the anode terminal and the cathode terminal are not connected to each other. When the light emission control signal is at a first low level, the anode terminal and the cathode terminal are connected to each other; a reset A circuit for determining a first node voltage of the first node according to a first control signal and a first reference voltage; a rectifier circuit coupled between the first node and a second node for The second node receives a second reference voltage. When the second reference voltage is greater than the first node voltage, the rectifier circuit turns on the first node and the second node. When the second reference voltage is less than or equal to the first reference voltage, One node When the rectifier circuit to disconnect the first node and the second node; and a write circuit according to a second control signal and a data voltage determined by the voltage of the first node. For example, the pixel circuit of claim 1, wherein the light emitting control signal is switched between the first high level and the first low level, and the first control signal and the second control signal are at a second high level. Switch between a low level and a second low level. In a reset phase, the light-emitting control signal is the first high level, and the first control signal and the second control signal are the second low level. The pixel circuit of claim 2, wherein, in the reset phase, the reset circuit passes the first reference voltage to the first node, and the rectifier circuit passes the second reference voltage to the first node. Node so that the first node voltage is between the first reference voltage and the second reference voltage. For example, in the pixel circuit of claim 2, in a compensation stage, the light emission control signal is the first high level, the first control signal is the second high level, and the second control signal is the first Second low level. The pixel circuit of claim 4, wherein the driving transistor has a threshold voltage, and in the compensation phase, the rectifier circuit sets the first node voltage to an absolute value of the second reference voltage and the threshold voltage. Difference. For example, in the pixel circuit of claim 2, in a data writing stage, when the first control signal is maintained at the second high level, the second control signal is first switched from the second high level to The second low level is switched from the second low level to the second high level, and the rectifier circuit disconnects the first node and the second node. For example, in the pixel circuit of claim 2, in a light emitting stage, the light emitting control signal is the first low level, the first control signal and the second control signal are the second high level, and the The rectifier circuit disconnects the first node and the second node. The pixel circuit of claim 1, wherein the reset circuit includes a first switch including a first terminal, a second terminal, and a control terminal. The first terminal of the first switch is configured to receive the first switch. A first reference voltage, the second terminal of the first switch is coupled to the first node, the control terminal of the first switch is used to receive the first control signal; and a first capacitor including a first terminal And a second terminal, the first terminal of the first capacitor is coupled to the first node, and the second terminal of the first capacitor is used to receive the power voltage. The pixel circuit as claimed in claim 8, wherein the rectifier circuit includes a second switch including a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second switch is coupled to the first switch. A second node, the second terminal of the second switch and the control terminal of the second switch are coupled to the first node. The pixel circuit of claim 9, wherein the writing circuit includes a third switch including a first terminal, a second terminal, and a control terminal, and the first terminal of the third switch is coupled to a A third node, the second end of the third switch is used to receive the data voltage, the control end of the third switch is used to receive the second control signal; and a second capacitor is coupled to the first node And the third node.