TWI698849B - Pixel circuit - Google Patents

Pixel circuit Download PDF

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Publication number
TWI698849B
TWI698849B TW108135943A TW108135943A TWI698849B TW I698849 B TWI698849 B TW I698849B TW 108135943 A TW108135943 A TW 108135943A TW 108135943 A TW108135943 A TW 108135943A TW I698849 B TWI698849 B TW I698849B
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terminal
switch
compensation
voltage
rectifier
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TW108135943A
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Chinese (zh)
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TW202115701A (en
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鄭貿薰
鄭景升
洪嘉澤
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友達光電股份有限公司
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Priority to CN202010211620.5A priority patent/CN111369928B/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

A pixel circuit includes a readout unit, a compensation unit, and a rectifying unit. The readout unit includes a first readout switch. The compensation unit is configured to compensate a threshold voltage variation of the first readout switch. The rectifying unit is configured to rectify an alternating current signal, and generate a first voltage associated with a peak value of the alternating current signal. The compensating unit is further configured to generate a compensation voltage according to the first voltage, and transmit the compensation voltage to the first readout switch. The readout unit is configured to output an output signal according to the compensation voltage.

Description

畫素電路 Pixel circuit

本揭示內容是關於一種畫素電路，特別是關於一種超音波感測的畫素電路。 The present disclosure relates to a pixel circuit, particularly to a pixel circuit for ultrasonic sensing.

隨著面板技術日新月異，面板的功能也隨之快速增加。因此，面板中的功能密度越來越高，面板的功能也不在限於單純顯示影像。 With the rapid development of panel technology, the functions of the panel also increase rapidly. Therefore, the density of functions in the panel is getting higher and higher, and the function of the panel is not limited to simply displaying images.

本揭示內容之一實施方式係關於一種畫素電路，其包含讀取單元、補償單元以及整流單元。讀取單元包含第一讀取開關。補償單元用以補償第一讀取開關的臨界電壓變異。整流單元用以整流交流訊號，並產生與交流訊號的峰值有關的第一電壓。補償單元更用以依據第一電壓產生補償電壓，並將補償電壓傳輸至第一讀取開關。讀取單元用以依據補償電壓輸出輸出訊號。 One embodiment of the present disclosure relates to a pixel circuit including a reading unit, a compensation unit, and a rectification unit. The reading unit includes a first reading switch. The compensation unit is used to compensate the threshold voltage variation of the first read switch. The rectifier unit is used to rectify the AC signal and generate a first voltage related to the peak value of the AC signal. The compensation unit is further configured to generate a compensation voltage according to the first voltage, and transmit the compensation voltage to the first read switch. The reading unit is used for outputting an output signal according to the compensation voltage.

綜上所述，本案一些實施例所提供的畫素電路可感應交流訊號的最大振幅，並依據最大振幅產生輸出訊號。如此，畫素電路再將輸出訊號傳輸至顯示層，使顯示裝 置具有響應交流訊號以顯示的功能。 In summary, the pixel circuit provided by some embodiments of the present case can sense the maximum amplitude of the AC signal and generate an output signal according to the maximum amplitude. In this way, the pixel circuit transmits the output signal to the display layer to make the display device The device has a display function in response to AC signals.

10‧‧‧顯示層 10‧‧‧Display layer

20‧‧‧薄膜電晶體層 20‧‧‧Thin Film Transistor Layer

30‧‧‧超音波感測層 30‧‧‧Ultrasonic sensing layer

UW‧‧‧超音波訊號 UW‧‧‧Ultrasonic signal

100‧‧‧畫素電路 100‧‧‧Pixel circuit

120‧‧‧讀取單元 120‧‧‧Reading Unit

140‧‧‧補償單元 140‧‧‧Compensation unit

160‧‧‧整流單元 160‧‧‧rectifier unit

200‧‧‧壓電材料 200‧‧‧Piezoelectric material

AC‧‧‧交流訊號 AC‧‧‧AC signal

T1‧‧‧整流開關 T1‧‧‧Rectifier switch

T2‧‧‧整流開關 T2‧‧‧Rectifier switch

T3‧‧‧補償開關 T3‧‧‧Compensation switch

T4‧‧‧補償開關 T4‧‧‧Compensation switch

T5‧‧‧讀取開關 T5‧‧‧Read switch

T6‧‧‧讀取開關 T6‧‧‧Read switch

D1‧‧‧整流器 D1‧‧‧rectifier

CST‧‧‧補償電容 C ST ‧‧‧Compensation capacitor

A‧‧‧節點 A‧‧‧node

B‧‧‧節點 B‧‧‧node

G‧‧‧節點 G‧‧‧node

VBIAS‧‧‧偏壓電壓 V BIAS ‧‧‧bias voltage

VINT‧‧‧初始電壓 V INT ‧‧‧Initial voltage

VRST‧‧‧重置電壓 V RST ‧‧‧Reset voltage

VR‧‧‧輸出訊號 V R ‧‧‧Output signal

FVDD‧‧‧供應電壓 FVDD‧‧‧Supply voltage

SINT‧‧‧初始控制訊號 S INT ‧‧‧Initial control signal

SINT1‧‧‧初始控制訊號 S INT1 ‧‧‧Initial control signal

SINT2‧‧‧初始控制訊號 S INT2 ‧‧‧Initial control signal

SRST‧‧‧重置控制訊號 S RST ‧‧‧Reset control signal

SCOMP‧‧‧補償控制訊號 S COMP ‧‧‧Compensation control signal

SREAD‧‧‧讀取控制訊號 S READ ‧‧‧Read control signal

P1‧‧‧工作時段 P1‧‧‧Working hours

P2‧‧‧工作時段 P2‧‧‧Working hours

P3‧‧‧工作時段 P3‧‧‧Working hours

P4‧‧‧工作時段 P4‧‧‧Working hours

藉由閱讀以下對實施例之詳細描述可以更全面地理解本揭示案，參考附圖如下：第1圖為根據本揭示文件之一些實施例所繪示之一種感測顯示系統的示意圖；第2圖為根據本揭示文件之一些實施例所繪示的畫素電路的示意圖；第3圖為根據本揭示文件之一些實施例所繪示的畫素電路的電路示意圖；第4A、4B、4C、4D圖為根據本揭示文件之一些實施例所繪示操作於第3圖所示的畫素電路的訊號波形圖；第5圖為根據本揭示文件之一些其他的實施例所繪示的畫素電路的電路示意圖；第6A、6B圖為根據本揭示文件之替代的實施例所繪示的畫素電路的電路示意圖；以及第7圖為根據本揭示文件之各種不同的實施例所繪示的畫素電路的電路示意圖。 The present disclosure can be understood more fully by reading the following detailed description of the embodiments, with reference to the accompanying drawings as follows: Figure 1 is a schematic diagram of a sensing display system according to some embodiments of the present disclosure; Figure is a schematic diagram of a pixel circuit drawn according to some embodiments of this disclosure; Figure 3 is a schematic diagram of a pixel circuit drawn according to some embodiments of this disclosure; 4A, 4B, 4C, The 4D diagram is a signal waveform diagram of the pixel circuit shown in FIG. 3 according to some embodiments of the present disclosure; FIG. 5 is a pixel diagram according to some other embodiments of the present disclosure Circuit schematic diagram of the circuit; Figures 6A and 6B are schematic diagrams of pixel circuits drawn according to alternative embodiments of the present disclosure; and Figure 7 is drawn according to various embodiments of the present disclosure Schematic diagram of the pixel circuit.

下文係舉實施例配合所附圖式作詳細說明，但所描述的具體實施例僅僅用以解釋本案實施例，並不用來限定本案實施例，而結構操作之描述非用以限制其執行之順 序，任何由元件重新組合之結構，所產生具有均等功效的裝置，皆為本案實施例揭示內容所涵蓋的範圍。 The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the specific embodiments described are only used to explain the embodiments of the present case, and are not used to limit the embodiments of the present case, and the description of the structure operation is not used to limit the execution order. Foreword, any device with an equal effect produced by a recombination of components is within the scope of the disclosure of the embodiments of this application.

關於本文中所使用之『耦接』或『連接』，均可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，亦可指二或多個元件相互操作或動作。 Regarding the "coupling" or "connection" used in this article, it can refer to two or more components directly making physical or electrical contact with each other, or indirectly making physical or electrical contact with each other, or two or more Interoperability or action of components.

參考第1圖。第1圖為根據本揭示文件之一些實施例所繪示之一種感測顯示系統的示意圖。如第1圖所示，感測顯示系統包含薄膜電晶體層10、超音波傳感層20以及顯示層30。超音波傳感層20設置於薄膜電晶體層10之下，以及薄膜電晶體層10設置於顯示層30之下。在一些實施例中，感測顯示系統包含更多的層於顯示層30與薄膜電晶體層10之間，其具有不同的功能，為了簡化圖式，第1圖中以虛線表示其中包含的多個層。 Refer to Figure 1. FIG. 1 is a schematic diagram of a sensing display system according to some embodiments of the present disclosure. As shown in FIG. 1, the sensing display system includes a thin film transistor layer 10, an ultrasonic sensing layer 20, and a display layer 30. The ultrasonic sensing layer 20 is disposed under the thin film transistor layer 10, and the thin film transistor layer 10 is disposed under the display layer 30. In some embodiments, the sensing display system includes more layers between the display layer 30 and the thin film transistor layer 10, which have different functions. In order to simplify the diagram, the dotted lines in Figure 1 indicate the multiple layers contained therein. Layers.

在一些實施例中，感測顯示系統用以藉由一交流訊號感測顯示層30上的接觸物體。例如，藉由超音波訊號UW感測與顯示層30接觸的手指紋路。 In some embodiments, the sensing display system is used to sense contact objects on the display layer 30 by an AC signal. For example, the ultrasonic signal UW is used to sense the fingerprint path of the hand contacting the display layer 30.

在一些實施例中，超音波傳感層20用以產生超音波訊號UW傳輸至顯示層30。超音波訊號UW被傳輸至顯示層30後，在與顯示層30接觸的物體反射後傳輸回超音波傳感層20。反射後的超音波訊號UW具有與顯示層30接觸的物體的表面形狀的資訊。例如，與顯示層30接觸的物體具有高低不平的表面(像是指紋)，反射後的超音波訊號UW依據表面的高低不同而有不同的反射強度。 In some embodiments, the ultrasonic sensing layer 20 is used to generate an ultrasonic signal UW and transmit it to the display layer 30. After the ultrasonic signal UW is transmitted to the display layer 30, it is transmitted back to the ultrasonic sensor layer 20 after being reflected by the object in contact with the display layer 30. The reflected ultrasonic signal UW has information on the surface shape of the object in contact with the display layer 30. For example, the object in contact with the display layer 30 has an uneven surface (such as a fingerprint), and the reflected ultrasonic signal UW has different reflection intensities depending on the height of the surface.

在一些實施例中，超音波傳感層20更用以接收 反射回來的超音波訊號UW，並依據接收的超音波訊號UW產生一交流訊號AC。其中，交流訊號AC的振幅隨時間變化，並且具有一最大峰值代表在該些振幅中最大的一個。 In some embodiments, the ultrasonic sensing layer 20 is further used to receive The reflected ultrasonic signal UW generates an AC signal AC according to the received ultrasonic signal UW. Among them, the amplitude of the AC signal AC varies with time, and has a maximum peak value representing the largest one among the amplitudes.

在一些實施例中，薄膜電晶體層10用以接收超音波傳感層20產生的交流訊號AC，並依據交流訊號產生輸出訊號VR。在一些實施例中，顯示層30用以依據薄膜電晶體層10產生的輸出訊號VR顯示對應的影像。 In some embodiments, the thin film transistor layer 10 is used to receive the AC signal AC generated by the ultrasonic sensor layer 20 and generate an output signal V R according to the AC signal. In some embodiments, the display layer corresponding to the image display 30 according to the output signal of the thin film transistor layer 10 generated V R.

上述感測顯示系統的配置與功能僅為釋例之用途。各種不同的感測顯示系統的配置與功能均在本揭示文件的考量與範疇之內。 The configuration and functions of the above-mentioned sensing and display system are for illustrative purposes only. The configurations and functions of various sensor display systems are within the consideration and scope of this disclosure.

參考第2圖。第2圖為根據本揭示文件之一些實施例所繪示的畫素電路100的示意圖。如第2圖所示，畫素電路100包含讀取單元120、補償單元140以及整流單元160。在一些實施例中，畫素電路100設置於感測顯示系統中，且由感測顯示系統中的薄膜電晶體層10的至少部分來組成。在一些實施例中，畫素電路100用以接收上述超音波傳感層20產生的交流訊號AC，並依據交流訊號產生輸出訊號VR。 Refer to Figure 2. FIG. 2 is a schematic diagram of a pixel circuit 100 according to some embodiments of the present disclosure. As shown in FIG. 2, the pixel circuit 100 includes a reading unit 120, a compensation unit 140 and a rectification unit 160. In some embodiments, the pixel circuit 100 is disposed in a sensing display system, and is composed of at least a part of the thin film transistor layer 10 in the sensing display system. In some embodiments, the pixel circuit 100 is used to receive the AC signal AC generated by the ultrasonic sensor layer 20 and generate an output signal V R according to the AC signal.

如第2圖所示，讀取單元120耦接補償單元140，以及補償單元140耦接整流單元160。在一些實施例中，畫素電路100耦接壓電材料200，其用以接收從壓電材料200產生的交流訊號。在一些實施例中，壓電材料200用以產生超音波訊號UW，以及接收反射回來的超音波訊號UW，並依據接收的超音波訊號UW產生交流訊號AC。在一些實施例中，壓電材料200設置於感測顯示系統中，且由感測系統中 的超音波傳感層20的至少部分來組成。 As shown in FIG. 2, the reading unit 120 is coupled to the compensation unit 140, and the compensation unit 140 is coupled to the rectification unit 160. In some embodiments, the pixel circuit 100 is coupled to the piezoelectric material 200 for receiving AC signals generated from the piezoelectric material 200. In some embodiments, the piezoelectric material 200 is used to generate the ultrasonic signal UW, receive the reflected ultrasonic signal UW, and generate the AC signal AC according to the received ultrasonic signal UW. In some embodiments, the piezoelectric material 200 is provided in a sensing display system, and is used in the sensing system At least part of the ultrasonic sensing layer 20 is composed.

在一些實施例中，整流單元160用以接收從壓電材料200產生的交流訊號AC，並依據交流訊號AC產生一第一電壓VA。整流單元160更用以將第一電壓傳輸至補償單元140。在一些實施例中，第一電壓VA代表交流訊號中最大的峰值。 In some embodiments, the rectifying unit 160 is used to receive the AC signal AC generated from the piezoelectric material 200 and generate a first voltage V A according to the AC signal AC. The rectifying unit 160 is further used to transmit the first voltage to the compensation unit 140. In some embodiments, the first voltage V A represents the largest peak value in the AC signal.

在一些實施例中，補償單元140用以接收第一電壓VA，並依據第一電壓VA產生補償電壓VG。補償單元140更用以將補償電壓VG傳輸至讀取單元120。在一些實施例中，第一電壓VA與補償電壓VG成正相關。 In some embodiments, the compensation unit 140 is used to receive the first voltage V A and generate the compensation voltage V G according to the first voltage V A. The compensation unit 140 is further used to transmit the compensation voltage V G to the reading unit 120. In some embodiments, the first voltage V A is positively correlated with the compensation voltage V G.

在一些實施例中，讀取單元120用以接收補償電壓VG，並依據補償電壓VG輸出輸出訊號VR。在一些實施例中，讀取單元120更耦接讀取線(未繪示)，並用以將輸出訊號VR透過讀取線傳輸至資料處理單元(未繪示)，資料處理單元依據接收的輸出訊號VR使感測顯示系統中的顯示層30可顯示對應於輸出訊號VR的影像。上述的讀取線與資料處理單元之配置僅為釋例之用途。各種不同的讀取線與資料處理單元之配置均在本揭示文件的考量與範疇之內。例如，資料處理單元可配置於薄膜電晶體層10或未繪示於第1圖中的其他層。 In some embodiments, the reading unit 120 is used to receive the compensation voltage V G and output the output signal V R according to the compensation voltage V G. In some embodiments, the reader 120 is further coupled to a read line (not shown) means, and for transmitting the output signal V R to the data processing unit (not shown) through the read line, according to the received data processing unit output signal V R so that the sensing layer of the display system 30 may be displayed corresponding to the output video signal V R. The configuration of the reading line and the data processing unit described above is for illustrative purposes only. Various configurations of reading lines and data processing units are within the consideration and scope of this disclosure. For example, the data processing unit may be disposed on the thin film transistor layer 10 or other layers not shown in the first figure.

參考第3圖。第3圖為根據本揭示文件之一些實施例所繪示的畫素電路100的電路示意圖。如第3圖所示，畫素電路100包含整流開關T1、整流開關T2、讀取開關T3、補償開關T4、補償開關T5、讀取開關T6、整流器D1以及補償 電容CST。在一些實施例中，整流開關T1、整流開關T2、讀取開關T3、補償開關T4、補償開關T5與讀取開關T6以P型薄膜電晶體實現，整流器D1以二極體實現。 Refer to Figure 3. FIG. 3 is a schematic circuit diagram of the pixel circuit 100 according to some embodiments of the present disclosure. As shown in FIG. 3, the pixel circuit 100 includes a rectifier switch T1, a rectifier switch T2, a read switch T3, a compensation switch T4, a compensation switch T5, a read switch T6, a rectifier D1, and a compensation capacitor C ST . In some embodiments, the rectifier switch T1, the rectifier switch T2, the read switch T3, the compensation switch T4, the compensation switch T5, and the read switch T6 are realized by a P-type thin film transistor, and the rectifier D1 is realized by a diode.

在一些實施例中，讀取單元120包含讀取開關T3與讀取開關T6，補償單元140包含補償開關T4、補償開關T5與補償電容CST，以及整流單元160包含整流開關T1、整流開關T2與整流器D1。 In some embodiments, the reading unit 120 includes a reading switch T3 and a reading switch T6, the compensation unit 140 includes a compensation switch T4, a compensation switch T5, and a compensation capacitor C ST , and the rectification unit 160 includes a rectification switch T1 and a rectification switch T2 With rectifier D1.

在一些實施例中，整流開關T1、整流開關T2、讀取開關T3、補償開關T4、補償開關T5與讀取開關T6均包含第一端、第二端與控制端，以及整流器D1與補償電容CST包含第一端與第二端。 In some embodiments, the rectifier switch T1, the rectifier switch T2, the read switch T3, the compensation switch T4, the compensation switch T5, and the read switch T6 all include a first terminal, a second terminal and a control terminal, as well as a rectifier D1 and a compensation capacitor C ST includes a first end and a second end.

如第3圖所示，整流開關T1的第一端用以接收初始電壓VINT，整流開關T1的第二端耦接整流器D1的第二端於節點B，以及整流開關T1的控制端耦接整流開關T2的控制端，並用以接收初始控制訊號SINT。整流開關T2的第一端用以接收初始電壓VINT，整流開關T2的第二端耦接整流器D1的第一端於節點A。在一些實施例中，節點A為整流單元160與補償單元140耦接之處。 As shown in Figure 3, the first terminal of the rectifier switch T1 is used to receive the initial voltage V INT , the second terminal of the rectifier switch T1 is coupled to the second terminal of the rectifier D1 at node B, and the control terminal of the rectifier switch T1 is coupled The control terminal of the rectifier switch T2 is used to receive the initial control signal S INT . The first terminal of the rectifier switch T2 is used to receive the initial voltage V INT , and the second terminal of the rectifier switch T2 is coupled to the first terminal of the rectifier D1 at node A. In some embodiments, the node A is where the rectifying unit 160 and the compensation unit 140 are coupled.

如第3圖所示，補償電容CST的第一端耦接整流開關T2的第二端與整流器D1的第一端於節點A，補償電容CST的第二端耦接補償開關T4的第一端與補償開關T5的第二端於節點G。補償開關T4的控制端用以接收重置控制訊號SRST，補償開關T4的第二端用以接收重置電壓VRST。補償開關T5的控制端用以接收補償控制訊號SCOMP，補償開關T5的 第一端耦接讀取開關T3的第二端與讀取開關T6的第二端。補償電容CST的第二端更耦接讀取開關T3的控制端於節點G。在一些實施例中，節點G與補償開關T5的第一端為補償單元140與讀取單元120耦接之處。 As shown in Figure 3, the first end of the compensation capacitor C ST is coupled to the second end of the rectifier switch T2 and the first end of the rectifier D1 at node A, and the second end of the compensation capacitor C ST is coupled to the second end of the compensation switch T4. One end and the second end of the compensation switch T5 are at node G. The control terminal of the compensation switch T4 is used for receiving the reset control signal S RST , and the second terminal of the compensation switch T4 is used for receiving the reset voltage V RST . The control terminal of the compensation switch T5 is used to receive the compensation control signal S COMP . The first terminal of the compensation switch T5 is coupled to the second terminal of the read switch T3 and the second terminal of the read switch T6. The second terminal of the compensation capacitor C ST is further coupled to the control terminal of the read switch T3 at the node G. In some embodiments, the node G and the first end of the compensation switch T5 are where the compensation unit 140 and the reading unit 120 are coupled.

如第3圖所示，讀取開關T3的第一端用以接收供應電壓FVDD。讀取開關T6的控制端用以接收讀取控制訊號SREAD，讀取開關T6的第一端用以輸出輸出訊號VR。 As shown in Figure 3, the first terminal of the read switch T3 is used to receive the supply voltage FVDD. The control end of the read switch T6 is used to receive the read control signal S READ , and the first end of the read switch T6 is used to output the output signal V R.

如第3圖所示，畫素電路100於節點B之處與壓電材料200耦接，壓電材料200更用以接收偏壓電壓VBIAS。在一些實施例中，壓電材料200藉由偏壓電壓VBIAS產生超音波訊號UW，並用以接收反射的超音波訊號UW以產生交流訊號AC於節點B。 As shown in FIG. 3, the pixel circuit 100 is coupled to the piezoelectric material 200 at the node B, and the piezoelectric material 200 is further used to receive the bias voltage V BIAS . In some embodiments, the piezoelectric material 200 generates the ultrasonic signal UW by the bias voltage V BIAS , and is used to receive the reflected ultrasonic signal UW to generate the AC signal AC at the node B.

在一些實施例中，畫素電路100於節點B接收交流訊號AC，其中整流單元160用以將交流訊號AC整流，並於節點A之處產生第一電壓VA。 In some embodiments, the pixel circuit 100 receives the AC signal AC at the node B, and the rectifier unit 160 is used to rectify the AC signal AC and generate the first voltage V A at the node A.

在一些實施例中，補償單元140用以接收第一電壓VA並於節點G之處產生補償電壓VG，補償單元140更用以將補償電壓VG傳輸至讀取單元120。 In some embodiments, the compensation unit 140 is used to receive the first voltage V A and generate the compensation voltage V G at the node G , and the compensation unit 140 is further used to transmit the compensation voltage V G to the reading unit 120.

在一些實施例中，讀取開關T3以薄膜電晶體實現。在製造薄膜電晶體的製程中會經過高溫程序，薄膜電晶體中的非晶及/或多晶結構因為高溫而具有不均勻的分布。因此，展現在電晶體的臨界電壓上造成晶圓區域上的變異。在一些實施例中，補償單元140用以補償讀取單元120中讀取開關T3的臨界電壓變異，使補償電壓VG隨著讀取開關T3的臨 界電壓而變化。 In some embodiments, the read switch T3 is implemented by a thin film transistor. In the process of manufacturing the thin film transistors, a high temperature process is passed, and the amorphous and/or polycrystalline structure in the thin film transistors has an uneven distribution due to the high temperature. Therefore, the threshold voltage exhibited by the transistor causes a variation on the wafer area. In some embodiments, the compensation unit 140 is used to compensate the threshold voltage variation of the read switch T3 in the read unit 120, so that the compensation voltage V G varies with the threshold voltage of the read switch T3.

在一些實施例中，讀取單元120用以於節點G接收補償電壓VG，並將讀取開關T3操作於電晶體特性的飽和區，使其依據補償電壓VG輸出輸出訊號VR。 In some embodiments, the reading unit 120 is used to receive the compensation voltage V G at the node G, and operate the reading switch T3 in the saturation region of the transistor characteristic, so that it outputs the output signal V R according to the compensation voltage V G.

參考第4A~4D圖。第4A~4D圖為根據本揭示文件之一些實施例所繪示操作於第3圖所示的畫素電路100的訊號波形圖。如第4A~4D圖所示，操作於畫素電路100的訊號波形圖包含四個工作時段P1、P2、P3、P4以及偏壓電壓VBIAS、初始控制訊號SINT、重置控制訊號SRST、補償控制訊號SCOMP、讀取控制訊號SREAD與節點B上的交流訊號AC的波形。第4A~4D圖依序討論工作時段P1~P4之操作。 Refer to Figure 4A~4D. FIGS. 4A to 4D are diagrams showing signal waveforms operating on the pixel circuit 100 shown in FIG. 3 according to some embodiments of the present disclosure. As shown in FIGS. 4A to 4D, the signal waveform diagram operating on the pixel circuit 100 includes four working periods P1, P2, P3, P4, and the bias voltage V BIAS , the initial control signal S INT , and the reset control signal S RST , Compensation control signal S COMP , read control signal S READ and the waveform of the AC signal AC on node B. Figures 4A~4D discuss the operation of working hours P1~P4 in order.

參考第4A圖。第4A圖為畫素電路100操作於工作時段P1的示意圖。在一些實施例中，工作時段P1亦稱為初始化階段。在工作時段P1中，初始控制訊號SINT與重置控制訊號SRST具有邏輯低電位，補償控制訊號SCOMP與讀取控制訊號SREAD具有邏輯高電位。具有邏輯低電位的初始控制訊號SINT與重置控制訊號SRST將整流開關T1、整流開關T2與補償開關T4開啟。具有邏輯高電位的補償控制訊號SCOMP與讀取控制訊號SREAD將補償開關T5與讀取開關T6關閉。 Refer to Figure 4A. FIG. 4A is a schematic diagram of the pixel circuit 100 operating in the working period P1. In some embodiments, the working period P1 is also referred to as the initialization phase. In the working period P1, the initial control signal S INT and the reset control signal S RST have a logic low level, and the compensation control signal S COMP and the read control signal S READ have a logic high level. The initial control signal S INT and the reset control signal S RST having a logic low potential turn on the rectifier switch T1, the rectifier switch T2, and the compensation switch T4. The compensation control signal S COMP and the read control signal S READ having a logic high potential turn off the compensation switch T5 and the read switch T6.

如第4A圖所示，因為整流開關T1與整流開關T2的開啟，節點A與節點B與初始電壓VINT導通，因此節點A的電壓VA與節點B上的電壓VB被初始化至與初始電壓VINT相同的電壓。此外，因為電壓VA與電壓VB相同，因此整流器D1兩端沒有壓差而關閉。 As shown in Figure 4A, because the rectifier switch T1 and the rectifier switch T2 are turned on, the nodes A and B are turned on with the initial voltage V INT , so the voltage V A of the node A and the voltage V B of the node B are initialized to the initial voltage V INT. The voltage V INT is the same voltage. In addition, because the voltage V A is the same as the voltage V B , the rectifier D1 is closed without a voltage difference across it.

如第4A圖所示，因為補償開關T4開啟以及補償開關T5關閉，節點G與重置電壓VRST導通，因此節點G上的電壓VG被初始化至與重置電壓VRST相同的電壓。在一些實施例中，初始電壓VINT與重置電壓VRST相同，因此補償電容CST兩端上的電壓相同。亦即電壓VA與電壓VG的電壓相同。 As shown in FIG. 4A, because the compensation switch T4 is turned on and the compensation switch T5 is turned off, the node G is turned on with the reset voltage V RST , so the voltage V G on the node G is initialized to the same voltage as the reset voltage V RST . In some embodiments, the initial voltage V INT is the same as the reset voltage V RST , so the voltage across the compensation capacitor C ST is the same. That is, the voltage of the voltage V A and the voltage of V G are the same.

如第4A圖所示，因為讀取開關T6關閉，因此沒有輸出訊號VR被讀取單元120輸出。 As shown in Figure 4A, since the read switch T6 off, so no output signal V R output unit 120 is read.

如第4A圖所示，在工作時段P1中，偏壓電壓VBIAS具有突波波形，壓電材料200接收偏壓電壓VBIAS而產生超音波訊號UW，產生的超音波訊號UW具有對應於偏壓電壓VBIAS的能量。 As shown in Figure 4A, in the working period P1, the bias voltage V BIAS has a surge waveform, the piezoelectric material 200 receives the bias voltage V BIAS to generate an ultrasonic signal UW, and the generated ultrasonic signal UW has a corresponding bias The energy of the voltage V BIAS .

在工作時段P1中，畫素電路100將節點A的電壓VA與節點B上的電壓VB初始化至初始電壓VINT，以及將節點G上的電壓VG初始化至重置電壓VRST。壓電材料200亦在工作時段P1中產生超音波訊號UW。在一些實施例中，壓電材料200不在工作時段P1產生超音波訊號UW，壓電材料200在工作時段P1之前產生超音波訊號UW。亦即，產生超音波訊號UW與初始化畫素電路100為可分開的兩個獨立操作。 In the working period P1, the pixel circuit 100 the voltage V B V A voltage on the node A and the node B is initialized to an initial voltage V INT, and the voltage on node V G G initialized to the reset voltage V RST. The piezoelectric material 200 also generates an ultrasonic signal UW during the working period P1. In some embodiments, the piezoelectric material 200 does not generate the ultrasonic signal UW during the working period P1, and the piezoelectric material 200 generates the ultrasonic signal UW before the working period P1. That is, generating the ultrasonic signal UW and initializing the pixel circuit 100 are two separate operations.

參考第4B圖。第4B圖為畫素電路100操作於工作時段P2的示意圖。在一些實施例中，工作時段P2亦稱為補償階段。在工作時段P2中，初始控制訊號SINT與補償控制訊號SCOMP具有邏輯低電位，重置控制訊號SRST與讀取控制訊號SREAD具有邏輯高電位。具有邏輯低電位的初始控制訊號SINT與補償控制訊號SCOMP將整流開關T1、整流開關T2與補 償開關T5開啟。具有邏輯高電位的重置控制訊號SRST與讀取控制訊號SREAD將補償開關T4與讀取開關T6關閉。 Refer to Figure 4B. FIG. 4B is a schematic diagram of the pixel circuit 100 operating in the working period P2. In some embodiments, the working period P2 is also referred to as the compensation phase. In the working period P2, the initial control signal S INT and the compensation control signal S COMP have a logic low level, and the reset control signal S RST and the read control signal S READ have a logic high level. The initial control signal S INT and the compensation control signal S COMP having a logic low potential turn on the rectifier switch T1, the rectifier switch T2, and the compensation switch T5. The reset control signal S RST and the read control signal S READ having a logic high potential turn off the compensation switch T4 and the read switch T6.

如第4B圖所示，整流單元160沒有接收到從壓電材料200來的交流訊號AC，因此整流單元160在工作時段P2中保持與工作時段P1操作後的狀態相同。 As shown in FIG. 4B, the rectifying unit 160 does not receive the AC signal AC from the piezoelectric material 200, so the rectifying unit 160 maintains the same state in the working period P2 as after the working period P1 is operated.

如第4B圖所示，因為讀取開關T3與補償開關T5開啟以及補償開關T4關閉，因此讀取開關T3與補償開關T5將供應電壓FVDD導通至節點G上。此外，因為讀取開關T3具有臨界電壓VTH3，因此補償單元140使節點G上的電壓VG具有大約為FVDD-|VTH3|的電壓。電壓VG接著被傳輸至讀取開關T3的控制端。 As shown in FIG. 4B, because the read switch T3 and the compensation switch T5 are turned on and the compensation switch T4 is closed, the read switch T3 and the compensation switch T5 conduct the supply voltage FVDD to the node G. In addition, because the read switch T3 has the threshold voltage V TH3 , the compensation unit 140 makes the voltage V G on the node G have a voltage of about FVDD-|V TH3 |. The voltage V G is then transmitted to the control terminal of the read switch T3.

如第4B圖所示，因為讀取開關T6關閉，因此沒有輸出訊號VR被讀取單元120輸出。 As shown in Figure 4B, since the read switch T6 off, so no output signal V R output unit 120 is read.

在工作時段P2中，補償單元140將具有讀取開關T3的臨界電壓的資訊傳輸至節點G上，並將電壓VG傳輸至讀取開關T3的控制端。換言之，補償單元140將具有臨界電壓VTH3的資訊的電壓VG補償至讀取單元120的讀取開關T3。因此，讀取開關T3的操作將依據具有本身臨界電壓VTH3的資訊的電壓VG來進行。 In the working period P2, the compensation unit 140 transmits the information with the threshold voltage of the read switch T3 to the node G, and transmits the voltage V G to the control terminal of the read switch T3. In other words, the compensation unit 140 compensates the voltage V G having the information of the threshold voltage V TH3 to the reading switch T3 of the reading unit 120. Therefore, the operation of reading the switch T3 will be performed based on the voltage V G having the information of its own threshold voltage V TH3 .

參考第4C圖。第4C圖為畫素電路100操作於工作時段P3的示意圖。在一些實施例中，工作時段P3亦稱為超音波感測階段。在工作時段P3中，壓電材料200接收反射回來的超音波訊號UW，並產生交流訊號AC傳輸至節點B。壓電材料200接收超音波訊號UW的能量後產生震盪的交流訊 號AC，如第4C圖所示，節點B上在工作時段P3具有交流訊號AC的波形。 Refer to Figure 4C. FIG. 4C is a schematic diagram of the pixel circuit 100 operating in the working period P3. In some embodiments, the working period P3 is also referred to as the ultrasonic sensing phase. In the working period P3, the piezoelectric material 200 receives the reflected ultrasonic signal UW, and generates an AC signal AC and transmits it to the node B. The piezoelectric material 200 generates an oscillating AC signal after receiving the energy of the ultrasonic signal UW AC, as shown in Fig. 4C, node B has the waveform of AC signal AC during working period P3.

在工作時段P3中，初始控制訊號SINT、重置控制訊號SRST、補償控制訊號SCOMP與讀取控制訊號SREAD具有邏輯高電位。具有邏輯高電位的初始控制訊號SINT、重置控制訊號SRST、補償控制訊號SCOMP與讀取控制訊號SREAD將整流開關T1、整流開關T2、補償開關T4、補償開關T5與讀取開關T6關閉。 In the working period P3, the initial control signal S INT , the reset control signal S RST , the compensation control signal S COMP and the read control signal S READ have a logic high potential. The initial control signal S INT with logic high potential, the reset control signal S RST , the compensation control signal S COMP and the read control signal S READ connect the rectifier switch T1, the rectifier switch T2, the compensation switch T4, the compensation switch T5 and the read switch T6 is closed.

如第4C圖所示，因為整流開關T1與整流開關T2的關閉，在整流器D1兩端的電壓VA、電壓VB與壓電材料200產生的交流訊號AC有關。節點B的電壓VB受交流訊號AC的影響上下震盪。整流器D1用以讓電流從節點A流向節點B，而禁止電流從節點B流向節點A。換言之，當節點A的電壓VA比節點B的電壓VB高時，原本存在節點A上的電荷流向節點B，使得節點A的電壓VA下降，且下降到與當時節點B的電壓VB相同。因此，只有當節點B的電壓VB下降時，節點A的電壓VA才會跟著變化。綜上所述，在工作時段P3中，整流器D1用以將交流訊號AC的負值部分整流至節點A上的電壓VA。更進一步地來說，因為當節點B的電壓VB比節點A的電壓VA低的時候，節點A的電壓VA才會跟著改變，因此節點A的電壓VA記錄著交流訊號負值部分中最低的峰值。 As shown in FIG. 4C, because the rectifier switch T1 and the rectifier switch T2 are closed, the voltage V A and the voltage V B across the rectifier D1 are related to the AC signal AC generated by the piezoelectric material 200. The voltage V B of the node B oscillates up and down under the influence of the AC signal AC. The rectifier D1 is used to allow current to flow from node A to node B, while prohibiting current from flowing from node B to node A. In other words, when the voltage V A of node A is higher than the voltage V B of node B, the original charge on node A flows to node B, so that the voltage V A of node A decreases and drops to the same level as the voltage V B of node B at the time. the same. Therefore, only when the voltage V B of the node B drops, the voltage V A of the node A will change accordingly. In summary, in the working period P3, the rectifier D1 is used to rectify the negative part of the AC signal AC to the voltage V A on the node A. Furthermore, because when the voltage V B of the node B is lower than the voltage V A of the node A, the voltage V A of the node A will change accordingly, so the voltage V A of the node A records the negative part of the AC signal The lowest peak in the

在工作時段P3中，因為補償開關T4與補償開關T5關閉，所以補償電容CST的節點G的電壓VG隨著節點A的電壓VA改變。舉例來說，當節點A的電壓VA隨著節點B的電 壓VB下降而下降時，節點G的電壓VG隨著節點A的電壓VA而下降。 In the working period P3, because the compensation switch T4 and the compensation switch T5 are closed, the voltage V G of the node G of the compensation capacitor C ST changes with the voltage V A of the node A. For example, when the voltage V A of the node A decreases as the voltage V B of the node B decreases, the voltage V G of the node G decreases as the voltage V A of the node A decreases.

在一些實施例中，如第4C圖所示，交流訊號AC的最低峰值為-△V，因此在節點A的電壓VA由大約VINT變化至大約VINT-△V，相應地，節點G的電壓VG隨之由大約FVDD-|VTH3|變化至大約FVDD-|VTH3|-△V。 In some embodiments, as shown in FIG. 4C, the lowest peak AC signal AC is - △ V, so the voltage V A of the node A to V INT of from about about changes in V INT - △ V, respectively, the node G followed by the voltage V G of about FVDD- | V TH3 | change to about FVDD- | V TH3 | - △ V .

如第4C圖所示，因為讀取開關T6關閉，因此沒有輸出訊號VR被讀取單元120輸出。 As shown in FIG. 4C, since the read switch T6 off, so no output signal V R output unit 120 is read.

在工作時段P3中，整流單元160將壓電材料200產生的交流訊號AC整流，並將交流訊號AC負值部分的峰值加載至節點A的電壓VA上，接著，補償單元140藉由感應節點A的電壓VA變化，使節點G的電壓VG隨之改變，並將具有臨界電壓VTH3與交流訊號的峰值資訊的電壓VG補償至讀取單元120的讀取開關T3。因此，讀取開關T3的操作將依據具有本身臨界電壓VTH3與交流訊號的峰值資訊的電壓VG來進行。 In the working period P3, the rectifying unit 160 rectifies the AC signal AC generated by the piezoelectric material 200, and loads the peak value of the negative portion of the AC signal AC on the voltage V A of the node A. Then, the compensation unit 140 uses the sensing node a variation of the voltage V a, the voltage V G of the node G will change, and will have a peak voltage V G to compensate the threshold voltage V TH3 information and communication signals to a reading unit 120 reads the switch T3. Therefore, the operation of reading the switch T3 will be performed based on the voltage V G having its own threshold voltage V TH3 and peak information of the AC signal.

參考第4D圖。第4D圖為畫素電路100操作於工作時段P4的示意圖。在一些實施例中，工作時段P4亦稱為讀取階段。在工作時段P4中，初始控制訊號SINT、重置控制訊號SRST與補償控制訊號SCOMP具有邏輯高電位，讀取控制訊號SREAD具有邏輯低電位。具有邏輯高電位的初始控制訊號SINT、重置控制訊號SRST與補償控制訊號SCOMP將整流開關T1、整流開關T2、補償開關T4與補償開關T5關閉。具有邏輯低電位的讀取控制訊號SREAD將讀取開關T6開啟。 Refer to Figure 4D. FIG. 4D is a schematic diagram of the pixel circuit 100 operating in the working period P4. In some embodiments, the working period P4 is also referred to as the read phase. In the working period P4, the initial control signal S INT , the reset control signal S RST and the compensation control signal S COMP have a logic high potential, and the read control signal S READ has a logic low potential. The initial control signal S INT , the reset control signal S RST and the compensation control signal S COMP with a logic high potential turn off the rectifier switch T1, the rectifier switch T2, the compensation switch T4 and the compensation switch T5. The read control signal S READ with a logic low level turns on the read switch T6.

如第4D圖所示，壓電材料200停止產生交流訊號AC，以及整流開關T1、整流開關T2、補償開關T4與補償開關T5關閉，因此，節點A的電壓VA與節點G的電壓VG大體上沒有變化。 As shown in Fig. 4D, the piezoelectric material 200 stops generating the AC signal AC, and the rectifier switch T1, the rectifier switch T2, the compensation switch T4, and the compensation switch T5 are closed. Therefore, the voltage V A of the node A and the voltage V G of the node G There is basically no change.

如第4D圖所示，讀取開關T6開啟，讀取單元120依據補償訊號VG產生輸出訊號VR。因為補償單元140產生的補償訊號VG具有交流訊號AC的峰值資訊，因此讀取開關T3依據具有交流訊號AC的峰值資訊的補償訊號VG操作，相應地，輸出訊號VR具有交流訊號AC的峰值資訊。 As shown in FIG. 4D, the reading switch T6 is turned on, and the reading unit 120 generates an output signal V R according to the compensation signal V G. Because the compensation signal V G generated by the compensation unit 140 has peak information of the AC signal AC, the reading switch T3 operates according to the compensation signal V G having the peak information of the AC signal AC. Accordingly, the output signal V R has the peak information of the AC signal AC. Peak information.

在一些實施例中，補償訊號VG具有大約為FVDD-|VTH3|-△V的電壓，讀取開關T3依據第一端與控制端的電壓差以及讀取開關T3本身的臨界電壓VTH3進行操作。更確切的來說，讀取開關T3操作在電晶體特性的飽和區，讀取開關T3依據飽和操作電壓FVDD-VG-|VTH3|來操作，其中，將補償訊號VG以FVDD-|VTH3|-△V帶入，飽和操作電壓可得為△V。因此，依據電晶體特性的飽和區，讀取開關T3導通的電流大體上與(△V)^2成正比。 In some embodiments, the compensation signal V G has a voltage of approximately FVDD-|V TH3 |-△V, and the reading switch T3 is performed according to the voltage difference between the first terminal and the control terminal and the threshold voltage V TH3 of the reading switch T3 itself. operating. More precisely, the read switch T3 operates in the saturation region of the transistor characteristic, and the read switch T3 operates according to the saturation operating voltage FVDD-V G -|V TH3 |, where the compensation signal V G is FVDD-| When V TH3 |-△V is brought in, the saturation operating voltage can be obtained as △V. Therefore, according to the saturation region of the transistor characteristic, the current at which the read switch T3 is turned on is roughly proportional to (ΔV)^2.

在一些實施例中，補償電壓VG中具有讀取開關T3臨界電壓VTH3的資訊，使得讀取開關T3導通的電流與本身的臨界電壓VTH3無關。換言之，在讀取開關T3的操作中，補償單元140用以補償讀取開關T3的臨界電壓，使讀取開關T3的操作可獨立於本身的臨界電壓VTH3。因此，當讀取開關T3的臨界電壓VTH3因製程上而有變異時，補償單元140可用以補償此臨界電壓的變異。 In some embodiments, the compensation voltage V G contains information about the threshold voltage V TH3 of the read switch T3, so that the current conducted by the read switch T3 is independent of its threshold voltage V TH3 . In other words, during the operation of the read switch T3, the compensation unit 140 is used to compensate the threshold voltage of the read switch T3, so that the operation of the read switch T3 can be independent of its own threshold voltage V TH3 . Therefore, when the threshold voltage V TH3 of the read switch T3 varies due to the manufacturing process, the compensation unit 140 can be used to compensate the threshold voltage variation.

參考第5圖。第5圖為根據本揭示文件之一些其他的實施例所繪示的畫素電路100的電路示意圖。如第5圖所示，畫素電路100包含讀取單元120、補償單元140以及整流單元160，其中讀取單元120以及整流單元160與第2圖中的讀取單元120以及整流單元160相同。 Refer to Figure 5. FIG. 5 is a schematic circuit diagram of the pixel circuit 100 according to some other embodiments of the present disclosure. As shown in FIG. 5, the pixel circuit 100 includes a reading unit 120, a compensation unit 140, and a rectifying unit 160. The reading unit 120 and the rectifying unit 160 are the same as the reading unit 120 and the rectifying unit 160 in FIG.

第5圖中的補償單元140包含補償開關T4、補償開關T5與補償電容CST。相較於第2圖，第5圖中的補償開關T4的第一端耦接補償開關T5的第一端、讀取開關T3的第二端與讀取開關T6的第二端，以及補償單元T5的控制端用以接收初始控制訊號SINT。在一些實施例中，上述的初始控制訊號SINT與補償控制訊號SCOMP相同。在一些實施例中，第5圖中的畫素電路100的操作與第2圖中的畫素電路100的操作相同。 The compensation unit 140 in FIG. 5 includes a compensation switch T4, a compensation switch T5, and a compensation capacitor C ST . Compared with Figure 2, the first end of the compensation switch T4 in Figure 5 is coupled to the first end of the compensation switch T5, the second end of the read switch T3 and the second end of the read switch T6, and the compensation unit The control terminal of T5 is used to receive the initial control signal S INT . In some embodiments, the aforementioned initial control signal S INT is the same as the compensation control signal S COMP . In some embodiments, the operation of the pixel circuit 100 in Figure 5 is the same as the operation of the pixel circuit 100 in Figure 2.

參考第6A、6B圖。第6A、6B圖為根據本揭示文件之替代的實施例所繪示的畫素電路100的電路示意圖。如第6A、6B圖所示，畫素電路100包含讀取單元120、補償單元140以及整流單元160，其中讀取單元120以及補償單元140與第2圖中的讀取單元120以及補償單元140相同。 Refer to figures 6A and 6B. FIGS. 6A and 6B are schematic circuit diagrams of the pixel circuit 100 according to an alternative embodiment of the present disclosure. As shown in FIGS. 6A and 6B, the pixel circuit 100 includes a reading unit 120, a compensation unit 140, and a rectification unit 160. The reading unit 120 and the compensation unit 140 are the same as the reading unit 120 and the compensation unit 140 in FIG. the same.

第6A圖中的整流單元160包含整流開關T1、整流開關T2與整流器D1。相較於第2圖，第6A圖中的整流開關T2的第一端耦接於整流開關T1的第二端，換言之，整流開關T2的第一端與第二端跨接整流器D1。 The rectifier unit 160 in FIG. 6A includes a rectifier switch T1, a rectifier switch T2, and a rectifier D1. Compared with Figure 2, the first end of the rectifier switch T2 in Figure 6A is coupled to the second end of the rectifier switch T1. In other words, the first and second ends of the rectifier switch T2 are connected across the rectifier D1.

第6B圖中的整流單元160包含整流開關T1、整流開關T2與整流器D1。相較於第2圖，第6B圖中的整流開關 T1的第一端耦接於整流開關T2的第二端，換言之，整流開關T1的第一端與第二端跨接整流器D1。 The rectifier unit 160 in FIG. 6B includes a rectifier switch T1, a rectifier switch T2, and a rectifier D1. Compared to Figure 2, the rectifier switch in Figure 6B The first terminal of T1 is coupled to the second terminal of the rectifier switch T2. In other words, the first terminal and the second terminal of the rectifier switch T1 are connected across the rectifier D1.

一些實施例中，第6A、6B圖中的畫素電路100的操作與第2圖中的畫素電路100的操作相同。 In some embodiments, the operation of the pixel circuit 100 in FIGS. 6A and 6B is the same as the operation of the pixel circuit 100 in FIG. 2.

參考第7圖。第7圖為根據本揭示文件之各種不同的實施例所繪示的畫素電路100的電路示意圖。如第7圖所示，畫素電路100包含讀取單元120、補償單元140以及整流單元160，其中讀取單元120與第2圖中的讀取單元120相同。 Refer to Figure 7. FIG. 7 is a schematic circuit diagram of the pixel circuit 100 according to various embodiments of the present disclosure. As shown in FIG. 7, the pixel circuit 100 includes a reading unit 120, a compensation unit 140, and a rectifying unit 160. The reading unit 120 is the same as the reading unit 120 in FIG.

第7圖中的整流單元160包含整流開關T1、整流開關T2與整流器D1。在一些實施例中，相較於第2圖，整流開關T1的第一端用以接收初始電壓VINT1，以及整流開關T2的第一端用以接收初始電壓VINT2。 The rectifier unit 160 in FIG. 7 includes a rectifier switch T1, a rectifier switch T2, and a rectifier D1. In some embodiments, compared to FIG. 2, the first terminal of the rectifier switch T1 is used to receive the initial voltage V INT1 , and the first terminal of the rectifier switch T2 is used to receive the initial voltage V INT2 .

第7圖中的補償單元140包含補償單元T4、補償單元T5與補償電容CST。在一些實施例中，相較於第2圖，補償單元T4的第二端用以接收初始電壓VINT1。在另一些實施例中，補償單元T4的第二端用以接收初始電壓VINT2。在一些替代的實施例中，補償單元T4的第二端用以接收重置電壓VSRT。 The compensation unit 140 in FIG. 7 includes a compensation unit T4, a compensation unit T5, and a compensation capacitor C ST . In some embodiments, compared to FIG. 2, the second terminal of the compensation unit T4 is used to receive the initial voltage V INT1 . In other embodiments, the second terminal of the compensation unit T4 is used to receive the initial voltage V INT2 . In some alternative embodiments, the second terminal of the compensation unit T4 is used to receive the reset voltage V SRT .

在一些實施例中，上述的初始電壓VINT1、初始電壓VINT2、初始電壓VINT與重置電壓VSRT相互不同。在另一些實施例中，上述的初始電壓VINT1、初始電壓VINT2、初始電壓VINT與重置電壓VSRT相互相同。在各種不同的實施例中，上述的初始電壓VINT1、初始電壓VINT2、初始電壓VINT與重置電壓VSRT至少部分相同。例如，初始電壓VINT1、初 始電壓VINT2與初始電壓VINT相同，但與重置電壓VSRT不同。又或例如，初始電壓VINT1與初始電壓VINT2不同，但初始電壓VINT1與重置電壓VSRT相同。 In some embodiments, the aforementioned initial voltage V INT1 , initial voltage V INT2 , initial voltage V INT and reset voltage V SRT are different from each other. In other embodiments, the aforementioned initial voltage V INT1 , initial voltage V INT2 , initial voltage V INT and reset voltage V SRT are the same as each other. In various embodiments, the aforementioned initial voltage V INT1 , initial voltage V INT2 , initial voltage V INT and reset voltage V SRT are at least partially the same. For example, the initial voltage V INT1 and the initial voltage V INT2 are the same as the initial voltage V INT but different from the reset voltage V SRT . For another example, the initial voltage V INT1 is different from the initial voltage V INT2 , but the initial voltage V INT1 is the same as the reset voltage V SRT .

在一些實施例中，第7圖中的畫素電路100的操作與第2圖中的畫素電路100的操作相同。 In some embodiments, the operation of the pixel circuit 100 in FIG. 7 is the same as the operation of the pixel circuit 100 in FIG. 2.

上述的畫素電路100的配置與操作僅為釋例之用途。各種不同的畫素電路100的配置與操作均在本揭示文件的考量與範疇之內。 The configuration and operation of the pixel circuit 100 described above are for illustrative purposes only. The configurations and operations of various pixel circuits 100 are within the consideration and scope of this disclosure.

雖然本案之實施例已揭露如上，然其並非用以限定本案實施例，任何熟習此技藝者，在不脫離本案實施例之精神和範圍內，當可做些許之更動與潤飾，因此本案實施例之保護範圍當以後附之申請專利範圍所界定為準。 Although the embodiment of this case has been disclosed as above, it is not intended to limit the embodiment of this case. Anyone who is familiar with this technique can make some changes and modifications without departing from the spirit and scope of the embodiment of this case. Therefore, the embodiment of this case The scope of protection shall prevail when the scope of patent application attached hereafter is defined.

T1‧‧‧整流開關 T1‧‧‧Rectifier switch

T2‧‧‧整流開關 T2‧‧‧Rectifier switch

T3‧‧‧補償開關 T3‧‧‧Compensation switch

T4‧‧‧補償開關 T4‧‧‧Compensation switch

T5‧‧‧讀取開關 T5‧‧‧Read switch

T6‧‧‧讀取開關 T6‧‧‧Read switch

D1‧‧‧整流器 D1‧‧‧rectifier

CST‧‧‧補償電容 C ST ‧‧‧Compensation capacitor

A‧‧‧節點 A‧‧‧node

B‧‧‧節點 B‧‧‧node

G‧‧‧節點 G‧‧‧node

VBIAS‧‧‧偏壓電壓 V BIAS ‧‧‧bias voltage

VINT‧‧‧初始電壓 V INT ‧‧‧Initial voltage

VRST‧‧‧重置電壓 V RST ‧‧‧Reset voltage

VR‧‧‧輸出訊號 V R ‧‧‧Output signal

FVDD‧‧‧供應電壓 FVDD‧‧‧Supply voltage

SINT‧‧‧初始控制訊號 S INT ‧‧‧Initial control signal

SRST‧‧‧重置控制訊號 S RST ‧‧‧Reset control signal

SCOMP‧‧‧補償控制訊號 S COMP ‧‧‧Compensation control signal

SREAD‧‧‧讀取控制訊號 S READ ‧‧‧Read control signal

Claims (10)

一種畫素電路，包含：一讀取單元，包含一第一讀取開關；一補償單元，用以補償該第一讀取開關的一臨界電壓變異；以及一整流單元，用以整流一交流訊號，並產生與該交流訊號的一峰值有關的一第一電壓，其中該補償單元更用以依據該第一電壓產生一補償電壓，並將該補償電壓傳輸至該第一讀取開關，以及該讀取單元用以依據該補償電壓輸出一輸出訊號。 A pixel circuit includes: a reading unit including a first reading switch; a compensation unit for compensating for a threshold voltage variation of the first reading switch; and a rectifying unit for rectifying an AC signal , And generate a first voltage related to a peak value of the AC signal, wherein the compensation unit is further used to generate a compensation voltage according to the first voltage, and transmit the compensation voltage to the first read switch, and the The reading unit is used for outputting an output signal according to the compensation voltage. 如請求項1所述的畫素電路，其中該讀取單元更包含：一第二讀取開關包含一第一端、一第二端與一控制端，其中該第一端用以輸出該輸出訊號，以及該控制端用以接收一讀取控制訊號，其中該第一讀取單元包含一第一端、一第二端與一控制端，其中該第一端用以接收一供應電壓，該第二端耦接該第二讀取開關的該第二端，以及該控制端用以接收該補償電壓。 The pixel circuit according to claim 1, wherein the reading unit further comprises: a second reading switch comprises a first terminal, a second terminal and a control terminal, wherein the first terminal is used to output the output Signal, and the control terminal is used to receive a read control signal, wherein the first reading unit includes a first terminal, a second terminal and a control terminal, wherein the first terminal is used to receive a supply voltage, the The second terminal is coupled to the second terminal of the second read switch, and the control terminal is used for receiving the compensation voltage. 如請求項1所述的畫素電路，其中該補償單元包含：一補償電容包含一第一端與一第二端； 一第一補償開關包含一第一端、一第二端與一控制端，其中該補償電容的該第一端用以接收該第一電壓，該補償電容的該第二端耦接該第一補償開關的該第二端，該第一補償開關的該第一端耦接該讀取單元，以及該控制端用以接收一補償控制訊號，其中該第一補償開關用以補償該第一讀取開關的該臨界電壓變異，並用以產生該補償電壓。 The pixel circuit according to claim 1, wherein the compensation unit includes: a compensation capacitor includes a first terminal and a second terminal; A first compensation switch includes a first terminal, a second terminal, and a control terminal. The first terminal of the compensation capacitor is used to receive the first voltage, and the second terminal of the compensation capacitor is coupled to the first terminal. The second end of the compensation switch, the first end of the first compensation switch is coupled to the reading unit, and the control end is used to receive a compensation control signal, wherein the first compensation switch is used to compensate the first reading The threshold voltage variation of the switch is taken and used to generate the compensation voltage. 如請求項3所述的畫素電路，其中該補償單元更包含：一第二補償開關包含一第一端、一第二端與一控制端，其中該第一端耦接該補償電容的該第二端，該第二端用以接收一重置電壓，以及該控制端用以接收一重置控制訊號，其中，該第二補償開關用以依據該重置控制訊號重置該補償電容的該第二端，使該補償電容的該第二端具有該重置電壓。 The pixel circuit according to claim 3, wherein the compensation unit further includes: a second compensation switch includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the compensation capacitor The second end, the second end is used to receive a reset voltage, and the control end is used to receive a reset control signal, wherein the second compensation switch is used to reset the compensation capacitor according to the reset control signal The second terminal enables the second terminal of the compensation capacitor to have the reset voltage. 如請求項3所述的畫素電路，其中該補償單元更包含：一第二補償開關包含一第一端、一第二端與一控制端，其中該第一端耦接該第一補償開關的該第一端，該第二端用以接收一重置電壓，以及該控制端用以接收一重置控制訊號， 其中，該第二補償開關用以，依據該重置控制訊號，通過該第一補償開關重置該補償電容的該第二端，使該補償電容的該第二端具有該重置電壓。 The pixel circuit according to claim 3, wherein the compensation unit further comprises: a second compensation switch includes a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first compensation switch The first terminal, the second terminal for receiving a reset voltage, and the control terminal for receiving a reset control signal, Wherein, the second compensation switch is used for resetting the second end of the compensation capacitor through the first compensation switch according to the reset control signal, so that the second end of the compensation capacitor has the reset voltage. 如請求項1所述的畫素電路，其中該整流單元包含：一整流器包含一第一端與一第二端；以及複數個整流開關，用以依據一初始控制訊號重置該整流器，使該整流器的該第一端與該第二端具有一初始電壓，其中該整流器的該第一端耦接該補償單元，該整流器的該第二端用以接收該交流訊號。 The pixel circuit according to claim 1, wherein the rectifier unit includes: a rectifier including a first terminal and a second terminal; and a plurality of rectifier switches for resetting the rectifier according to an initial control signal to make the rectifier The first terminal and the second terminal of the rectifier have an initial voltage, wherein the first terminal of the rectifier is coupled to the compensation unit, and the second terminal of the rectifier is used for receiving the AC signal. 如請求項6所述的畫素電路，其中該些整流開關包含：一第一整流開關包含一第一端、一第二端與一控制端；以及一第二整流開關包含一第一端、一第二端與一控制端，其中該第一整流開關的該控制端與該第二整流開關的該控制端用以接收該初始控制訊號，該第一整流開關的該第一端與該第二整流開關的該第一端用以接收該初始電壓，該第一整流開關的該第二端耦接該整流器的該第二端，以及該第二整流開關的該第二端耦接該整流器的該第一端。 The pixel circuit according to claim 6, wherein the rectifier switches include: a first rectifier switch includes a first terminal, a second terminal, and a control terminal; and a second rectifier switch includes a first terminal, A second terminal and a control terminal, wherein the control terminal of the first rectifier switch and the control terminal of the second rectifier switch are used to receive the initial control signal, the first terminal of the first rectifier switch and the first terminal The first terminal of the two rectifier switches is used to receive the initial voltage, the second terminal of the first rectifier switch is coupled to the second terminal of the rectifier, and the second terminal of the second rectifier switch is coupled to the rectifier Of the first end. 如請求項6所述的畫素電路，其中該些整流開關包含：一第一整流開關包含一第一端、一第二端與一控制端；以及一第二整流開關包含一第一端、一第二端與一控制端，其中該第一整流開關的該控制端與該第二整流開關的該控制端用以接收該初始控制訊號，該第一整流開關的該第一端用以接收該初始電壓，該第一整流開關的該第二端耦接第二整流開關的該第一端，以及該第二整流開關的該第一端與該第二端跨接該整流器。 The pixel circuit according to claim 6, wherein the rectifier switches include: a first rectifier switch includes a first terminal, a second terminal, and a control terminal; and a second rectifier switch includes a first terminal, A second terminal and a control terminal, wherein the control terminal of the first rectifier switch and the control terminal of the second rectifier switch are used for receiving the initial control signal, and the first terminal of the first rectifier switch is used for receiving For the initial voltage, the second terminal of the first rectifier switch is coupled to the first terminal of the second rectifier switch, and the first terminal and the second terminal of the second rectifier switch are connected across the rectifier. 如請求項1所述的畫素電路，更包含：一壓電材料，耦接該整流單元，用以接收一超音波訊號以產生該交流訊號，以及該壓電材料具有一薄膜形狀。 The pixel circuit according to claim 1, further comprising: a piezoelectric material coupled to the rectifying unit for receiving an ultrasonic signal to generate the AC signal, and the piezoelectric material has a film shape. 如請求項1所述的畫素電路，其中該第一讀取開關為一薄膜電晶體，用以產生該輸出訊號，其中該輸出訊號不包含該臨界電壓變異的一訊息。 The pixel circuit according to claim 1, wherein the first read switch is a thin film transistor for generating the output signal, wherein the output signal does not include a message of the threshold voltage variation.
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