TWI569249B - Pixel circuit - Google Patents

Description

Pixel circuit

The present invention relates to a pixel circuit, and more particularly to a pixel circuit having a dual gate transistor element.

With the gradual development of display technology, the resolution of mobile phone screens has gradually improved from the earliest Video Graphics Array (VGA) or the Video Image Array (QVGA) of video image arrays. 720p. Later, with the rise of industry standards, the resolution of mobile phone screens increased to 1080p. Under the 1080P specification, it has been difficult for users to distinguish pixels with the naked eye. Eventually, with the advancement of display technology, the resolution of mobile phone screens has evolved to a 2K resolution that is completely indistinguishable from pixels.

The higher the resolution, the smaller the pixel area must be in the same screen size. However, in the current technology, the pixel circuit must have a plurality of thin film transistors (TFTs) in order to properly drive the pixel illumination or compensate the luminance of the pixels. Therefore, among the areas planned for a single pixel, the pixel circuit is bound to take up part of the area, and the area that can be used in the light-emitting area of the pixel is reduced. In other words, when the number of components of the pixel circuit is reduced or the area occupied by the pixel circuit is reduced, the overall area of the pixel can be effectively reduced. But so far, the pixel area of the industry is still unable to fall further because the pixel circuit needs to occupy a certain area.

The present invention provides a pixel circuit to overcome the problem that the pixel area of the current industry is still unable to be further lowered due to the fact that the pixel circuit needs to occupy a certain area.

A pixel circuit disclosed in the present invention includes a first transistor, a second transistor, a first capacitor, a writing unit, and a light emitting diode element. The first end of the first transistor is configured to receive the first voltage. The second end of the first transistor is coupled to the first node. The first control end of the first transistor is coupled to the second node. The second control end of the first transistor is configured to receive the first control signal. The first transistor is selectively turned on according to the voltage level of the second node and the voltage level of the first control signal. The first end of the second transistor is configured to receive a data signal. The second end of the second transistor is coupled to the second node. The control end of the second transistor is configured to receive the second control signal. The two ends of the first capacitor are respectively coupled to the first node and the second node. The writing unit is coupled to the first node. The writing unit is configured to adjust the voltage level of the first node according to the first reference voltage. One end of the LED component is coupled to the first node, and the other end is coupled to the second voltage.

In summary, the present invention provides a pixel circuit, wherein a first transistor in a pixel circuit has a first control end and a second control end, and the first transistor is controlled via the first control end and the second control end. The voltage level of the second node and the first control signal. The pixel circuit can realize complex timing control by using fewer components, thereby appropriately driving the light-emitting two-element component to emit light or compensating for the light-emitting luminance of the light-emitting diode component while reducing the number of components.

The above description of the disclosure and the following description of the embodiments of the present invention are intended to illustrate and explain the spirit and principles of the invention, and to provide further explanation of the scope of the invention.

The detailed features and advantages of the present invention are set forth in the Detailed Description of the Detailed Description of the <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> <RTIgt; The objects and advantages associated with the present invention can be readily understood by those skilled in the art. The following examples are intended to describe the present invention in further detail, but are not intended to limit the scope of the invention.

Please refer to FIG. 1. FIG. 1 is a schematic circuit diagram of a pixel circuit according to an embodiment of the invention. As shown in FIG. 1, the pixel circuit 1 has a first transistor T1, a second transistor T2, a first capacitor C1, a writing unit 12, and a light emitting diode element D.

The first end of the first transistor T1 is configured to receive the first voltage V1. The second end of the first transistor T1 is coupled to the first node N1. The first control end of the first transistor T1 is coupled to the second node N2. The second control end of the first transistor T1 is configured to receive the first control signal VC1. The first transistor T1 is selectively turned on according to the voltage level of the second node N2 and the voltage level of the first control signal VC1. In an embodiment, the first transistor T1 is, for example, a dual gate transistor or a multi-gate transistor, and the first voltage V1 is, for example, a relatively high voltage level in the system, but neither of them is used. Limited.

The first end of the second transistor T2 is configured to receive the data signal Vdata. The second end of the second transistor T2 is coupled to the second node N2. The control end of the second transistor T2 is configured to receive the second control signal VC2. In this embodiment, the two ends of the first capacitor C1 are respectively coupled to the first node N1 and the second node N2. The second transistor T2 is, for example, a thin film transistor (TFT), but is not limited thereto. In this embodiment, the second transistor T2 is an N-type doped thin film transistor, but in other embodiments, the second transistor T2 is also used in conjunction with adjusting the relative level of other signals. It can be a P-type doped film transistor.

The writing unit 12 is coupled to the first node N1. The writing unit 12 is configured to adjust the voltage level of the first node N1 according to the first reference voltage Vref1. In this embodiment, the write unit 12 is, for example, a second capacitor C2. One end of the second capacitor C2 is coupled to the first node N1, and the other end of the second capacitor C2 is configured to receive the first reference voltage Vref1. In other embodiments, the write unit 12 may be an element other than a capacitor or a related circuit composed of a plurality of elements, and is not limited by the examples.

One end of the LED component D is coupled to the first node N1, and the other end is coupled to the second voltage V2. The light emitting diode element D is, for example, an organic light emitting diode (OLED) element, but is not limited thereto. The second voltage V2 is, for example, a relatively low voltage level in the system, but is not limited thereto.

Please refer to FIG. 2 to illustrate the operation mode of the pixel circuit 1. FIG. 2 is a timing diagram of the related signals illustrated by the pixel circuit of FIG. 1 according to the present invention. A precharge phase P1, a compensation phase P2, a write phase P3, and an illumination phase P4 are defined in the timing diagram. The pre-charging phase P1 precedes the compensation phase P2, the compensation phase P2 precedes the writing phase P3, and the writing phase P3 precedes the lighting phase P4.

In the pre-charging phase P1, the first control signal VC1 is a relatively high voltage level, the second control signal VC2 is a relatively high voltage level, the first reference voltage Vref1 is a relative high voltage level, and the data signal Vdata is The voltage level is a compensation voltage value Vofs. At this time, the first transistor T1 may be turned on or off, and the second transistor T2 is turned on. The voltage level VN1 of the first node N1 can be expressed as Equation (1): Formula 1)

In the compensation phase P2, the first control signal VC1 is a relatively high voltage level, the second control signal VC2 is a relatively high voltage level, the first reference voltage Vref1 is a relatively low voltage level, and the data signal Vdata has a compensation. Voltage value Vofs. At this time, the first transistor T1 is turned on, and the second transistor T2 is turned on. The voltage level of the first node N1 and the voltage level of the second node N2 can be expressed as Equations (2) and (3). Among them, in the formula (3) It is the turn-on threshold voltage of the first transistor T1. At this time, the first reference voltage Vref1 is a relatively low voltage level to ensure that the voltage level of the second node N2 is written to the desired voltage level. Formula (2) Formula (3)

In the writing phase P3, the first control signal VC1 is a relatively low voltage level, the second control signal VC2 is a relatively high voltage level, the first reference voltage Vref1 is a relatively low voltage level, and the data signal Vdata has Signal voltage value Vsig. At this time, the first transistor T1 is not turned on, and the second transistor T2 is turned on. The voltage level of the first node N1 and the voltage level of the second node N2 can be expressed as Equations (4) and (5). Wherein, a in the formula (5) is a voltage division ratio formed by the first capacitor C1 and the second capacitor C2. If the capacitance value of the first capacitor C1 is briefly represented by the reference numeral C1, and the capacitance value of the second capacitor C2 is represented by the reference numeral C2, the voltage division ratio a can be expressed as Equation (6). At this time, the signal voltage value Vsig of the data signal Vdata is written into the first node N1, and the signal voltage value Vsig of the data signal Vdata is divided by the capacitive coupling effect of the first capacitor C1 and the first capacitor C1 and the second capacitor C2. The voltage level of the second node N2 is further affected. In this embodiment, the signal voltage value Vsig is higher than the compensation voltage value Vofs, but in practice, the compensation voltage value Vofs may also be higher than the signal voltage value Vsig and is not limited by the embodiment. Formula (4) Formula (5) Formula (6)

In the illuminating phase P4, the first control signal VC1 is a relatively high voltage level, the second control signal VC2 is a relatively low voltage level, the first reference voltage Vref1 is a relatively high voltage level, and the data signal Vdata is compensated. Voltage value Vofs. At this time, the first transistor T1 is turned on, and the second transistor T2 is not turned on. The voltage levels of the first node N1 and the second node N2 can be expressed as in Equations (7) and (8). Wherein, in the formula (7) and the formula (8) It is the turn-on voltage of the light-emitting diode element D. At this time, the light-emitting diode element D is turned on, and the light-emitting diode element D emits light correspondingly according to the current ID supplied from the first transistor T1. The current ID can be expressed as in the formula (9-1). The parameter k of the current ID can be expressed as in the formula (9-2). Where in formula (9-2) For carrier mobility, The unit capacitance of the gate oxide layer, It is the ratio of the gate width of the gold oxide half field effect transistor to the gate length. Formula (7) Formula (8) Equation (9-1) Equation (9-2)

Through the first control end and the second control end of the first transistor T1, relatively complicated timing control of the first transistor T1 is performed. Therefore, in this embodiment, the transistor in the pixel circuit 1 can be reduced to only the first transistor T1 and the second transistor T2, and a relatively simple two transistor 2 capacitor (2T2C) can be formed. The structure, thereby reducing the area occupied by the pixel circuit 1. On the other hand, in the case where the respective control signals are appropriately adjusted, the current ID provided by the first transistor T1 is stabilized by the current which can be supplied by the general thin film transistor, and the light-emitting diode element D is correspondingly improved. Luminous stability.

Please refer to FIG. 3. FIG. 3 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present invention. In contrast to the embodiment shown in Fig. 1, the pixel circuit 1' of Fig. 3 further has a third transistor T3' and a fourth transistor T4'. Further, in the embodiment shown in Fig. 3, the writing unit 12' of the pixel circuit 1' is the fifth transistor T5'.

In more detail, the first end of the third transistor T3' is coupled to the second node N2'. The second end of the third transistor T3' is coupled to the third node N3'. The control terminal of the third transistor T3' is for receiving the third control signal VC3'. Both ends of the first capacitor C1' are coupled to the first node N1' and the third node N3', respectively. The first end of the fourth transistor T4' is coupled to the third node N3'. The second end of the fourth transistor T4' is for receiving the second reference voltage Vref2'. The control terminal of the fourth transistor T4' is for receiving the second control signal VC2'. The first end of the fifth transistor T5' is coupled to the first node N1'. The second end of the fifth transistor T5' is for receiving the first reference voltage Vref1'. The control terminal of the fifth transistor T5' is for receiving the fourth control signal VC4'. The third transistor T3', the fourth transistor T4' and the fifth transistor T5' are, for example, thin film transistors, but are not limited thereto. The third transistor T3', the fourth transistor T4' and the fifth transistor T5' are N-type doped thin film transistors, but in other embodiments, the relative level of other signals is adjusted. Next, the third transistor T3', the fourth transistor T4', and the fifth transistor T5' may also be P-type doped thin film transistors.

Since the circuit architecture of the embodiment shown in FIG. 4 is different from the embodiment shown in FIG. 3, the timing of the control of the signal is also different. Please refer to FIG. 4 to illustrate the timing of the operation of the pixel circuit 1'. FIG. 4 is a timing diagram of the related signals shown in the pixel circuit of FIG. A precharge phase P1', a compensation phase P2' and an illumination phase P3' are illustrated in FIG. Here, the precharge phase P1' precedes the compensation phase P2', and the compensation phase P2' precedes the illumination phase P3'.

In the pre-charging phase P1', the first control signal VC1' and the third control signal VC3' are at a relative low voltage level, and the second control signal VC2' and the fourth control signal VC4' are at a relatively high voltage level. The second transistor T2', the fourth transistor T4' and the fifth transistor T5' are turned on, and the first transistor T1' and the third transistor T3' are not turned on. The voltage level of the first node N1', the voltage level of the second node N2', and the voltage level of the third node N3' can be expressed as Equations (10), (11), and (12). among them, Is the voltage level of the first node N1', Is the voltage level of the second node N2', It is the voltage level of the third node N3'. Formula (10) Formula (11) Formula (12)

In the compensation phase P2', the third control signal and the fourth control signal are at a low voltage level, and the first control signal and the second control signal are at a high voltage level. The first transistor T1', the second transistor T2' and the fourth transistor T4' are turned on, and the third transistor T3' and the fifth transistor T5' are not turned on. The voltage level of the first node N1', the voltage level of the second node N2', and the voltage level of the third node N3' can be expressed as Equations (13), (14), and (15). among them, It is the turn-on threshold voltage of the first transistor T1'. Formula (13) Formula (14) Formula (15)

In the illuminating phase P3', the second control signal VC2' and the fourth control signal VC4' are at a low voltage level, and the first control signal VC1' and the third control signal VC3' are at a high voltage level. The first transistor T1' and the third transistor T3' are turned on, and the second transistor T2', the fourth transistor T4' and the fifth transistor T5' are not turned on. The voltage level of the first node N1' and the voltage level of the second node N2' can be expressed as in equations (16) and (17). At this time, the light-emitting diode element D' emits light correspondingly according to the current ID' supplied from the first transistor T1'. Among them, the current ID' can be expressed as in the formula (18-1). Current ID' parameter Then, it can be expressed as the formula (18-2). Wherein, in the formula (18-2), For carrier mobility, The unit capacitance of the gate oxide layer, It is the ratio of the gate width of the gold oxide half field effect transistor to the gate length. Formula (16) Formula (17) Equation (18-1) Equation (18-2)

In summary, the present invention provides a pixel circuit, wherein a first transistor in a pixel circuit has a first control end and a second control end, and the first transistor is controlled via the first control end and the second control end. The voltage level of the second node and the first control signal. By the circuit structure formed by the first transistor and other components, the pixel circuit can realize complex timing control with fewer components, and the output current of the first transistor is less susceptible to noise. Therefore, in the case of reducing the number of components, the light-emitting two-body element is appropriately driven to emit light or compensates for the light-emitting luminance of the light-emitting diode element, and the overall area of the pixel unit is also reduced.

Although the present invention has been disclosed above in the foregoing embodiments, it is not intended to limit the invention. It is within the scope of the invention to be modified and modified without departing from the spirit and scope of the invention. Please refer to the attached patent application for the scope of protection defined by the present invention.

1, 1'‧‧‧ pixel circuit
12, 12'‧‧‧ write unit
C1, C1'‧‧‧ first capacitor
C2‧‧‧second capacitor
D, D'‧‧‧Lighting diode components
N1, N1'‧‧‧ first node
N2, N2'‧‧‧ second node
N3'‧‧‧ third node
P1, P1'‧‧‧ precharge stage
P2, P2'‧‧‧ Compensation phase
P3‧‧‧writing stage
P4, P3'‧‧‧Lighting stage
T1, T1'‧‧‧ first transistor
T2, T2'‧‧‧second transistor
T3'‧‧‧ third transistor
T4'‧‧‧ fourth transistor
T5'‧‧‧ fifth transistor
V1, V1'‧‧‧ first voltage
V2, V2'‧‧‧ second voltage
VC1, VC1'‧‧‧ first control signal
VC2, VC2'‧‧‧ second control signal
VC3'‧‧‧ third control signal
VC'4‧‧‧ fourth control signal
Vdata, Vdata'‧‧‧ data signal
Vofs‧‧‧compensation voltage value
Vref1, Vref1'‧‧‧ first reference voltage
Vref2'‧‧‧second reference voltage
Vsig‧‧‧ signal voltage value

1 is a circuit diagram of a pixel circuit according to an embodiment of the invention. FIG. 2 is a timing diagram of related signals illustrated by the pixel circuit of FIG. 1 according to the present invention. 3 is a circuit diagram of a pixel circuit according to another embodiment of the present invention. 4 is a timing diagram showing related signals of the pixel circuit of FIG. 3 according to the present invention.

1‧‧‧ pixel circuit

12‧‧‧Write unit

C1‧‧‧first capacitor

C2‧‧‧second capacitor

D‧‧‧Lighting diode components

N1‧‧‧ first node

N2‧‧‧ second node

T1‧‧‧first transistor

T2‧‧‧second transistor

V1‧‧‧ first voltage

V2‧‧‧second voltage

VC1‧‧‧ first control signal

VC2‧‧‧ second control signal

Vdata‧‧‧Information Signal

Vref1‧‧‧ first reference voltage

Claims (10)

A pixel circuit includes: a first transistor, a first end of the first transistor is configured to receive a first voltage, and a second end of the first transistor is coupled to a first node, the first a first control end of the first transistor is coupled to a second node, and a second control end of the first transistor is configured to receive a first control signal, wherein the first transistor is in accordance with a voltage level of the second node The voltage level of the first control signal is selectively turned on; a second transistor, the first end of the second transistor is configured to receive a data signal, and the second end of the second transistor is coupled to the second a node, the control end of the second transistor is configured to receive a second control signal; a first capacitor, the two ends of the first capacitor are respectively coupled to the first node and the second node; The writing unit is coupled to the first node, the writing unit is configured to adjust a voltage level of the first node according to a first reference voltage; and a light emitting diode component, one end of the LED component is coupled The first node is coupled to a second voltage at the other end; wherein the write As a second capacitor, one end of the second capacitor is coupled to the first node, the other end of the second capacitor for receiving the first reference voltage. The pixel circuit of claim 1, wherein the first control signal, the second control signal, and the first reference voltage are at a high voltage level, and the voltage level of the data signal is one. Compensating for the voltage value, the second transistor is turned on. The pixel circuit of claim 2, wherein in the compensation phase after the pre-charging phase, the first control signal and the second control signal are at a high voltage level, and the first reference voltage is a low voltage level The voltage level of the data signal is the compensation voltage value, and the first transistor and the second transistor are turned on. The pixel circuit of claim 3, wherein in the writing phase after the compensation phase, the second control signal is a high voltage level, and the first control signal and the first reference voltage are low voltage standards Bit, the voltage level of the data signal is a signal voltage value, the first transistor is not turned on, and the second transistor is turned on. The pixel circuit of claim 4, wherein the signal voltage value is higher than the compensation voltage value. The pixel circuit of claim 4, wherein in the illuminating phase after the writing phase, the first control signal and the first reference voltage are at a high voltage level, and the second control signal is a low voltage level In position, the first transistor is turned on, and the second transistor is not turned on. A pixel circuit includes: a first transistor, a first end of the first transistor is configured to receive a first voltage, and a second end of the first transistor is coupled to a first node, the first a first control end of the first transistor is coupled to a second node, and a second control end of the first transistor is configured to receive a first control signal, wherein the first transistor is in accordance with a voltage level of the second node The voltage level of the first control signal is selectively turned on; a second transistor, the first end of the second transistor is configured to receive a data signal, and the second end of the second transistor is coupled to the second a node, the control end of the second transistor is configured to receive a second control signal; a first capacitor, the two ends of the first capacitor are respectively coupled to the first node and the second node; a write unit, the write unit is coupled to the first node, and the write unit is used according to a first a reference voltage is used to adjust a voltage level of the first node; a light emitting diode element having one end coupled to the first node and the other end coupled to a second voltage; a third transistor The first end of the third transistor is coupled to the second node, the second end of the third transistor is coupled to a third node, and the control end of the third transistor is configured to receive a third control signal. The first ends of the first capacitor are respectively coupled to the first node and the third node; and a fourth transistor, the first end of the fourth transistor is coupled to the third node, and the second transistor is second The terminal is configured to receive a second reference voltage, and the control end of the fourth transistor is configured to receive the second control signal; wherein the writing unit is a fifth transistor, and the first end of the fifth transistor is coupled Connected to the first node, the second end of the fifth transistor is configured to receive the first reference voltage, Fifth electrical control terminal for receiving a crystal of the fourth control signal. The pixel circuit of claim 7, wherein in the pre-charging stage, the first control signal and the third control signal are at a low voltage level, and the second control signal and the fourth control signal are at a high voltage level The second transistor, the fourth transistor and the fifth transistor are turned on, and the first transistor and the third transistor are not conductive. The pixel circuit of claim 8, wherein the third control signal and the fourth control signal are at a low voltage level in a compensation phase after the pre-charging phase, the first control The signal and the second control signal are at a high voltage level, and the first transistor, the second transistor and the fourth transistor are turned on, and the third transistor and the fifth transistor are non-conductive. The pixel circuit of claim 9, wherein the second control signal and the fourth control signal are at a low voltage level, the first control signal and the third control in an illumination phase after the compensation phase The signal is at a high voltage level, the first transistor and the third transistor are turned on, and the second transistor, the fourth transistor and the fifth transistor are not turned on.