TW201329939A - Pixel circuits - Google Patents

Abstract

A pixel circuit is provided. The pixel circuit comprises a switch transistor, a driving transistor, and a first diode. The switch transistor has a first gate terminal for receiving a scan signal, a first electrode terminal for receiving a data signal, and a second electrode terminal. The driving transistor has a first gate terminal coupled to the second electrode terminal of the switch transistor, a second gate terminal, a first electrode terminal coupled to a first voltage source, and a second electrode terminal. The second gate terminal of the driving transistor is coupled to a second voltage source through the first diode. The voltage provided by the second voltage source is lower than the voltage provided by the first voltage source.

Description

Pixel circuit

The present invention relates to a pixel circuit, and more particularly to a pixel circuit using a dual gate transistor for improving image uniformity.

Fig. 1 is a diagram showing a pixel circuit of a conventional organic light emitting display. Referring to FIG. 1, the pixel circuit 1 includes a switching transistor 10, a driving transistor 11, a capacitor 12, and a light emitting diode 13. The switching transistor 10 is controlled by a scan signal SS10 and receives a data signal DS10. When the switching transistor 10 is turned on according to the scanning signal SS10, the driving transistor 11 generates a driving current I10 according to the data signal DS10 to drive the light-emitting diode 13 to emit light. The threshold voltage (Vth) of the driving transistor 11 changes with the operation time, which causes an image mura phenomenon to occur in the display.

The invention provides a pixel circuit comprising a switching transistor, a driving transistor, and a first diode. The switching transistor has a first gate terminal) receiving a scan signal, a first electrode terminal receiving a data signal, and a second electrode terminal. The driving transistor has a first gate terminal electrically connected to the second electrode end of the switching transistor, a second gate terminal, a first electrode terminal electrically connected to a first voltage source, and a second electrode terminal. The second gate of the driving transistor is electrically connected to a second voltage source through the first diode. The second voltage source provides a voltage that is lower than the voltage provided by the first voltage source.

In some embodiments, the switching transistor further includes a second gate terminal. The second gate terminal of the switching transistor is electrically connected to the second voltage source through the first diode.

In other embodiments, the pixel circuit further includes a second diode, and the switching transistor further includes a second gate terminal. The second gate terminal of the switching transistor is electrically connected to the second voltage source through the second diode.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 2 is a diagram showing a pixel circuit in accordance with an embodiment of the present invention. Referring to FIG. 2, the pixel circuit 2 is applied to an organic light emitting display panel, and includes a switching transistor 20, a driving transistor 21, a capacitor 22, and a diode 23. In this embodiment, both the switching transistor 20 and the driving transistor 21 are implemented as a double gate transistor. As shown in FIG. 2, the switching transistor 20 has an upper gate terminal B20, a lower gate terminal G20, and two electrode terminals D20 and S20. In this embodiment, the two electrode terminals D20 and S20 of the switching transistor 20 are the 汲 extreme and the source terminal, respectively. The driving transistor 21 has an upper gate terminal B21, a lower gate terminal G21, and two electrode terminals D21 and S21. In this embodiment, the two electrode terminals D21 and S21 of the driving transistor 21 are the 汲 terminal and the source terminal, respectively.

The gate terminal G20 of the switching transistor 20 receives a scan signal SS20, the drain terminal D20 receives a data signal DS20, and its source terminal S20 is electrically coupled to a node N20. The gate terminal G21 of the driving transistor 21 is electrically connected to the node N20, the 汲 terminal D21 is electrically connected to the voltage source VDD, and the source S21 terminal thereof is electrically connected to the anode terminal of the diode 23. The capacitor 22 is electrically connected between the gate terminal G21 and the source terminal S21 below the driving transistor 21. In the embodiment of FIG. 2, the gate terminal B20 above the switching transistor 20 and the gate terminal B21 above the switching transistor 21 are electrically connected to the voltage source VSS through the diode 23. In detail, the anode terminal of the diode 23 is electrically connected to the gate terminal B20 above the switching transistor 20 and the gate terminal B21 above the driving transistor 21, and the cathode terminal of the diode 23 is electrically connected to the voltage source VSS. In this embodiment, the voltage source VSS provides a voltage that is lower than the voltage provided by the voltage source VDD.

In the embodiment of Fig. 2, the source terminal S20 of the switching transistor 20 and the gate terminal G21 below the driving transistor 21 are connected in common to the node N20. In other embodiments, depending on the driving path of the data signal DS22 to the driving transistor 21, at least one component, such as a capacitor and a switch, may be disposed between the source terminal S20 of the switching transistor 20 and the gate terminal G21 of the driving transistor 21. The source terminal S20 of the switching transistor 20 and the gate terminal G21 below the driving transistor 21 are electrically connected to each other.

In another embodiment, the drive transistor 21 is implemented as a dual gate transistor and the switch transistor 20 is implemented as a single gate transistor. In this example, only the gate terminal B21 above the driving transistor 21 is electrically connected to the voltage source VSS through the diode 23.

Referring to FIG. 2, when the switching transistor 20 is turned on according to the scanning signal SS20, the data signal DS20 is transmitted to the node N20. The driving transistor 21 supplies a driving current I20 according to the voltage on the node N20 to drive the diode 23 to emit light.

Figure 3 is a graph showing the relationship between the gate current and the gate voltage of a single gate transistor. Figure 4 is a graph showing the relationship between the gate current and the gate voltage of a double gate transistor. Referring to Fig. 3, curve 30 shows the gate current (Id) and gate (Vg) voltage of the single gate transistor at the time T0 when the gate-source voltage is greater than zero (Vgs>0). Relationship diagram; curve 31 is a graph showing the relationship between the gate current and the gate voltage at the time T1 when the gate-source voltage is greater than zero (Vgs>0) in a single gate transistor, wherein Time T1 is later than T0. According to Fig. 3, as the usage time increases, the threshold voltage of the single gate transistor is positively shifted. Referring to Fig. 4, curve 40 is a graph showing the relationship between the drain current and the lower gate voltage at the time T0 when the upper gate-source voltage is less than or equal to zero (Vbs ≦ 0) in the double gate transistor. Curve 41 is a graph showing the relationship between the drain current and the lower gate voltage during the use time T1 when the upper gate-source voltage is less than or equal to zero (Vbs ≦ 0). According to Fig. 4, as the usage time increases, the threshold voltage of the double gate transistor is positively shifted. According to Figure 3-4, as the usage time increases, the threshold voltage forward offset of the double gate transistor is less than the threshold voltage forward offset of the single gate transistor.

According to the embodiment of Fig. 2, the gate terminal B21 and the source terminal S21 above the driving transistor 21 are electrically connected to each other. Therefore, the gate-source voltage (Vbs) above the driving transistor 21 is equal to zero. In addition, the gate-source voltage (Vbs) above the switching transistor 20 is less than zero. According to the characteristics of the double gate transistor, when the pixel circuit 2 is used for a long time, the offset of the threshold voltage can be reduced, thereby improving the image uniformity.

Fig. 5 is a cross-sectional view showing the structure of the driving transistor 21 and the light-emitting diode 23 in the pixel circuit 2. Referring to FIG. 5, the pixel circuit 2 includes a substrate 500, conductive layers 501, 505-506, 508-509, and 511, insulating layers 502, 504, 509, active layer 503, insulating layer 504, protective layer 507, and organic Layer 510. The conductive layer 501 is disposed on the substrate 500 and serves as the gate terminal G21 below the driving transistor 21. The insulating layer 502 is disposed on the substrate 500 and covers the conductive layer 501. The active layer 503 is disposed on the insulating layer 502 and above the conductive layer 501. In this embodiment, the active layer 503 may include indium gallium zinc oxide (InGaZnO4, IGZO). The insulating layer 504 is disposed on the insulating layer 502 and covers the active layer 503. Referring to Figure 5, the insulating layer 504 has two openings 512 and 513 to expose portions of the active layer 503. The conductive layer 505 is disposed on the insulating layer 504 and extends into the opening 512 to connect the active layer 503. The conductive layer 505 serves as the source terminal S21 of the driving transistor 21. The conductive layer 506 is disposed on the insulating layer 504 and extends into the opening 513 to connect the active layer 503. The conductive layer 506 serves as the drain terminal D21 of the driving transistor 21.

The protective layer 507 is disposed on the insulating layer 504 and covers the conductive layers 505 and 506. The protective layer 504 has an opening 514 to expose the conductive layer 505. Conductive layer 508 is disposed on protective layer 507 and has two portions 508A and 508B. A portion 508A of conductive layer 508 extends into opening 514 to connect conductive layer 505. Another portion 508B of conductive layer 508 is over active layer 503 and serves as gate terminal B21 above drive transistor 21. The insulating layer 509 is disposed on the conductive layer 508 and has an opening 515 to expose a portion 508A of the conductive layer 508. The organic layer 510 is disposed on the insulating layer 509 and extends into the opening 515 to connect a portion 508A of the conductive layer 508. In this embodiment, the organic layer 510 includes an organic material. The conductive layer 511 is disposed on the base layer of the organic layer 510.

Referring to FIG. 5, conductive layers 501, 505, 506, and 508 form a driving transistor 21, and a portion 508A of the conductive layer 508, the organic layer 510, and the conductive layer 511 form a diode 23.

Figure 6 is a diagram showing a pixel circuit in accordance with another embodiment of the present invention. Referring to FIG. 6, the pixel circuit 6 is applied to an organic light emitting display panel, and includes a switching transistor 60, a driving transistor 61, a capacitor 62, a light emitting diode 63, and a diode 64. In this embodiment, both the switching transistor 60 and the driving transistor 61 are implemented as a double gate transistor. As shown in Fig. 6, the switching transistor 60 has an upper gate terminal B60, a lower gate terminal G60, and two electrode terminals D60 and S60. In this embodiment, the two electrode terminals D60 and S60 of the switching transistor 60 are the 汲 extreme and the source terminal, respectively. The driving transistor 61 has an upper gate terminal B61, a lower gate terminal G61, and two electrode terminals D61 and S61. In this embodiment, the two electrode terminals D61 and S61 of the driving transistor 61 are the 汲 terminal and the source terminal, respectively.

The lower gate G60 of the switching transistor 60 receives a scan signal SS60, the drain terminal D60 receives a data signal DS60, and its source terminal S60 is electrically coupled to a node N60. The lower gate G61 of the driving transistor 61 is electrically connected to the node N60, the 汲 terminal D61 is electrically connected to the voltage source VDD, and the source S61 terminal is electrically connected to the anode terminal of the illuminating diode 63. The capacitor 62 is electrically connected between the gate terminal G61 and the source terminal S61 below the switching transistor 62. The cathode terminal of the light-emitting diode 63 is electrically connected to the voltage source VSS. In the embodiment of FIG. 6, the upper gate B60 of the switching transistor 60 and the upper gate B61 of the driving transistor 61 are electrically connected to the voltage source VSS through the diode 64. In detail, the anode terminal of the diode 64 is electrically connected to the gate terminal B60 above the switching transistor 60 and the gate terminal B61 above the driving transistor 61, and the cathode terminal of the diode 64 is electrically connected to the voltage source VSS. In this embodiment, the voltage source VSS provides a voltage that is lower than the voltage provided by the voltage source VDD.

In another embodiment, the drive transistor 61 is implemented as a dual gate transistor and the switch transistor 60 is implemented as a single gate transistor. In this example, only the upper gate B61 of the driving transistor 61 is electrically connected to the voltage source VSS through the diode 64.

Referring to Fig. 6, when the switching transistor 60 is turned on in accordance with the scanning signal SS60, the data signal DS60 is transmitted to the node N60. The driving transistor 21 supplies a driving current I60 according to the voltage on the node N60 to drive the light-emitting diode 63 to emit light.

According to the embodiment of Fig. 6, the anode terminal of the diode 64 is electrically connected to the gate terminal B60 above the switching transistor 60 and the gate terminal B61 above the driving transistor 61. Since the gate terminal B60 above the switching transistor 60 and the gate terminal B61 above the driving transistor 61 do not additionally apply a voltage source, the diode 64 and the switching transistor 60 and the driving transistor 61 do not form a current path, and therefore, there is no current. It flows through the diode 64, and the diode 64 does not emit light. The voltage at the anode terminal of diode 64 will eventually be close to or equal to the voltage provided by voltage source VSS. From this, it can be known that the gate-source voltage (Vbs) above the driving transistor 61 and the gate-source voltage (Vbs) above the switching transistor 60 are less than or equal to zero. According to the characteristics of the double gate transistor shown in Figs. 3-4, when the pixel circuit 6 is used for a long time, the offset of the threshold voltage can be reduced, thereby improving the image uniformity.

Fig. 7A is a cross-sectional view showing the structure of the switching transistor 60, the driving transistor 61, the light-emitting diode 63, and the diode 64 in the pixel circuit 6. Referring to FIG. 7, the pixel circuit 6 includes a substrate 700, conductive layers 701-702, 707-710, 712, and 715, insulating layers 703, 706, and 713, active layers 704-705, a protective layer 711, and an organic layer. 714. The conductive layer 701 is disposed on the substrate 700 and serves as the gate terminal G61 of the driving transistor 61. The conductive layer 702 is disposed on the substrate 700 and serves as a gate terminal of the switching transistor 60. G60. The insulating layer 703 is disposed on the substrate 700 and covers the conductive layers 701 and 702. The active layer 704 is disposed on the insulating layer 703 and above the conductive layer 701. The active layer 705 is disposed on the insulating layer 703 and above the conductive layer 707. In this embodiment, the active layers 704 and 705 may include indium gallium zinc oxide (InGaZnO4, IGZO). The insulating layer 706 is disposed on the insulating layer 703 and covers the active layers 704 and 705. The insulating layer 706 has openings 716 and 717 to expose portions of the active layer 704. And an active layer 705 having openings 718 and 719 to expose portions.

The conductive layer 707 is disposed on the insulating layer 706 and extends into the opening 707 to connect the active layer 704, wherein the conductive layer 707 serves as the source terminal S61 of the driving transistor 61. The conductive layer 708 is disposed on the insulating layer 706 and extends into the opening 717 to connect the active layer 704, wherein the conductive layer 708 serves as the drain terminal D61 of the driving transistor 61. The conductive layer 709 is disposed on the insulating layer 706 and extends into the opening 718 to connect the active layer 705. The conductive layer 709 serves as the source terminal S60 of the switching transistor 60, and the conductive layer 701 is electrically connected. The conductive layer 710 is disposed on the insulating layer 706 and extends into the opening 719 to connect the active layer 705, wherein the conductive layer 710 serves as the drain D60 of the switching transistor 60. The protective layer 711 is disposed on the insulating layer 706 and covers the conductive layers 708-710. The protective layer 711 has an opening 720 to expose the conductive layer 707. The conductive layer 712 is disposed on the protective layer 711 and has four portions 712A, 712B, 712C, and 712D. Portion 712A of conductive layer 712 separates other portions 712B-712D, i.e., one portion 712A of conductive layer 712 is not connected to other portions 712B-712D. A portion 712A of conductive layer 712 extends into opening 720 to connect conductive layer 707. A portion 712B of the conductive layer 712 is over the active layer 704 and acts as a gate terminal B61 above the drive transistor 61. Another portion 712D of conductive layer 712 is over active layer 705 and acts as gate terminal B60 above switching transistor 60.

The insulating layer 713 is disposed on the conductive layer 712 and has an opening 721 to expose the first portion 712A of the conductive layer 712 and an opening 722A to expose a portion 712C of the conductive layer 712. A portion 712B of conductive layer 712 is located between the two portions 712A and 712C. The organic layer 714 is disposed on the insulating layer 713 and extends into the opening 721 to connect a portion 712A of the conductive layer 712 and extend into the opening 722A to connect a portion 712C of the conductive layer 712. In this embodiment, the organic layer 714 includes an organic material. The conductive layer 715 is disposed on the organic layer 714. A portion 712C of the conductive layer 712, the organic layer 714, and the conductive layer 715 form a diode 64. One portion 712A of the conductive layer 712, the organic layer 714, and the conductive layer 715 form a light-emitting diode 63.

In FIG. 7A, the opening 722A of the insulating layer 713 exposes a portion 712C of the conductive layer 712. In other embodiments, the insulating layer 713 can have an opening that exposes a portion 712B or 712D of the conductive layer 712. For example, referring to FIG. 7B, insulating layer 713 has an opening 722B that exposes one portion 712B of conductive layer 712. According to the structure of FIG. 7B, one portion 712B of the conductive layer 712, the organic layer 714, and the conductive layer 715 form a diode 64.

Figure 8 is a diagram showing a pixel circuit in accordance with another embodiment of the present invention. Referring to FIG. 8, the pixel circuit 8 is applied to an organic light emitting display panel, and includes a switching transistor 80, a driving transistor 81, a capacitor 82, a light emitting diode 83, and diodes 84 and 85. In this embodiment, both the switching transistor 80 and the driving transistor 81 are implemented as a double gate transistor. As shown in Fig. 8, the switching transistor 80 has an upper gate terminal B80, a lower gate terminal G80, and two electrode terminals D80 and S80. In this embodiment, the two electrode terminals D80 and S80 of the switching transistor 80 are the 汲 extreme and the source terminal, respectively. The driving transistor 81 has an upper gate terminal B81, a lower gate terminal G81, and two electrode terminals D81 and S81. In this embodiment, the two electrode terminals D81 and S81 of the driving transistor 81 are the 汲 terminal and the source terminal, respectively.

The lower gate G80 of the switching transistor 80 receives a scan signal SS80, the drain terminal D80 receives a data signal DS80, and its source terminal S80 is electrically coupled to a node N80. The gate terminal G81 of the driving transistor 81 is electrically connected to the node N80, the 汲 terminal D81 is electrically connected to the voltage source VDD, and the source S81 terminal thereof is electrically connected to the anode terminal of the illuminating diode 83. The capacitor 82 is electrically connected between the gate terminal G81 and the source terminal S81 below the switching transistor 82. The cathode terminal of the light-emitting diode 83 is electrically connected to a voltage source VSS. In the embodiment of FIG. 8, the gate terminal B80 of the switching transistor 80 is electrically connected to the voltage source VSS through the diode 85, and the gate terminal B81 of the driving transistor 81 is electrically connected to the voltage source VSS through the diode 84. In detail, the anode terminal of the diode 85 is electrically connected to the gate terminal B80 of the switching transistor 80, and the cathode terminal of the diode 85 is electrically connected to the voltage source VSS; the anode terminal of the diode 84 is driven over the transistor 81. The gate terminal B81 and the cathode terminal of the diode 84 are electrically connected to the voltage source VSS. In this embodiment, the voltage source VSS provides a voltage that is lower than the voltage provided by the voltage source VDD.

In another embodiment, the drive transistor 81 is implemented as a dual gate transistor and the switch transistor 80 is implemented as a single gate transistor. In this example, only the upper gate terminal B81 of the driving transistor 81 is electrically connected to the voltage source VSS through the diode 84.

Referring to Fig. 8, when the switching transistor 80 is turned on in accordance with the scanning signal SS80, the data signal DS80 is transmitted to the node N80. The driving transistor 21 supplies a driving current I80 according to the voltage on the node N80 to drive the light-emitting diode 83 to emit light.

According to the embodiment of Fig. 8, the anode terminal of the diode 85 is electrically connected to the gate terminal B80 above the switching transistor 80, and the anode terminal of the diode 84 is electrically connected to the gate terminal B81 above the driving transistor 81. Since no voltage is applied to the gate terminal B80 above the switching transistor 80 and the gate terminal B81 above the driving transistor 81, no current flows through the diodes 85 and 84, and the diodes 85 and 84 do not emit light. The voltage at the anode terminal of diode 85 is ultimately equal to the voltage provided by voltage source VSS, and the voltage at the anode terminal of diode 84 is ultimately equal to the voltage provided by voltage source VSS. From this, it can be seen that the gate-source voltage (Vbs) above the driving transistor 81 is equal to zero, and the gate-source voltage (Vbs) above the switching transistor 80 is also equal to zero. According to the characteristics of the double gate transistor shown in Figs. 3-4, when the pixel circuit 8 is used for a long time, the offset of the threshold voltage can be reduced, thereby improving the image uniformity.

Fig. 9 is a cross-sectional view showing the structure of the switching transistor 80, the driving transistor 81, the light-emitting diode 83, and the diodes 84 and 85 in the pixel circuit 8. Referring to Fig. 9, the structure of the pixel circuit 8 is substantially the same as that of the pixel circuit 6. The difference is that in order to form the diodes 84 and 85, the insulating layer 713 has two openings 922A and 922B, replacing the first Opening 722A of Figure 7. Openings 922A and 922B expose two portions 712B and 712D of conductive layer 712, respectively. According to the structure of FIG. 9, one portion 712B of the conductive layer 712, the organic layer 714, and the conductive layer 715 form a diode 74; a portion 712D of the conductive layer 712, an organic layer 714, and a conductive layer 715 form a diode 85. Further, in Fig. 9, the two portions 712B and 712D of the conductive layer 712 are separated from each other (not connected to each other) due to the formation of the diodes 84 and 85.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

Figure 1:

1. . . Pixel circuit

10. . . Switching transistor

11. . . Drive transistor

12. . . Capacitor

13. . . Light-emitting diode

DS10. . . Data signal

I10. . . Drive current

SS10. . . Scanning signal

Figure 2:

2. . . Pixel circuit

20. . . Switching transistor

twenty one. . . Drive transistor

twenty two. . . Capacitor

twenty three. . . Dipole

B20, B21. . . Upper gate extreme

D20, D21. . . Extreme

DS20. . . Data signal

G20, G21. . . Lower gate extreme

I20. . . Drive current

N20. . . node

S20, S21. . . Source extreme

SS20. . . Scanning signal

VDD, VSS. . . power source

Figure 3-4:

30, 31, 40, 41. . . curve

T0, T1. . . Time point

Figure 5:

500. . . Substrate

501, 505, 506, 508, 509, 511. . . Conductive layer

502, 504, 509. . . Insulation

503. . . Active layer

504. . . Insulation

507. . . The protective layer

510. . . Organic layer

Figure 6:

6. . . Pixel circuit

60. . . Switching transistor

61. . . Drive transistor

62. . . Capacitor

63. . . Light-emitting diode

64. . . Dipole

B60, B61. . . Upper gate extreme

D60, D61. . . Extreme

DS60. . . Data signal

G60, G61. . . Lower gate extreme

I60. . . Drive current

N60. . . node

S60, S61. . . Source extreme

SS60. . . Scanning signal

VDD, VSS. . . power source

Figure 7A-7B:

700. . . Substrate

701, 702, 707...710, 712, 715. . . Conductive layer

703, 706, 713. . . Insulation

704, 705. . . Active layer

711. . . The protective layer

714. . . Organic layer

716...721, 722A, 722B. . . Opening

Figure 8:

8. . . Pixel circuit

80. . . Switching transistor

81. . . Drive transistor

82. . . Capacitor

83. . . Light-emitting diode

84, 85. . . Dipole

B80, B81. . . Upper gate extreme

D80, D81. . . Extreme

DS80. . . Data signal

G80, G81. . . Lower gate extreme

I80. . . Drive current

N80. . . node

S80, S81. . . Source extreme

SS80. . . Scanning signal

VDD, VSS. . . power source

Figure 9:

922A, 922B. . . Opening

Figure 1 shows a pixel circuit of a conventional organic light emitting display;

Figure 2 is a diagram showing a pixel circuit in accordance with an embodiment of the present invention;

Figure 3 is a graph showing the relationship between the gate current and the gate voltage of a single-gate transistor;

Figure 4 is a graph showing the relationship between the gate current and the gate voltage of a double gate transistor;

Figure 5 is a cross-sectional view showing the structure of the pixel circuit in Figure 2;

Figure 6 shows a pixel circuit in accordance with another embodiment of the present invention;

Figure 7A is a cross-sectional view showing the structure of an embodiment of the pixel circuit of Figure 6;

Figure 7B is a cross-sectional view showing the structure of another embodiment of the pixel circuit of Figure 6;

Figure 8 is a diagram showing a pixel circuit in accordance with still another embodiment of the present invention;

Fig. 9 is a cross-sectional view showing the structure of an embodiment of the pixel circuit of Fig. 8.

2. . . Pixel circuit

20. . . Switching transistor

twenty one. . . Drive transistor

twenty two. . . Capacitor

twenty three. . . Dipole

B20, B21. . . Upper gate extreme

D20, D21. . . Extreme

DS20. . . Data signal

G20, G21. . . Lower gate extreme

I20. . . Drive current

N20. . . node

S20, S21. . . Source extreme

SS20. . . Scanning signal

VDD, VSS. . . power source

Claims (16)

A pixel circuit includes: a switching transistor having a first gate terminal receiving a scan signal, a first electrode terminal receiving a data signal, and a second electrode terminal; and a driving transistor having a first gate terminal electrically connected to a second electrode end, a second gate terminal, and a first electrode end of the switching transistor are electrically connected to a first voltage source and a second electrode end; and a first diode, wherein the driving transistor is second The gate terminal is electrically connected to the second voltage source through the first diode, and the voltage provided by the second voltage source is lower than the voltage provided by the first voltage source. The pixel circuit of claim 1, wherein the anode end of the first diode is electrically connected to the second gate terminal and the second electrode terminal of the driving transistor, and the first diode is negative. The second voltage source is electrically connected to the pole. The pixel circuit of claim 2, wherein the first diode is a light emitting diode, and the driving transistor provides a driving current to drive the first diode to emit light. The pixel circuit of claim 3, wherein the switching transistor further comprises a second gate terminal, and the second gate terminal of the switching transistor is electrically connected to the anode terminal of the first diode. The pixel circuit of claim 1, wherein an anode end of the first diode is electrically connected to a second gate terminal of the driving transistor, and a cathode end of the first diode is electrically connected to the first Two voltage sources. The pixel circuit of claim 5, further comprising a light emitting diode electrically connected between the second electrode end of the driving transistor and the second voltage source. The pixel circuit of claim 6, wherein the driving transistor provides a driving current to drive the light emitting diode to emit light. The pixel circuit of claim 6, wherein the switching transistor further comprises a second gate terminal, and the second gate terminal of the switching transistor is electrically connected to the anode terminal of the first diode. The pixel circuit of claim 6, further comprising a second diode, wherein the switch transistor further comprises a second gate terminal, and the anode terminal of the second diode is electrically connected to the switch a second gate terminal of the crystal, and a cathode terminal of the second diode is electrically connected to the second gate terminal of the switching transistor electrically connected to the second voltage source. The pixel circuit of claim 1, wherein the switching transistor further comprises a second gate terminal, and the second gate terminal of the switching transistor electrically connects the second voltage through the first diode source. The pixel circuit of claim 1, further comprising a second diode, wherein the switching transistor further comprises a second gate terminal, and the second gate terminal of the switching transistor transmits the second gate The diode is electrically connected to the second voltage source. The pixel circuit of claim 1, further comprising: a substrate, the driving transistor is disposed on the substrate; a protective layer disposed on the substrate and covering the driving transistor, wherein The protective layer has a first opening to expose the second electrode end of the driving transistor; a first conductive layer disposed on the protective layer and having a first portion and a second portion, wherein the first conductive portion a first portion of the layer extends into the first opening to connect the second electrode end of the driving transistor, and a second portion of the first conductive layer is above the driving transistor and serves as a second of the driving transistor a gate electrode; an insulating layer disposed on the first conductive layer and having a second opening to expose the first portion of the first conductive layer; an organic layer disposed on the third insulating layer and extending into The second opening is connected to the first portion of the first conductive layer; and a second conductive layer is disposed on the organic layer, wherein the second conductive layer, the organic layer, and the first conductive layer The first part forms the first diode . The pixel circuit of claim 1, further comprising: a substrate, the switch transistor and the driving transistor are disposed on the substrate; a protective layer disposed on the substrate and covering the switch The transistor and the driving transistor, wherein the protective layer has a first opening to expose the second electrode end of the driving transistor; a first conductive layer disposed on the protective layer and having the first portion And a second portion, wherein the first portion of the first conductive layer extends into the first opening to connect to the second electrode end of the driving transistor, and the second portion of the first conductive layer covers the driving Above the crystal and as the second gate terminal of the driving transistor, wherein the first portion of the first conductive layer is not connected to the second portion; an insulating layer is disposed on the first conductive layer and has a second opening Exposing the first portion of the first conductive layer and having a third opening to expose the second portion of the first conductive layer; an organic layer disposed on the insulating layer and extending into the second opening to connect the first portion a conductive layer a first portion, and a second portion extending into the third opening to connect the first conductive layer; and a second conductive layer disposed on the organic layer, wherein the second conductive layer, the organic The layer and the second portion of the first conductive layer form the first diode. The pixel circuit of claim 13, further comprising a light emitting diode electrically connected between the second electrode end of the driving transistor and the second voltage source, wherein the second conductive layer The organic layer and the first portion of the first conductive layer form the light emitting diode. The pixel circuit of claim 13, wherein the switching transistor further comprises a second gate terminal, and the second gate terminal of the switching transistor is electrically connected to the second terminal through the first diode a voltage source; and wherein the second portion of the first conductive layer acts as a second gate terminal of the switching transistor. The pixel circuit of claim 13, wherein the first conductive layer further has a third portion overlying the driving transistor and serving as a second gate terminal of the driving transistor, and the first a third portion of the conductive layer is not connected to the second portion; and wherein the insulating layer has a fourth opening to expose the third portion of the first conductive layer, and the second conductive layer, the organic layer, and the A third portion of the first conductive layer forms the second diode.