TW201944506A - 封裝件及其形成方法 - Google Patents

封裝件及其形成方法 Download PDF

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Publication number
TW201944506A
TW201944506A TW108112623A TW108112623A TW201944506A TW 201944506 A TW201944506 A TW 201944506A TW 108112623 A TW108112623 A TW 108112623A TW 108112623 A TW108112623 A TW 108112623A TW 201944506 A TW201944506 A TW 201944506A
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Taiwan
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forming
die
encapsulation body
hole
item
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TW108112623A
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TWI705509B (zh
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余振華
郭宏瑞
蔡惠榕
謝昀蓁
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台灣積體電路製造股份有限公司
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Abstract

本發明實施例揭露封裝件及其形成方法。一種封裝件的形成方法包括形成晶粒，所述晶粒包括襯墊及位於襯墊之上的鈍化層。形成穿過鈍化層一直到襯墊的通孔。在通孔上形成焊料帽，其中焊料帽的第一材料流動到通孔的側壁。在一些實施例中，將通孔包封在第一包封體中，其中第一包封體是被選擇成具有低的熱膨脹係數和/或低的固化溫度的聚合物或模塑化合物。在一些實施例中，藉由蝕刻製程從通孔的側壁移除焊料帽的第一材料並將通孔包封在第一包封體中。

Description

使用包封體進行通孔側壁黏合的半導體元件
隨著現代積體電路的大小縮減，相關聯特徵的大小也縮減。隨著電晶體縮減，例如穿孔及其他內連線構件等特徵的大小也縮減。在許多實例中，晶片上、晶粒上、封裝件中、印刷電路板（printed circuit board，PCB）上及其他基底上的各層電路通過通孔（vias）在各個層之間進行內連。通孔藉由在穿過基底的開口中填充導電金屬形成。通常，通孔連接到跡線（traces）或其他導電結構以允許不同層中的未對準的接觸點能夠連接。
以下公開內容提供用於實施本發明的不同特徵的許多不同的實施例或實例。以下闡述構件及排列方式的具體實例以簡化本公開內容。當然，這些僅為實例且不旨在進行限制。舉例來說，以下說明中將第一特徵形成在第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、以使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用參考編號和/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例和/或配置之間的關係。
此外，為便於進行說明，本文中可使用例如「之下」、「下方」、「下部」、「上方」、「上部」等空間相對用語來闡述圖中所說明的一個構件或特徵與另外的構件或特徵的關係。除了圖中所繪示的定向之外，所述空間相對用語還旨在囊括裝置在使用或操作中的不同定向。設備可以其他方式進行定向（旋轉90°或處於其他定向），且同樣地可對本文中所使用的空間相對描述符加以相應地解釋。
本發明實施例會改善在晶粒之上一直形成到晶粒襯墊的通孔與周圍包封體（例如聚合物或模塑化合物）之間的側壁黏合。本發明實施例可使用具有包括低的熱膨脹係數或低溫固化的熱性質的包封體以減小包封體與通孔的側壁分層的可能性，尤其是在可能形成焊料的位置處。本發明實施例還可在形成包封體之前使用蝕刻製程來從通孔的側壁移除焊料，以使得通孔的側壁與包封體之間的黏合得到改善，從而減小包封體與通孔的側壁分層的可能性。對焊料進行蝕刻的本發明實施例還可提供一致的界面，以減少由可能位於通孔的頂部上及通孔的側壁上的焊料殘留物造成的線上視覺缺陷（in-line visual defect）。
圖1到圖19示出根據一些實施例的製造包括嵌入式晶粒的封裝件的各個中間階段的剖視圖。圖1至圖8示出根據一些實施例在晶粒上形成通孔。
圖1示出上面形成有一個或多個接觸襯墊105的晶粒101。儘管圖中僅示出一個接觸襯墊，然而應理解在晶粒101的表面之上可形成另外的接觸襯墊。晶粒101可包括被動元件晶粒或主動元件晶粒，被動元件晶粒實質上不含有任何主動區，主動元件晶粒包括其中形成有至少一個主動元件的基底。接觸襯墊105可連接到晶粒101的不同的訊號線、電力線及接地線。
晶粒101可包括基底、主動元件及內連線結構（未各別地單獨示出）。晶粒101的基底可包含例如經摻雜或未經摻雜的塊狀矽、或絕緣體上半導體（semiconductor-on-insulator，SOI）基底的主動層。一般來說，SOI基底包括形成在絕緣體層上的半導體（例如矽）材料層。絕緣體層可為例如埋入氧化物（buried oxide，BOX）層或氧化矽層。絕緣體層設置在基底（例如矽或玻璃基底）上。作為另外一種選擇，晶粒101的基底可包含以下材料：另一種元素半導體，例如鍺；化合物半導體，包括碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或其組合。也可使用其他基底，例如多層式基底（multi-layered substrate）或梯度基底（gradient substrate）。晶粒101的基底可為晶圓的一部分，所述晶圓在以下所述形成晶粒之後被單體化成各別的晶粒。
基底可包括例如位於晶粒101的基底的頂表面處的主動側，在主動側處可形成例如電晶體、二極體、光電二極體等主動元件。在一些實施例中，在晶粒101的基底的頂表面處或者在上覆的內連線結構中也可包括被動元件（例如，電容器、電阻器、熔絲等）。內連線結構可形成在主動元件及基底之上。內連線結構可包括層間介電（inter-layer dielectric，ILD）層和/或金屬間介電（inter-metal dielectric，IMD）層，所述ILD層和/或IMD層包含使用任何合適的方法形成在ILD層和/或IMD層中的導電特徵（例如，包含銅、鋁、鎢、其組合等的導電線及導通孔）。ILD層和/或IMD層可包含設置在此種導電特徵之間的介電常數值例如低於約4.0或甚至低於2.0的低介電常數介電材料。在一些實施例中，ILD層和/或IMD層可由通過任何合適的方法（例如旋塗、化學氣相沉積（chemical vapor deposition，CVD）及電漿增強化學氣相沉積（plasma-enhanced CVD，PECVD））形成的例如以下材料製成：磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼磷矽酸鹽玻璃（borophosphosilicate glass，BPSG）、氟矽酸鹽玻璃（fluorosilicate glass，FSG）、SiOxCy、旋塗玻璃、旋塗聚合物、碳化矽材料、其化合物、其組合物、其組合等。內連線結構對各個主動元件進行電連接以形成晶粒101的功能電路。由此種電路提供的功能可包括記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路系統等。所屬領域中的一般技術人員將理解，提供以上實例僅是出於例示目的以進一步解釋應用各種實施例，且並非旨在以任何方式限制所述實施例。可視需要對給定應用使用其他電路系統。
可在每一個主動元件晶粒的內連線結構之上形成輸入/輸出特徵及保護特徵。舉例來說，可在內連線結構之上形成接觸襯墊105，且接觸襯墊105可經由內連線結構中的各種導電特徵電連接到主動元件。接觸襯墊105可包含導電材料，例如鋁、銅等。
參照圖2，可在內連線結構及接觸襯墊105之上形成一個或多個鈍化層（passivation layer）109，且在鈍化層109中形成開口110以暴露出接觸襯墊105。在一些實施例中，鈍化層109可由例如以下無機材料形成：氧化矽、未經摻雜的矽酸鹽玻璃、氮氧化矽等。還可使用其他合適的保護材料。在一些實施例中，鈍化層可包含介電材料，例如SiN、另一種氮化物、SiO、另一種氧化物或其組合。開口110可使用任何合適的微影製程形成。鈍化層109的一些部分可餘留下來且可覆蓋接觸襯墊105的邊緣部分。還可在接觸襯墊之上可選地形成另外的內連線特徵，例如另外的鈍化層、導電柱和/或凸塊下金屬（under bump metallurgy，UBM）層。
晶粒101的各種特徵可通過任何合適的方法形成且在本文中未進一步詳細闡述。另外，上述晶粒101的一般特徵及配置只是一個示例性實施例，且晶粒101可包括任何數目的以上特徵以及其他特徵的任何組合。
現參照圖3至圖8，在被暴露出的接觸襯墊105中的每一者之上形成通孔。儘管闡述了特定製程以形成通孔，然而應理解可使用任何合適的製程。在圖3中，在鈍化層109之上且在穿過鈍化層109的開口110中形成晶種層113。在一些實施例中，晶種層113是金屬層。在一些實施例中，一個或多個另外的晶種層（例如晶種層117）可由不同的材料形成。在一些實施例中，晶種層113可包括鈦層且晶種層117可包括位於所述鈦層之上的銅層。晶種層113及晶種層117可使用例如物理氣相沉積（physical vapor deposition，PVD）等形成。
現參照圖4，接著在晶種層117上形成光阻121且將光阻121圖案化。光阻121可通過旋轉塗佈等來形成且可曝光以進行圖案化。光阻的圖案對應於將在接觸襯墊105之上形成的導通孔。所述圖案化穿過光阻形成開口122以暴露出晶種層117。
如圖5所示，在光阻121的開口122中以及在晶種層117的被暴露出的部分上形成導通孔125（或金屬柱）。導通孔125可通過鍍覆（例如電鍍或無電鍍覆等）形成。導通孔125可為導電材料，包括金屬（如銅、鈦、金、鋁、鎢、鈷、鈀、鎳、銀、其化合物或合金）或其他導電材料。
參照圖6，在開口122（參見圖5）中在導通孔125之上形成焊料帽（solder cap）129。在一些實施例中，焊料帽129可通過鍍覆（例如電鍍或無電鍍覆等）形成。在其他實施例中，焊料帽129可通過其他手段形成，例如通過焊料印刷等形成。焊料帽129可為包含與導通孔125不同的金屬的導電材料，例如共晶材料（eutectic material），如具有錫、鉛、銀等或其組合的焊料。
參照圖7及圖8，移除光阻121（參見圖6）以及晶種層113及晶種層117的上面未形成導通孔125的一些部分。在圖7中，光阻121可通過可接受的灰化製程或剝除製程（例如使用氧電漿等）來移除。在圖8中，一旦光阻被移除，則例如通過使用可接受的蝕刻製程（例如通過濕式蝕刻或乾式蝕刻）來移除晶種層113及晶種層117的被暴露出的部分。晶種層113、晶種層117的其餘部分與導通孔125形成與接觸襯墊105接觸的導電特徵。
在一些實例中，可使用焊料帽129來覆蓋導通孔125的頂表面，尤其是在可能易於受因例如元件或封裝件製作製程的步驟而引起的腐蝕、污染或表面缺陷的影響的通孔之上。焊料帽129還可用於對不同的金屬通孔進行鍍覆以提高後續層或結構的黏合或者改變通孔的表面電性質。舉例來說，可使用鈷來加蓋銅通孔以抗腐蝕且防止銅浸析到後續層中。
參照圖9，可使用焊料帽129來對晶粒101進行測試。晶粒101可由探針135來進行測試或者由具有探針135的測試設備來進行測試，探針135與焊料帽129接合。焊料帽129對探針提供更柔軟的材料，此使測試更可靠。
圖10A示出根據一些實施例的位於導通孔125之上的焊料帽129的放大圖。如圖中所示，由於之前的處理步驟（例如光阻121的灰化（參見圖6）或晶種層113及晶種層117的蝕刻（參見圖8）），焊料帽129可能會變形且可能會發生回流。在此製程中，在導通孔125的側壁上可能會進行一些焊料浸潤（wetting），從而使側壁焊料部分130形成在導通孔125上。
圖10B是導通孔125的通過圖10A所示線A-A截取的水準剖視圖。如圖中所示，側壁焊料部分130中的焊料環可與導通孔125的側壁相鄰地形成。
包封體可形成為環繞導通孔125，然而，由於存在側壁焊料部分130，因此在後續處理中可能會出現問題，此導致在側壁焊料部分130處分層或者在導通孔的側壁與環繞的包封材料之間形成空隙。舉例來說，當側壁焊料部分130余留下來時，包封體（例如，參見圖12）、側壁焊料部分130及導通孔125之間的熱膨脹係數（coefficients of thermal expansion，CTE）的失配可能會造成分層。舉例來說，焊料可具有約21百萬分率/攝氏度（parts per million per degree Celsius, ppm/℃）的CTE，導通孔125的銅可具有約17 ppm/℃的CTE，且包封體可具有約44 ppm/℃的CTE。在包封體固化期間，該些材料中的每一者之間的失配可能造成分層。相似地，由於對側壁焊料部分130之差的包封體浸潤，可能會在形成包封體時形成空隙。如果焊料帽129是通過研磨製程或拋光製程而被移除的，則側壁焊料部分130可能會餘留下來，從而造成生產線處理缺陷（line processing defect）。舉例來說，當線上上檢查過程（in line inspection process）中對晶粒101進行檢查時，側壁焊料部分130可能在處理過程中造成視覺缺陷誤差且導致良率降低。
圖11及圖12示出焊料帽129的移除以及導通孔125的可選的包封。參照圖11，為防止形成分層及空隙，在對導通孔125進行包封之前，通過使用蝕刻劑的蝕刻製程來移除焊料帽129，所述蝕刻劑在焊料帽129的材料（例如，錫）與導通孔125的材料（例如，銅）之間具有高的選擇性。在包封之前移除焊料帽129使導通孔125的側壁與包封體（參見圖15A所示包封體317或圖15B所示包封體201）（例如，聚合物或模塑化合物）之間的黏合（或浸潤）更好。
用於移除焊料帽129的蝕刻製程可為濕式蝕刻或電漿蝕刻。合適的蝕刻材料在焊料帽129的材料與導通孔125的材料之間具有高的選擇性。在一些實施例中，可將蝕刻材料選擇成使焊料帽129的材料與導通孔125的材料之間的選擇性使蝕刻速率比（etch rate ratio）大於約10:1。合適的蝕刻材料可包括針對濕式蝕刻選擇的化學物質，所述化學物質包括例如酸中的氧化劑，例如HNO3 、H2 SO4 或HCl中的H2 O2 、Cu2+ 或Fe3+ 。可使用這些氧化劑與酸的組合。還可使用其他合適的氧化劑或酸。合適的蝕刻材料可包括在電漿蝕刻中使用的製程氣體，所述製程氣體包括具有鹵素氣體的混合氣體，例如Cl2 /Ar、Cl2 /O2 /Ar、F2 /Ar、F2 /Ar/O2 、I2 /Ar、I2 /Ar/O2或其組合。可使用其他合適的混合氣體及鹵素。
在蝕刻製程之後，可實質上移除導通孔125周圍的側壁焊料部分130（參見圖10A及圖10B）的焊料，從而利用隨後形成的包封體得出更好的黏合性能。對焊料帽129進行蝕刻的實施例還可提供一致的界面，來減少由原本可能餘留在導通孔125的頂部上及環繞導通孔125的焊料殘留物造成的線上視覺缺陷。在此種實施例中，導通孔125的側壁與包封體（參見，例如圖12的包封體201或圖14A的包封體317）之間的界面可實質上不含焊料的材料（例如，包括錫）。
參照圖10C及圖10D，圖10C及圖10D分別示出根據一些實施例的在對焊料帽129進行蝕刻之後的與圖10A及圖10B相似的橫截面。圖10D所示橫截面是通過圖10C所示線B-B截取的。在一些實施例中，蝕刻製程可部分地移除側壁焊料部分130同時使一些焊料餘留在導通孔125的側壁上，從而形成焊料殘留物131。舉例來說，蝕刻製程可使焊料殘留物131位於導通孔125的頂表面下方的導通孔125的側壁上。在此種實施例中，位於導通孔125的頂表面之上的焊料帽129以及側壁焊料部分130的位於導通孔125的頂表面附近的部分可實質上被移除，而側壁焊料部分130的另一部分（焊料殘留物131）可餘留下來，所述另一部分不像被移除的部分一樣靠近導通孔125的頂表面。頂部側壁界面132實質上不含焊料，此可減少線上視覺缺陷且仍提供改善的黏合，從而降低導通孔125與隨後形成的包封體（由表示包封體201（圖12）或包封體317（圖14A）的虛線示出）之間形成分層或空隙的風險。
現參照圖12，在蝕刻製程之後，可執行可選的包封製程以使用包封體201（例如聚合物或模塑化合物）在側向上包封導通孔125。在實施例製程中，可將包封體201的材料選擇成使通孔125與包封體201之間的熱失配減小，此在以下進行更詳細地解釋。
熱失配可由包封體201與通孔125的熱膨脹係數（CTE）之差造成。熱失配還受用于形成包封體201的材料（例如，用於固化包封體201）所需的熱預算影響。舉例來說，聚合物包封體材料在室溫下可具有約9百萬分率/攝氏度（ppm/℃）的熱膨脹係數（介於約8百萬分率/攝氏度（ppm/℃）與約40百萬分率/攝氏度（ppm/℃）之間），所述聚合物包封體可在約400℃的溫度下固化以實現80%的環化（cyclization）。環化是指移除預聚物中的溶劑並將預聚物轉換成難以處理的狀態（intractable state），從而形成聚合物。80%程度的環化表示轉換已完成80%，此可為聚合物獲得期望的物理性質（例如介電性質等）所需的合適的轉換程度。
在一些實施例中，可將包封體201的材料選擇或改性成具有比其他聚合物或模塑化合物低的CTE，以使通孔125與包封體201之間的CTE失配減小。舉例來說，如果通孔125是銅，則通孔125的CTE可為約17 ppm/℃。包封體201可具有介於約8 ppm/℃到約40 ppm/℃的範圍內（例如約9 ppm/℃）的CTE。在一些實施例中，包封體201的CTE可介於通孔125的材料的CTE的0.5倍與2.5倍之間。換句話說，包封體201的CTE對通孔125的CTE的比率可介於約0.5:1與約2.5:1之間。預期存在其他可接受的比率範圍，且其他可接受的比率範圍可取決於針對通孔125及包封體201選擇的材料。舉例來說，包封體201的CTE對通孔125的CTE的比率可介於約0.5:1與約2:1之間或者可介於約1:1與約2:1之間，等等。除了CTE失配造成黏合問題的可能性之外，包封體201的材料以及通孔125的材料中的一些還可因其他物理性質而提供比其他材料更好的黏合。
在一些實施例中，可將包封體201的材料選擇成具有比其他聚合物或模塑化合物低的固化溫度以使處理溫度可降低以形成包封體201，例如實現合適的環化。換句話說，可將包封體201的材料選擇成具有形成包封體201所需的低熱預算要求。在一些實施例中，可將包封體201的材料選擇成具有介於100℃與250℃之間的固化溫度（例如約200℃）以實現80%的環化。在更高的固化溫度下，聚合物的CTE可增大。儘管CTE通常是在室溫下表達的（如上所述），然而包封體201的CTE舉例來說在室溫下可為約9 ppm/℃，且在260℃下可增大到約44 ppm/℃。因此，可將固化溫度選擇成在固化溫度下，通孔125與包封體201之間的CTE失配減小。
由於材料的熱膨脹取決於溫度，因此較低的固化溫度也會使膨脹D較低。以下實例並非旨在進行限制，而是出於例示目的而包括在本文中。將在350℃下具有約17 ppm/℃的CTE的銅通孔125的膨脹計算成約5950 ppm（或0.595%）。將在350℃下具有約55 ppm/℃的CTE的聚合物的膨脹計算成約19,250 ppm（或1.925%），差異為13,300 ppm（或1.33%）。在較低的溫度（例如200℃）下，將銅通孔125的膨脹計算成約3400 ppm（或0.34%）。如果聚合物被改性成在較低的溫度下進行處理，則將在200℃下為約55 ppm/℃的CTE計算成約11,000 ppm（或約1.1%），差異為7600 ppm（或約0.76%）。在此種情形中，即使在未對包封體201的CTE進行調整的條件下，較低的處理溫度仍將使有效熱膨脹失配減小43%（在此實例中，將13,300 ppm與7600 ppm進行比較）。
在一些實施例中，可將包封體201選擇或改性成具有較低的CTE及較低的固化溫度二者。通過將包封體201選擇成具有較低的CTE或較低的固化溫度（或二者），通孔125與包封體201之間的熱失配減小。在一些實施例中，可將包封體201及通孔125選擇成具有小於約25 ppm/℃（例如，在200℃下為5000 ppm）的有效熱膨脹失配。換句話說，在形成包封體201所需的處理溫度下，通孔125與包封體201之間的熱膨脹之差因其不同的CTE而小於約0.5%。在約200℃的處理溫度下，CTE之差小於約25 ppm/℃。在約250℃的處理溫度下，CTE之差小於約20 ppm/℃。
包封體201的材料在一些實施例中可為聚合物，例如聚苯並惡唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide）、苯並環丁烯（benzocyclobutene，BCB）等。為實現形成聚合物所需的較低的熱預算，聚合物可經歷主鏈改性（backbone modification），其中聚合物主鏈的元素被反應性較高的元素取代。由於主鏈具有反應性較高的元素，因此需要較小的熱預算來實現期望的環化並實現難以處理的狀態（即，形成聚合物）。在主鏈改性的非限制性實例中，聚合物前體可為烷氧基矽烷（alkoxysilane）、氨基矽烷（aminosilane）或環型烷氧基矽烷系前體（cyclic type alkoxysilane-based precursor）。在形成聚合物期間，所得聚合物的主鏈可被改性從而以另一種元素來取代一個或多個氧原子，舉例來說，使用硫化物與前體的組合來取代硫。可執行其他合適的主鏈改性。在一些實施例中，作為主鏈改性的結果，包封體201可在介於約100℃到約250℃之間（例如約200℃）的固化溫度下實現超過80%的環化，而在主鏈改性之前，將需要約300℃到約400℃的固化溫度來實現超過80%的環化。聚合物主鏈改性可因此更改包封體201的材料的熱預算要求。
為實現較低的CTE，包封體201可被添加填料材料，例如奈米填料材料。填料材料可包括任何合適的材料。舉例來說，填料可包括陶瓷、黏土、矽、碳奈米管、石墨烯等中的一種或多種。填料可介於包封體201的約1重量%與約20重量%之間，但是此並非旨在進行限制且預期存在其他百分比。
在形成包封體201之後，可將晶粒14從晶圓單體化。包封體201的側向範圍可與晶粒101的基底的側向範圍相同。換句話說，包封體201可延伸到晶粒14的側向範圍。
返回參照圖11，在對焊料帽129進行蝕刻之後，在一些實施例中，可將晶粒101從晶圓單體化成晶粒12。參照圖12，在其他實施例中，在對焊料帽129進行蝕刻、形成包封體201及平坦化之後，在一些實施例中，可將晶粒101從晶圓單體化成晶粒14。在又一些實施例中，可形成代表晶粒12的晶粒以及代表晶粒14的晶粒。
圖13A到圖21示出根據一些實施例的使用嵌入式晶粒形成封裝元件中的各個中間步驟。參照圖13A，可通過晶粒貼合膜（die attach film，DAF）釋放層（未示出）來將經單體化的晶粒12貼合到載體301。載體301包括至少兩個晶粒放置區350（標記為350A及350B）。如以下將更詳細地闡述，在各個晶粒放置區350中的載體301上形成特徵，且隨後將每一晶粒放置區350中的特徵從載體301上的其他特徵單體化。因此，可同時形成多個封裝件。
載體301可為玻璃載體基底、陶瓷載體基底等。載體301可為晶圓，以使得可在載體301上同時形成多個積體被動元件（integrated passive device，IPD）封裝件。釋放層可由聚合物系材料形成，所述聚合物系材料可與載體301一起從將在後續步驟中形成的上覆結構被移除。在一些實施例中，釋放層是在受熱時會失去其黏著性質的環氧樹脂系熱釋放材料，例如光熱轉換（Light-to-Heat-Conversion，LTHC）釋放塗層。在其他實施例中，釋放層可為紫外（ultra-violet，UV）膠，所述紫外膠在被暴露到紫外光時會失去其黏著性質。釋放層可作為液體進行分配並進行固化，或者可為被疊層到載體301上的疊層膜（laminate film）。釋放層的頂表面可為齊平的（leveled）且可具有高平面程度（degree of planarity）。
在一些實施例中，可在晶粒12與載體301之間形成背側重佈線結構305。在此種實施例中，釋放層可將晶粒12貼合到重佈線結構305。重佈線結構305可包括一個或多個重佈線層（redistribution layer，RDL），所述一個或多個重佈線層分別包括含有設置在其中的導電特徵（例如，包含銅、鋁、鎢、其組合等的導電線及導通孔）的ILD層和/或IMD層，所述導電特徵可使用任何合適的方法形成。ILD層和/或IMD層可包含設置在此種導電特徵之間的介電常數值例如低於約4.0或甚至低於2.0的低介電常數介電材料。在一些實施例中，ILD層和/或IMD層可由通過任何合適的方法（例如旋塗、化學氣相沉積（CVD）及電漿增強型化學氣相沉積（PECVD））形成的例如以下材料製成：磷矽酸鹽玻璃（PSG）、硼磷矽酸鹽玻璃（BPSG）、氟矽酸鹽玻璃（FSG）、SiOxCy、旋塗玻璃、旋塗聚合物、碳化矽材料、其化合物、其組合物、其組合等。在一些實施例中，可在移除載體301之後形成背側重佈線結構305（參見圖18）。
重佈線結構305的導電特徵也可包括形成在重佈線結構305的表面處的一個或多個接觸件309。可使用任何合適的製程在所述一個或多個接觸件309之上形成對應的通孔313。通孔313可將特徵從背側重佈線結構305耦合到隨後形成的前側重佈線結構或連接件陣列（例如，參見圖16）。在一些實施例中，可形成通孔313以進行隨後的處理。在一個實施例中，舉例來說，可在所述一個或多個接觸件309之上形成光阻（未示出）並將所述光阻圖案化以通過光阻中的開口暴露出所述一個或多個接觸件309。通孔313可通過鍍覆（例如通過電鍍或無電鍍覆等）形成。通孔313可由導電材料製成，所述導電材料包括金屬（如銅、鈦、金、鋁、鎢、鈷、鈀、鎳、銀、其化合物或合金）或其他導電材料。在形成通孔313之後，可例如通過灰化製程將光阻移除。在一些實施例中，在形成光阻之前可使用晶種層，在此種情形中，在將光阻灰化之後，可將其餘的被暴露出的晶種層移除。
可通過拾取及放置製程將晶粒12放置在晶粒放置區350中，且可通過釋放層將晶粒12貼合到重佈線結構305或載體301（如上所述）。
現參照圖14A，可接著使用包封體317在側向上包封晶粒12，包封體317可為模塑化合物或其他合適的材料。包封體317可具有使包封體317的熱性質更改的主鏈改性，例如以上針對包封體201所論述。包封體317可包含環氧樹脂、樹脂、可塑聚合物（例如PBO、模塑底部填充物（molded underfill，MUF）或另一種可塑材料）。包封體317在俯視圖（未示出）中可包圍晶粒12。在實施例中，可通過壓縮模塑、轉移模塑等來施加包封體317。包封體317可以液體形式施加，且隨後可被固化以提供固體包封體。
現參照圖15A，在實施例中，可施加包封體317來覆蓋晶粒12的頂表面且隨後可對包封體317進行拋光或研磨以暴露出晶粒12的導通孔125並將導通孔125的頂表面及包封體317的頂表面平坦化。在拋光或研磨期間，由於已通過蝕刻移除焊料帽129（參見圖10A），因此拋光將形成比存在焊料帽129的情形更平滑的表面。存在焊料帽129可使導通孔125的頂表面周圍形成斜邊（beveling），從而導致線上缺陷且使隨後形成的前側RDL（參見圖16）的表面更不均勻。
現返回參照圖13B，根據一些實施例，可通過釋放層（未示出）將經單體化的晶粒14（包括包封體201）（參見圖12）貼合到載體301。載體301及釋放層可與以上針對圖13A所論述者相似地進行配置。可通過拾取及放置製程將晶粒14放置在晶粒放置區350中，且可通過釋放層將晶粒14貼合到晶粒放置區350。
在一些實施例中，可在載體301與經包封的晶粒14之間形成背側重佈線結構305。背側重佈線結構305可使用例如以上針對圖13A所述的製程及材料等製程及材料來形成。在一些實施例中，可在移除載體301之後形成背側重佈線結構305（參見圖17）。
在一些實施例中，可使用與圖13A所示通孔313的形成相似的製程及材料來形成通孔313，不再對所述製程及材料予以贅述。通孔313可將特徵從背側重佈線結構305（或載體301）耦合到隨後形成的前側重佈線結構或連接件陣列（參見圖16）。
仍參照圖13B，在放置晶粒14之後，在一些實施例中，可通過平坦化製程來使晶粒14的最上表面齊平，例如通過化學機械平坦化（chemical mechanical planarization，CMP）或其他合適的製程。平坦化製程可在形成通孔313之前或之後執行。
參照圖14B，可接著使用包封體317在側向上包封晶粒14，包封體317可為模塑化合物或其他合適的材料，例如以上針對圖14A所述。在一些實施例中，包封體317可具有使包封體317的熱性質更改的主鏈改性或填料（或者主鏈改性及填料二者），例如以上針對包封體201所論述。在其他實施例中，包封體317可不具有為更改熱性質而添加的主鏈改性或填料，以使包封體201與包封體317之間可出現熱失配。
參照圖15B，在使用包封體317對晶粒14（包括導通孔125及包封體201）及通孔313進行包封之後，可通過平坦化製程（例如通過CMP或其他合適的製程）來使包封體307的頂表面、通孔313的頂表面及經包封的晶粒14（包括導通孔125及包封體201）的頂表面齊平。在一些實施例中，導通孔125及包封體201可不在單獨的步驟中被平坦化而是在與對包封體317進行平坦化的同一步驟中被平坦化。
通常，當使各個頂表面齊平時，焊料殘留物可使導通孔125的金屬與來自焊料帽129的殘留物之間的拋光速率不同，此可能會造成斜邊以及線上視覺缺陷。然而，在實施例製程中，從焊料帽129蝕刻掉焊料殘留物會使包封體201更好地浸潤且形成更一致的表面以執行平坦化及進一步處理。
圖16示出根據一些實施例的前側重佈線結構321的形成。圖16示出圖13A所示結構（使用晶粒12）與圖13B所示結構（使用晶粒14）的組合圖。所屬領域中的一般技術人員將理解，載體301在同一載體301上可具有晶粒12（不具有包封體201）、晶粒14（具有包封體201）或其組合。重佈線結構321可包括一個或多個重佈線層（RDL），所述一個或多個重佈線層分別可包括含有設置在其中的導電特徵（例如，包含銅、鋁、鎢、其組合等的導電線及導通孔）的ILD層和/或IMD層，所述導電特徵可使用任何合適的方法形成。ILD層及IMD層可包含設置在此種導電特徵之間的介電常數值例如低於約4.0或甚至低於2.0的低介電常數介電材料。在一些實施例中，ILD層及IMD層可由通過任何合適的方法（例如旋塗、化學氣相沉積（CVD）及電漿增強化學氣相沉積（PECVD））形成的例如以下材料製成：磷矽酸鹽玻璃（PSG）、硼磷矽酸鹽玻璃（BPSG）、氟矽酸鹽玻璃（FSG）、SiOxCy、旋塗玻璃、旋塗聚合物、碳化矽材料、其化合物、其組合物、其組合等。重佈線結構321可包括積體扇出型（integrated fan-out，InFO）元件的扇出型RDL。
現參照圖17，可在重佈線結構321上形成可選的連接件325。在一些實施例中，可通過移除重佈線結構321的最頂部介電層的一些部分來暴露出重佈線結構321的導電特徵。移除最頂部介電層的一些部分可包括任何合適的圖案化和/或平坦化製程。在暴露出重佈線結構321的導電特徵之後，在重佈線結構321的導電特徵上設置連接件325。連接件325可設置在重佈線結構321的最頂部介電層中的開口中。在一些實施例中，連接件325包括焊料球，例如微凸塊、受控塌陷晶片連接（controlled collapse chip connection，C4）凸塊、球柵陣列（ball gate array，BGA）球等。此只是形成連接件325的一個實例。所屬領域中的技術人員將理解，可以可選地不形成連接件325或者連接件325可在製程中的不同步驟處形成。
現參照圖18，執行載體301剝離來從重佈線結構305分離（剝離）載體301。根據一些實施例，所述剝離包括將例如雷射或紫外光等光投射在釋放層上以使釋放層在光的熱量下分解，且可移除載體301。
參照圖19，可將所述結構翻轉並放置在膠帶401上。在剝離載體301之後，可穿過重佈線結構305的最外部介電層形成開口以暴露出重佈線結構305內的導電特徵的一些部分，例如接觸件309或電耦合到接觸件309的導電特徵。可例如使用雷射鑽孔（laser drilling）、蝕刻等來形成開口。隨後，如圖19所示，可將連接件329設置在重佈線結構305的最外部介電層中的開口中。在一些實施例中，連接件329包括焊料球，例如微凸塊、C4凸塊、BGA球等。
如圖20所示，可沿切割道505（例如，在相鄰的晶粒放置區350（參見圖16及圖17標記為350A及350B）之間）執行單體化製程。可使用例如機械鋸/刀片、雷射、其組合等（由構件501表示）、使用任何合適的製程來執行單體化。在所示出的實施例中，切割道505不會延伸穿過重佈線結構305及重佈線結構321中的任何導電特徵。
圖21示出完工的元件封裝件550。元件封裝件550包括包封在包封體317中的多個晶粒12（和/或晶粒14）。重佈線結構321可包括具有電連接到晶粒12（和/或晶粒14）的導電特徵的扇出型RDL。重佈線結構321可在側向上延伸超過晶粒12（和/或晶粒14）的邊緣。在使用晶粒14的實施例中，包封體317在側向上包封包封體201（參見圖19）。
一些實施例選擇具有低CTE或低固化溫度（或二者）的包封體（例如聚合物或模塑化合物）以減小包封體與通孔之間分層的可能性，其中焊料可能餘留在通孔的側壁上。一些實施例還進行一種蝕刻製程來在包封體中進行包封之前移除位於晶粒的通孔的側壁上的焊料，以減小通孔側壁與包封體之間分層的可能性。還可將包封體選擇成具有低的CTE或低的固化溫度以進一步減小分層的可能性。
一個實施例包括一種方法，所述方法包括形成晶粒，晶粒包括襯墊及位於襯墊之上的鈍化層。形成穿過鈍化層的第一開口。在晶粒之上沉積抗蝕劑層。將抗蝕劑層圖案化以形成對準第一開口的第二開口。在第二開口中形成通孔。在通孔上形成焊料帽，其中焊料帽的第一材料流動到通孔的側壁。將通孔包封在第一包封體中，其中第一包封體具有CTE，其中第一包封體的CTE對通孔的CTE的比率小於2.5:1或者其中第一包封體具有低於250℃的固化溫度。
另一實施例包括一種方法，所述方法包括在晶粒的接觸襯墊之上設置耦合到晶粒的接觸襯墊的金屬柱，金屬柱包含第一材料。在金屬柱之上形成焊料帽，焊料帽包含第二材料。使用在第二材料與第一材料之間具有選擇性的蝕刻劑對焊料帽進行蝕刻。將晶粒貼合到載體。
另一實施例包括一種封裝件，所述封裝件包括嵌入式晶粒，嵌入式晶粒具有形成在嵌入式晶粒的主動側的多個接觸襯墊。金屬通孔設置在所述多個接觸襯墊中的對應的接觸襯墊之上。第一包封體在側向上包封金屬通孔，其中第一包封體接觸金屬通孔的側壁，且其中金屬通孔的側壁與第一包封體之間的界面在與金屬通孔的頂表面相鄰之處不含有錫。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及更改。
12、14、101‧‧‧晶粒
105‧‧‧接觸襯墊
109‧‧‧鈍化層
110、122‧‧‧開口
113、117‧‧‧晶種層
121‧‧‧光阻
125‧‧‧通孔
129‧‧‧焊料帽
130‧‧‧側壁焊料部分
131‧‧‧焊料殘留物
132‧‧‧頂部側壁界面
135‧‧‧探針
201、317‧‧‧包封體
301‧‧‧載體
305‧‧‧重佈線結構
309‧‧‧接觸件
313‧‧‧通孔
321‧‧‧重佈線結構
325、329‧‧‧連接件
350、350A、350B‧‧‧晶粒放置區
401‧‧‧膠帶
501‧‧‧構件
505‧‧‧切割道
550‧‧‧元件封裝件
A-A、B-B‧‧‧線
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據業界中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1到圖8示出根據實施例的製造晶粒的各個中間階段的剖視圖。
圖9示出根據一些實施例的測試製程。
圖10A、圖10B、圖10C及圖10D示出根據一些實施例的在製造包括嵌入式晶粒的封裝件的中間階段處的導通孔及焊料帽的各個剖視圖。
圖11到圖12示出根據一些實施例的在移除焊料帽之後的晶粒的剖視圖。
圖13A到圖21示出根據各種實施例的製造包括嵌入式晶粒的封裝件的各個中間階段的剖視圖。

Claims (20)

  1. 一種封裝件的形成方法，包括： 形成晶粒，所述晶粒包括襯墊及位於所述襯墊之上的鈍化層； 形成穿過所述鈍化層的第一開口； 在所述晶粒之上沉積抗蝕劑層； 將所述抗蝕劑層圖案化，以形成對準所述第一開口的第二開口； 在所述第二開口中形成通孔，所述通孔具有第一熱膨脹係數； 在所述通孔上形成焊料帽，其中所述焊料帽的第一材料流動到所述通孔的側壁；以及 將所述通孔包封在第一包封體中，其中所述第一包封體具有第二熱膨脹係數及固化溫度，其中所述第二熱膨脹係數與所述第一熱膨脹係數的比率小於2.5:1或者所述固化溫度低於250℃。
  2. 如申請專利範圍第1項所述的封裝件的形成方法，更包括： 在包封所述通孔之前，將所述晶粒從晶圓單體化。
  3. 如申請專利範圍第1項所述的封裝件的形成方法，更包括： 在包封所述通孔之後，將所述晶粒從晶圓單體化。
  4. 如申請專利範圍第1項所述的封裝件的形成方法，更包括： 在包封所述通孔之前，對所述焊料帽進行蝕刻以從所述通孔的所述側壁移除所述第一材料。
  5. 如申請專利範圍第1項所述的封裝件的形成方法，更包括： 通過探測所述焊料帽來測試所述晶粒。
  6. 如申請專利範圍第1項所述的封裝件的形成方法，形成所述通孔包括鍍覆導電材料，且其中形成所述焊料帽包括在所述導電材料之上鍍覆所述第一材料。
  7. 如申請專利範圍第1項所述的封裝件的形成方法，更包括： 將所述晶粒貼合到載體；以及 使用第二包封體在側向上包封所述晶粒，其中所述第二包封體的材料不同於所述第一包封體的材料。
  8. 一種封裝件的形成方法，包括： 設置金屬柱，所述金屬柱在晶粒的接觸襯墊之上並耦合到所述晶粒的所述接觸襯墊，所述金屬柱包含第一材料； 在所述金屬柱之上形成焊料帽，所述焊料帽包含第二材料； 對所述焊料帽進行蝕刻，其中所述蝕刻使用在所述第二材料與所述第一材料之間具有選擇性的蝕刻劑；以及 將所述晶粒貼合到載體。
  9. 如申請專利範圍第8項所述的封裝件的形成方法，更包括： 通過探測所述焊料帽來測試所述晶粒。
  10. 如申請專利範圍第8項所述的封裝件的形成方法，其中所述蝕刻是濕式蝕刻製程。
  11. 如申請專利範圍第8項所述的封裝件的形成方法，其中所述蝕刻是電漿蝕刻製程。
  12. 如申請專利範圍第8項所述的封裝件的形成方法，更包括： 在對所述焊料帽進行蝕刻之後使用第一包封體包封所述金屬柱。
  13. 如申請專利範圍第12項所述的封裝件的形成方法，其中所述第一包封體是聚合物或模塑化合物，所述第一包封體具有介於8 ppm/℃與40 ppm/℃之間的第一熱膨脹係數。
  14. 如申請專利範圍第12項所述的封裝件的形成方法，更包括： 在250℃或低於250℃的溫度下固化所述第一包封體。
  15. 如申請專利範圍第12項所述的封裝件的形成方法，更包括： 在包封所述金屬柱之前，將所述晶粒從晶圓單體化；以及 將所述晶粒貼合到載體。
  16. 如申請專利範圍第12項所述的封裝件的形成方法，更包括： 在包封所述金屬柱之後，將所述晶粒從晶圓單體化； 將所述晶粒貼合到載體；以及 使用第二包封體包封所述晶粒。
  17. 一種封裝件，包括： 嵌入式晶粒，具有形成在所述嵌入式晶粒的主動側的接觸襯墊； 金屬通孔，設置在所述接觸襯墊之上；以及 第一包封體，在側向上包封所述金屬通孔，其中所述第一包封體接觸所述金屬通孔的側壁，其中所述金屬通孔的所述側壁與所述第一包封體之間的界面在與所述金屬通孔的頂表面相鄰之處不含有錫。
  18. 如申請專利範圍第17項所述的封裝件，其中所述第一包封體包含具有第一熱膨脹係數的第一材料，其中所述金屬通孔包含具有第二熱膨脹係數的第二材料，其中所述第一熱膨脹係數對所述第二熱膨脹係數的比率介於0.5:1與2.5:1之間。
  19. 如申請專利範圍第17項所述的封裝件，其中所述第一包封體具有為250℃或低於250℃的固化溫度。
  20. 如申請專利範圍第17項所述的封裝件，其中所述第一包封體設置在所述嵌入式晶粒的側向範圍以內，其中所述嵌入式晶粒在側向上被第二包封體包封。
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