TW201933499A - Wiring substrate and stackable semiconductor assembly using the same and method of making the same - Google Patents

Abstract

The wiring substrate includes a cavity and a plurality of metal leads disposed around the cavity. The metal leads are bonded with a resin compound and provide horizontal and vertical routing for a semiconductor device to be disposed in the cavity. The resin compound fills in spaces between the metal leads and surrounds the cavity and provides a dielectric platform for a re-distribution layer or a build-up circuitry optionally deposited thereon.

Description

Circuit substrate, stacked semiconductor assembly and manufacturing method thereof

The present invention relates to a circuit substrate, a semiconductor assembly thereof and a manufacturing method thereof, and more particularly to a circuit substrate provided with a series of metal leads surrounding a cavity, and a stacked semiconductor assembly using the circuit substrate and a manufacturing method thereof. Metal leads can be used as vertical interconnect channels.

The market trend of multimedia devices tends to be faster and thinner. One method is to assemble multiple components on a circuit board in a stacked manner, so that the electrical performance can be improved and the size can be reduced. U.S. Patent No. 7,894,203 discloses a circuit substrate with a recess for this purpose. The substrate is formed by bonding two separated components to each other by an adhesive, and an electrical connection is formed between the two components through a conductive material (such as solder or a conductive bump). Because the substrate is a stacked structure, the mismatch in thermal expansion coefficient or warpage between the two components will cause misalignment or solder cracking, which results in the disadvantage of such a stacked structure having poor reliability in practical applications. Alternatively, as described in U.S. Patent No. 7,989,950, solder balls can be connected on the substrate to form vertical connection channels, and the vertical connection channels can be sealed by a buried process to form a cavity. In addition, solder deformation and cracking may occur during the embedding process, or peeling between the sealing material and the substrate after thermal cycling, which causes problems such as sudden failure of components and failure to connect to I / O.

For the above reasons and other reasons described below, there is an urgent need to develop a circuit substrate with integrally formed metal leads, where the metal leads extend from the bottom to the bottom of the circuit substrate for use in a three-dimensional stacked semiconductor assembly.

It is an object of the present invention to provide a circuit substrate whose recess can be formed by etching a sacrificial metal block at a predetermined position. Since the resin compound mechanically supports and completely surrounds the sacrificial metal block, once a selected part of the metal is removed, a cavity having a predetermined size and depth and surrounded by the resin compound can be formed, and then an element can be set in the cavity , And least to make the final group too thick.

Another object of the present invention is to provide a circuit substrate whose vertical stacking channel is formed by providing a plurality of metal leads to surround the cavity. Therefore, a component disposed in the cavity can be stacked with another component through a metal lead without the need for other external interconnections.

Yet another object of the present invention is to provide a circuit substrate in which all components are bonded to each other by a resin compound, so that a stable mechanical structure can be obtained to ensure that solder cracking, warping or misalignment does not occur during thermal cycling. .

Yet another object of the present invention is to provide a circuit substrate, which optionally has a routing circuit, so that electrical signals can be re-routed from leads located at edges to designated locations, and the electrical characteristics of the semiconductor group can be greatly improved. .

According to the above and other objectives, the present invention provides a method for manufacturing a circuit substrate, which includes the following steps: providing a metal frame, a metal block, and a plurality of metal leads, wherein the metal block is located in the metal frame, and the metal leads Integrally connected to the metal frame, and each of the metal leads has an inner end, the inner end is facing inwardly toward the metal frame, and toward the metal block; a resin compound is provided, which fills the remaining in the metal frame Space, and the top surface of the resin compound is substantially coplanar with the metal leads and the top side of the metal block; and removing at least a selected portion of the metal block to form a cavity, wherein the cavity The entrance is located at the top surface of the resin compound. The manufacturing method of the circuit substrate may optionally further include the following steps: forming a top redistribution layer on the top surface of the resin compound, and the top redistribution layer is electrically coupled to the metal leads; and / or A bottom build-up circuit is formed on the bottom surface of the resin compound, and the bottom build-up circuit is electrically coupled to the metal leads. In addition, the present invention also provides a method for manufacturing a stacked semiconductor assembly, which includes the following steps: providing the circuit substrate by the above-mentioned manufacturing method, and arranging a semiconductor element in the cavity of the circuit substrate, and borrowing A bonding wire is used to electrically couple the semiconductor element to the circuit substrate.

Unless specifically described or steps must occur sequentially, the order of the above steps is not limited to the above, and can be changed or rearranged according to the desired design.

Accordingly, the present invention may provide a circuit substrate including a plurality of metal leads, each of which has an inner end and an outer end, wherein the inner end faces a predetermined area, and the outer end is more than the The inner end is farther away from the predetermined area; a resin compound fills the space between the metal leads and extends laterally beyond the inner ends of the metal leads, and then extends into the predetermined area to surround the predetermined area. A cavity in which the top surface of the resin compound and the top side of the metal leads are substantially coplanar; and a cushion layer covering a bottom of the cavity, wherein the thickness of the cushion layer is less than that of the resin compound And the thickness of the metal leads, and the bottom surface of the cushion layer and the bottom surface of the resin compound are substantially coplanar. The circuit substrate may optionally further include: a top redistribution layer on the top surface of the resin compound, and the top redistribution layer is electrically coupled to the metal leads; and / or a bottom buildup circuit on the The bottom surface of the resin compound, and the bottom build-up circuit is electrically coupled to the metal leads. In addition, the present invention also provides a stacked semiconductor assembly, which includes a semiconductor element disposed in the cavity of the circuit substrate, and is electrically coupled to the circuit substrate through a bonding wire.

The circuit substrate of the present invention, its three-dimensional stacked semiconductor assembly and its manufacturing method have many advantages. For example, the method of providing a metal lead around the cavity is particularly advantageous because the semiconductor element can be disposed in the cavity, and the metal lead can be electrically connected to the semiconductor element through a bonding wire, and the metal The leads can provide horizontal routing and vertical connection paths between opposite sides of the circuit board. Since the semiconductor element is disposed in the cavity, there is no need to perform additional wheel grinding or polishing steps on the semiconductor element in order to achieve the characteristics of the ultra-thin vertically stacked semiconductor group body. Bonding a resin compound to a metal lead provides a complete platform on which high-resolution circuits can be deposited. Forming a top redistribution layer on a resin compound can improve the wiring flexibility of the circuit substrate, and can enable components with fine pad pitch, such as flip-chip wafers and surface mount components, to be assembled on the circuit substrate. And interconnected to the metal leads through the top redistribution layer.

The above and other features and advantages of the present invention can be made clearer by the following detailed description of the preferred embodiments.

In the following, examples will be provided to explain the aspects of the present invention in detail. The advantages and effects of the present invention will be more significant by the content disclosed by the present invention. The attached drawings are simplified and used for illustration. The number, shape and size of the components shown in the drawings can be modified according to the actual situation, and the configuration of the components may be more complicated. The present invention can also be practiced or applied in other aspects, and various changes and adjustments can be made without departing from the spirit and scope defined by the present invention.

[Example 1]

FIG. 1-16 is a diagram of a method for manufacturing a semiconductor assembly in the first embodiment of the present invention, which includes a plurality of metal leads, a metal pad, a metal film, a resin compound, a semiconductor element, a plurality of bonding wires, and a mold. Sealing material.

FIG. 1, FIG. 2, and FIG. 3 are a schematic sectional view, a top perspective view, and a bottom perspective view of the patterned metal plate 10, respectively. The patterned metal plate 10 is generally made of a copper alloy, steel, or alloy 42, which can be formed by a wet etching or stamping / punching process on a rolled metal strip. Wherein the rolled metal strip has a thickness ranging from about 0.15 mm to about 1.0 mm. Here, an etching process may be performed on one or both sides to etch through the metal strip to form the metal strip into a patterned metal plate 10 having a predetermined entire pattern, which includes a metal frame 11, a plurality of metal leads 13, and a metal block. 15 and plural coupling rods 16. The metal leads 13 extend laterally from the metal frame 11 toward a central region in the metal frame 11. Therefore, each metal lead 13 has an outer end 131 and an inner end 133. The outer end 131 of the metal lead 13 is integrally connected to the inner side wall of the metal frame 11, and the inner end 133 of the metal lead 13 faces away inward. Metal frame 11. The metal block 15 is located in a central region within the metal frame 11 and is connected to the metal frame 11 by a connecting rod 16. In addition, the specific embodiment further performs a selective half-etching process from the bottom side of the patterned metal plate 10. Accordingly, the metal leads 13 have a stepped peripheral edge, and each metal lead 13 has a horizontally extending portion 136 and a vertically protruding portion 137. The vertical protruding portion 137 is directed downward and protrudes from the lower surface of the horizontal extending portion 136.

4, 5, and 6 are a schematic cross-sectional view, a top perspective view, and a bottom perspective view of the resin compound 30, respectively. The resin compound 30 can be formed by coating a resin material in the remaining space in the metal frame 11, wherein the resin material can be formed by paste printing, compression molding, and transfer molding. ), Liquid injection molding, spin coating or other suitable methods. Next, a heat treatment (or a thermosetting process) is performed to harden the resin material to convert the resin material into a solid molding compound. Accordingly, the resin compound 30 covers the lower surface of the horizontally extending portion 136, the side wall of the vertical protruding portion 137, and the side wall of the metal block 15. Since the metal lead 13 has a stepped cross-sectional profile, the resin compound 30 can be firmly bonded to the metal lead 13 to prevent the metal lead 13 from detaching from the resin compound 30 in a vertical direction, and avoid forming a crack at the interface in a vertical direction. . In this illustration, through the planarization step, the top surface 301 of the resin compound 30 and the top side 101 of the metal lead 13 and the metal block 15 are substantially coplanar, and the bottom surface 303 of the resin compound 30 and the metal lead 13 And the bottom side 103 of the metal block 15 is substantially coplanar.

The resin compound 30 generally includes a binder resin, a filler, a hardener, a diluent, and an additive. The bonding resin used in the present invention is not particularly limited. For example, the adhesive resin can be selected from epoxy resin, phenol resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, acrylic resin, and bismaleimide. , BMI) at least one of the groups of resins and their equivalents. Adhesive resin can provide close adhesion between the adhesive and the filler. The adhesive resin can also be linked by a chain of fillers to provide thermal conductivity. In addition, the binding resin can also improve the physical and chemical stability of the molding compound.

In addition, the filler used in the present invention is not particularly limited. For example, a thermally conductive filler can be used, which is selected from the group consisting of alumina, aluminum nitride, silicon carbide, tungsten carbide, boron carbide, silicon dioxide, and their equivalents. More specifically, if an appropriate filler is dispersed therein, the resin compound 30 may become thermally conductive or have a low coefficient of thermal expansion (CTE). For example, aluminum nitride (AlN) or silicon carbide (SiC) has a relatively high thermal conductivity, a relatively high electrical resistance, and a relatively low thermal expansion coefficient. Accordingly, when such a material is used as a filler in the resin compound 30, the resin compound 30 can exhibit better heat dissipation efficiency and electrical insulation efficiency, and its low CTE characteristic can prevent peeling or cracking of the circuit or interface. The maximum particle diameter of the thermally conductive filler can be 25 μm or less. The content of the filler can be in the range of 10 to 90 weight percent. If the content of the thermally conductive filler is less than 10% by weight, the thermal conductivity may be insufficient and the viscosity may be too low. Low viscosity means that during coating or molding, the resin is too easy to flow out of the tool, making the process difficult to operate and control. On the other hand, if the content of the filler is more than 90% by weight, the adhesive strength of the molding material may be reduced, and the viscosity may be too high. High-viscosity molding materials have poor workability because the resin cannot flow out of the tool during coating or molding. In addition, the resin compound 30 may include more than one filler. For example, polytetrafluoroethylene (PTFE) can be used as the second filler to further improve the electrical insulation characteristics of the resin compound 30. In short, the resin compound 30 preferably has an elastic modulus of more than 1.0 GPa and a linear thermal expansion coefficient in a range of about 5 x 10 ^-6 K ^-1 to 15 x 10 ^-6 K ^-1 .

7, 8 and 9 are a schematic cross-sectional view, a top perspective view and a bottom perspective view, respectively, after the metal block 15 is selectively removed. Various techniques can be used to selectively remove the metal block 15, such as wet etching, electrochemical etching, or laser, thereby forming a cavity 305, wherein the entrance of the cavity 305 is located on the top surface 301 of the resin compound 30 . The remaining portion of the metal block 15 is composed of a metal pad 156 and a metal film 158. The top surface 152 of the metal pad 156 is the bottom of the cavity 305, and the bottom surface 153 of the metal pad 156 is substantially coplanar with the bottom surface 303 of the resin compound 30 and the bottom side 101 of the metal lead 13. The metal film 158 is located on the inner surface of the resin compound 30 and is integrated with the metal pad 156 and surrounds the cavity 305 laterally. According to this, the uncut circuit substrate 100 is completed at this stage, and includes the metal frame 11, the metal lead 13, the metal pad 156, the metal film 158, the connecting rod 16, and the resin compound 30.

10 and 11 are a schematic cross-sectional view and a top perspective view of a semiconductor element 61 electrically coupled to the circuit substrate 100, respectively. The semiconductor device 61 (shown as a wafer) is disposed face-up in the cavity 305 and is attached to the metal pad 156 and is electrically coupled to the metal lead 13 and the metal film 158 through the bonding wire 71. According to this, the semiconductor element 61 can be thermally connected to the metal pad 156 and electrically coupled to the metal lead 13 through the bonding wire 71 to form a signal route. At the same time, the semiconductor element 61 is electrically coupled to the metal film 158 through the bonding wire 71. In order to form a ground connection, the bonding wire 71 can usually be electrically connected to the metal lead 13 and the metal film 158 by gold or copper ball bonding or gold or aluminum wedge bonding. .

12 and 13 are a schematic cross-sectional view and a top perspective view, respectively, of a molding material 81 provided. A molding material 81 may be selectively provided to cover and bury the semiconductor element 61 and the bonding wire 71 from above, and the molding material 81 further extends into the gap between the semiconductor element 61 and the inner wall of the cavity 305.

14, 15, and 16 are a schematic cross-sectional view, a top perspective view, and a bottom perspective view of the semiconductor assembly 110 after the metal frame 11 is removed, respectively. The metal frame 11 can be separated from the outer end 131 of the metal lead 13 by various methods including chemical etching, mechanical cutting / cutting or sawing. Accordingly, the outer end 131 of the metal lead 13 is located at the peripheral edge of the circuit substrate 100 after cutting, and the side surface of the outer end 131 of the metal lead 13 is flush with the peripheral edge of the resin compound 30.

17 and 18 are a schematic cross-sectional view and a top perspective view of a three-dimensional stacked semiconductor package, respectively, which have two semiconductor groups 110 shown in FIG. 14, and the semiconductor groups 110 are electrically connected to each other through solder balls 85. . The upper semiconductor group 110 passes through the solder balls 85 and is stacked and electrically coupled to the lower semiconductor group 110. The solder balls 85 are in contact with the metal lead 13 vertical protrusions 137 of the upper semiconductor group 110 and the lower semiconductor group 110.的 金属 线 13Horizontal extension 136.

FIG. 19 is a schematic cross-sectional view of another semiconductor group 120. A semiconductor element 90 is electrically coupled to the circuit substrate 100 shown in FIG. 7. The semiconductor device 90 includes a routing circuit 91, a reinforcing layer 93, a first wafer 94 and a second wafer 95. The routing circuit 91 is shown as a multilayer build-up circuit, which includes a dielectric layer 911 and a circuit layer 913. The thickness of the dielectric layer 911 is usually 0.5 micrometers, and may be made of epoxy resin, glass epoxy resin, polyimide, or the like. The circuit layer 913 is usually made of copper and extends laterally on the dielectric layer 911 and includes a conductive blind hole 914 extending through the dielectric layer 911. In this figure, the routing circuit 91 can provide a first conductive pad 915 and a terminal pad 917 at the top surface 901 and a second conductive pad 919 at the bottom surface 903. The pad size and pad pitch of the terminal pad 917 are larger than the pad size and pad pitch of the first conductive pad 915, and the second conductive pad 919 is exposed through the opening 935 of the reinforcing layer 93 (on the bottom surface 903 of the routing circuit 91). The reinforcing layer 93 may be made of resin, ceramic, metal, metal composite, or a single-layer or multi-layer circuit structure having sufficient mechanical strength to provide mechanical support for the routing circuit 91. The first chip 94 is electrically coupled to the top surface 901 of the routing circuit 91, and the second chip 95 is disposed in the cavity 907 formed by the bottom surface 903 of the routing circuit 91 and the inner wall 905 of the opening 935 of the reinforcing layer 93 and is electrically Coupled to the bottom surface 903 of the routing circuit 91. In this embodiment, the first chip 94 passes through the first conductive bump 943 and is electrically coupled to the first conductive pad 915 of the routing circuit 91, and the second chip 95 passes through the second conductive bump 953. The second conductive pad 919 is coupled to the routing circuit 91 and attached to the metal pad 156. The routing circuit 91 is electrically connected to the circuit substrate 100 through a bonding wire 71. The bonding wire 71 is connected to the terminal pad 917 of the routing circuit 91 and the metal lead 13 of the circuit substrate 100. According to this, the first chip 94 and the second chip 95 can be electrically connected to each other through the routing circuit 91, and further electrically connected to the circuit substrate 100 through the bonding wire 71.

20 and 21 are respectively a schematic sectional view and a top perspective schematic view of another aspect of an uncut circuit substrate in the first embodiment of the present invention. The uncut circuit substrate 130 is similar to the structure shown in FIGS. 7-9 except that the inner surface of the resin compound 30 does not have a metal film. Therefore, the recess 305 is formed by the top surface of the metal pad 156 and the inner sidewall surface of the resin compound 30.

22 and 23 are a schematic cross-sectional view and a top perspective view of the semiconductor element 61 electrically coupled to the circuit substrate 130, respectively. The semiconductor element 61 is disposed in the cavity 305 with the surface facing upward, is attached to the metal pad 156, and is electrically coupled to the metal lead 13 through a bonding wire 71.

24 and 25 are a schematic cross-sectional view and a top perspective view, respectively, of a molding material 81 provided. A molding material 81 may be selectively provided to cover and bury the semiconductor element 61 and the bonding wire 71 from above, and the molding material 81 further extends into the gap between the semiconductor element 61 and the inner wall of the cavity 305.

26, 27, and 28 are a schematic cross-sectional view, a top perspective view, and a top perspective view of the semiconductor assembly 140 after the metal frame 11 is removed, respectively. The metal frame 11 can be separated from the outer end 131 of the metal lead 13 by various methods including chemical etching, mechanical cutting / cutting or sawing. By separating the metal frame 11, the connection between the outer ends 131 of the metal leads 13 can be cut. Accordingly, the circuit board 130 includes a metal lead 13, a metal pad 156, a connecting rod 16, and a resin compound 30.

29 and 30 are a schematic cross-sectional view and a top perspective view of a three-dimensional stacked semiconductor package, respectively, which have two semiconductor groups 140 as shown in FIGS. 26-28, and the semiconductor groups 140 are electrically connected to each other through solder balls 85. Sexual connection. The upper semiconductor group 140 is stacked and electrically coupled to the lower semiconductor group 140 through the solder balls 85.

FIG. 31 is a schematic cross-sectional view of another semiconductor group 150. A semiconductor element 90 is electrically coupled to the circuit substrate 130 shown in FIG. 20. The semiconductor device 90 includes a routing circuit 91, a reinforcing layer 93, a first wafer 94 and a second wafer 95. The routing circuit 91 is shown as a multilayer build-up circuit, which includes dielectric layers 911 and circuit layers 913 formed alternately and alternately. The first chip 94 is electrically coupled to the routing circuit 91 from the top surface 901 of the routing circuit 91, and the second chip 95 is electrically coupled to the routing circuit 91 from the bottom surface 903 of the routing circuit 91. In this embodiment, the first chip 94 passes through the first conductive bump 943 and is electrically coupled to the first conductive pad 915 of the routing circuit 91, and the second chip 95 passes through the second conductive bump 953. The second conductive pad 919 is coupled to the routing circuit 91 and attached to the metal pad 156. The routing circuit 91 is electrically connected to the circuit substrate 130 through a bonding wire 71. The bonding wire 71 is connected to the terminal pad 917 of the routing circuit 91 and the metal lead 13 of the circuit substrate 130. The reinforcing layer 93 covers the bottom surface 903 of the routing circuit 91, and surrounds and covers the second wafer 95 in the same shape. Alternatively, the reinforcing layer 93 may be omitted.

32 and 33 are a schematic cross-sectional view and a top perspective view of another aspect of the circuit board after cutting according to the first embodiment of the present invention. The circuit substrate 160 in this aspect includes a plurality of metal leads 13, a metal pad 156, a metal film 158, a plurality of connecting rods 16, a resin compound 30, and a top redistribution layer 51. The thickness of the metal pad 156 is smaller than the thickness of the metal lead 13 and the thickness of the resin compound 30. The metal film 158 is integrally formed with the metal pad 156 and is made of the same material, and the metal film 158 is connected to the connecting rod 16. A top surface of the metal pad 156 and a side surface of the metal film 158 form a cavity 305. The resin compound 30 provides a stable mechanical bonding force between the metal leads 13, and is bonded to the metal pad 156 and the metal film 158, and provides a dielectric platform for depositing the top redistribution layer 51. The top redistribution layer 51 is formed on the top surface 301 of the resin compound 30 by a metal pattern deposition method described below, and is electrically coupled to the metal lead 13.

First, before forming the cavity 305, the top surface of the structure can be metallized by various techniques (such as electroplating, electroless plating, evaporation, sputtering, or a combination thereof) to form a single or multiple conductive layer (typically For copper). The conductive layer may be made of Cu, Ni, Ti, Au, Ag, Al, a combination thereof, or other suitable conductive materials. Generally, a seed layer is formed on the topmost surface of the structure before the conductive layer is plated to a desired thickness. The seed layer can be formed by a diffusion resistance layer and a plating bus layer. The diffusion resistance layer is used to offset oxidation or erosion of the conductive layer (such as copper). In most examples, the diffusion barrier layer can be used as an adhesion-reinforcing layer for the underlying material, and can be formed by physical vapor deposition (PVD). For example, sputtering can form Ti or TiW layer. However, the diffusion barrier layer can also be made of other materials, such as TaN or other suitable materials, and its thickness is not limited to the above range. The plating carrier layer is usually made of the same material as the conductive layer and has a thickness ranging from about 0.1 μm to 1 μm. For example, when the conductive layer is copper, the plating carrier layer is preferably a copper thin film made by physical vapor deposition or electroless plating. However, the electroplated support layer can also be made of other suitable materials, such as silver, gold, chromium, nickel, tungsten, or a combination thereof, and its thickness is not limited to the above range.

After the seed layer is deposited, a photoresist layer (not shown) is formed on the seed layer. The photoresist layer can be formed by a wet process (such as a spin coating process) or a dry process (such as a lamination dry film). After the photoresist layer is formed, the photoresist layer is patterned to form openings, and then the openings are filled with a covering metal (such as copper) to form a top redistribution layer 51. The thickness of the cladding metal layer usually ranges from about 10 μm to 100 μm. After the metal is plated, the exposed seed layer is removed through an etching process to form conductive wires that are electrically isolated from each other. In this illustration, the top redistribution layer 51 is a top patterned metal layer 515 having a uniform thickness, which laterally extends from the top surface 301 of the resin compound 30 and the top side 101 of the metal lead 13.

34 and 35 are a schematic cross-sectional view and a top perspective view of the semiconductor assembly 170, respectively. The semiconductor element 61 and the passive element 65 are electrically connected to the circuit substrate 160 shown in FIGS. 32 and 33. The semiconductor device 61 is attached to the metal pad 156 and is electrically coupled to the metal film 158 and the top redistribution layer 51 through a bonding wire 71. The passive component 65 is connected to the resin compound 30 and is electrically coupled to the top redistribution layer 51. A molding compound 81 may be selectively provided to cover and bury the semiconductor element 61 and the bonding wire 71 from above.

36 is a schematic cross-sectional view of a three-dimensional stacked semiconductor package, which has two semiconductor groups 170 as shown in FIG. 34, and the semiconductor groups 170 are electrically connected to each other through solder balls 85. The upper semiconductor group 170 passes through the solder balls 85 and is stacked and electrically coupled to the lower semiconductor group 170. The solder balls 85 are in contact with the metal leads 13 of the upper semiconductor group 170 and the top redistribution layer of the lower semiconductor group 170. 51.

37 is a schematic cross-sectional view of another aspect of an uncut circuit substrate in the first embodiment of the present invention. The uncut circuit substrate 180 is similar to the structure shown in FIG. 32, except that it further includes an electrical component 20 embedded in the resin compound 30, and the metal frame 11 has not been separated from the metal lead 13. Here, the electrical component 20 is installed in the metal frame 11 before the resin compound 30 is provided. In this embodiment, the thickness of the electrical component 20 is smaller than the thickness of the metal lead 13 and the thickness of the resin compound 30. The top side 201 of the electrical component 20 is substantially the same as the top side 101 of the metal lead 13 and the top surface 301 of the resin compound 30 flat. The electrical component 20 may be a resistor, a capacitor, an inductor, or any other passive or active component. The top redistribution layer 51 extends laterally on the top surface 301 of the resin compound 30, the top side 101 of the metal lead 13, and the top side 201 of the electrical component 20. Accordingly, the top redistribution layer 51 can electrically couple the electrical component 20 to the metal lead 13.

[Example 2]

38-45 are diagrams of a method for fabricating a circuit substrate with a top build-up circuit in a second embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiment 1 is incorporated herein, and it is not necessary to repeat the same description.

38 and 39 are a schematic cross-sectional view and a bottom perspective view of the structure of FIG. 4 after the metal frame 11 is removed. The metal frame 11 can be removed by various methods including chemical etching, mechanical cutting / cutting or sawing. By separating the metal frame 11, the connection between the metal leads 13 can be cut. Accordingly, the patterned metal plate 10 includes a metal lead 13, a metal block 15, and a connecting rod 16.

40 and 41 are a schematic cross-sectional view and a bottom perspective view of a dielectric layer 531 formed on the patterned metal plate 10 and the resin compound 30, and a first blind hole 533 and a second blind hole 534 formed in the dielectric layer 531, respectively. The dielectric layer 531 is usually formed by pressure bonding or coating. The dielectric layer 531 contacts the patterned metal plate 10 and the resin compound 30, and is covered from below and extends laterally on the patterned metal plate 10 and the resin compound 30. After the dielectric layer 531 is formed, various techniques are used to form the first blind hole 533 and the second blind hole 534, such as laser drilling, plasma etching, and lithography. The first blind hole 533 and the second blind hole 534 generally have a diameter of 50 micrometers and extend through the dielectric layer 531. Pulse lasers can be used to improve laser drilling performance. Alternatively, a scanning laser beam can be used with a metal mask. The first blind hole 533 is aligned with a selected portion of the metal lead 13, and the second blind hole 534 is aligned with a selected portion of the metal block 15.

42 and 43 are a schematic cross-sectional view and a bottom perspective view of a bottom patterned metal layer 535 formed on the dielectric layer 531 through a metal deposition and metal patterning process, respectively. The bottom patterned metal layer 535 extends downward from the metal lead 13 and the metal block 15 and fills the first blind hole 533 and the second blind hole 534 to form a first contact directly contacting the metal lead 13 and the metal block 15 respectively. The metallized blind hole 537 and the second metallized blind hole 538 extend laterally on the dielectric layer 531 at the same time. Therefore, the bottom patterned metal layer 535 can provide horizontal signal routing in the X and Y directions and vertical routing through the first blind hole 533 and the second blind hole 534.

At this stage, the fabrication of the bottom build-up circuit 53 is completed. In this figure, the bottom build-up circuit 53 includes a dielectric layer 531 and a bottom patterned metal layer 535.

44 and 45 are a schematic cross-sectional view and a top perspective view respectively after the metal block 15 is selectively removed. The metal block 15 is selectively removed to form a cavity 305. Here, the remaining portion of the metal block 15 includes a metal pad 156 and a metal film 158. The metal pad 156 is located at the bottom of the cavity 305 and thermally conducts to the bottom build-up circuit 53 through the second metallized blind hole 538 as a heat pipe. The metal pad 156 can also be electrically connected to the metal lead 13 through the bottom build-up circuit 53 to achieve the purpose of grounding. The metal film 158 is integrally formed with the metal pad 156, and the metal film 158 surrounds the cavity 305 laterally. Accordingly, the completed circuit board 200 includes the metal lead 13, the metal pad 156, the metal film 158, the connecting rod 16, the resin compound 30, and the bottom build-up circuit 53.

46 and 47 are a schematic cross-sectional view and a top perspective view of the semiconductor assembly 210 after the semiconductor element 61 is electrically coupled to the circuit substrate 200 and packaged with a molding compound 81, respectively. The semiconductor element 61 is attached to the metal pad 156 and is electrically coupled to the metal lead 13 and the metal film 158 through the bonding wire 71. According to this, the semiconductor element 61 can be thermally connected to the metal pad 156 and electrically coupled to the bottom build-up circuit 53 through the metal lead 13. Optionally, a molding compound 81 may be further provided to cover and bury the semiconductor element 61 and the bonding wire 71 from above.

FIG. 48 is a schematic cross-sectional view of a three-dimensional stacked semiconductor package. The semiconductor group 110 shown in FIG. 14 is stacked on the semiconductor group 210 shown in FIG. 46 through solder balls 85. The upper semiconductor group body 110 is stacked and electrically coupled to the lower semiconductor group 210 through the solder balls 85. In addition, an additional solder ball 87 can be selectively connected to the bottom build-up circuit 53 of the lower semiconductor group 210.

FIG. 49 is a schematic cross-sectional view of another semiconductor group 220. The semiconductor element 90 is electrically coupled to the circuit substrate 200 shown in FIG. 44. The semiconductor device 90 is similar to the structure shown in FIG. 31 except that it further includes a passive device 97 and a metal pillar 98. The passive element 97 and the metal pillar 98 are electrically coupled to the routing circuit 91 from the bottom surface 903 of the routing circuit 91. In this figure, the second chip 95 is thermally conducted to the metal pad 156 for heat dissipation, and the metal pillar 98 is electrically connected to the metal pad 156 to form a ground connection. The routing circuit 91 is electrically connected to the circuit substrate 200 through a bonding wire 71. The bonding wire 71 is connected to the routing circuit 91 of the semiconductor element 90 and the metal lead 13 of the circuit substrate 200. The reinforcing layer 93 also surrounds, covers uniformly and surrounds the passive element 97 and the metal pillar 98.

[Example 3]

50-61 are diagrams of a method for manufacturing a semiconductor assembly in which a semiconductor element is attached to a resin pad in a third embodiment of the present invention.

For the purpose of brief description, any description that can be used for the same application in the above embodiments is incorporated herein, and it is not necessary to repeat the same description.

FIG. 50 is a schematic cross-sectional view of the patterned metal plate 10. The patterned metal plate 10 is similar to the structure shown in FIGS. 1-3 except that it does not have a connecting rod, and the thickness of the metal block 15 is smaller than the thickness of the metal frame 11 and the thickness of the metal lead 13.

51 and 52 are a schematic sectional view and a bottom perspective view of the resin compound 30 and the resin pad 40, respectively. The resin compound 30 covers the lower surface of the horizontally extending portion 136, the side wall of the vertical protruding portion 137, and the side wall of the metal block 15. The resin pad 40 covers the bottom side 153 of the metal block 15 from below, and is integrally molded with the resin compound 30. The resin compound 30 and the resin pad 40 may be integrally formed by coating a resin material with the remaining space in the metal frame 11. Through the planarization step, the bottom surface 403 of the resin pad 40 may be substantially coplanar with the bottom surface 303 of the resin compound 30, the bottom side 103 of the metal frame 11, and the bottom side 103 of the metal lead 13.

53 and 54 are a schematic cross-sectional view and a top perspective view after the metal block 15 is removed, respectively. Here, the metal block 15 is entirely removed to form a cavity 305, and the top surface 401 of the resin pad 40 is exposed from the cavity 305. The uncut circuit substrate 300 completed at this stage includes a metal frame 11, a metal lead 13, a resin compound 30 and a resin pad 40.

55 and 56 are a schematic cross-sectional view and a top perspective view of the semiconductor element 61 electrically coupled to the circuit substrate 300, respectively. The semiconductor element 61 is disposed in the cavity 305 with the surface facing upward, is attached to the resin pad 40, and is electrically coupled to the metal lead 13 through a bonding wire 71.

57 and 58 are a schematic cross-sectional view and a top perspective view, respectively, of a molding compound 81 provided. A molding compound 81 may be selectively provided to cover and bury the semiconductor element 61 and the bonding wire 71 from above.

59, 60, and 61 are a schematic cross-sectional view, a top perspective view, and a bottom perspective view of the semiconductor assembly 310 after the metal frame 11 is removed, respectively. The metal frame 11 can be removed by various methods including chemical etching, mechanical cutting / cutting or sawing. By separating the metal frame 11, the connection between the metal leads 13 can be cut. Accordingly, the circuit board 300 includes a metal lead 13, a resin compound 30, and a resin pad 40.

62 and 63 are a schematic cross-sectional view and a top perspective view of a three-dimensional stacked semiconductor package, respectively, which have two semiconductor groups 310 as shown in FIG. 59, and the semiconductor groups 310 are electrically connected to each other through solder balls 85. . The upper semiconductor group body 310 is stacked and electrically coupled to the lower semiconductor group body 310 through the solder balls 85.

FIG. 64 is a schematic cross-sectional view of another semiconductor group 320. The semiconductor element 90 is electrically coupled to the circuit substrate 300 shown in FIG. 53 through a bonding wire 71. The semiconductor element 90 is similar to the semiconductor element structure in FIG. 49 except that (i) the first chip 94 is electrically connected to the routing circuit 91 through a bonding wire 945, and (ii) the third chip 96 is further provided. The third conductive bump 963 is electrically coupled to the routing circuit 91, (iii) the unembedded metal pillar 98 in the reinforcing layer 93. Accordingly, the first chip 94, the second chip 95, and the third chip 96 can be electrically connected to the circuit substrate 300 through the routing circuit 91 and the bonding wires 71 connected to the routing circuit 91 and the metal lead 13.

65 is a schematic cross-sectional view of another aspect of a circuit substrate in a third embodiment of the present invention. The circuit substrate 330 in this aspect includes a plurality of metal leads 13, a resin compound 30, a resin pad 40, and a top redistribution layer 51. The top surface of the resin pad 40 and the surface of the inner wall of the resin compound 30 form a cavity 305. The top redistribution layer 51 is formed on the top surface 301 of the resin compound 30 and is electrically coupled to the metal lead 13. In this figure, the top redistribution layer 51 is a top patterned metal layer.

66 is a schematic cross-sectional view of another aspect of a circuit substrate in a third embodiment of the present invention. The circuit substrate 340 in this aspect is similar to the structure shown in FIG. 65, except that it further includes a metal layer 46 on the top surface of the resin pad 40. In this aspect, the metal layer 46 is formed by selectively removing the metal block 15 in FIG. 51, so as to retain the remaining portion of the metal block 15 on the resin pad 40.

FIG. 67 is a schematic sectional view of another aspect of a circuit substrate in a third embodiment of the present invention. The circuit substrate 350 in this aspect is similar to the structure shown in FIG. 66, except that it further includes a metal film 48 on the inner sidewall surface of the resin compound 30, and further includes a bottom build-up circuit 53 on the bottom surface 303 of the resin compound 30 and On the bottom surface 403 of the resin pad 40, the bottom build-up circuit 53 is electrically coupled to the metal lead 13. The metal layer 46 and the metal film 48 are integrally formed by selectively removing the metal block 15 in FIG. 51 so that the remaining portion of the metal block 15 is retained on the top surface of the metal pad 40 and the surface of the inner wall of the resin compound. In this figure, the bottom build-up circuit 53 includes a dielectric layer 531 and a bottom patterned metal layer 535 that are alternately formed. The dielectric layer 531 contacts the metal lead 13, the resin compound 30, and the resin pad 40, and covers and extends laterally on the metal lead 13, the resin compound 30, and the resin pad 40 from below. The bottom patterned metal layer 535 extends laterally on the dielectric layer 531 and includes a first metallized blind hole 537 contacting the metal lead 13.

FIG. 68 is a schematic cross-sectional view of a semiconductor assembly 360, in which a semiconductor element 61 and a passive element 65 are electrically connected to the circuit substrate 350 shown in FIG. 67. The semiconductor device 61 is attached to the metal layer 46 and is electrically coupled to the top redistribution layer 51 through a bonding wire 71. According to this, the semiconductor element 61 can be connected to the bottom build-up circuit 53 through the bonding wire 71, the top redistribution layer 51, and the metal lead 13, and the passive element 65 is connected to the resin compound 30 and electrically coupled to the top weight布 层 51。 Cloth layer 51. In addition, a molding compound 81 may be selectively provided so as to cover and bury the semiconductor element 61, the passive element 65, and the bonding wire 71 from above.

As shown in the above embodiment, the present invention constructs a unique circuit substrate having a cavity surrounded by a metal lead. The circuit substrate of the present invention includes: a plurality of metal leads, each metal lead having an inner end and an outer end, wherein the inner end faces a predetermined area, and the outer end is farther from the predetermined area than the inner end; a resin A compound that fills the space between the metal leads and extends laterally beyond the inner ends of the metal leads, and then extends into the predetermined area to surround a cavity at the predetermined area, wherein the top of the resin compound The surface is substantially coplanar with the top side of the metal leads; and a pad layer adjacent to the bottom of the cavity, wherein the thickness of the pad layer is less than the thickness of the resin compound and the metal leads, and the pad The bottom surface of the layer is substantially coplanar with the bottom surface of the resin compound. In a preferred embodiment, the metal leads are separated from the metal frame and can provide horizontal and vertical signal transmission paths, or provide ground / power planes for energy transfer and return; the resin compound surrounds the cavity, and It is bonded to a metal wire, and the inner side wall surface of the resin compound extends beyond the top surface of the cushion layer; the cavity is formed by selectively removing the metal block or the entire metal block; the cushion layer may be a metal pad or a resin Pad, covering the bottom of the cavity, and surrounded by a resin compound.

Each metal lead is preferably an integrally formed lead, and can be separated from the metal frame after the resin compound is provided. The metal lead separated from the metal frame may have a top side, a bottom side, and an outer side surface perpendicular to the top side and the bottom side that are not covered by the compound layer. In a preferred embodiment, the thickness of the metal lead ranges from about 0.15 mm to 1.0 mm, and the perimeter of the metal lead preferably extends at least laterally to coincide with the periphery of the resin compound. In order to securely bond the metal lead and the resin compound, the metal lead may have a stepped peripheral edge bonded to the resin compound. Therefore, the resin compound also has a stepped cross-sectional profile at the point of contact with the metal lead to prevent the metal lead from detaching from the resin compound in the vertical direction and to prevent the formation of cracks at the interface in the vertical direction.

The resin compound may be formed by paste printing, compressive molding, transfer molding, liquid injection molding, spin coating, or other suitable methods. To bond with metal leads. Preferably, the top surface of the resin compound is substantially coplanar with the top side of the metal lead, and the bottom surface of the resin compound is substantially coplanar with the bottom side of the metal lead. In addition, the resin compound may have a high elastic modulus of more than 1.0 GPa and a linear thermal expansion coefficient ranging from about 5 x 10 ^-6 K ^-1 to 15 x 10 ^-6 K ^-1 . Furthermore, in order to have sufficient thermal conductivity and proper viscosity, the resin compound may include 10 to 90 weight percent of a thermally conductive filler. For example, the thermally conductive filler can be made of aluminum nitride (AlN), aluminum oxide, silicon carbide (SiC), tungsten carbide, boron carbide, silicon dioxide, or the like, and preferably has a relatively high thermal conductivity and a relatively high resistance Rate and relatively low thermal expansion coefficient. Accordingly, the resin compound can exhibit better heat dissipation efficiency and electrical insulation performance, and its low CTE characteristic can avoid peeling or cracking of the top redistribution layer or interface deposited on it. In addition, the maximum particle diameter of the thermally conductive filler can be 25 μm or less.

The cushion layer may be made of a metal material or a resin material. For example, in the case of the heat dissipation gain type, after the resin compound is provided, the metal block in the metal frame can be selectively removed to retain the remaining part of the metal block as a metal pad. Here, the material of the metal pad is the same as that of the metal lead, and the peripheral edge of the metal pad is bonded to the resin compound, and the bottom surface of the metal pad is substantially coplanar with the bottom surface of the resin compound and the bottom surface of the metal lead. According to this, the cavity has a metalized bottom to serve as a heat dissipation platform for the semiconductor element or / and a vertical electromagnetic shielding layer. In this way, the heat generated by the semiconductor element can be conducted away through the metallic cushion layer, and / Or reduce vertical electromagnetic interference. The step of selectively removing the metal block may further include: retaining another additional remaining part of the metal block on the inner sidewall surface of the resin compound. Therefore, the inner sidewall surface of the resin compound can be completely covered by a metal film, wherein the metal film is integrally formed with a metal pad, and the cavity can have a metallized sidewall to provide a semiconductor element disposed in the cavity Horizontal electromagnetic shielding. Alternatively, the thickness of the metal block may be smaller than the thickness of the metal lead and the thickness of the resin compound, and the step of providing the resin compound may further include: providing a resin pad on the bottom side of the metal block as the pad layer. In a preferred embodiment, the resin pad is integrally formed with the resin compound, and the material of the resin pad is the same as that of the resin compound, and the bottom surface of the resin pad is substantially coplanar with the bottom surface of the resin compound and the bottom surface of the metal lead. Here, the resin pad and the resin compound may be integrally formed by a molding step such as a resin material. The top surface of the resin pad may be selectively covered by a remaining portion of the metal block, and the thickness of the resin pad and the remaining portion of the metal block is less than the thickness of the resin compound. Accordingly, the remaining part of the metal block can be used as a heat dissipation platform for the semiconductor element, and / or provide a vertical electromagnetic shielding effect for the semiconductor element. Similarly, the inner sidewall surface of the resin compound may be further covered by another additional remaining part of the metal block to provide a horizontal electromagnetic shielding effect for the semiconductor element disposed in the cavity.

Optionally, a top redistribution layer can be further formed on the top surface of the resin compound, and the top redistribution layer is electrically coupled to the metal lead, thereby improving the wiring flexibility of the circuit substrate. The top redistribution layer may be a top patterned metal layer deposited by lithography process metal, which has a uniform thickness smaller than the thickness of the metal lead. In a preferred embodiment, the top patterned metal layer is formed by sputtering followed by an electroplating process, which contacts the top surface of the resin compound and extends laterally on the top surface of the resin compound, and further extends laterally. On the top side of the metal lead. Therefore, the top redistribution layer can provide pad contacts on the resin compound for component connection.

Optionally, an electrical component can be further provided, which is embedded in a resin compound and electrically connected to the metal lead through a top redistribution layer. In a preferred embodiment, the thickness of the electrical component is less than the thickness of the metal lead, the top side of the electrical component is electrically coupled to the top redistribution layer, and the bottom side of the electrical component is covered by a resin compound. Here, the electrical component may be a resistor, a capacitor, an inductor, or any other passive or active component.

Optionally, a bottom build-up circuit can be further formed on the bottom surface of the resin compound, which can be electrically connected to the top redistribution layer through a metal lead. Thereby, the dual routing circuits on both sides of the resin compound can improve the wiring flexibility of the circuit substrate. In a preferred embodiment, the bottom build-up circuit may include at least one dielectric layer and at least one bottom patterned metal layer. The bottom patterned metal layer extends through the dielectric layer and laterally extends over the dielectric layer. on. The dielectric layer and the bottom patterned metal layer can be alternately formed alternately and can be repeatedly formed if necessary. According to this, the bottom build-up circuit can be electrically coupled to the metal lead through the metallized blind hole in the dielectric layer and be thermally conductive with the metal pad layer.

The present invention also provides a semiconductor assembly, wherein the semiconductor element is electrically connected to the circuit substrate. More specifically, the semiconductor element may be disposed face-up on the top surface of the pad, and electrically connected to the metal lead through a bonding wire connected to the metal lead or the top redistribution layer. In the thermal gain type example, the semiconductor element can be attached to the remaining part of the metal block, and can be further electrically coupled to another additional remaining part of the metal block on the surface of the inner wall of the resin compound through at least one bonding wire. To form a ground connection.

The group can be a first- or second-stage single crystal or polycrystalline device. For example, the group may be a first-level package including a single chip or multiple chips. Alternatively, the group may be a second-level module including a single package or multiple packages, where each package may include a single or multiple chips.

The semiconductor device may be a packaged wafer or an unpackaged wafer. For example, the semiconductor device may be a bare wafer or a wafer-level package die. Alternatively, the semiconductor device may include a routing circuit, a first chip, and a second chip. Here, the first chip can be electrically coupled to the top surface of the routing circuit by a conductive bump with the active surface facing the routing circuit by using a conventional flip-chip bonding process, and no metallized blind hole contacts the first The chip; or the first chip can be electrically coupled to the top surface of the routing circuit through a bonding wire in an active-side-to-back routing circuit manner using a wire bonding process. Similarly, the second chip can also use the conventional flip-chip bonding process to electrically connect the conductive bump to the bottom surface of the routing circuit with the active surface facing the routing circuit, and no metalized blind hole contacts the second Wafer. The semiconductor device optionally further includes a reinforcing layer, and the reinforcing layer is bonded to the routing circuit and surrounds the second chip laterally.

The routing circuit may be a layered circuit without a core layer to provide preliminary fan-out routing / interconnection and the shortest interconnection distance between the first chip and the second chip. Preferably, the routing circuit is a multilayer build-up circuit, which may include at least one dielectric layer and at least one circuit layer. The circuit layer extends laterally on the dielectric layer and has conductive blind holes in the dielectric layer. . The dielectric layer and the circuit layer are continuously formed alternately, and can be formed repeatedly if necessary. According to this, the routing circuit is formed with a first conductive pad and a selective terminal pad at its top surface, and a second conductive pad is formed at its bottom surface. The first conductive pad and the terminal pad may be electrically connected to the second conductive pad through a conductive blind hole. In addition, the terminal pads are electrically connected to the metal leads or the top redistribution layer on the circuit board. In a preferred embodiment, the pad size and pad pitch of the terminal pads used to connect the bonding wires are larger than the pad size and pad pitch of the first conductive pad, the second conductive pad, and the first and second chip I / O pads. The selective reinforcement layer extends laterally to the peripheral edge of the routing circuit to provide mechanical support for the routing circuit. The reinforcing layer may cover the second wafer in the same shape, or the reinforcing layer may have an opening aligned with the second conductive pad to expose the second conductive pad of the routing circuit. According to this, the bottom surface of the routing circuit and the inner sidewall surface of the reinforcement layer opening can form a cavity in the reinforcement layer opening, and the second chip can be disposed in the cavity. The inner wall surface is kept at a distance, and the second chip is electrically coupled to the second conductive pad. In a preferred embodiment, the thickness of the reinforcing layer is substantially equal to the thickness of the second wafer and the second conductive pad.

The term "coverage" means incomplete and complete coverage in vertical and / or lateral directions. For example, the resin compound may cover the side wall of the metal lead regardless of whether another component is located between the metal lead and the resin compound.

The meanings of "attached to" and "connected to" include contact and non-contact with one or more components. For example, in a preferred embodiment, a semiconductor element may be attached to a resin pad, regardless of whether the semiconductor element is separated from the resin pad by a metal layer.

The terms "electrically connected" and "electrically coupled" mean directly or indirectly electrically connected. For example, in a preferred embodiment, the semiconductor element can be electrically connected to the metal lead through a bonding wire, but the semiconductor element does not contact the metal lead.

The circuit substrate of the present invention has many advantages. For example, the metal pad can provide a heat dissipation path to dissipate heat generated by the semiconductor device. The resin compound can provide a strong mechanical connection between the metal leads, and can provide a dielectric platform for the top redistribution layer and / or the bottom build-up circuit to be deposited on it. The metal leads can provide preliminary horizontal and vertical routing, while the top redistribution layer and bottom build-up circuit can provide further routing to improve the flexibility of the wiring substrate. The circuit substrate prepared by this method has high reliability, low price, and is very suitable for mass production.

The manufacturing method of the present invention has high applicability, and uses various mature electrical and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing method of the present invention can be implemented without expensive tools. Therefore, compared with the traditional technology, this production method can greatly improve the yield, yield, efficiency and cost effectiveness.

The embodiments described herein are for illustrative purposes, and the embodiments may simplify or omit elements or steps that are well known in the technical field, so as not to obscure the features of the present invention. Similarly, to make the drawings clear, the drawings may omit repeated or unnecessary components and component symbols.

100, 130, 160, 180, 200, 300, 330, 340, 350‧‧‧ circuit substrates

110, 120, 140, 150, 170, 210, 220, 310, 320, 360‧‧‧ semiconductor group

10‧‧‧ patterned metal plate

101, 201‧‧‧ Top side

103‧‧‧ bottom side

11‧‧‧ metal frame

13‧‧‧metal lead

131‧‧‧ outer end

133‧‧‧Inner end

136‧‧‧Horizontal extension

137‧‧‧Vertical protrusion

15‧‧‧ metal block

152, 301, 401, 901‧‧‧

153, 303, 403, 903‧‧‧ underside

156‧‧‧metal pad

158, 48‧‧‧ metal film

16‧‧‧ coupling rod

20‧‧‧ Electrical components

30‧‧‧resin compound

305, 907‧‧‧Dent

40‧‧‧resin pad

46‧‧‧metal layer

51‧‧‧ top redistribution layer

53‧‧‧Bottom layer increase circuit

531, 911‧‧‧Dielectric layer

533‧‧‧First blind hole

534‧‧‧second blind hole

535‧‧‧ bottom patterned metal layer

537‧‧‧First metallized blind hole

538‧‧‧Second metallized blind hole

61, 90‧‧‧ semiconductor components

65, 97‧‧‧ Passive components

71, 945‧‧‧ bonding wire

81‧‧‧Moulding material

85, 87‧‧‧ solder balls

905‧‧‧ inside wall

91‧‧‧ routing circuit

913‧‧‧line layer

914‧‧‧Conductive blind hole

915‧‧‧The first conductive pad

917‧‧‧Terminal Pad

919‧‧‧Second conductive pad

93‧‧‧Enhancement

935‧‧‧ opening

94‧‧‧ first chip

943‧‧‧The first conductive bump

95‧‧‧Second Chip

953‧‧‧Second conductive bump

96‧‧‧Third chip

963‧‧‧The third conductive bump

98‧‧‧metal pillar

With reference to the accompanying drawings, the present invention can be more clearly understood through the detailed description of the following preferred embodiments, wherein: FIG. 1, FIG. 2 and FIG. 3 are cross sections of a patterned metal plate in the first embodiment of the present invention, respectively. Schematic diagram, top perspective diagram and bottom perspective diagram; FIGS. 3, 4 and 5 are cross-sectional schematic diagrams, top perspective diagrams and top perspective diagrams of resin compounds provided in the structure of FIG. 1, FIG. 2 and FIG. 3, respectively, in the first embodiment of the present invention; Bottom perspective view; Figures 6, 7 and 8 are the first embodiment of the present invention, respectively, to selectively etch the patterned metal plate in the structure of Figure 4, Figure 5 and Figure 6 to complete the uncut circuit substrate A schematic cross-sectional view, a top perspective view, and a bottom perspective view; FIGS. 10 and 11 are respectively a cross-sectional view and a top perspective view of a semiconductor device and a bonding wire provided in the structure of FIG. 7 and FIG. 8 in the first embodiment of the present invention; 12 and FIG. 13 are respectively a cross-sectional schematic diagram and a top perspective schematic diagram of a molding material formed in the structure of FIG. 10 and FIG. 11 in the first embodiment of the present invention; FIG. 14, FIG. 15, and FIG. In the embodiment, a schematic cross-sectional view, a top perspective view, and a bottom perspective view of a semiconductor assembly formed by cutting the structures of FIGS. 12 and 13 are shown. FIGS. 17 and 18 are two examples of the first embodiment of the present invention. A schematic cross-sectional view and a top perspective view of a three-dimensional stacked semiconductor package of a semiconductor assembly; FIG. 19 is a schematic cross-sectional view of another semiconductor assembly in the first embodiment of the present invention, which has another semiconductor configuration type electrically coupled Connected to the uncut circuit substrate shown in Fig. 7; Figs. 20 and 21 are respectively a schematic sectional view and a top perspective view of another aspect of the uncut circuit substrate in the first embodiment of the present invention; Figs. 22 and 23 In the first embodiment of the present invention, a cross-sectional schematic diagram and a top perspective view of a semiconductor element and a bonding wire are provided in the structure of FIG. 20 and FIG. 21 respectively. FIGS. 24 and 25 are respectively a first embodiment of the present invention and FIG. 22. Fig. 26, Fig. 27 and Fig. 28 are respectively a semi-conductive guide formed by cutting the structure of Figs. 24 and 25 in the first embodiment of the present invention. A schematic cross-sectional view, a top perspective view, and a bottom perspective view of the assembly; FIGS. 29 and 30 are schematic cross-sectional views of a three-dimensional stacked semiconductor package having two semiconductor assemblies shown in FIG. 26 in the first embodiment of the present invention; Top perspective view; FIG. 31 is a schematic cross-sectional view of another semiconductor assembly in the first embodiment of the present invention, which has another semiconductor configuration electrically coupled to the uncut circuit substrate shown in FIG. 20; FIG. 32 And FIG. 33 are respectively a schematic cross-sectional view and a top three-dimensional schematic view of another aspect of a circuit substrate in the first embodiment of the present invention, which directly deposits a top redistribution layer on a resin compound; FIGS. 34 and 35 are respectively the first of the present invention. In the embodiment, a cross-sectional schematic diagram and a top perspective schematic diagram of a semiconductor element, a passive element, a bonding wire, and a molding material are provided in the structure of FIG. 32 and FIG. 33; FIG. 36 is a first embodiment of the present invention. A schematic cross-sectional view of a three-dimensional stacked semiconductor package of a semiconductor assembly; FIG. 37 is a schematic cross-sectional view of another aspect of an uncut circuit substrate in the first embodiment of the present invention It has electrical components embedded in a resin compound; FIGS. 38 and 39 are a schematic sectional view and a bottom perspective view of a patterned metal plate bonded to a resin compound, respectively, in a second embodiment of the present invention; FIGS. 40 and 41 are respectively In the second embodiment of the present invention, a sectional view and a bottom perspective view of the dielectric layer, the first blind hole and the second blind hole are provided in the structure of FIG. 38 and FIG. 39; FIG. 42 and FIG. 43 are the second embodiment of the present invention, respectively. In the embodiment, a schematic cross-sectional view and a bottom perspective view of the bottom patterned metal layer are provided in the structure of FIG. 40 and FIG. 41. FIG. 44 and FIG. 45 are views of the structure of FIG. 42 and FIG. 43 respectively in the second embodiment of the present invention. A patterned metal plate is selectively etched to produce a cross-sectional schematic diagram and a top perspective schematic diagram of a completed circuit substrate; FIGS. 46 and 47 are respectively a second embodiment of the present invention, and semiconductor elements and bonding wires are provided in the structure of FIGS. 44 and 45 Sectional schematic diagram and top perspective diagram of the molding compound; and FIG. 48 is a three-dimensional stack having the semiconductor group shown in FIG. 14 stacked on the semiconductor group shown in FIG. 46 in the second embodiment of the present invention. 49 is a schematic cross-sectional view of another semiconductor assembly in a second embodiment of the present invention, which has another semiconductor element electrically coupled to the circuit substrate shown in FIG. 44; 50 is a schematic cross-sectional view of a patterned metal plate in the third embodiment of the present invention; FIG. 51 and FIG. 52 are a cross-sectional schematic view and a bottom perspective view of the molding material provided in the structure of FIG. 50 in the third embodiment of the present invention; 53 and 54 are a cross-sectional schematic diagram and a top perspective schematic diagram of a third embodiment of the present invention, in which the patterned metal plate in the structure of FIG. 51 and FIG. 52 is selectively etched to produce an uncut circuit substrate; 55 and FIG. 56 are respectively a cross-sectional schematic diagram and a top perspective schematic diagram of a semiconductor element and a bonding wire provided in the structure of FIG. 53 and FIG. 54 in the third embodiment of the present invention; and FIG. 57 and FIG. 58 are respectively a third embodiment of the present invention. In the structure of Fig. 55 and Fig. 56, a cross-sectional schematic diagram and a top perspective diagram of the molding material are provided; Fig. 59, Fig. 60 and Fig. 61 are the third embodiment of the present invention, which are cut from the structure of Fig. 57 and 58 A schematic cross-sectional view, a top perspective view, and a bottom perspective view of the completed semiconductor assembly; FIGS. 62 and 63 are diagrams of a three-dimensional stacked semiconductor package having two semiconductor assemblies shown in FIG. 59 in the third embodiment of the present invention, respectively. A schematic cross-sectional view and a top perspective view; FIG. 64 is a schematic cross-sectional view of another semiconductor assembly in the third embodiment of the present invention, which has another semiconductor element electrically coupled to the uncut circuit substrate shown in FIG. 53 65 is a schematic cross-sectional view of another circuit substrate in the third embodiment of the present invention; FIG. 66 is a cross-sectional schematic view of another circuit substrate in the third embodiment of the present invention; In the embodiment, another cross-sectional view of a circuit substrate is shown. FIG. 68 is a schematic cross-sectional view of a semiconductor device, a passive device, a bonding wire, and a molding material provided in the structure of FIG. 67 in the third embodiment of the present invention.

Claims (23)

A method for manufacturing a circuit substrate includes the following steps: providing a metal frame, a metal block, and a plurality of metal leads, wherein the metal block is located in the metal frame, and the metal leads are integrally connected to the metal frame, and each Some of the metal leads have an inner end, the inner end facing away from the metal frame and toward the metal block; a resin compound is provided to fill the remaining space in the metal frame, and the top surface of the resin compound Are substantially coplanar with the metal leads and the top side of the metal block; and removing at least a selected portion of the metal block to form a cavity, wherein the entrance of the cavity is located on the top surface of the resin compound Office. The manufacturing method described in item 1 of the patent application scope further includes a step of separating the metal frame from the metal leads. The manufacturing method according to item 2 of the scope of patent application, wherein the step of separating the metal frame includes chemical etching or mechanical cutting or cutting. The manufacturing method according to item 1 of the scope of patent application, wherein the step of removing at least one selected part of the metal block includes retaining a remaining part of the metal block as a metal pad, and the metal pad is adjacent to The bottom of the cavity. The manufacturing method according to item 4 of the scope of patent application, wherein the bottom surface of the metal pad is substantially coplanar with the bottom surface of the resin compound and the bottom side of the metal leads. The manufacturing method according to item 4 of the scope of patent application, wherein the step of removing at least one selected part of the metal block further comprises retaining an additional remaining part of the metal block, and the additional remaining part is located in the resin compound On the inside wall surface. The manufacturing method according to item 1 of the patent application scope further includes a step of forming a top redistribution layer on the top surface of the resin compound, and the top redistribution layer is electrically coupled to the metal leads . The manufacturing method as described in item 7 of the scope of patent application, further comprising a step: before providing the resin compound, an electric component is set in the metal frame, wherein the top redistribution layer is more electrically coupled to the electric property. A component to at least one of the metal leads. The manufacturing method described in item 1 of the scope of patent application further includes a step of forming a bottom build-up circuit on the bottom surface of the resin compound, and the bottom build-up circuit is electrically coupled to the metal leads. The manufacturing method according to item 9 of the scope of patent application, wherein the step of removing at least one selected part of the metal block includes retaining a remaining part of the metal block as a metal pad, and the metal pad is adjacent to The bottom of the cavity, and the bottom build-up circuit is electrically coupled and thermally conducted to the metal pad. The manufacturing method according to item 1 of the scope of the patent application, wherein the thickness of the metal block is smaller than the thickness of the metal leads, and the step of providing the resin compound includes providing a resin pad on the bottom side of the metal block, And the resin pad is integrally formed with the resin compound. A manufacturing method of a stacked semiconductor assembly includes the following steps: A circuit is made by the manufacturing method described in any one of the first to third items and the seventh to the ninth items of the patent application scope. A substrate; and a semiconductor element is disposed in the cavity of the circuit substrate, and the semiconductor element is electrically coupled to the circuit substrate through a bonding wire. The manufacturing method according to item 12 of the scope of patent application, wherein the step of removing at least one selected part of the metal block includes: retaining a remaining part of the metal block as a metal pad, and the metal pad is adjacent The step of electrically coupling the semiconductor element to the circuit board at the bottom of the cavity and retaining an additional remaining part of the metal block on the inner sidewall surface of the resin compound The method includes: electrically coupling the semiconductor element to the extra remaining portion of the metal block through at least one of the bonding wires. The manufacturing method according to item 12 of the scope of patent application, wherein (i) the semiconductor element includes a routing circuit, a first chip, and a second chip, and (ii) the first chip is electrically coupled to the routing circuit The top surface is (iii) the second chip is electrically coupled to the bottom surface of the routing circuit, and (iv) the bonding wires are electrically coupled to the routing circuit to the circuit substrate. A circuit substrate includes: a plurality of metal leads, each of which has an inner end and an outer end, wherein the inner end faces a predetermined area, and the outer end is farther from the predetermined area than the inner end; A resin compound that fills the spaces between the metal leads and extends laterally beyond the inner ends of the metal leads, and then extends into the predetermined area to surround a cavity at the predetermined area, wherein the resin The top surface of the compound is substantially coplanar with the top side of the metal leads; and a cushion layer covering a bottom of the cavity, wherein the thickness of the cushion layer is less than the thickness of the resin compound and the thickness of the metal leads. And the bottom surface of the cushion layer is substantially coplanar with the bottom surface of the resin compound. The circuit substrate according to item 15 of the scope of the patent application, wherein the pad layer is a metal pad or a resin pad. The circuit substrate according to item 15 of the patent application scope further includes: a top redistribution layer disposed on the top surface of the resin compound and electrically coupled to the metal leads. The circuit substrate according to item 17 of the scope of patent application, further comprising: an electrical component embedded in the resin compound, wherein the top side of the electrical component is in line with the top sides of the metal leads. Substantially coplanar, and the top redistribution layer is more electrically coupled to the electrical component to at least one of the metal leads. The circuit substrate according to item 15 of the patent application scope further includes: a bottom build-up circuit, which is disposed on the bottom surface of the resin compound and is electrically coupled to the metal leads. The circuit substrate according to item 19 of the scope of patent application, wherein the pad layer is a metal pad, and the bottom build-up circuit is electrically coupled and thermally conducted to the metal pad. The circuit substrate according to item 15 of the scope of patent application, further comprising: a metal film provided on the surface of the inner side wall of the resin compound, wherein the pad layer is a metal pad and is connected to the metal film. A stacked semiconductor assembly, comprising: the circuit substrate according to any one of claims 15 to 19 in the scope of application for a patent; and a semiconductor element disposed in the cavity of the circuit substrate, and The semiconductor element is electrically coupled to the circuit substrate through a bonding wire. The stacked semiconductor assembly according to item 22 of the scope of the patent application, wherein the pad layer is a metal pad, and the circuit substrate further includes a metal film, which is disposed on the inner sidewall surface of the resin compound and is The metal pads are connected, and the semiconductor element is electrically coupled to the metal film and the metal leads through the bonding wires.