TW201924071A - Tft array structure and binding region thereof, and method for manufacturing binding region - Google Patents

Abstract

A TFT array structure and a binding region thereof, and a method for manufacturing the binding region, the binding region comprising a first substrate, a metal stack layer arranged on the first substrate, an insulating stack layer arranged on the first substrate and covering the edge of the metal stack layer, and a light transmissive electrically conductive layer arranged on the metal stack layer; the metal stack layer comprises a first metal layer having a Cu layer; and the light transmissive electrically conductive layer covers the first metal layer. In the binding region of the TFT array structure, the metal layer is protected by means of arranging the light transmissive electrically conductive layer on the metal layer, preventing oxidative corrosion of the Cu metal in the metal layer.

Description

Thin film transistor array structure, binding region thereof and binding region manufacturing method

The present invention relates to the field of illuminating display technology, and in particular, to a method for fabricating a bonding region and a binding region of a thin film transistor (TFT) array structure.

The existing active-matrix organic light-emitting diode (AMOLED) technology uses a top emission structure. The pixel electrode layer (PE) of the existing active OLED top emission Array structure generally adopts a three-layer structure of indium tin oxide (ITO)/Ag/indium tin oxide (ITO). , where Ag is an easily oxidizable material. If the ITO/Ag/ITO layer is left in the bonding region, it is prone to corrosion affecting the bonding pad contact resistance, so it is generally left in the bonded pad region. The pixel electrode layer and the source and drain electrode (SD, Source and Drain Electrode) metal use an anti-oxidation Ti/Al/Ti metal structure to avoid oxidative corrosion after exposure.

In the active OLED top emission Array structure, the source and the ruthenium metal also have a two-layer structure of copper (Cu) process (Mo/Cu, molybdenum alloy/Cu or Ti/Cu). Etc.), in which the Cu metal is usually disposed above, and because the Cu surface is not provided with an anti-oxidation film layer for protection, oxidative corrosion is likely to occur, which may affect the contact resistance of the bonding pad and affect product reliability.

The technical problem to be solved by the present invention is to provide a bonding region of a thin film transistor array structure for avoiding oxidative corrosion of Cu metal in a metal layer, and a thin film transistor array structure having the binding region, and the binding region Production Method.

The technical solution adopted by the present invention to solve the technical problem thereof is to provide a binding region including a substrate, a metal laminate disposed on the substrate, and an insulating stack disposed on the substrate and covering the edge of the metal laminate a layer, a pixel electrode layer disposed on the metal stack, a pixel defining layer disposed on the insulating stack and covering an edge of the pixel electrode layer, and a metal protective layer disposed on the pixel electrode layer .

The invention also provides a thin film transistor array structure comprising a display area and the binding area described above; the binding area is connected at a periphery of the display area.

The present invention also provides a method for fabricating the above binding region, comprising the following steps: Step S1: performing a first photoresist patterning on the pixel electrode layer on the thin film transistor array structure to make the binding region The pixel electrode layer is exposed; step S2: sequentially performing the first etching and the second etching on the pixel electrode layer on the bonding region, respectively, respectively, the top transparent conductive layer of the pixel electrode layer and The reflective conductive layer is etched to leave the bottom transparent conductive layer of the pixel electrode layer; Step S3: performing a second photoresist patterning on the bottom transparent conductive layer on the binding region, which will be located in the The bottom transparent conductive layer on the metal layer of the binding region is covered; Step S4: performing a third etching on the bottom transparent conductive layer on the bonding region to remove other bottoms than the metal laminate a light-transmissive conductive layer leaving the bottom light-transmissive conductive layer on the metal stack of the bonding region to form a light-transmitting conductive layer overlying the first metal layer of the metal layer having a Cu layer Floor.

The beneficial effects of the invention: in the binding region of the thin film transistor array structure, the metal layer is protected by the arrangement of the light-transmitting conductive layer on the metal layer to avoid oxidative corrosion of Cu metal in the metal layer.

Compared with the prior art, the binding region of the present invention adds a second photoresist patterning process, leaving the light-transmissive conductive layer at the bottom of the pixel electrode layer as a protective layer of the bonding region, and the metal of the bonding region. The layer is protected.

For a better understanding of the technical features, objects and effects of the present invention, the embodiments of the present invention are described in detail with reference to the accompanying drawings.

The bonding region of the thin film transistor array structure of the present invention, wherein the thin film transistor array structure is used in an active organic light emitting diode display as an array of active organic light emitting diodes (AMOLED top emission Array) structure .

As shown in FIG. 1 , the bonding region of the thin film transistor array structure of the first embodiment of the present invention may include a first substrate 10 , a metal laminate 20 disposed on the first substrate 10 , and a first substrate 10 . The insulating laminate 30 covering the edge of the metal laminate 20 and the light-transmissive conductive layer 40 disposed on the metal laminate 20 are disposed, and both ends of the light-transmitting conductive layer 40 are in contact with the insulating laminate 30.

The metal laminate 20 is a metal laminate having a copper (Cu) layer, and the light-transmitting conductive layer 40 is protected on the metal laminate 20 to avoid oxidative corrosion of the Cu metal.

In the present embodiment, the metal laminate 20 includes a first metal layer 21 having a Cu layer. The light-transmitting conductive layer 40 is disposed on the first metal layer 21 to cover a portion where the upper surface of the first metal layer 21 is exposed.

The light-transmitting conductive layer 40 is an indium tin oxide (ITO) layer or an indium zinc oxide (IZO) layer.

The light-transmitting conductive layer 40 is a bottom light-transmitting conductive layer which is left after the pixel electrode layer (OLED (organic light-emitting diode) anode) disposed on the first metal layer 21 is etched. The pixel electrode layer is usually a three-layer structure composed of a high transmittance, high conductivity transparent conductive layer and a highly reflective, high conductivity and corrosion resistant reflective conductive layer, usually ITO/Ag/ITO or IZO/Ag. /IZO three-layer structure. When the light-transmitting conductive layer 40 is formed, the adjacent light-transmitting conductive layer and the reflective conductive layer are sequentially etched to leave a light-transmitting conductive layer therein, that is, the light-transmitting conductive layer 40 on the first metal layer 21 is formed.

Alternatively, the first metal layer 21 may have a two-layer structure including a Cu layer and a metal conductive layer disposed on a side of the Cu layer toward the first substrate 10; the metal conductive layer is Al, Mo, Cu, Ti, Mo alloy, and oxidation It is made of at least one of a metal such as gallium zinc (GZO) and zinc indium oxide (ZIO), an alloy or a conductor metal oxide. For the first metal layer 21 of the two-layer structure, the Cu layer faces the light-transmitting conductive layer 40.

Alternatively, the first metal layer 21 may also have a three-layer structure including a Cu layer and a metal conductive layer disposed on opposite sides of the Cu layer and facing the first substrate 10 and the light-transmitting conductive layer 40, respectively; the metal conductive layer is Al, It is made of at least one of a metal, an alloy, or a conductor metal oxide such as Mo, Cu, Ti, Mo alloy, GZO, and ZIO.

In this embodiment, corresponding to the first metal layer 21, the insulating laminate 30 is disposed on the first substrate 10 and covers the edge of the first metal layer 21 to protect the boundary of the first metal layer 21. The insulating laminate 30 may be an insulating layer made of yttrium oxide (SiOx) or tantalum nitride (SiNx).

As shown in FIG. 2, the bonding region of the thin film transistor array structure of the second embodiment of the present invention may include a first substrate 10, a metal laminate 20 disposed on the first substrate 10, and a first substrate 10. The insulating laminate 30 covering the edges of the metal laminate 20 and the light-transmitting conductive layer 40 disposed on the metal laminate 20 are covered.

The metal laminate 20 is a metal laminate having a copper (Cu) layer, and the light-transmitting conductive layer 40 is protected on the metal laminate 20 to avoid oxidative corrosion of the Cu metal.

In this embodiment, the metal laminate 20 includes a first metal layer 21 and a second metal layer 22 having a Cu layer, and the second metal layer 22 is disposed between the first metal layer 21 and the first substrate 10; the first metal layer 21 and the second metal layer 22 are joined by via holes. It is to be understood that in other embodiments, the manner in which the first metal layer 21 and the second metal layer 22 are joined may be other methods, such as soldering or bonding, and the invention is not specifically limited.

The light-transmitting conductive layer 40 is overlaid on the first metal layer 21. The transparent conductive layer 40 and the first metal layer 21 can be specifically referred to in the foregoing first embodiment, and details are not described herein again.

The second metal layer 22 may be made of the same material as the first metal layer 21, and may also have a two-layer or three-layer structure. For example, the second metal layer 22 is a two-layer structure including a Cu layer and a metal conductive layer disposed on a side of the Cu layer toward the first substrate 10; the metal conductive layers are Al, Mo, Cu, Ti, Mo alloy, GZO, and ZIO It is made of at least one of a metal, an alloy or a conductor metal oxide. Alternatively, the second metal layer 22 has a three-layer structure including a Cu layer and metal conductive layers disposed on opposite sides of the Cu layer and facing the first substrate 10 and the first metal layer 21 respectively; the metal conductive layer is Al, Mo, Cu At least one of a metal, an alloy, or a conductor metal oxide such as Ti, Mo alloy, GZO, and ZIO.

Further, the second metal layer 22 may be a single layer structure made of a metal such as Al, Mo, Cu, Ti, Mo alloy, GZO, or ZIO, an alloy, or a conductor metal oxide.

In the present embodiment, the insulating laminate 30 includes a first insulating layer 31 and a second insulating layer 32 corresponding to the metal laminate 20. The second insulating layer 32 is disposed on the first substrate 10 and covers the second metal layer 22 to protect the boundary of the second metal layer 22, and the covered region may be an edge portion or a whole of the second metal layer 22. The first insulating layer 31 is disposed on the second insulating layer 32 and covers the edge of the first metal layer 21 to protect the boundary of the first metal layer 21.

The first insulating layer 31 and the second insulating layer 32 may each be made of a material such as yttrium oxide (SiOx) or tantalum nitride (SiNx).

As shown in FIG. 3, the thin film transistor array structure of the present invention comprises a display area and the above-mentioned binding area (non-display area); the binding area is connected to the periphery of the display area. In Fig. 3, the left part of the broken line is the display area, and the right part is the binding area. The TFT array structure of the present invention is used in an AMOLED display as an active organic light emitting diode (AMOLED top emission Array) structure.

In one embodiment of the thin film transistor array structure of the present invention, the display region includes a second substrate 1, a first metal electrode 2 disposed on the second substrate 1, and a second substrate 1 disposed on the second substrate 1 and covering the first metal electrode 2 The insulating layer 3, the island-shaped semiconductor layer 4 disposed on the insulating layer 3, the second metal electrode 5 disposed on the insulating layer 3 and extending to the island-shaped semiconductor layer 4, and sequentially disposed on the second metal electrode 5 The protective layer 6 and the planarization layer 7, the pixel electrode layer 8 disposed on the planarization layer 7, and the pixel definition layer 9 disposed on the planarization layer 7 and covering the edge of the pixel electrode layer 8.

The pixel defining layer 9 protects the boundary of the pixel electrode layer 8. The pixel defining layer 9 is made of an organic material.

The planarization layer 7 is provided with a through hole 71 extending through the planarization layer 7 to the protective layer 6; the pixel electrode layer 8 extends along the planarization layer 7 and covers the inner surface of the through hole 71. The through hole 71 is an open hole, and the bottom surface thereof may be located on the surface of the second metal electrode 5.

The planarization layer 7 is made of an organic material and further is a photoresist-type organic material.

The second substrate 1 and the first substrate 10 of the binding region are integrally connected to form an integral substrate.

The first metal electrode 2 and the second metal layer 22 of the bonding region are formed by patterning the same metal layer formed by deposition, and both are on the same plane. The second metal electrode 5 and the first metal layer 21 of the bonding region are formed by patterning the same metal layer formed by deposition, and both are on the same plane. The insulating layer 3 and the second insulating layer 32 of the bonding region are formed by processing the same insulating material layer, and both are on the same plane. The protective layer 6 and the first insulating layer 31 of the bonding region are formed by processing the same insulating material layer, and both are on the same plane. The processing methods and the like of the above layers can be realized by the prior art.

It can be understood that the preparation, structure and the like of the display region of the thin film transistor array structure of the present invention can be realized by the prior art.

The formation of the binding region of the thin film transistor array structure of the present invention can be formed during the fabrication of the entire thin film transistor array structure. Alternatively, the method for manufacturing the binding area may include the following steps:

Step S1: During the preparation of the thin film transistor array structure, the first photoresist layer (MASK) is patterned on the pixel electrode layer thereon, so that the pixel electrode layer on the bonding region is exposed.

Step S2: sequentially performing the first etching and the second etching on the pixel electrode layer on the binding region, respectively etching the top transparent conductive layer and the reflective conductive layer of the pixel electrode layer, leaving the bottom of the pixel electrode layer transparent. Conductive layer.

At the first etching, the etching solution used was an oxalic acid solution, and the top transparent conductive layer (ITO) of the pixel electrode layer was etched. The oxalic acid solution does not etch the reflective conductive layer (Ag). After the first etch, the reflective conductive layer is exposed.

In the second etching, the etching solution used is an acid solution of a phosphoric acid acetic acid nitric acid base, and the reflective conductive layer (Ag) is etched. The acid solution of the phosphoric acid acetic acid nitric acid base does not etch the light-transmitting conductive layer (ITO), so the bottom light-transmitting conductive layer (ITO) is not etched.

Step S3: performing a second photoresist patterning on the bottom transparent conductive layer on the binding region to cover the bottom transparent conductive layer on the metal laminate 20 of the binding region.

In actual operation, the photoresist patterning is a full surface, and the second photoresist patterned region does not only have a bonding region, but also includes a second photoresist patterning of the display region.

Step S4: performing a third etching on the bottom transparent conductive layer on the binding region to remove other bottom transparent conductive layers other than the metal laminate 20, leaving the bottom of the metal laminate 20 located in the binding region transparent. The photoconductive layer is formed to form a light-transmitting conductive layer 40 overlying the first metal layer 21 having a Cu layer of the metal laminate 20, as shown in FIGS.

Further, after the step S3, a third etching is performed on the region where the bottom transparent conductive layer is not left, and the bottom transparent conductive layer is etched away.

It can be understood that the fabrication of the thin film transistor array structure of the present invention can be implemented by using the prior art. On the basis of the prior art, a second photoresist (MASK) is added to transmit the bottom of the pixel electrode layer located in the binding region. The conductive layer remains as a protective layer of the metal layer on the bonding region, and the Cu metal in the protective metal layer is not oxidized and etched.

The above is only the embodiment of the present invention, and is not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformation of the present invention and the contents of the drawings may be directly or indirectly applied to other related technologies. The fields are all included in the scope of patent protection of the present invention.

1‧‧‧second substrate

2‧‧‧First metal electrode

3‧‧‧Insulation

4‧‧‧ island-like semiconductor layer

5‧‧‧Second metal electrode

6‧‧‧Protective layer

7‧‧‧Flating layer

8‧‧‧pixel electrode layer

9‧‧‧ pixel definition layer

10‧‧‧First substrate

20‧‧‧metal laminate

21‧‧‧First metal layer

22‧‧‧Second metal layer

30‧‧‧Insulation laminate

31‧‧‧First insulation

32‧‧‧Second insulation

40‧‧‧Light conductive layer

71‧‧‧through hole

The present invention will be further described with reference to the accompanying drawings and embodiments. FIG. 1 is a schematic structural diagram of a binding zone according to a first embodiment of the present invention. 2 is a schematic structural diagram of a binding area according to a second embodiment of the present invention. 3 is a schematic structural view of a thin film transistor array structure according to an embodiment of the present invention.

Claims (16)

A bonding region of a thin film transistor array structure, comprising a first substrate, a metal laminate disposed on the first substrate, an insulating laminate disposed on the first substrate and covering an edge of the metal laminate And a light transmissive conductive layer disposed on the metal stack; the metal stack includes a first metal layer having a Cu layer; the light transmissive conductive layer overlying the first metal layer. The bonding region of the thin film transistor array structure according to claim 1, wherein the light-transmitting conductive layer is an ITO layer or an IZO layer. The binding region of the thin film transistor array structure of claim 1, wherein the transparent conductive layer is a bottom light transmission after the pixel electrode layer disposed on the first metal layer is etched. Conductive layer. The binding region of the thin film transistor array structure of claim 1, wherein the first metal layer is a two-layer structure including the Cu layer and disposed on the Cu layer toward the first substrate a metal conductive layer on one side; the metal conductive layer is made of at least one of Al, Mo, Cu, Ti, Mo alloy, GZO, and ZIO. The binding region of the thin film transistor array structure according to claim 1, wherein the first metal layer is a three-layer structure including the Cu layer and disposed on opposite sides of the Cu layer and respectively oriented The first substrate and the metal conductive layer of the light-transmitting conductive layer; the metal conductive layer is made of at least one of Al, Mo, Cu, Ti, Mo alloy, GZO, and ZIO. The bonding region of the thin film transistor array structure of claim 1, wherein the metal laminate further comprises a second metal layer disposed between the first metal layer and the first substrate; The first metal layer and the second metal layer are joined by via holes. The binding region of the thin film transistor array structure according to claim 6, wherein the second metal layer is a two-layer structure including a Cu layer and disposed on the side of the Cu layer facing the first substrate a metal conductive layer; the metal conductive layer being made of at least one of Al, Mo, Cu, Ti, Mo alloy, GZO, and ZIO. The bonding region of the thin film transistor array structure according to claim 6, wherein the second metal layer is a three-layer structure including a Cu layer and disposed on opposite sides of the Cu layer and respectively facing the a first substrate and a metal conductive layer of the first metal layer; the metal conductive layer is made of at least one of Al, Mo, Cu, Ti, Mo alloy, GZO, and ZIO. The bonding region of the thin film transistor array structure of claim 6, wherein the insulating laminate comprises a first insulating layer and a second insulating layer; the second insulating layer is disposed on the first substrate And covering the second metal layer, the first insulating layer is disposed on the second insulating layer and covering an edge of the first metal layer. A thin film transistor array structure comprising a display region and a binding region of the thin film transistor array structure according to any one of claims 1 to 9; wherein the binding region is connected to the display The perimeter of the district. The thin film transistor array structure of claim 10, wherein the display region comprises a second substrate, a first metal electrode disposed on the second substrate, disposed on the second substrate, and covered An insulating layer of the first metal electrode, an island-shaped semiconductor layer disposed on the insulating layer, a second metal electrode disposed on the insulating layer and extending to the island-shaped semiconductor layer, and sequentially disposed at the a protective layer and a planarization layer on the second metal electrode, a pixel electrode layer disposed on the planarization layer, and a pixel definition layer disposed on the planarization layer and covering an edge of the pixel electrode layer. The thin film transistor array structure of claim 11, wherein the planarization layer is provided with a through hole extending through the planarization layer to the protective layer; the pixel electrode layer Extending along the planarization layer and covering an inner surface of the through hole. The thin film transistor array structure according to claim 11, wherein the second substrate and the first substrate of the binding region are integrally connected to form an integral substrate. The thin film transistor array structure according to claim 11, wherein the first metal electrode and the second metal layer of the bonding region are formed by patterning a same metal layer formed by deposition; The second metal electrode and the first metal layer of the bonding region are formed by patterning the same metal layer formed by deposition. A method of producing a binding region of a thin film transistor according to any one of claims 1 to 9, which comprises the following steps: Step S1: during the preparation of the thin film transistor array structure Performing a first photoresist pattern on the upper pixel electrode layer to expose the pixel electrode layer on the bonding region; Step S2: sequentially performing the first etching on the pixel electrode layer on the bonding region And a second etching, respectively etching the top transparent conductive layer and the reflective conductive layer of the pixel electrode layer to leave a bottom transparent conductive layer of the pixel electrode layer; Step S3: on the binding region Performing a second photoresist pattern on the bottom transparent conductive layer to cover the bottom transparent conductive layer on the metal layer of the binding region; Step S4: performing the The bottom transparent conductive layer is etched for a third time to remove other bottom transparent conductive layers other than the metal laminate, leaving the bottom transparent conductive layer on the metal stack of the bonding region to Forming a cover over the metal laminate Transmitting conductive layer on the first metal layer of the Cu layer. The method for fabricating a binding region of a thin film transistor according to claim 15, wherein in the step S2, the etching solution used in the first etching is an oxalic acid solution; and the second etching is performed. The etching solution is an acid solution of a phosphoric acid acetic acid nitric acid base.