TW201919467A - Semiconductor package recycling and utilization method, recycling and utilizing semiconductor package and fixture including a recycling step, a loading step, a remolding step, and a cutting step - Google Patents
Semiconductor package recycling and utilization method, recycling and utilizing semiconductor package and fixture including a recycling step, a loading step, a remolding step, and a cutting step Download PDFInfo
- Publication number
- TW201919467A TW201919467A TW107109621A TW107109621A TW201919467A TW 201919467 A TW201919467 A TW 201919467A TW 107109621 A TW107109621 A TW 107109621A TW 107109621 A TW107109621 A TW 107109621A TW 201919467 A TW201919467 A TW 201919467A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor package
- recycling
- semiconductor
- package
- jig
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 285
- 238000000034 method Methods 0.000 title claims abstract description 119
- 238000004064 recycling Methods 0.000 title claims abstract description 55
- 238000005520 cutting process Methods 0.000 title claims abstract description 11
- 238000000465 moulding Methods 0.000 claims abstract description 52
- 229910000679 solder Inorganic materials 0.000 claims description 41
- 229920006336 epoxy molding compound Polymers 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 238000010330 laser marking Methods 0.000 claims description 16
- 238000007789 sealing Methods 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 230000009477 glass transition Effects 0.000 claims description 4
- 238000009751 slip forming Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 description 78
- 235000012431 wafers Nutrition 0.000 description 63
- 239000000758 substrate Substances 0.000 description 37
- 239000000463 material Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 14
- 238000004806 packaging method and process Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 230000006870 function Effects 0.000 description 8
- LIMFPAAAIVQRRD-BCGVJQADSA-N N-[2-[(3S,4R)-3-fluoro-4-methoxypiperidin-1-yl]pyrimidin-4-yl]-8-[(2R,3S)-2-methyl-3-(methylsulfonylmethyl)azetidin-1-yl]-5-propan-2-ylisoquinolin-3-amine Chemical compound F[C@H]1CN(CC[C@H]1OC)C1=NC=CC(=N1)NC=1N=CC2=C(C=CC(=C2C=1)C(C)C)N1[C@@H]([C@H](C1)CS(=O)(=O)C)C LIMFPAAAIVQRRD-BCGVJQADSA-N 0.000 description 7
- 239000000470 constituent Substances 0.000 description 7
- 230000002950 deficient Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 239000004033 plastic Substances 0.000 description 5
- 229920003023 plastic Polymers 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000005192 partition Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 238000001035 drying Methods 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 238000007781 pre-processing Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000003063 flame retardant Substances 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 230000000704 physical effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- 206010011469 Crying Diseases 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 239000013543 active substance Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000002173 cutting fluid Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 239000000206 moulding compound Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
本發明涉及一種半導體封裝回收利用方法、回收利用半導體封裝以及為其的夾具，涉及回收利用在製造工程中被判斷為不良或已用半導體封裝的技術。 The present invention relates to a method for recycling semiconductor packages, recycling semiconductor packages, and jigs therefor, and to a technology for recycling semiconductor packages that are judged to be defective or used in manufacturing processes.
一般，製造半導體的後工程包括：在印刷電路板(PCB,Printed Circuit Board)安裝附著從晶圓(wafer)分離的半導體晶片的管芯焊接(die bonding)工程；利用金屬線(metal wire)等電連接附著有半導體晶片的印刷電路板的金線鍵合(wire bonding)工程；通過利用密封材料密封半導體晶片及印刷電路板製造成積體電路封裝的模制(molding)工程；以及為了裝運的半導體晶片切割工程(Package Sawing)。 Generally, post-processes for manufacturing semiconductors include: die bonding process of mounting a printed circuit board (PCB, Printed Circuit Board) with a semiconductor wafer separated from a wafer (wafer) attached; using a metal wire, etc. A wire bonding process for electrically connecting a printed circuit board to which a semiconductor wafer is attached; a molding process for manufacturing a integrated circuit package by sealing the semiconductor wafer and the printed circuit board with a sealing material; and for shipping Semiconductor wafer cutting engineering (Package Sawing).
直到切割半導體封裝的切割過程以各個IC(Integrated Circuit)連續排列的條形態製備。此時，在工程中，半導體晶片以如基板(Substrate)或引線框架(Lead Frame)的形態使用，在封裝切割過程中被切割成單個IC形態。 The dicing process until the semiconductor package is cut is prepared in the form of a continuous array of individual ICs (Integrated Circuit). At this time, in the engineering, the semiconductor wafer is used in a form such as a substrate or a lead frame, and is cut into a single IC form in a package cutting process.
如上所述方式製造的過程中，在鐳射打標(raser Marking)工程會發生誤記在IC上面(Top Surface)記載的資訊(PART NUMBER)的情況。此時，由於不能銷售這些IC，因此，需要消除鐳射打標重新進行鐳射打標或廢棄。 During the manufacturing process as described above, the information (PART NUMBER) recorded on the IC (Top Surface) may be mistakenly recorded during the laser marking process. At this time, since these ICs cannot be sold, it is necessary to eliminate laser marking and perform laser marking again or discard it.
若廢棄處理IC，則不利於節儉費用方面，因此，摸索消除鐳射打標重新利用的方法。 Disposal of ICs is not conducive to cost savings. Therefore, a method of eliminating and reusing laser marking has been explored.
直作為此方法，有以下方法：第一，因鐳射打標的深度為50μm，將前面切削為50μm的方法，第二，在鐳射打標上面塗布特殊墨水硬化的方法。所述第一方法存在顏色變化的問題，第二方法存在由於用手塗布特殊墨水的所有過程，因此，收率低的問題。 As this method, there are the following methods: first, because the laser marking depth is 50 μm, the front is cut by 50 μm, and second, the laser marking is coated with a special ink to harden. The first method has a problem of color change, and the second method has a problem of low yield due to all processes of applying special ink by hand.
由於從印刷電路板等去除的半導體晶片為高價，因此，比起廢棄優選回收利用，但是，由於工作人員需對回收利用的半導體晶片進行手工作，因此，存在耗時間多的問題。 Since semiconductor wafers removed from printed circuit boards and the like are expensive, recycling is preferred over disposal. However, since workers need to perform manual work on the recycled semiconductor wafers, there is a problem that it takes a lot of time.
本發明的目的在於解決所述問題以及其他問題。其他目的在於，提供一種回收利用在製造工程中判斷為不良或已使用的半導體封裝的方法，由此製造的回收利用半導體以及為其的夾具。 It is an object of the present invention to solve the problems and other problems. Another object is to provide a method for recycling a semiconductor package that has been judged to be defective or used in a manufacturing process, and to recycle the semiconductor manufactured therefrom and a jig therefor.
為達成所述或其他目的，根據本發明的一側面，可以提供半導體封裝回收利用方法，其中包括：回收要再利用的半導體封裝的步驟；將所述回收的多個半導體封裝 裝載在形成有多個大小與半導體封裝對應的開口部的夾具的步驟；重新模制裝載在所述夾具上的半導體封裝的模制面的步驟；以及切割所述重新模制的半導體封裝的步驟，經由所述重新模制的半導體封裝的厚度增加了50至1000μm。 In order to achieve the stated or other objectives, according to one aspect of the present invention, a method for recycling semiconductor packages may be provided, including: a step of recycling a semiconductor package to be reused; and loading the recovered plurality of semiconductor packages in A step of a jig having an opening portion corresponding to a semiconductor package; a step of re-molding a molding surface of the semiconductor package mounted on the jig; and a step of cutting the re-molded semiconductor package through the re-molding The thickness of the molded semiconductor package is increased by 50 to 1000 μm.
根據本發明的一側面，所述夾具由金屬板而形成，在一面可附著與所述半導體封裝的另一面相對的密封部件。 According to one aspect of the present invention, the jig is formed of a metal plate, and a sealing member opposite to the other surface of the semiconductor package can be attached to one side.
根據本發明的一側面，在所述裝載步驟中，所述回收的半導體封裝可連續排列在所述夾具上。 According to one aspect of the present invention, in the loading step, the recovered semiconductor packages may be continuously arranged on the jig.
根據本發明的一側面，回收所述半導體封裝的步驟，包括：從疊層2個以上的半導體封裝而形成的疊層型半導體封裝分離出要再利用的半導體封裝的步驟；以及去除形成在所述分離的半導體封裝的另一面的焊球的步驟。 According to one aspect of the present invention, the step of recovering the semiconductor package includes: a step of separating a semiconductor package to be reused from a stacked semiconductor package formed by stacking two or more semiconductor packages; and removing the semiconductor package formed in the semiconductor package. The steps of separating the solder balls on the other side of the semiconductor package are described.
根據本發明的一側面，用於所述重新模制的環氧樹脂模塑膠(EMC,Epoxy Molding Compound)的玻璃轉移溫度為180℃以上。 According to one aspect of the present invention, a glass transition temperature of the epoxy molding compound (EMC, Epoxy Molding Compound) used for the remolding is 180 ° C or more.
根據本發明的一側面，進一步包括：在所述重新模制步驟以後對所述要再利用的半導體封裝的另一面附著焊球的步驟；以及在所述附著焊球的步驟以後，對所述重新模制面進行鐳射打標的步驟。 According to one aspect of the present invention, further comprising: a step of attaching a solder ball to the other side of the semiconductor package to be reused after the remolding step; and after the step of attaching the solder ball, Steps to re-mold faces for laser marking.
根據本發明的一側面，可以提供回收利用半導體封裝，其中回收要再利用的半導體封裝，重新模制所述回 收的半導體封裝的模制面，重新模制的半導體封裝的厚度增加了50至1000μm。 According to one aspect of the present invention, it is possible to provide a recycled semiconductor package, in which a semiconductor package to be reused is recycled, a molding surface of the recycled semiconductor package is remolded, and a thickness of the remolded semiconductor package is increased by 50 to 1000 μm. .
根據本發明的一側面，其為用於回收利用在一面形成有模製件的半導體封裝的夾具，其中包括：金屬板，用於裝載回收的多個半導體封裝，形成有多個開口部，所述多個開口部的大小與所述半導體封裝相對應；以及密封部件，與所述半導體封裝的另一面相對地設置在所述金屬板的一面。 According to one aspect of the present invention, it is a jig for recycling a semiconductor package having a molded part formed on one side, which includes a metal plate for loading and recycling a plurality of semiconductor packages with a plurality of openings formed thereon. A size of the plurality of openings corresponds to the semiconductor package; and a sealing member is provided on one surface of the metal plate opposite to the other surface of the semiconductor package.
根據本發明的一側面，所述金屬板由銅板而成，所述多個開口部以預定間隔連續形成。 According to one aspect of the present invention, the metal plate is made of a copper plate, and the plurality of openings are continuously formed at predetermined intervals.
說明根據本發明的半導體封裝回收利用裝置及方法的效果為如下。 The effects of the device and method for recycling semiconductor packages according to the present invention are as follows.
根據本發明的實施例中的至少一實施例，存在不廢棄被判斷為不良或已使用的半導體封裝而能夠回收利用的優點。 According to at least one of the embodiments of the present invention, there is an advantage that a semiconductor package that is judged to be defective or used is not discarded and can be recycled.
根據本發明的實施例中的至少一實施例，通過在已模制的部分重疊模制，存在對外部衝擊更加安全的優點。 According to at least one of the embodiments of the present invention, there is an advantage that it is safer against external impact by overmolding the molded part.
根據本發明的實施例中的至少一實施例，通過防止半導體封裝的變形，改善組裝精密度及焊接可靠性，可 以提高安裝半導體元件時的生產性。 According to at least one of the embodiments of the present invention, by preventing deformation of the semiconductor package, improving assembly accuracy and soldering reliability, it is possible to improve productivity when mounting a semiconductor element.
根據本發明的實施例中的至少一實施例，通過防止發生半導體封裝的變形，在安裝時與半導體元件的電連接出色，從而可以提高半導體封裝的生產收率。 According to at least one of the embodiments of the present invention, by preventing deformation of the semiconductor package, the electrical connection with the semiconductor element during mounting is excellent, so that the production yield of the semiconductor package can be improved.
根據本發明的實施例中的至少一實施例，存在利用現有的工程可以回收利用半導體晶片的效果。 According to at least one of the embodiments of the present invention, there is an effect that semiconductor wafers can be recycled using existing processes.
根據本發明的實施例中的至少一實施例，通過將多個半導體封裝形成為連續排列的條形(Strip)，從而，一次能回收利用更多的半導體晶片。 According to at least one of the embodiments of the present invention, by forming a plurality of semiconductor packages into a stripe in a continuous arrangement, more semiconductor wafers can be recycled at a time.
可適用本發明的附加範圍可通過以下的詳細說明將會明確。但是，本領域的技術人員可以明確理解在本發明的思想及範圍內所做的各種變更及修改，因此，應理解為詳細說明及如本發明的優選實施例的特定實施例是舉例說明的。 Additional scopes to which the present invention can be applied will be made clear by the following detailed description. However, those skilled in the art can clearly understand various changes and modifications made within the spirit and scope of the present invention, and therefore, it should be understood that the detailed description and specific embodiments as the preferred embodiments of the present invention are illustrated.
10‧‧‧夾具 10‧‧‧ Fixture
11‧‧‧金屬板 11‧‧‧ metal plate
12‧‧‧隔壁 12‧‧‧ next door
13‧‧‧密封部件 13‧‧‧sealing parts
14‧‧‧凹槽 14‧‧‧ groove
100‧‧‧半導體封裝 100‧‧‧Semiconductor Package
110‧‧‧半導體晶片 110‧‧‧Semiconductor wafer
120‧‧‧基板 120‧‧‧ substrate
130‧‧‧金屬線 130‧‧‧metal wire
140‧‧‧焊球 140‧‧‧soldering ball
150‧‧‧模塑料 150‧‧‧moulding compound
160‧‧‧黏合劑 160‧‧‧Adhesive
200‧‧‧疊層型半導體封裝 200‧‧‧ stacked semiconductor package
200a‧‧‧第一半導體封裝 200a‧‧‧First semiconductor package
200b‧‧‧第二半導體封裝 200b‧‧‧Second Semiconductor Package
圖1是根據本發明的半導體封裝的截面圖。 FIG. 1 is a cross-sectional view of a semiconductor package according to the present invention.
圖2是根據本發明的回收利用半導體封裝的前處理工程順序圖。 FIG. 2 is a sequence diagram of a pre-processing process for recycling a semiconductor package according to the present invention.
圖3是根據本發明的夾具的立體圖。 Fig. 3 is a perspective view of a jig according to the present invention.
圖4是根據本發明的重新模制的半導體封裝的模制面的示意圖。 FIG. 4 is a schematic diagram of a molding surface of a remolded semiconductor package according to the present invention.
圖5是沿圖4的A-A線的截面圖。 Fig. 5 is a sectional view taken along the line A-A in Fig. 4.
圖6是通過本發明的一實施例的工程裝載半導體封裝的狀態的夾具的示意圖。 FIG. 6 is a schematic diagram of a jig in a state in which a semiconductor package is mounted by a process according to an embodiment of the present invention.
圖7是根據本發明的半導體封裝回收利用方法的流程圖。 FIG. 7 is a flowchart of a method for recycling semiconductor packages according to the present invention.
圖8是根據本發明的疊層的半導體封裝的模式圖。 FIG. 8 is a schematic view of a stacked semiconductor package according to the present invention.
下面，參照附圖詳細說明本說明書所公開的實施例，與圖面符號無關對相同或類似的構成要素標注相同的符號，並省略對其的詳細說明。在以下說明中所使用的對構成要素的結尾詞“部”是為了容易撰寫說明書而賦予或混用的，其本身不具備區別的含義或起區別的作用。而且，在說明本說明書公開的實施例時，若判斷對相關公知技術的具體說明會使本說明書的實施例不明確，則省略對其的詳細說明。而且，應理解為附圖是用來更加容易理解本說明書的實施例而提供的，並不限定本說明書中公開的技術思想，包含本發明的思想及技術範圍所包含的所有變更、均等物乃至代替物。 Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the drawings. The same or similar components are denoted by the same symbols regardless of the drawing symbols, and detailed descriptions thereof are omitted. The term “part” used in the following description of the constituent elements is given or mixed for ease of writing the description, and it does not have a distinctive meaning or a distinguishing function. Furthermore, in describing the embodiments disclosed in this specification, if it is judged that the specific description of the related publicly known technology will make the embodiments of this specification unclear, detailed descriptions thereof will be omitted. Moreover, it should be understood that the accompanying drawings are provided to more easily understand the embodiments of the present specification, and do not limit the technical ideas disclosed in the present specification, and include all changes, equivalents, and even the scope of the present invention. substitute.
第一、第二等包含序數的術語可用來說明多樣的構成要素，但是這些構成要素並不由所述術語所限定。使用所述術語的目的是用於區別一個構成要素和其他構成要素。 The terms such as first, second and the like including ordinal numbers can be used to describe various constituent elements, but these constituent elements are not limited by the terms. The term is used to distinguish one constituent element from the other constituent elements.
在文章中沒有明確的含義時，單數的表現包含 複數的表現。 When there is no clear meaning in the article, the singular expression includes the plural expression.
在本發明中，「包括」或「具有」等術語是用來指定說明書中記載的特徵、數字、步驟、動作、構成要素、零件或組合這些的存在，並不排除一個以上的其他的特徵或數字、步驟、動作、構成要素、零件或組合這些的存在或附加可能性。 In the present invention, terms such as "including" or "having" are used to specify the existence of features, numbers, steps, actions, constituent elements, parts, or combinations described in the description, and do not exclude one or more other features or The existence or additional possibility of numbers, steps, actions, constituent elements, parts or combinations.
一般，在半導體技術領域中封裝是將半導體最後產品化的過程，指將電路連接成能夠對半導體晶片傳遞電信號等，並從外部環境安全地保護而進行模制的過程。以往，由於只重視半導體晶片的單一功能，主要進行如DIP(雙列直插式封裝)等插入式封裝，但是，隨著安裝面積的縮小要求，經過SOP(Small Outline Package)、QFP(Quad Flat Package)、TSOP(Thin Small Outline Package)等表面安裝形態的封裝形狀，最近發展到了尺寸與晶片相同的CSP(Chip Size Package)、將多個晶片構成為一個封裝的MCP(Multi Chip Package)、SiP(System In Package)等超小型複合形態。 In general, in the field of semiconductor technology, packaging is a process of finalizing a semiconductor, and refers to a process in which circuits are connected to be capable of transmitting electrical signals to a semiconductor wafer and the like, and are safely protected from the external environment for molding. In the past, because only a single function of the semiconductor wafer was valued, plug-in packages such as DIP (Dual In-line Package) were mainly implemented. However, as the mounting area was reduced, SOP (Small Outline Package), QFP (Quad Flat) Packages (packages), TSOP (Thin Small Outline Package), and other surface-mount package shapes have recently developed into CSP (Chip Size Package) with the same size as the chip, MCP (Multi Chip Package), and SiP that form multiple packages into one package. (System In Package).
半導體封裝技術中，模制工程為了從物理、電、化學衝擊保護半導體封裝而利用模制材料密封半導體封裝來保護半導體晶片，並散發在使用產品時產生的熱的工程。 In the semiconductor packaging technology, a molding process is a process in which a semiconductor package is sealed with a molding material to protect a semiconductor wafer in order to protect the semiconductor package from physical, electrical, and chemical shocks, and to dissipate heat generated during use of the product.
換而言之，半導體晶片是多個微細電路集成而成，其本身不能起半導體成品的作用，會被外部的物理、化學衝擊而損壞。為了防止受損開發了半導體封裝技術，該技 術是將半導體晶片安裝在基板(Lead-frame or PCB：Printed Circuit Board)上後電連接，利用EMC(Epoxy Molding Compound)等密封包裝以從外部的濕氣或雜質保護，從而能夠發揮作為半導體的功能的技術。進一步，本發明的一實施例中，除了利用EMC進行封裝以外，根據半導體晶片的小型化、封裝方式的變化等可通過液相密封劑進行模制。 In other words, a semiconductor wafer is an integration of a plurality of fine circuits, which itself cannot play the role of a semiconductor finished product, and will be damaged by external physical and chemical shocks. In order to prevent damage, a semiconductor packaging technology has been developed. This technology is to mount a semiconductor wafer on a substrate (Lead-frame or PCB: Printed Circuit Board) and then electrically connect it, and use an EMC (Epoxy Molding Compound) or other sealed package to prevent external moisture. Technology that protects against gas or impurities so that it can function as a semiconductor. Further, in one embodiment of the present invention, in addition to encapsulation using EMC, the liquid crystal sealant may be used for molding according to the miniaturization of the semiconductor wafer, changes in the packaging method, and the like.
所述半導體封裝可分為將半導體晶片與各種基板(Lead Frame,Package Substrate等)連接的步驟；以及連接上述基板(Substrate)和主機板的步驟。嚴格的講，第二步驟應定義為組裝(assembly)工程而不是封裝工程，但是，可包含於廣義的封裝範圍。 The semiconductor package can be divided into a step of connecting a semiconductor wafer with various substrates (Lead Frame, Package Substrate, etc.); and a step of connecting the above substrate (Substrate) and a motherboard. Strictly speaking, the second step should be defined as an assembly project rather than a packaging project, but it can be included in a broader scope of packaging.
作為執行第一步驟的方法有金屬佈線(Metal Wiring)方式和凸點(Bumping)方式，作為執行第二步驟的方法有使用引線框架(Lead Frame)的方式和使用球(Ball)的方式(BGA：Ball Grid Array)。 As a method of performing the first step, there are a metal wiring method and a bumping method. As a method of performing the second step, there are a method using a lead frame and a method using a ball (BGA). : Ball Grid Array).
本發明的一實施例中，將由所述第一步驟而形成的結構稱為上部結構，由第二步驟而形成的結構稱為下部結構。 In an embodiment of the present invention, the structure formed by the first step is referred to as an upper structure, and the structure formed by the second step is referred to as a lower structure.
即所述上部結構是指半導體晶片和基板(Substrate)之間的連接部，所述下部結構是指基板(Substrate)和主機板(Main Board)之間的連接部。所述半導體晶片包含CPU、GPU、各種ASIC等非記憶體半導體以 及DRAM、快閃記憶體(Flash Memory)等記憶體半導體。所述基板(Substrate)包括傳統的引線框架(Lead Frame)方式和球(Ball)方式(Package Substrate,BGA,CSP等有各種稱呼)。主機板是指構成電子產品電路部的基板的PCB(Printed Circuit Board)，有PC的主機板(Mother Board)或手機的主機板(Main Board)。 That is, the upper structure refers to a connection portion between a semiconductor wafer and a substrate (Substrate), and the lower structure refers to a connection portion between a substrate (Substrate) and a main board (Main Board). The semiconductor chip includes a non-memory semiconductor such as a CPU, a GPU, and various ASICs, and a memory semiconductor such as a DRAM or a flash memory. The substrate includes a traditional lead frame method and a ball method (Package Substrate, BGA, CSP, etc. have various names). The main board refers to a printed circuit board (PCB) constituting a substrate of an electronic product circuit section. There are a mother board of a PC or a main board of a mobile phone.
另外，以三維方式疊層IC的技術可包括晶圓疊層(wafer-on-wafer)、管芯疊層晶圓(die-on-wafer)、管芯疊層管芯(die-on-die)、以及封裝疊層封裝(package-on-package，PoP)。作為一例，封裝疊層封裝構造物的典型的形成工程中，2個以上的IC封裝體為了路由選擇其之間的信號具有電通信介面相互疊層。此構造體在手機、個人數位助理(personal digital assistant，PDA)以及數位相機等裝置上允許更高的零件密度。尤其，LPDDR(Low Power DDR)是為用於智慧手機、平板電腦等移動設備而開發的DDR SDRAM，其特徵是耗電少，本發明的一實施例是與此相關的技術。此時，所述LPDDR存在由於比NAND記憶體薄、面積大，因此對熱脆弱，容易發生熱變形(warpage)的問題。 In addition, the technology of stacking ICs in three dimensions may include wafer-on-wafer, die-on-wafer, and die-on-die. ), And package-on-package (PoP). As an example, in a typical formation process of a package-and-stack package structure, two or more IC packages have electrical communication interfaces stacked on each other for routing signals therebetween. This structure allows higher part density on devices such as mobile phones, personal digital assistants (PDAs), and digital cameras. In particular, LPDDR (Low Power DDR) is a DDR SDRAM developed for use in mobile devices such as smart phones and tablet computers. It is characterized by low power consumption. An embodiment of the present invention is related to this technology. At this time, the LPDDR has a problem that it is thinner and larger in area than a NAND memory, and therefore vulnerable to heat, and is prone to thermal warpage.
另外，半導體製造工程分為在晶圓上面形成電路的前工程(FE：Front-End)和後工程(BE：Back-End)，前工程再分為晶圓擴散(Wafer Diffusion)工程和晶圓測試 (Wafer Test)工程，後工程再分為封裝工程(或者組裝工程)和測試工程。 In addition, the semiconductor manufacturing process is divided into a front process (FE: Front-End) and a back process (BE: Back-End) where circuits are formed on the wafer, and the front process is further divided into a wafer diffusion (Wafer Diffusion) process and a wafer. The test (Wafer Test) project is divided into packaging engineering (or assembly engineering) and testing engineering.
本發明的一實施例涉及所述後工程中的尤其封裝工程，所述半導體封裝工程大致為如下。 An embodiment of the present invention relates to a packaging process in particular in the post-processing. The semiconductor packaging process is roughly as follows.
半導體封裝工程包括：利用含有無定型氧化矽、四甲基氫氧化銨(TMAH)等的研磨液研磨在半導體前工程經加工的晶圓的背面的工程所謂背面研磨(Back Grinding)工程；利用含有介面活性劑等的切削液等以個別單位切割所述晶圓的工程所謂晶圓切割(Wafer Sawing(Dicing))工程；利用含有環氧樹脂、酚醛樹脂等的粘合劑在基板(substrate)粘合固定被切割的所述晶片的工程所謂晶片粘合(Die Attaching)工程；利用金絲等金屬線電連接晶片的工程所謂引線鍵合(Wire Bonding)工程；為了從外部環境保護晶片，利用由環氧樹脂、酚醛樹脂、二氧化矽等而組成的環氧樹脂模塑膠(EMC)等包裹晶片的工程所謂模塑(Molding)工程；用鐳射對各產品標刻產品資訊的工程所謂鐳射打標(Laser Marking)工程；在電路基板塗覆焊劑(flux)粘接焊球(solder ball)製備輸出端的工程所謂焊球附著(Solder Ball Mount)工程；切割成單獨的半導體並安裝到模組/板/卡的工程所謂封裝切割(Package Sawing)工程。 The semiconductor packaging process includes: the process of polishing the back of the processed wafer with a polishing solution containing amorphous silicon oxide, tetramethylammonium hydroxide (TMAH), etc .; the so-called back grinding process; Wafer Sawing (Dicing) process in which the wafer is cut in individual units by a cutting fluid such as an interface active agent; the substrate is adhered to the substrate using an adhesive containing an epoxy resin, a phenolic resin, or the like. The process of holding and fixing the cut wafer is called a die attaching process; the process of electrically connecting the wafers with metal wires such as gold wires is a wire bonding process; in order to protect the wafers from the outside, The process of encapsulating wafers such as epoxy resin molding compound (EMC) composed of epoxy resin, phenol resin, silicon dioxide, etc. is called the molding process; the process of marking product information with lasers is called laser marking (Laser Marking) project; the process of applying flux to the circuit substrate to bond solder balls to prepare the output end; the so-called solder ball mounting process; cutting Into individual semiconductor and is mounted to the module / board / card package called engineering cutting (Package Sawing) project.
此時，圖1是根據本發明的半導體封裝100的截 面圖，參照圖1，在基板120安裝有半導體晶片110的狀態的半導體封裝100，一般由半導體晶片110、基板120、金屬線130(或者凸點)、焊球140(或者引線框架)、模塑料150、粘合劑160等而組成。各組成要素的功能為如下。本發明的一實施例中，已封裝所述半導體晶片110的零件指稱為半導體封裝100。 At this time, FIG. 1 is a cross-sectional view of a semiconductor package 100 according to the present invention. Referring to FIG. 1, a semiconductor package 100 in a state where a semiconductor wafer 110 is mounted on a substrate 120 is generally composed of a semiconductor wafer 110, a substrate 120, and a metal wire 130 (or Bumps), solder balls 140 (or lead frames), molding compound 150, adhesive 160, and the like. The functions of each component are as follows. In an embodiment of the present invention, a component in which the semiconductor wafer 110 has been packaged is referred to as a semiconductor package 100.
首先，基板120(substrate)安裝有半導體晶片110的部件，在半導體晶片110和主印刷電路板(PCB)之間起電信號連接通道作用，是在絕緣體的上面排列能夠傳遞電信號的導體的結構，將半導體晶片110的微細佈線變換為主印刷電路板的規模。 First, the substrate 120 (substrate) is mounted with components of the semiconductor wafer 110, and functions as an electrical signal connection channel between the semiconductor wafer 110 and a main printed circuit board (PCB). It is a structure in which conductors capable of transmitting electrical signals are arranged on an insulator The micro-wiring of the semiconductor wafer 110 is converted to a scale of a main printed circuit board.
金屬線130相互連接半導體晶片110和基板120之間，主要使用金(Au)或銅(Cu)等，還可以使用在半導體晶片110的焊盤(Pad)上形成突起的凸點(Bump)來代替金屬線130。 The metal wire 130 connects the semiconductor wafer 110 and the substrate 120 to each other. Gold (Au) or copper (Cu) is mainly used. A bump (Bump) formed on the pad (Pad) of the semiconductor wafer 110 may be used. Instead of metal wire 130.
焊球140起相互連接基板120和主電路基板的功能，還可以使用引線框架來代替所述焊球140。 The solder ball 140 functions to connect the substrate 120 and the main circuit substrate to each other, and a lead frame may be used instead of the solder ball 140.
模塑料150是為了模制產品及固定零件而使用。模塑料150的材料可以使用陶瓷、金屬、塑料等，多使用價格低廉的塑料。本發明的一實施例中使用了在環氧樹脂添加矽等無機材料和各種輔助材料(硬化材料、阻燃材料、脫模劑等)的EMC(Epoxy Molding Compound)。 The molding compound 150 is used for molding products and fixed parts. The material of the molding compound 150 may be ceramic, metal, plastic, or the like, and low-cost plastic is often used. In one embodiment of the present invention, EMC (Epoxy Molding Compound) is used in which inorganic materials such as silicon and various auxiliary materials (hardening materials, flame retardant materials, release agents, etc.) are added to the epoxy resin.
所述凸點是導電性突起，其用於將半導體晶片110以載帶自動鍵合(TAB)或倒裝晶片(Flip Chip)方式連接在基板120，或者將BGA及GPS等直接連接至電路基板。與焊線(Bonding Wire)相同，作為凸點的材料可以使用金或焊料(Solder)。所述焊料的材料可以使用鉛和錫(Pb+Sn)或SAC(Sn-Ag-Cu：錫-銀-銅)。 The bumps are conductive protrusions, and are used to connect the semiconductor wafer 110 to the substrate 120 by a tape automatic bonding (TAB) or a flip chip, or directly connect BGA, GPS, and the like to a circuit substrate. . Like the bonding wire, gold or solder can be used as the material of the bumps. The material of the solder may be lead and tin (Pb + Sn) or SAC (Sn-Ag-Cu: tin-silver-copper).
模制工程結束後，進行分離(Singulation)工程，此工程是沿著模塑樹脂和管腳的切割線(Sawing Line)切割成為單位半導體封裝的工程。 After the molding process is completed, a Singulation process is performed. This process is a process of cutting into a unit semiconductor package along a cutting line of a molding resin and a pin.
本發明的一實施例是回收利用已生產使用或者因不良等原因而未使用的半導體封裝的技術，尤其，在PoP封裝中回收利用半導體封裝的技術。 An embodiment of the present invention is a technology for recycling semiconductor packages that have been used in production or unused due to defects, and in particular, a technology for recycling semiconductor packages in PoP packages.
首先，圖2是根據本發明的回收利用半導體封裝的前處理工程順序圖，圖8是根據本發明的疊層型半導體封裝所謂PoP封裝200的概略模式圖，下面，參照圖2及圖8說明回收利用半導體封裝的前處理(pre-treatment)工程。所述前處理工程主要是關於分離要回收利用的半導體封裝(或者半導體晶片)的工程。本發明的一實施例是關於回收利用如PoP(Package on Package)形態疊層的半導體封裝200的一部分的方法，作為PoP結構是適用於例如疊層移動DRAM(或LPDDR)晶片封裝(以下，稱為第一半導體封裝200a)及移動應用處理器(Application Processor,AP)晶片封裝(以下， 稱為第二半導體封裝200b)的技術。由於PoP是在焊盤上面雙重疊層封裝，因此可以加大每單位面積的效率。PoP不僅用於疊層LPDDR晶片封裝200a和移動AP晶片封裝200b，而且，還適用於疊層移動AP晶片封裝和通信用基帶晶片封裝。 First, FIG. 2 is a sequence diagram of a pretreatment process for recycling a semiconductor package according to the present invention, and FIG. 8 is a schematic diagram of a so-called PoP package 200 of a stacked semiconductor package according to the present invention. Pre-treatment process for recycling semiconductor packages. The pretreatment process is mainly a process for separating a semiconductor package (or a semiconductor wafer) to be recycled. An embodiment of the present invention relates to a method for recycling a part of a semiconductor package 200 stacked in a PoP (Package on Package) form. The PoP structure is suitable for, for example, a stacked mobile DRAM (or LPDDR) chip package (hereinafter, referred to as The technology is a first semiconductor package 200a) and a mobile application processor (Application Processor (AP)) chip package (hereinafter, referred to as a second semiconductor package 200b). Since PoP is a double-layer package on the pad, the efficiency per unit area can be increased. PoP is not only used for stacked LPDDR chip package 200a and mobile AP chip package 200b, but also suitable for stacked mobile AP chip package and baseband chip package for communication.
即，本發明的一實施例主要適用於回收利用PoP，更具體地，適用於回收利用移動LPDDR晶片封裝(第一半導體封裝200a)和移動AP晶片封裝(第二半導體封裝200b)的第一半導體封裝200a和第二半導體封裝200b，還可適用於通信用基帶晶片封裝(第一半導體封裝200a)和移動AP晶片封裝(第二半導體封裝200b)的晶片封裝。此時，適用於PoP的晶片(DRAM，AP，BB)比其他的晶片大，所以，需要減小封裝空間，為此，通過在第二半導體封裝200b的上面雙重疊層其他封裝的第一半導體封裝200a，從而，PoP可以減小封裝空間。 That is, an embodiment of the present invention is mainly applicable to recycling PoP, and more specifically, it is applicable to recycling a first semiconductor of a mobile LPDDR chip package (first semiconductor package 200a) and a mobile AP chip package (second semiconductor package 200b). The package 200a and the second semiconductor package 200b are also applicable to a chip package for a communication baseband chip package (first semiconductor package 200a) and a mobile AP chip package (second semiconductor package 200b). At this time, the chips suitable for PoP (DRAM, AP, BB) are larger than other chips. Therefore, it is necessary to reduce the packaging space. To this end, the second semiconductor package 200b is double-stacked on top of the first semiconductor of another package The package 200a is packaged, so that the PoP can reduce the package space.
若需再利用的半導體封裝200入庫，則執行入庫及檢測(S110)。在此過程中，確認搬運數量的同時，用眼睛確認原材料是否為不良。然後，以板(board)狀態在約125℃下實行烘乾工程(S120)240分鐘，去除留在板上的濕氣。此時，對半導體封裝第一次施加熱。此時的板是包括所述第一半導體封裝200a及第二半導體封裝200b的狀態。 If the semiconductor package 200 to be reused is stored, storage and inspection are performed (S110). In this process, while confirming the quantity to be transported, confirm with your eyes whether the raw materials are defective. Then, a drying process (S120) was performed in a board state at about 125 ° C for 240 minutes to remove moisture remaining on the board. At this time, heat is applied to the semiconductor package for the first time. The board at this time is in a state including the first semiconductor package 200a and the second semiconductor package 200b.
以往，在半導體封裝工程中以錫(Sn)和鉛(Pb)為主成分執行錫焊，可在220℃以下的溫度下進行封裝。但 是，最近不能使用鉛，在錫混合銀(Ag)和銅(Cu)，因此，熔點比以前高，為約221℃。因此，現在不能執行以往在220℃以下的溫度下執行的工程，為了順利執行工程，至少保持245℃以上的溫度。如此，因工程的溫度變高，對熱變形帶來更不好的影響。若不進行烘乾工作，則在板上回出現龜裂或孔。 In the past, soldering was mainly performed with tin (Sn) and lead (Pb) in semiconductor packaging engineering, and packaging was performed at a temperature of 220 ° C or lower. However, recently, lead cannot be used, and since silver (Ag) and copper (Cu) are mixed in tin, the melting point is higher than before and is about 221 ° C. Therefore, it is not possible to perform a project previously performed at a temperature lower than 220 ° C. In order to smoothly execute the project, a temperature of at least 245 ° C is maintained. In this way, as the temperature of the process becomes higher, it has a worse effect on thermal deformation. If drying is not performed, cracks or holes will appear on the board.
而且，在堆積已入庫到分離設備上的半導體封裝200的狀態下，利用分離工具(detach tool)在245℃以下的溫度分離對象半導體封裝200a(S130)。此時，對所述第一半導體封裝200a第一次施加熱。在分離工程中利用顯微鏡確認對象半導體封裝即第一半導體封裝200a是否有封裝龜裂或刮痕(scratch)。 Then, in a state where the semiconductor packages 200 that have been stored in the separation device are stacked, the target semiconductor package 200a is separated by a detach tool at a temperature of 245 ° C. or less (S130). At this time, heat is applied to the first semiconductor package 200a for the first time. In the separation process, it is confirmed with a microscope whether the target semiconductor package, that is, the first semiconductor package 200a has a package crack or a scratch.
然後，在第一半導體封裝200a的邊緣上有突出的底填劑(underfill)時去除底填劑，並去除被粘在所述第一半導體封裝200a的焊球墊面上的剩餘焊料及底填劑。此時的底填劑可為熱硬化性樹脂。在本發明的一實施例中，將所述工程稱為修整(dressing)工程(S140)。所述修整工程在約250℃下執行60秒，對所述第一半導體封裝200a第二次施加熱。然後，執行清洗及乾燥(cleaning and dry)工程(S150)，以去除在去除底填劑及修整工程中留下的焊劑及剩餘物。此時，利用蒸餾水(de-ionized water,DI water)進行清洗。所述焊劑為水溶性時，由於可溶解於水，因此可以 利用純淨水(pure water)即DI water用刷子等進行清洗。並檢查所述第一半導體封裝200a是否有龜裂、刮痕等，並檢查圖形是否翹起(lift)等。通過如上所述的前處理工程從半導體封裝200分離需要再利用的半導體封裝200a並成為去除焊料的狀態。 Then, when there is a protruding underfill on the edge of the first semiconductor package 200a, the underfill is removed, and the remaining solder and underfill that are stuck on the solder ball pad surface of the first semiconductor package 200a are removed. Agent. The underfill at this time may be a thermosetting resin. In an embodiment of the present invention, the process is referred to as a dressing process (S140). The trimming process is performed at about 250 ° C. for 60 seconds, and heat is applied to the first semiconductor package 200 a for a second time. Then, a cleaning and dry process (S150) is performed to remove the flux and residues left in the underfill removal and trimming process. At this time, washing was performed using de-ionized water (DI water). When the flux is water-soluble, it can be dissolved in water, so it can be cleaned with a brush such as pure water (DI water). It is also checked whether the first semiconductor package 200a is cracked, scratched, etc., and whether the pattern is lifted or not. The semiconductor package 200a to be reused is separated from the semiconductor package 200 through the pre-processing process as described above, and the solder is removed.
若前處理工程結束，重新模制第一半導體封裝200a。重新模制工程之後，在半導體晶片的表面塗覆焊劑，然後利用手動模板(manual stencil)等設備執行形成焊球(solder ball)的焊球附著(solder ball attach)工程之後，檢查焊球是否被消失或者是否與鄰接的焊球接觸。然後，利用回流(reflow)在約250℃下執行焊接(soldering)。通過此時的焊接工程，對所述第一半導體封裝200a第三次施加熱。此時的檢查是確認焊球是否被丟失(missing ball)或兩個以上的焊球是否相接觸的步驟。 If the pre-processing process is completed, the first semiconductor package 200a is re-molded. After the remolding process, apply a flux to the surface of the semiconductor wafer, and then use a manual stencil or other equipment to perform a solder ball attaching process to form a solder ball, and check whether the solder ball is Disappear or contact with adjacent solder balls. Then, soldering was performed using reflow at about 250 ° C. Through the soldering process at this time, heat is applied to the first semiconductor package 200 a for the third time. The inspection at this time is a step of confirming whether a solder ball is missing or whether two or more solder balls are in contact.
然後，按照的客戶的要求真空包裝等後交貨。 Then, it is vacuum-packed and delivered in accordance with customer requirements.
如此，不僅在製造半導體封裝的工程，在回收利用的過程中也對半導體封裝施加3次熱。因此熱第一半導體封裝200a發生熱變形，本發明的一實施例不僅能改善熱變形現象，還能回收利用第一半導體封裝200a。 In this way, not only in the process of manufacturing a semiconductor package, but also in the process of recycling, heat is applied to the semiconductor package three times. Therefore, the thermal first semiconductor package 200a is thermally deformed. An embodiment of the present invention can not only improve the thermal deformation phenomenon, but also recycle the first semiconductor package 200a.
一般，半導體封裝根據工程中的溫度發生各種各樣的熱變形。即EMC模制過程中，在固化(curing)及冷卻工程中發生熱變形，而且，在焊料回流的過程中也發生變 形。發生熱變形是因為根據所使用封裝材料的熱膨脹係數(Coefficient Thermal Expansion,CTE)之差而發生的熱應力。更具體而言，熱變形及損壞是封裝工程中因不同的熱膨脹係數及溫度差而發生的熱應力和內部殘留應力而發生。封裝的熱變形現象取決於封裝的結構、封裝材料的物性及工程條件。因此，需要選擇適當的封裝材料及適當的封裝結構。此條件同樣適用於回收利用半導體封裝的封裝(重新模制)工程。 Generally, a semiconductor package undergoes various thermal deformations depending on the temperature in the process. That is, during the EMC molding process, thermal deformation occurs during curing and cooling processes, and deformation also occurs during solder reflow. Thermal deformation occurs because of thermal stress that occurs according to the difference in the coefficient of thermal expansion (CTE) of the packaging material used. More specifically, thermal deformation and damage are caused by thermal stress and internal residual stress that occur due to different thermal expansion coefficients and temperature differences in packaging engineering. The thermal deformation of a package depends on the structure of the package, the physical properties of the packaging material, and the engineering conditions. Therefore, it is necessary to select an appropriate packaging material and an appropriate packaging structure. This condition also applies to the packaging (remolding) process for recycling semiconductor packages.
半導體封裝的熱變形現象可以利用懸臂梁(cantilever beam)模型而定義。接合物性相不同的梁時，根據施加的溫度而發生熱變形現象。封裝時導致熱變形現象的最大因素是不同材料之間的熱膨脹係數(單位ppm/℃)之差。由於在製備封裝的工程中不可避免地發生的高溫，因此，會發生熱變形現象，根據材料的CTE決定熱變形的狀態。發生熱變形的最代表性的工程是模制工程，在所述模制工程中主要施加的溫度是約120℃至180℃。尤其，本發明的一實施例的重新模制工程中將溫度限定在約170℃至180℃。 The thermal deformation phenomenon of a semiconductor package can be defined using a cantilever beam model. When joining beams having different physical properties, a thermal deformation phenomenon occurs depending on the applied temperature. The biggest factor that causes thermal deformation during packaging is the difference in thermal expansion coefficients (units ppm / ° C) between different materials. Due to the unavoidable high temperature in the process of preparing the package, a thermal deformation phenomenon occurs, and the state of thermal deformation is determined according to the CTE of the material. The most representative process in which thermal deformation occurs is a molding process, in which the mainly applied temperature is about 120 ° C to 180 ° C. In particular, in the remolding process of an embodiment of the present invention, the temperature is limited to about 170 ° C to 180 ° C.
因EMC和半導體晶片之間的CTE之差，溫度從約170℃變化至常溫(25℃)，因此，半導體封裝發生熱變形，封裝為凸出形態時，稱為negative warpage或crying warpage，往下凹陷時，稱為positive warpage或smile warpage。 Due to the difference between the CTE between EMC and the semiconductor wafer, the temperature changes from about 170 ° C to normal temperature (25 ° C). Therefore, the semiconductor package is thermally deformed. When the package is in a protruding form, it is called a negative warpage or crying warpage. When sunken, it is called positive warpage or smile warpage.
在半導體封裝發生熱變形的具體理由為如下。 仔細觀察半導體封裝的內部可知存在構成半導體封裝的典型的幾種材料。由矽組成的半導體晶片、固定所述半導體晶片可接電線的由銅(Cu)材料而組成的引線框架(Lead frame)或有高分子(Polymer)材料而組成的基板(substrate)、用於將所述半導體晶片粘接在引線框架或基板上的熱硬化性樹脂粘合劑即粘合劑(Adhesive)或底填劑、以及覆蓋上面所有組成的EMC(Epoxy Molding Compound)。還有與所述半導體晶片和引線框架/基板成為電通道的金絲(Gold(Au)wire)/錫凸點(Tin(Sn)bump)等。 The specific reason for thermal deformation in a semiconductor package is as follows. A closer look at the inside of the semiconductor package reveals that there are several typical materials that make up a semiconductor package. A semiconductor wafer composed of silicon, a lead frame made of a copper (Cu) material or a substrate made of a polymer material that fixes the semiconductor wafer and can be connected to a wire, and is used for The semiconductor wafer is bonded to a lead frame or a substrate with a thermosetting resin adhesive, that is, an adhesive or an underfill, and EMC (Epoxy Molding Compound) covering all the components. There is also a gold (Au) wire / tin (Sn) bump which is an electrical channel with the semiconductor wafer and the lead frame / substrate.
本發明的一實施例中，在回收利用半導體封裝的過程中，包含半導體晶片的半導體封裝有時會被加熱，施加溫度高達270℃。在此過程中，在半導體封裝200a發生熱變形。 In an embodiment of the present invention, during the process of recycling the semiconductor package, the semiconductor package including the semiconductor wafer is sometimes heated, and the application temperature is as high as 270 ° C. During this process, thermal deformation occurs in the semiconductor package 200a.
所述半導體晶片附著在AP(Application Processor)、基板(substrate)或印刷電路板(PCB)等板(board)上而使用時，因半導體晶片和板之間的熱膨脹之差對焊接接合部的壽命導致影響，因焊接接合部的反復變形最後發生破裂(crack)。為此，減小半導體晶片(或半導體封裝)和板之間的熱膨脹之差為非常重要。 When the semiconductor wafer is used by being attached to a board such as an AP (application processor), a substrate, or a printed circuit board (PCB), the life of the solder joint is affected by the difference in thermal expansion between the semiconductor wafer and the board. As a result, cracks may occur due to repeated deformation of the welded joint. For this reason, it is very important to reduce the difference in thermal expansion between the semiconductor wafer (or semiconductor package) and the board.
因此，作為能夠減小熱變形的方案優選使用熱膨脹係數與半導體晶片類似的EMC。但實際上很難開發具有與半導體晶片類似的熱膨脹係數的EMC，因此，需要儘量減 低EMC的熱膨脹係數。 Therefore, as a solution capable of reducing thermal deformation, it is preferable to use EMC having a thermal expansion coefficient similar to that of a semiconductor wafer. However, it is actually difficult to develop EMC with a thermal expansion coefficient similar to that of semiconductor wafers. Therefore, it is necessary to minimize the thermal expansion coefficient of EMC.
進一步，除了使用熱膨脹係數低的EMC之外，還能考慮使用玻璃轉移溫度(Tg)高的EMC的方法。通常，EMC的熱膨脹係數以Tg為準大大增加，因此，當EMC材料的Tg高於模制溫度時，只有Tg前的CTE對半導體封裝的熱變形導致影響，因此，通過提高Tg來獲得能夠減小半導體封裝的熱變形的效果。即，本發明的一實施例中，使用玻璃轉移溫度為180℃以上的環氧模塑料150。 Furthermore, in addition to using EMC with a low thermal expansion coefficient, a method using EMC with a high glass transition temperature (Tg) can also be considered. Generally, the thermal expansion coefficient of EMC is greatly increased based on Tg. Therefore, when the Tg of EMC material is higher than the molding temperature, only the CTE before Tg will affect the thermal deformation of the semiconductor package. Therefore, it can be reduced by increasing Tg. The effect of thermal deformation of small semiconductor packages. That is, in one embodiment of the present invention, an epoxy molding compound 150 having a glass transition temperature of 180 ° C. or higher is used.
下面參照附圖說明根據本發明的一實施例的用於回收利用半導體封裝100的裝置以及利用此裝置的半導體封裝100的回收利用方法。 An apparatus for recycling the semiconductor package 100 and a method for recycling the semiconductor package 100 using the same according to an embodiment of the present invention will be described below with reference to the drawings.
首先，圖3是根據本發明的夾具的立體圖，圖7是根據本發明的半導體晶片110的回收利用方法的流程圖，下面參照圖3及圖7進行說明。 First, FIG. 3 is a perspective view of a jig according to the present invention, and FIG. 7 is a flowchart of a recycling method of a semiconductor wafer 110 according to the present invention, which will be described below with reference to FIGS. 3 and 7.
首先，本發明的一實施例的用於回收利用半導體封裝100的夾具10是用於回收利用在一面形成有模製件(Molding)的半導體封裝100的裝置，夾具具備：多個金屬板11，用於裝載經回收的多個半導體封裝100，形成有與所述半導體封裝100對應的大小的多個開口部14；密封部件13，在所述金屬板11的一面與所述半導體封裝100的另一面相面對形成。 First, a jig 10 for recycling a semiconductor package 100 according to an embodiment of the present invention is a device for recycling a semiconductor package 100 having a molding formed on one side thereof. The jig includes a plurality of metal plates 11. A plurality of recovered semiconductor packages 100 are mounted thereon, and a plurality of openings 14 having a size corresponding to the semiconductor package 100 are formed; a sealing member 13 is formed on one surface of the metal plate 11 and another of the semiconductor package 100. Formed face to face.
對所述金屬板11沒有特別的限制，但是，本發 明的一實施例中，通過由銅板製作，不僅節省費用，還能體現與基板類似的功能。 The metal plate 11 is not particularly limited. However, in one embodiment of the present invention, by making a copper plate, not only the cost is saved, but also functions similar to those of the substrate can be realized.
而且，本發明的一實施例是涉及同時回收利用多個半導體晶片110或半導體封裝100的技術，因此，形成在所述金屬板11上的多個開口部14連續形成為多個行及多個列。此時，開口部14的形狀大致與半導體晶片110或半導體封裝100的大小相對應，具有正方形或長方形形狀。嚴格地講具有與半導體封裝100的大小相對應的大小。 Furthermore, an embodiment of the present invention relates to a technology for simultaneously recycling a plurality of semiconductor wafers 110 or semiconductor packages 100. Therefore, the plurality of openings 14 formed in the metal plate 11 are continuously formed in a plurality of rows and a plurality of Column. At this time, the shape of the opening portion 14 substantially corresponds to the size of the semiconductor wafer 110 or the semiconductor package 100 and has a square or rectangular shape. Strictly speaking, it has a size corresponding to the size of the semiconductor package 100.
根據本發明的一實施例的回收利用半導體封裝100的方法是涉及不廢棄從手機、SSD、記憶體模組等分離出的半導體晶片110(Memory IC,Application Processor等)或者在製備工程中被判斷為不良的半導體封裝100、更嚴格地講不廢棄半導體晶片110而回收利用的方法。 The method for recycling the semiconductor package 100 according to an embodiment of the present invention involves not discarding the semiconductor wafer 110 (Memory IC, Application Processor, etc.) separated from a mobile phone, an SSD, a memory module, or the like, or is judged in a manufacturing process. A method for recycling a defective semiconductor package 100 and more strictly, without discarding the semiconductor wafer 110.
作為一例，還可以作為用於遮蓋在模制面鐳射打標的用途而使用，是涉及回收利用在一面形成有模製件(Molding)的半導體封裝100的方法。本發明的一實施例中，所述半導體封裝100的一面是指刻有半導體封裝100的資訊的上面，半導體封裝100的另一面是指形成有焊球140的底面。 As an example, the method can also be used for covering laser marking on a molding surface, and is a method involving recycling a semiconductor package 100 having a molding formed on one surface. In an embodiment of the present invention, one side of the semiconductor package 100 refers to an upper surface engraved with information of the semiconductor package 100, and the other side of the semiconductor package 100 refers to a bottom surface on which the solder balls 140 are formed.
在本發明的一實施例中，為了回收利用半導體封裝100，先回收要再利用的半導體封裝100(S210)，將回收的半導體封裝100裝載(Loading)在形成有多個尺寸與半 導體封裝100對應的開口部14的夾具10上(S220)。此時，所述開口部14由隔壁12而形成，半導體封裝100以與所述隔壁12的內側面相接觸的狀態被裝載。所述隔壁12是在所述金屬板11上除開口部14的剩餘部分。 In an embodiment of the present invention, in order to recycle the semiconductor package 100, the semiconductor package 100 to be reused is recovered first (S210), and the recovered semiconductor package 100 is loaded with a plurality of sizes corresponding to the semiconductor package 100. On the jig 10 of the opening 14 (S220). At this time, the opening portion 14 is formed by the partition wall 12, and the semiconductor package 100 is mounted in a state of being in contact with the inner side surface of the partition wall 12. The partition wall 12 is a portion of the metal plate 11 excluding the opening 14.
本發明的一實施例的半導體封裝的大小雖稍有誤差但被切割為預定的大小，在所述隔壁12和半導體封裝100之間具有可忽視程度的間隔。由此，所述半導體封裝100插入於所述夾具10時以強制插入方式進行插入。如此，通過所述半導體封裝100強制插入於夾具10，從而，模塑料150不會堆積在一處。 Although the size of the semiconductor package according to an embodiment of the present invention is slightly different, it is cut to a predetermined size, and there is a negligible gap between the partition wall 12 and the semiconductor package 100. Therefore, when the semiconductor package 100 is inserted into the jig 10, it is inserted in a forced insertion manner. In this way, the semiconductor package 100 is forcibly inserted into the jig 10 so that the molding compound 150 does not accumulate in one place.
所述經回收的多個半導體封裝100同時裝載在一個夾具10上，從而，一次能回收利用多個半導體晶片110。如此，本發明的一實施例中，通過將回收的多個半導體封裝100裝載在一個夾具10上，從而一次自動回收利用多個半導體晶片110，因此，與以往工作人員進行手工作時相比，有利於節儉費用及縮短時間。 The recovered plurality of semiconductor packages 100 are simultaneously loaded on one jig 10, so that a plurality of semiconductor wafers 110 can be recovered and used at a time. In this way, in one embodiment of the present invention, a plurality of semiconductor packages 100 that are recovered are mounted on one jig 10 to automatically recover and reuse a plurality of semiconductor wafers 110 at a time. Therefore, compared with conventional manual work performed by workers, Conducive to saving costs and shortening time.
此時，在重新模制所述半導體封裝100之前，需要乾淨地去除附著在半導體封裝100的異物。在此過程中，需要去除形成在最初製備完成的半導體封裝100的焊球140。這是因為若形成於半導體封裝100的焊球140哪怕一次粘接在其他的基板上，焊球140也會受損，而難以安裝在電路基板上，並且，不能發揮電性功能。即需要進行去除形成 在半導體封裝100的另一面的焊球140的鉛的工程以及重新附著焊球的工程。若半導體封裝100的焊球140未被損傷，則不需要進行去除及重新附著焊球140的工程。 At this time, before the semiconductor package 100 is remolded, the foreign matter adhering to the semiconductor package 100 needs to be cleanly removed. In this process, it is necessary to remove the solder balls 140 formed in the semiconductor package 100 that is initially prepared. This is because if the solder ball 140 formed on the semiconductor package 100 is adhered to another substrate at a time, the solder ball 140 is damaged, and it is difficult to mount the solder ball 140 on a circuit board, and it cannot perform electrical functions. That is, a process of removing the lead of the solder balls 140 formed on the other surface of the semiconductor package 100 and a process of reattaching the solder balls are required. If the solder ball 140 of the semiconductor package 100 is not damaged, the process of removing and reattaching the solder ball 140 is not required.
然後，重新模制(Remolding)裝載在所述夾具10上的半導體封裝100的一面(S230)。本發明的一實施例是回收利用已完成製造工程的半導體封裝100的例，在最初製造工程中一次性地已模制於半導體晶片110，由於是後模制，所以可稱為重新模制或二次模制(second molding)。即本發明的一實施例中以模制於半導體封裝100的狀態下執行二次模制。所述重新模制工程是通過利用模制模塑樹脂模制半導體晶片110和基板120部件的一部分的積體電路封裝模制裝置而執行，所述模制裝置有上部模具和下部模具而構成。上部模具，為了形成執行模制的模制空間而在上部模具的下面形成凹陷形態的模制槽，在下部模具的上面固定設置半導體封裝100。並且，上部模具緊貼按壓下部模具後，模塑樹脂注入到模制槽內，並對半導體封裝100(SD)執行模制工程。 Then, one side of the semiconductor package 100 loaded on the jig 10 is remolded (S230). An embodiment of the present invention is an example of recycling a semiconductor package 100 that has completed a manufacturing process. The semiconductor package 110 has been molded once in the initial manufacturing process. Since it is post-molded, it can be referred to as re-molding or Secondary molding. That is, in one embodiment of the present invention, the secondary molding is performed in a state where the semiconductor package 100 is molded. The remolding process is performed by molding an integrated circuit package molding device that molds a part of the semiconductor wafer 110 and a part of the substrate 120 with a molding resin, and the molding device includes an upper mold and a lower mold. In the upper mold, a recessed molding groove is formed on the lower surface of the upper mold in order to form a molding space for performing the molding, and the semiconductor package 100 is fixedly provided on the upper surface of the lower mold. In addition, after the upper mold is pressed closely against the lower mold, a molding resin is injected into the molding groove, and a molding process is performed on the semiconductor package 100 (SD).
如此，通過重新模制可以遮蓋形成於半導體封裝100的上面的現有產品資訊。此時，重新模制的厚度應該是安裝在印刷電路板(PCB)時電子設備不變厚的程度。這是考慮製造工程中發生的誤差而設計的，更具體而言，在半導體封裝100鐳射列印時，由鐳射標刻資訊的部分的深度大 約為50μm，通過鐳射填滿標刻資訊的陰刻部分，進而，考慮工程中的誤差，例如可以形成為約200μm。通過如此重新模制，以後進行鐳射打標時的限制減少，能夠更加有效地防止經由再利用工程的半導體封裝100的變形。通過本發明的一實施例的重新模制，將半導體封裝100的厚度增加限定為50至1000μm。若所述半導體封裝100的厚度超過1000μm，則安裝在電子設備時會造成電子設備的厚度增加。相反，所述半導體封裝100的厚度小於50μm時，不能完全遮蓋鐳射打標，而且，對進一步進行的鐳射打標工程造成不好影響。而且，為了回收利用的半導體封裝100不受熱變形的影響，應製造為預定程度以上的厚度，因此，本發明的一實施例中將回收利用半導體封裝100的厚度增加限定為50μm以上。 In this way, the existing product information formed on the semiconductor package 100 can be covered by re-molding. At this point, the thickness of the remold should be such that the electronic device does not become thicker when mounted on a printed circuit board (PCB). This is designed in consideration of errors that occur during manufacturing. More specifically, when semiconductor package 100 is laser printed, the depth of the part marked by laser is about 50 μm, and the undercut part of the marked information is filled by laser. Furthermore, considering an error in engineering, for example, it can be formed to about 200 μm. By re-molding in this way, restrictions when laser marking is performed later can be reduced, and deformation of the semiconductor package 100 through the reuse process can be prevented more effectively. By re-molding an embodiment of the present invention, the thickness increase of the semiconductor package 100 is limited to 50 to 1000 μm. If the thickness of the semiconductor package 100 exceeds 1000 μm, the thickness of the electronic device will increase when it is mounted on the electronic device. On the contrary, when the thickness of the semiconductor package 100 is less than 50 μm, the laser marking cannot be completely covered, and further, the laser marking project is further affected. In addition, in order to prevent the recycled semiconductor package 100 from being affected by thermal deformation, it should be manufactured to a thickness greater than a predetermined level. Therefore, in one embodiment of the present invention, the thickness increase of the recycled semiconductor package 100 is limited to 50 μm or more.
然後，為了在印刷電路板上安裝半導體封裝100而進行附著焊球(S240)的工程。這時的焊球附著工程是重新附著在前面去除的焊球的工程，與現有焊球附著工程相同。此時，對回收利用的半導體封裝100重新加熱。 Then, a process of attaching solder balls (S240) is performed in order to mount the semiconductor package 100 on the printed circuit board. The solder ball attachment process at this time is the process of reattaching the solder balls removed in the front, which is the same as the existing solder ball attachment process. At this time, the recycled semiconductor package 100 is reheated.
在焊球附著工程以後進行列印(Marking)(S250)工程，這是在半導體封裝100的上面利用鐳射等標刻半導體封裝100的固有號碼等資訊的工程。本發明的一實施例中指鐳射打標(Laser Marking)工程，這是與現有的鐳射打標相同，因此，在此省略對其的具體說明。 After the solder ball attachment process, a marking (S250) process is performed, which is a process of marking the information such as the unique number of the semiconductor package 100 with a laser or the like on the semiconductor package 100. An embodiment of the present invention refers to a laser marking (Laser Marking) process, which is the same as the existing laser marking. Therefore, detailed descriptions thereof are omitted here.
然後，對所述重新模制的半導體封裝100進行切 割(S260)，經測試後出貨。 Then, the remolded semiconductor package 100 is diced (S260) and shipped after testing.
根據本發明的一實施例，由於所述回收利用半導體封裝100為已完成半導體製造工程的狀態，因此，附著有基板120，在去除或未去除基板的狀態下，可以執行模制及焊球附著等工程。是因為根據本發明的一實施例的半導體封裝100的回收利用方法，從模制工程開始重新通過半導體的後工程製造半導體封裝100。即，並不是必須去除基板120才能利用根據本發明的半導體封裝回收利用方法，還可以在附著於要回收利用的半導體封裝100的基板120上進行重新模制。 According to an embodiment of the present invention, since the recycled semiconductor package 100 is in a state where a semiconductor manufacturing process has been completed, the substrate 120 is attached, and molding or solder ball attachment can be performed with or without the substrate removed. And so on. This is because, according to the recycling method of the semiconductor package 100 according to an embodiment of the present invention, the semiconductor package 100 is manufactured through the post-process of the semiconductor again from the molding process. That is, it is not necessary to remove the substrate 120 to use the semiconductor package recycling method according to the present invention, and it is also possible to re-mold the substrate 120 attached to the semiconductor package 100 to be recycled.
如圖3所示，所述夾具10由金屬板11而形成，在一面附著有與去除所述焊球140的下面相對的密封部件13。所述夾具10的材料優選包含導電性出色且價格低廉的銅。並且，所述密封部件13可使用透明或半透明的塑料。作為一例，所述密封部件13可為由塑料而成的粘膠帶。如此，通過將密封部件13使用粘膠帶，存在能夠固定所述半導體封裝100的移動，而且，能夠防止模塑料150溢出的效果。 As shown in FIG. 3, the jig 10 is formed of a metal plate 11, and a sealing member 13 opposite to a lower surface from which the solder ball 140 is removed is attached to one surface. The material of the jig 10 preferably contains copper with excellent conductivity and low cost. In addition, the sealing member 13 can be made of transparent or translucent plastic. As an example, the sealing member 13 may be an adhesive tape made of plastic. As described above, by using the adhesive tape for the sealing member 13, there is an effect that the movement of the semiconductor package 100 can be fixed and the molding compound 150 can be prevented from overflowing.
圖4是根據本發明的重新模制的半導體晶片的模制面的示意圖，表示在夾具10模制模塑料150的狀態圖，圖5是沿圖4的A-A線的截面圖，圖6是從焊球140的前面看通過本發明的一實施例的工程裝載半導體封裝100的狀態的夾具的示意圖。 FIG. 4 is a schematic diagram of a molding surface of a remolded semiconductor wafer according to the present invention, showing a state in which a molding compound 150 is molded in a jig 10, FIG. 5 is a cross-sectional view taken along a line AA in FIG. 4, and FIG. The front view of the solder ball 140 is a schematic view of a jig in a state where the semiconductor package 100 is engineered to be loaded by an embodiment of the present invention.
圖6是在重新模制回收利用半導體封裝100的狀態下重新模制的半導體封裝100的切割(S260)工程之前的狀態示意圖。 FIG. 6 is a schematic view showing a state before the cutting (S260) process of the remolded semiconductor package 100 in a state where the semiconductor package 100 is remolded and recycled.
而且，重新模制所述半導體封裝100的一面的步驟是以在已模制的面重疊的方式進行2次模制的步驟。此時，厚度比最初半導體封裝100的厚度稍微變厚。但是，此時重新模制的厚度只要是能覆蓋不良半導體晶片110的最初模制面就充分，所以，不會發生因厚度變厚而引起的問題。即所述回收的不良半導體封裝100在鐳射打標具有錯誤時，只要能解決此問題即可。 Further, the step of remolding one side of the semiconductor package 100 is a step of performing two moldings so as to overlap the molded surface. At this time, the thickness is slightly thicker than the thickness of the first semiconductor package 100. However, at this time, the thickness of the remolding is sufficient as long as it can cover the first molding surface of the defective semiconductor wafer 110, so that no problem caused by the thickening will occur. That is, when the recovered bad semiconductor package 100 has an error in laser marking, it only needs to solve the problem.
如上所述，模制部件可使用陶瓷、金屬、塑料等，但是，本發明的一實施例中使用了在環氧樹脂添加矽等無機材料和各種輔助材料(硬化材料、阻燃材料、脫模劑等)的EMC(Epoxy Molding Compound)。 As described above, ceramics, metals, plastics, and the like can be used for the molded parts. However, in one embodiment of the present invention, an inorganic material such as silicon is added to the epoxy resin, and various auxiliary materials (hardened materials, flame retardant materials, and mold release materials) are used. Agents, etc.) EMC (Epoxy Molding Compound).
由本發明的一實施例可知所述回收的半導體封裝100在所述夾具10上被條形化後再被模制。因此，所述夾具10是用於多個半導體封裝100的夾具10，可以命名為共同夾具10，多個開口部14相互以預定間隔隔開形成。如此，在本發明的一實施例中，通過在將要回收利用的多個半導體封裝100連續排列在夾具10形成為條形後重新模制，從而，能夠在短時間內自動化處理大量的半導體封裝。 According to an embodiment of the present invention, it can be known that the recovered semiconductor package 100 is stripped on the jig 10 and then molded. Therefore, the jig 10 is a jig 10 for a plurality of semiconductor packages 100, and may be named a common jig 10, and a plurality of openings 14 are formed at a predetermined interval from each other. As described above, in one embodiment of the present invention, a plurality of semiconductor packages 100 to be recycled are continuously arranged in a stripe shape in the jig 10 and remolded, so that a large number of semiconductor packages can be automatically processed in a short time.
以上所述的詳細說明是舉例說明的，並不限定 本發明。本發明的範圍應由申請專利範圍的合理的解釋而決定，在本發明的等價範圍內的所有變更皆包含於本發明的範圍。 The above detailed description is illustrative and does not limit the present invention. The scope of the present invention should be determined by a reasonable interpretation of the scope of the patent application, and all changes within the equivalent scope of the present invention are included in the scope of the present invention.
Claims (10)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ??10-2017-0144604 | 2017-11-01 | ||
| KR20170144604 | 2017-11-01 | ||
| ??10-2018-0006027 | 2018-01-17 | ||
| KR1020180006027A KR101992263B1 (en) | 2017-11-01 | 2018-01-17 | Recycling method for semiconductor package and recycling semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201919467A true TW201919467A (en) | 2019-05-16 |
| TWI663899B TWI663899B (en) | 2019-06-21 |
Family
ID=66546632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW107109621A TWI663899B (en) | 2017-11-01 | 2018-03-21 | Method for recycling semiconductor package, and method for recycling semiconductor package |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR101992263B1 (en) |
| TW (1) | TWI663899B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112864041B (en) * | 2019-11-27 | 2024-03-22 | 西安航思半导体有限公司 | Semiconductor device packaging device |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100336481B1 (en) * | 2000-08-11 | 2002-05-15 | 윤종용 | Repairable Multi Chip Package And Memory Card Using The Repaired Package |
| JP4246095B2 (en) * | 2004-03-31 | 2009-04-02 | 三菱電機株式会社 | Semiconductor package mounting structure and semiconductor package mounting method |
| KR100722597B1 (en) * | 2005-07-04 | 2007-05-28 | 삼성전기주식회사 | Semiconductor package board having dummy area formed copper pattern |
| KR100670893B1 (en) * | 2006-03-14 | 2007-01-19 | 원용권 | Semiconductor package type receiving tray and manufacturing method for it |
| JP4846411B2 (en) * | 2006-03-30 | 2011-12-28 | 株式会社ディスコ | Semiconductor package jig |
| US20080313894A1 (en) * | 2007-06-21 | 2008-12-25 | General Electric Company | Method for making an interconnect structure and low-temperature interconnect component recovery process |
| KR20100037875A (en) * | 2008-10-02 | 2010-04-12 | 삼성전자주식회사 | Semiconductor package and fabricating the same |
| KR101461630B1 (en) * | 2008-11-06 | 2014-11-20 | 삼성전자주식회사 | Wafer level chip on chip package, package on package improving solder joint reliability but reducing mounting height and manufacturing method thereof |
| KR101003678B1 (en) * | 2008-12-03 | 2010-12-23 | 삼성전기주식회사 | wafer level package and method of manufacturing the same and method for reusing chip |
| WO2012088098A2 (en) * | 2010-12-20 | 2012-06-28 | Solar Machines Incorporated | Single cell encapsulation and flexible-format module architecture for photovoltaic power generation and method for constructing the same |
| TWI417040B (en) * | 2011-05-02 | 2013-11-21 | Powertech Technology Inc | Semiconductor packaging method to form double side electromagnetic shielding layers and device fabricated from the same |
| US10047256B2 (en) * | 2013-03-06 | 2018-08-14 | Dic Corporation | Epoxy resin composition, cured product, heat radiating material, and electronic member |
-
2018
- 2018-01-17 KR KR1020180006027A patent/KR101992263B1/en active IP Right Grant
- 2018-03-21 TW TW107109621A patent/TWI663899B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20190049328A (en) | 2019-05-09 |
| KR101992263B1 (en) | 2019-06-25 |
| TWI663899B (en) | 2019-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100551641B1 (en) | A method of manufacturing a semiconductor device and a semiconductor device | |
| US7361533B1 (en) | Stacked embedded leadframe | |
| US8766424B2 (en) | Thin substrate PoP structure | |
| US7772685B2 (en) | Stacked semiconductor structure and fabrication method thereof | |
| TWI402950B (en) | A sip module with a single sided lid | |
| US20080111224A1 (en) | Multi stack package and method of fabricating the same | |
| US20070155049A1 (en) | Method for Manufacturing Chip Package Structures | |
| US20120326306A1 (en) | Pop package and manufacturing method thereof | |
| TWI663899B (en) | Method for recycling semiconductor package, and method for recycling semiconductor package | |
| US20090154125A1 (en) | Semiconductor device and method of forming the same | |
| JP2014107554A (en) | Lamination-type semiconductor package | |
| US20080122122A1 (en) | Semiconductor package with encapsulant delamination-reducing structure and method of making the package | |
| US20090321920A1 (en) | Semiconductor device and method of manufacturing the same | |
| TW508703B (en) | Manufacturing method of semiconductor chip package structure | |
| US20080290513A1 (en) | Semiconductor package having molded balls and method of manufacturing the same | |
| KR100871379B1 (en) | Method of manufacturing semiconductor package | |
| JP4994148B2 (en) | Manufacturing method of semiconductor device | |
| US11823975B2 (en) | Semiconductor packages including different type semiconductor chips having exposed top surfaces and methods of manufacturing the semiconductor packages | |
| CN109755105A (en) | Semiconductor packages recoverying and utilizing method recycles semiconductor packages and fixture | |
| JP2005277434A (en) | Semiconductor device | |
| US9184067B1 (en) | Methods of mitigating defects for semiconductor packages | |
| KR20070120376A (en) | Method of fabricating chip scale package | |
| US20080251910A1 (en) | Fabricating method of semiconductor package and heat-dissipating structure applicable thereto | |
| KR0178626B1 (en) | Method of making a semiconductor package and structure of the same | |
| JP2004172647A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |