CN109755105A - Semiconductor packages recoverying and utilizing method recycles semiconductor packages and fixture - Google Patents
Semiconductor packages recoverying and utilizing method recycles semiconductor packages and fixture Download PDFInfo
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- CN109755105A CN109755105A CN201810321341.7A CN201810321341A CN109755105A CN 109755105 A CN109755105 A CN 109755105A CN 201810321341 A CN201810321341 A CN 201810321341A CN 109755105 A CN109755105 A CN 109755105A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
It the present invention relates to a kind of semiconductor packages recoverying and utilizing method, recycling semiconductor packages and is its fixture, the semiconductor packages recoverying and utilizing method, comprising: the step of recycling the semiconductor packages to be recycled；Multiple semiconductor packages of recycling are loaded in the step being formed on the fixture of the opening portion of multiple sizes corresponding with semiconductor packages；The step of re-molding the molding face for the semiconductor packages being loaded on the fixture；The step of semiconductor packages re-molded described in cutting, increases 50 to 1000 μm via the thickness of the semiconductor packages re-molded.
Description
Technical field
It the present invention relates to a kind of semiconductor packages recoverying and utilizing method, recycling semiconductor packages and is its folder
Tool, is related to recycling and is judged as technology that is bad or having used semiconductor packages in manufacturing engineering.
Background technique
Generally, the rear engineering for manufacturing semiconductor includes: to pacify at printed circuit board (PCB, Printed Circuit Board)
Die bond (die bonding) engineering of dress attachment from wafer (wafer) semiconductor chip separated；Utilize metal wire
Electrical connections such as (metal wire) are attached with gold thread bonding (wire bonding) engineering of the printed circuit board of semiconductor chip；
By manufacturing molding (molding) work at integrated antenna package using sealing material sealing semiconductor chips and printed circuit board
Journey；And in order to which the semiconductor chip of shipment cuts engineering (Package Sawing).
Until the cutting process of cutting semiconductor encapsulation is with each IC (Integrated Circuit) continuously arranged item
Form preparation.At this point, in engineering, semiconductor chip is such as substrate (Substrate) or lead frame (Lead Frame)
Form uses, and is cut into single IC form in encapsulation cutting process.
As described above during manufacture, misdescription can occur in IC in laser marking (raser Marking) engineering
The case where information (PART NUMBER) that (Top Surface) is recorded above.At this point, since these IC cannot be sold,
It needs to eliminate laser marking and re-starts laser marking or discarded.
If waste treatment IC, in terms of being unfavorable for thrifty expense, therefore, grope to eliminate the side that laser marking re-uses
Method.
As the method, there are a following methods: first, it is 50 μm by front cutting because the depth of laser marking is 50 μm
Method, second, in the method for laser marking coated thereon special inks hardening.There are color change to ask for the first method
Topic, second method exist due to all processes with hand coating special inks, the low problem of yield.
Due to being high price from the semiconductor chip of the removals such as printed circuit board, compared with discarded preferred recycling, but
It is that, since staff need to carry out manual work to the semiconductor chip of recycling, accordingly, there exist the problems more than time-consuming.
One side according to the present invention, for for recycling the folder in the semiconductor packages for being formed with moulded parts on one side
Tool, including: metal plate is formed with multiple opening portions, the multiple opening for loading multiple semiconductor packages of recycling
The size in portion is corresponding with the semiconductor packages；And seal member, it is relatively set with the another side of the semiconductor packages
Set the one side in the metal plate.
One side according to the present invention, the metal plate are formed by copper sheet, and the multiple opening portion is continuous at a predetermined interval
It is formed.
Summary of the invention
The technical problem to be solved in the present invention
It is an object of the invention to solve described problem and other problems.Other purposes are, provide a kind of recycling benefit
Be judged as the method for bad or used semiconductor packages in manufacturing engineering, the recycling semiconductor thus manufactured with
And the fixture for it.
Technical solution
Semiconductor packages recycling side can be provided to reach described or other purposes, one side according to the present invention
Method, including: the step of recycling the semiconductor packages to be recycled；Multiple semiconductor packages of the recycling are loaded in shape
The step of at the fixture for having multiple sizes opening portion corresponding with semiconductor packages；Re-mold half be loaded on the fixture
The step of molding face of conductor encapsulation；And cutting described in re-mold semiconductor packages the step of, via the mould again
The thickness of the semiconductor packages of system increases 50 to 1000 μm.
One side according to the present invention, the fixture are formed by metal plate, can be adhered to and the semiconductor package in one side
The opposite seal member of the another side of dress.
One side according to the present invention, in the loading step, the semiconductor packages of the recycling can continuous arrangement exist
On the fixture.
One side according to the present invention, the step of recycling the semiconductor packages, comprising: from lamination 2 or more partly lead
The step of laminated semiconductor package that body is encapsulated and formed isolates the semiconductor packages to be recycled；And removal is formed in
The step of soldered ball of the another side of the isolated semiconductor packages.
One side according to the present invention, for epoxy molding material (EMC, the Epoxy Molding re-molded
Compound glass transition temperature) is 180 DEG C or more.
One side according to the present invention further comprises: is recycled after step in described re-mold to described
The another side of semiconductor packages adheres to the step of soldered ball；And the attachment soldered ball the step of after, re-molded to described
Face carries out the step of laser marking.
One side according to the present invention can provide recycling semiconductor packages, wherein recycling to be recycled partly lead
Body encapsulation, re-molds the molding face of the semiconductor packages of the recycling, the thickness of the semiconductor packages re-molded increases
50 to 1000 μm.
Beneficial effect
Illustrate that the effect of semiconductor packages recycle device according to the present invention and method is as follows.
An at least embodiment in embodiment according to the present invention, cannot not exist discardedly be judged as it is bad or used half
The advantages of conductor is encapsulated and can be recycled.
An at least embodiment in embodiment according to the present invention, by the molding that partly overlaps moulded, existing pair
The safer advantage of external impact.
An at least embodiment in embodiment according to the present invention improves assembling by preventing the deformation of semiconductor packages
Productivity when installation semiconductor element can be improved in precision and soldering reliability.
An at least embodiment in embodiment according to the present invention is being pacified by preventing the deformation of semiconductor packages
It is outstanding with being electrically connected for semiconductor element when dress, so as to improve the yield of semiconductor packages.
An at least embodiment in embodiment according to the present invention is existed to be recycled using existing engineering and partly be led
The effect of body chip.
An at least embodiment in embodiment according to the present invention, by the way that multiple semiconductor packages are formed as continuous arrangement
Bar shaped (Strip), thus, once can recycle more semiconductor chips.
Applicable additional range of the invention can will be defined by detailed description below.But the technology of this field
Personnel can be expressly understood that the various changes and modification made in thought and range of the invention, it is therefore to be understood that in detail
Illustrate and if the specific embodiment of the preferred embodiment of the present invention is to illustrate.
Detailed description of the invention
Fig. 1 is the sectional view of semiconductor packages according to the present invention.
Fig. 2 is the Pretreatment Engineering precedence diagram according to the present invention for recycling semiconductor packages.
Fig. 3 is the perspective view of fixture according to the present invention.
Fig. 4 is the schematic diagram in the molding face of the semiconductor packages according to the present invention re-molded.
Fig. 5 is the sectional view of the line A-A along Fig. 4.
Fig. 6 is the schematic diagram for the fixture that the engineering of an embodiment through the invention loads the state of semiconductor packages.
Fig. 7 is the flow chart of semiconductor packages recoverying and utilizing method according to the present invention.
Fig. 8 is the ideograph of the semiconductor packages of lamination according to the present invention.
Description of symbols:
10: fixture, 11: metal plate, 12: next door, 13: seal member, 14: groove, 100: semiconductor packages, 110: partly leading
Body chip, 120: substrate, 130: metal wire, 140: soldered ball, 150: moulding compound, 160: adhesive, 200: laminated semiconductor envelope
Dress, the 200a: the first semiconductor packages, the 200b: the second semiconductor packages
Specific embodiment
In the following, embodiment disclosed in this specification is explained in detail with reference to the accompanying drawings, it is unrelated with drawing symbol to identical or class
As constituent element mark identical symbol, and omit detailed description thereof.Composition is wanted used in the following description
The ending word " portion " of element is assigned or is used with to be easy to write specification, itself is not had the meaning of difference or is played area
Other effect.Moreover, in the embodiment for illustrating this disclosure, if judging that illustrating for related known technology can be made
The embodiment of this specification is indefinite, then omits detailed description thereof.Also, it is to be understood that attached drawing is for being more easier to manage
It solves the embodiment of this specification and provides, do not limit technical idea disclosed in this specification, include thought of the invention
And technical scope included have altered, equipollent or even sub.
The first, second equal term comprising ordinal number can be used to the constituent element for illustrating multiplicity, but these constituent elements are simultaneously
It is not limited by the term.Purpose using the term is for distinguishing a constituent element and other constituent elements.
When in article without specific meaning, singular performance of the performance comprising plural number.
In the present invention, the terms such as " comprising " or " having " are used to refer to the feature for determining to record in specification, number, step
Suddenly, movement, constituent element, part or the presence for combining these, it is not excluded that more than one others feature or number, step
Suddenly, movement, constituent element, part or the presence or additional possibility of combining these.
Generally, in technical field of semiconductors encapsulation be by the process of semiconductor final product, refer to by circuit connection at
Electric signal etc. can be transmitted to semiconductor chip, and safely protected from external environment and the process that is moulded.In the past, due to
The simple function for only paying attention to semiconductor chip is substantially carried out the encapsulation of such as DIP (dual-inline package) plug-in type, still, with
Mounting area diminution requirement, by SOP (Small Outline Package), QFP (Quad Flat Package),
The encapsulation shape of form is installed on the surfaces such as TSOP (Thin Small Outline Package), and size and core have been arrived in latest developments
The identical CSP of piece (Chip Size Package), MCP (the Multi Chip that multiple chips are configured to an encapsulation
Package), the microminiatures complex morphological such as SiP (System In Package).
In semiconductor packaging, engineering is moulded in order to protect semiconductor packages from physics, electricity, chemical shock and utilizes mould
Prepared material sealing semiconductor encapsulates to protect semiconductor chip, and distributes the engineering of the heat generated when using product.
In other words, to be that multiple fine circuits are integrated form semiconductor chip, itself cannot play the work of finished semiconductor
With, can by external physics, chemical shock and damage.In order to prevent be damaged develop semiconductor packaging, the technology be by
Semiconductor chip is electrically connected after being mounted on substrate (Lead-frame or PCB:Printed Circuit Board), is utilized
The sealed packages such as EMC (Epoxy Molding Compound) so as to play to make from external moisture or impurity protection
For the technology of the function of semiconductor.Further, in one embodiment of the invention, other than being packaged using EMC, according to half
Miniaturization, variation of packaged type of conductor chip etc. can be moulded by liquid phase sealant.
The semiconductor packages can be divided into semiconductor chip and various substrates (Lead Frame, Package
Substrate etc.) connection the step of；And the step of connection aforesaid substrate (Substrate) and mainboard.Strictly, second
Step should be defined as assembling (assembly) engineering rather than encapsulate engineering and still may be included in the encapsulation range of broad sense.
There are metal line (Metal Wiring) mode and salient point (Bumping) side as the method for executing first step
Formula has the mode using lead frame (Lead Frame) and the mode using ball (Ball) as the method for executing second step
(BGA:Ball Grid Array)。
In one embodiment of the invention, the structure formed by the first step is known as superstructure, by second step
Structure that is rapid and being formed is known as substructure.
The i.e. described superstructure refers to the interconnecting piece between semiconductor chip and substrate (Substrate), the lower junction
Structure refers to the interconnecting piece between substrate (Substrate) and mainboard (Main Board).The semiconductor chip include CPU,
The memory semiconductors such as the non-memory semiconductors such as GPU, various ASIC and DRAM, flash memory (Flash Memory).The substrate
It (Substrate) include traditional lead frame (Lead Frame) mode and ball (Ball) mode (Package
Substrate, BGA, CSP etc. have various addresses).Mainboard refers to the PCB (Printed for constituting the substrate in electron product circuit portion
Circuit Board), there are the mainboard (Mother Board) of PC or the mainboard (Main Board) of mobile phone.
In addition, the technology of lamination IC may include wafer lamination (wafer-on-wafer), die stacks crystalline substance in three dimensions
Circle (die-on-wafer), die stacks tube core (die-on-die) and encapsulation stacked package (package-on-
Package, PoP).As an example, being typically formed in engineering for stacked package structure, 2 or more IC package bodies are encapsulated
In order to which signal of the Route Selection between it has the mutual lamination of electrical communication interface.This tectosome is in mobile phone, personal digital assistant
Allow higher parts density on the devices such as (personal digital assistant, PDA) and digital camera.In particular,
LPDDR (Low Power DDR) is the DDR SDRAM to develop for mobile devices such as smart phone, tablet computers, special
Sign is little power consumption, and one embodiment of the invention is technology related to this.At this point, the LPDDR exists due to storing than NAND
The problem of device is thin, area is big, therefore to hot-short weak, is easy to happen thermal deformation (warpage).
In addition, semiconductors manufacture engineering is divided into preceding engineering (FE:Front-End) He Hougong for forming circuit on wafer
Journey (BE:Back-End), preceding engineering are further divided into wafer diffusion (Wafer Diffusion) engineering and wafer test (Wafer
Test) engineering, rear engineering are further divided into encapsulation engineering (or packing engineering) and testing engineering.
One embodiment of the invention is related to the especially encapsulation engineering in the rear engineering, and the semiconductor packages engineering is substantially
It is as follows.
Semiconductor packages engineering includes: to utilize the grinding containing unformed silica, tetramethylammonium hydroxide (TMAH) etc.
The so-called grinding back surface of engineering (Back Grinding) engineering at liquid grinding back side of the processed wafer of engineering before semiconductor；
The so-called wafer cutting (Wafer of engineering for cutting the wafer using cutting fluid containing interfacial agent etc. etc. with discrete units
Sawing (Dicing)) engineering；It is bonded using the adhesive containing epoxy resin, phenolic resin etc. at substrate (substrate)
The so-called chip adhesive of engineering (Die Attaching) engineering of the fixed chip cut；Utilize the metal wires such as spun gold electricity
Connect the so-called wire bonding of engineering (Wire Bonding) engineering of chip；In order to protect chip from external environment, using by ring
The so-called molding of engineering of oxygen resin, phenolic resin, silica etc. and the package chip such as epoxy molding material (EMC) of composition
(Molding) engineering；With laser to the so-called laser marking of engineering (Laser Marking) work of each product marking product information
Journey；In the so-called soldered ball attachment of engineering that circuit substrate coated with flux (flux) bonding soldered ball (solder ball) prepares output end
(Solder Ball Mount) engineering；It is cut into individual semiconductor and is installed to the so-called encapsulation of module/board/card engineering and cut
Cut (Package Sawing) engineering.
At this point, Fig. 1 is the sectional view of semiconductor packages 100 according to the present invention, referring to Fig.1, half is equipped in substrate 120
The semiconductor packages 100 of the state of conductor chip 110, it is generally (or convex by semiconductor chip 110, substrate 120, metal wire 130
Point), soldered ball 140 (or lead frame), moulding compound 150, adhesive 160 etc. and form.The function of each element is as follows.
In one embodiment of the invention, it is semiconductor packages 100 that the part for having encapsulated the semiconductor chip 110, which is censured,.
Firstly, substrate 120 (substrate) is equipped with the component of semiconductor chip 110, in semiconductor chip 110 and master
Play electric signal interface channel between printed circuit board (PCB), is that can transmit electric signal in the arrangement of the upper surface of insulator
The fine wiring of semiconductor chip 110 is transformed to the scale of main printed circuit board by the structure of conductor.,
Metal wire 130 is connected with each other between semiconductor chip 110 and substrate 120, main to use gold (Au) or copper (Cu) etc.,
The salient point (Bump) for forming protrusion on the pad (Pad) of semiconductor chip 110 can also be used to replace metal wire 130.
Soldered ball 140 acts the function of being connected with each other substrate 120 and main circuit substrate, can also be using lead frame to replace
State soldered ball 140.
Moulding compound 150 is used to mould product and retaining element.The material of moulding compound 150 can be used ceramics,
Metal, plastics etc. use cheap plastics more.It has been used in one embodiment of the invention in nothings such as epoxy resin addition silicon
EMC (the Epoxy Molding of machine material and various auxiliary materials (hardened material, fire proofing, release agent etc.)
Compound)。
The salient point is electric conductivity protrusion, is used for semiconductor chip 110 with tape automated bonding (TAB) or upside-down mounting core
Piece (Flip Chip) mode is connected to substrate 120, or BGA and GPS etc. is connected directly to circuit substrate.With bonding wire
(Bonding Wire) is identical, and gold or solder (Solder) can be used in the material as salient point.The material of the solder can be with
Use lead and tin (Pb+Sn) or SAC (Sn-Ag-Cu: tin-silver-copper).
After moulding engineering, (Singulation) engineering is separated, this engineering is along moulding resin and pin
Cutting line (Sawing Line) is cut into the engineering of unit semiconductor packages.
One embodiment of the invention is to recycle to have produced and used or the not used semiconductor because of the reasons such as bad
The technology of encapsulation, in particular, recycling the technology of semiconductor packages in PoP encapsulation.
Firstly, Fig. 2 is the Pretreatment Engineering precedence diagram according to the present invention for recycling semiconductor packages, Fig. 8 is basis
The outline ideograph of the so-called PoP encapsulation 200 of laminated semiconductor package of the invention, in the following, illustrating to recycle referring to Fig. 2 and Fig. 8
Utilize pre-treatment (pre-treatment) engineering of semiconductor packages.The Pretreatment Engineering will be recycled primarily with regard to separation
The engineering of the semiconductor packages (or semiconductor chip) utilized.One embodiment of the invention is about recycling such as PoP
The method of a part of the semiconductor packages 200 of (Package on Package) form lamination, is to be suitable for as PoP structure
Such as lamination mobile DRAM (or LPDDR) chip package (hereinafter referred to as the first semiconductor packages 200a) and mobile application are handled
The technology of device (Application Processor, AP) chip package (hereinafter referred to as the second semiconductor packages 200b).Due to
PoP is the dual stacked package on pad, therefore can increase the efficiency of per unit area.PoP is applied not only to lamination LPDDR
Chip package 200a and mobile AP chip package 200b, moreover, applying also for the mobile AP chip package of lamination and communication base band
Chip package.
That is, one embodiment of the invention, which is primarily adapted for use in, recycles PoP, more specifically, being suitable for recycling movement
The first the half of LPDDR chip package (the first semiconductor packages 200a) and mobile AP chip package (the second semiconductor packages 200b)
Conductor encapsulates 200a and the second semiconductor packages 200b, could be applicable to communication baseband chip encapsulation (the first semiconductor packages
200a) and the chip package of mobile AP chip package (the second semiconductor packages 200b).At this point, being suitable for the chip of PoP
(DRAM, AP, BB) is bigger than other chips, it is therefore desirable to reduce encapsulated space, for this purpose, by the second semiconductor packages
First semiconductor packages 200a of other encapsulation of the dual lamination of the upper surface of 200b, thus, PoP can reduce encapsulated space.
If the semiconductor packages 200 that need to be recycled is put in storage, storage and detection (S110) are executed.In the process, confirm
It whether is bad with eyes confirmation raw material while carrying quantity.Then, it is carried out at about 125 DEG C with plate (board) state
Dry engineering (S120) 240 minutes, moisture onboard is stayed in removal.At this point, applying heat for the first time to semiconductor packages.At this time
Plate is the state for including the first semiconductor packages 200a and the second semiconductor packages 200b.
It in the past, is that principal component executes soldering with tin (Sn) and lead (Pb) in semiconductor packages engineering, it can be at 220 DEG C or less
At a temperature of be packaged.But lead cannot be used recently, in tin combined silver (Ag) and copper (Cu), therefore, fusing point was than former
Height is about 221 DEG C.Therefore, the engineering executed at 220 DEG C of temperature below in the past cannot be executed, now in order to smoothly execute
Engineering at least keeps 245 DEG C or more of temperature.In this way, the temperature because of engineering is got higher, more deleterious effect is brought to thermal deformation.
If onboard returning back out existing cracking or hole without drying work.
Moreover, utilizing separating tool in the state of semiconductor packages 200 that accumulation has been put in storage on separation equipment
(detach tool) is in 245 DEG C of temperature separation object semiconductor packages 200a (S130) below.At this point, to described the first half
Conductor encapsulates 200a and applies heat for the first time.Object semiconductor packages i.e. the first semiconductor is confirmed using microscope in separation engineering
Whether encapsulation 200a has encapsulation cracking or scratch (scratch).
Then, bottom is removed when having bottom outstanding to fill out agent (underfill) on the edge of the first semiconductor packages 200a to fill out
Agent, and remove the remaining solder that is bonded on the solder ball pad face of the first semiconductor packages 200a and agent is filled out at bottom.Bottom at this time
Filling out agent can be thermosetting resin.In one embodiment of this invention, the engineering is known as modifying (dressing) engineering
(S140).The finishing work executes 60 seconds at about 250 DEG C, applies heat for the second time to the first semiconductor packages 200a.
Then, cleaning and dry (cleaning and dry) engineering (S150) are executed, agent and finishing work are filled out at removal bottom with removal
In the solder flux and residue that leave.At this point, being cleaned using distilled water (de-ionized water, DI water).It is described
When solder flux is water-soluble, due to being dissolvable in water water, pure water (pure water) i.e. DI water brush can use
Etc. being cleaned.And check whether the first semiconductor packages 200a has cracking, scratch etc., and check whether figure tilts
(lift) etc..The semiconductor packages for needing to recycle from the separation of semiconductor packages 200 by Pretreatment Engineering as described above
200a and the state for becoming removal solder.
If Pretreatment Engineering terminates, the first semiconductor packages 200a is re-molded.After re-molding engineering, in semiconductor
Then the surface coated with flux of chip executes to form soldered ball (solder using equipment such as Manual formwork (manual stencil)
Ball) soldered ball attachment (solder ball attach) engineering after, check soldered ball whether disappeared or whether with adjoining
Data area.Then, welding (soldering) is executed at about 250 DEG C using reflux (reflow).Pass through welding at this time
Engineering applies heat to the first semiconductor packages 200a third time.Inspection at this time is whether confirmation soldered ball is lost
The step of whether (missing ball) or more than two soldered balls are in contact.
Then, according to client requirement vacuum packaging etc. rear delivery.
In this way, also applying 3 to semiconductor packages during recycling not only in the engineering of manufacture semiconductor packages
Secondary heat.Therefore thermal deformation occurs for the first semiconductor packages 200a of heat, and one embodiment of the invention can not only improve thermal deformation phenomenon,
The first semiconductor packages 200a can also be recycled.
Generally, according to the temperature in engineering various thermal deformations occur for semiconductor packages.I.e. in EMC molding process,
Thermal deformation occurs in solidification (curing) and cooling engineering, moreover, also deforming during solder reflux.Heat occurs
Deformation be because according to the thermal expansion coefficient (Coefficient Thermal Expansion, CTE) of used encapsulating material it
Poor and generation thermal stress.More specifically, thermal deformation and damage are in encapsulation engineering because of different thermal expansion coefficient and temperature
Difference and occur thermal stress and internal residual stresses and occur.The thermal deformation phenomenon of encapsulation depends on the structure of encapsulation, package material
The physical property and engineering specifications of material.Therefore, it is necessary to select encapsulating material appropriate and encapsulating structure appropriate.This condition is equally applicable
Engineering (is re-molded) in the encapsulation for recycling semiconductor packages.
The thermal deformation phenomenon of semiconductor packages can use cantilever beam (cantilever beam) model and define.Engagement
When the mutually different beam of physical property, thermal deformation phenomenon is occurred according to the temperature of application.Cause when encapsulation thermal deformation phenomenon it is maximum because
Element is the difference of the thermal expansion coefficient (ppm/ DEG C of unit) between different materials.Due to preparation encapsulation engineering in inevitably
The high temperature of generation, therefore, it may occur that thermal deformation phenomenon determines the state of thermal deformation according to the CTE of material.Thermal deformation occurs most
Representative engineering is molding engineering, and the temperature mainly applied in the molding engineering is about 120 DEG C to 180 DEG C.In particular, this
One embodiment of invention re-molds limit temperature in engineering at about 170 DEG C to 180 DEG C.
Because of the difference of the CTE between EMC and semiconductor chip, temperature is changed to room temperature (25 DEG C) from about 170 DEG C, therefore, half
Thermal deformation occurs for conductor encapsulation, when being encapsulated as protrusion form, referred to as negative warpage or crying warpage, down
When recess, referred to as positive warpage or smile warpage.
It is as follows that the specific reason of thermal deformation occurs in semiconductor packages.It is deposited known to the inside for examining semiconductor packages
In the typical different materials for constituting semiconductor packages.Semiconductor chip, the fixed semiconductor chip being made of silicon can connect
The lead frame (Lead frame) of electric wire being made of copper (Cu) material is made of macromolecule (Polymer) material
Substrate (substrate), the thermosetting resin bonding for being bonded in the semiconductor chip on lead frame or substrate
EMC (the Epoxy Molding of agent and all above composition of covering is filled out at agent, that is, adhesive (Adhesive) or bottom
Compound).There are also become with the semiconductor chip and lead frame/substrate the spun gold (Gold (Au) wire) of electric channel/
Tin salient point (Tin (Sn) bump) etc..
In one embodiment of the invention, during recycling semiconductor packages, partly leading comprising semiconductor chip
Body encapsulation is heated sometimes, is applied temperature and is up to 270 DEG C.In the process, thermal deformation occurs in semiconductor packages 200a.
The semiconductor chip is attached to AP (Application Processor), substrate (substrate) or printing electricity
On the plates such as road plate (PCB) (board) and in use, because the difference of the thermal expansion between semiconductor chip and plate is to welded joint
Service life causes to influence, because the repeated deformation of welded joint finally occurs to rupture (crack).For this purpose, reduction semiconductor chip (or
Semiconductor packages) and plate between thermal expansion difference be it is extremely important.
Therefore, as that can reduce the scheme of thermal deformation, it is preferable to use EMC as thermal expansion coefficient and chip type semiconductor.
But actually it is difficult exploitation with the EMC with thermal expansion coefficient as chip type semiconductor, therefore, it is necessary to lower EMC's as far as possible
Thermal expansion coefficient.
Further, other than the EMC for using thermal expansion coefficient low, moreover it is possible to consider high using glass transition temperature (Tg)
The method of EMC.In general, the thermal expansion coefficient of EMC is subject to Tg and is greatly increased, therefore, when the Tg of EMC material is higher than molding temperature
When, the CTE before only Tg causes to influence on the thermal deformation of semiconductor packages, therefore, can reduce half by improving Tg to obtain
The effect of the thermal deformation of conductor encapsulation.That is, in one embodiment of the invention, the ring for the use of glass transition temperature being 180 DEG C or more
Oxygen moulding compound 150.
Illustrate the device for being used to recycle semiconductor packages 100 of an embodiment according to the present invention with reference to the accompanying drawings
And the recoverying and utilizing method of the semiconductor packages 100 using this device.
Firstly, Fig. 3 is the perspective view of fixture according to the present invention, Fig. 7 is returning for semiconductor chip 110 according to the present invention
The flow chart for receiving the method for utilizing, is illustrated referring to Fig. 3 and Fig. 7.
Firstly, one embodiment of the invention is for recycling benefit for recycling the fixture 10 of semiconductor packages 100
Used in the device for the semiconductor packages 100 for being formed with moulded parts (Molding) on one side, fixture has: multiple metal plates 11 are used for
Recovered multiple semiconductor packages 100 are loaded, multiple opening portions of size corresponding with the semiconductor packages 100 are formed with
14；Seal member 13, in the facing formation of another side of the one side and the semiconductor packages 100 of the metal plate 11.
The metal plate 11 is not particularly limited, still, in one embodiment of the invention, by being made by copper sheet,
It not only saves money, moreover it is possible to embody the function similar with substrate.
Moreover, one embodiment of the invention is to be related to recycling multiple semiconductor chips 110 or semiconductor packages simultaneously
100 technology, therefore, the multiple opening portions 14 being formed on the metal plate 11 are formed continuously as multiple rows and multiple column.This
When, the shape of opening portion 14 is substantially corresponding with the size of semiconductor chip 110 or semiconductor packages 100, have square or
Rectangular shape.Strictly there is size corresponding with the size of semiconductor packages 100.
The method of the recycling semiconductor packages 100 of an embodiment according to the present invention be related to not discarding from mobile phone,
Semiconductor chip 110 (Memory IC, Application Processor etc.) that SSD, memory module etc. are isolated or
It is judged as undesirable semiconductor packages 100 in preparation engineering, cannot not say discardedly semiconductor chip 110 tighter and recycles benefit
Method.
As an example, it is also used as using for covering the purposes in molding face laser marking, is to be related to recycling benefit
Used in the method for the semiconductor packages 100 for being formed with moulded parts (Molding) on one side.In one embodiment of the invention, described half
Conductor encapsulation 100 refers to the upper surface of the information for being carved with semiconductor packages 100 on one side, and the another side of semiconductor packages 100 refers to
It is formed with the bottom surface of soldered ball 140.
In one embodiment of this invention, in order to recycle semiconductor packages 100, the semiconductor to be recycled first is recycled
100 (S210) are encapsulated, the semiconductor packages 100 of recycling is loaded into (Loading) and is being formed with multiple sizes and semiconductor packages
On the fixture 10 of 100 corresponding opening portions 14 (S220).At this point, the opening portion 14 is formed, semiconductor packages by next door 12
100 are loaded with the state being in contact with the medial surface in the next door 12.The next door 12 be on the metal plate 11 except
The remainder of oral area 14.
Though the size of the semiconductor packages of one embodiment of the invention slightly error but scheduled size is cut into, in institute
Stating has the interval that can ignore degree between next door 12 and semiconductor packages 100.The semiconductor packages 100 is inserted in as a result,
It is inserted into a manner of being forcibly inserted into when the fixture 10.In this way, being forcibly inserted by the semiconductor packages 100 in fixture
10, thus, moulding compound 150 will not be deposited at one.
Recovered multiple semiconductor packages 100 are loaded on a fixture 10 simultaneously, thus, it can once recycle benefit
With multiple semiconductor chips 110.In this way, in one embodiment of the invention, by the way that multiple semiconductor packages 100 of recycling are loaded
On a fixture 10, to once recycle multiple semiconductor chips 110 automatically, therefore, carried out with previous staff
By hand as when compare, be conducive to thrifty expense and shorten the time.
At this point, before re-molding the semiconductor packages 100, needs neatly to remove and be attached to semiconductor packages
100 foreign matter.In the process, need to remove the soldered ball 140 for being formed in the semiconductor packages 100 that initially preparation is completed.This is
Because soldered ball 140 can be also damaged if being formed in the soldered ball 140 of semiconductor packages 100 even being once bonded on other substrates,
And it is difficult to be mounted on circuit substrate, also, electrical functionality cannot be played.It needs to be removed to be formed in semiconductor packages
The engineering of the lead of the soldered ball 140 of 100 another side and the engineering for adhering to soldered ball again.If the soldered ball 140 of semiconductor packages 100
It is not damaged, does not then need the engineering for being removed and adhering to again soldered ball 140.
Then, the one side for the semiconductor packages 100 that (Remolding) is loaded on the fixture 10 is re-molded
(S230).One embodiment of the invention is to recycle the example for the semiconductor packages 100 that manufacturing engineering is completed, initially manufactured
Semiconductor chip 110 is disposably overmolded in engineering, due to being rear molding, so can be described as re-molding or molded
(second molding).To be overmolded to execute secondary mould in the state of semiconductor packages 100 i.e. in one embodiment of the invention
System.The engineering that re-molds is one by utilizing molding moulding resin molded semiconductor chip 110 and 120 component of substrate
Point integrated antenna package device for molding and execute, the device for molding has upper die and lower mould and constitutes.Upper mould
Tool, in order to form the molding slot for executing the molding space of molding and forming sink shape below upper die, in lower die
The upper surface of tool fixed setting semiconductor packages 100.Also, after upper die is close to pressing lower mould, moulding resin is injected into
It moulds in slot, and molding engineering is executed to semiconductor packages 100 (SD).
In this way, the existing product information for being formed in the upper surface of semiconductor packages 100 can be covered by re-molding.This
When, electronic equipment does not thicken when the thickness re-molded should be mounted in printed circuit board (PCB) degree.This is to consider system
It makes the error occurred in engineering and designs, more specifically, in 100 laser printing of semiconductor packages, believed by laser index carving
The depth of the part of breath is about 50 μm, carves part by the yin that laser fills up marking information, in turn, considers the mistake in engineering
Difference, such as about 200 μm can be formed as.By so re-molding, limitation when carrying out laser marking later is reduced, Neng Gougeng
Add the deformation being effectively prevented via the semiconductor packages 100 for recycling engineering.The mould again of an embodiment through the invention
System, is limited to 50 to 1000 μm for the thickness increase of semiconductor packages 100.If the thickness of the semiconductor packages 100 is more than
1000 μm, then the thickness that will cause electronic equipment when being mounted on electronic equipment increases.On the contrary, the thickness of the semiconductor packages 100
When degree is less than 50 μm, it cannot be completely covered by laser marking, moreover, the laser marking engineering to further progress causes bad shadow
It rings.Moreover, the influence of the 100 not temperature distortion of semiconductor packages for recycling, should be fabricated to the thickness of predetermined extent or more
Therefore the thickness increase for recycling semiconductor packages 100 is limited to 50 μm or more in one embodiment of the invention by degree.
Then, the engineering of attachment soldered ball (S240) is carried out for mounting semiconductor package 100 on a printed circuit.This
When soldered ball attachment engineering be to be re-attached to the engineering for the soldered ball that front removes, with existing soldered ball adhere to engineering it is identical.At this point,
The semiconductor packages 100 of recycling is reheated.
(Marking) (S250) engineering is printed after soldered ball adheres to engineering, this is in the upper of semiconductor packages 100
Face utilizes the engineering of the information such as the intrinsic numbers of markings semiconductor packages 100 such as laser.One embodiment of the invention middle finger laser
Mark (Laser Marking) engineering, this be it is identical as existing laser marking, therefore, omit herein and it illustrated.
Then, (S260) is cut to the semiconductor packages 100 re-molded, after tested rear shipment.
An embodiment according to the present invention, since the recycling semiconductor packages 100 is that semiconductors manufacture is completed
Therefore the state of engineering is attached with substrate 120, in the state of removing or not removing substrate, can execute molding and soldered ball is attached
Etc. engineerings.It is the recoverying and utilizing method because of the semiconductor packages 100 of an embodiment according to the present invention, is opened from molding engineering
Begin to manufacture semiconductor packages 100 again through the rear engineering of semiconductor.I.e., it is not essential however to which root could be utilized by removing substrate 120
It, can also be in the base for being attached to the semiconductor packages 100 to be recycled according to semiconductor packages recoverying and utilizing method of the invention
It is re-molded on plate 120.
As shown in figure 3, the fixture 10 is formed by metal plate 11, it is being attached on one side and is removing the soldered ball 140
Opposite seal member 13 below.The material of the fixture 10 preferably comprises the outstanding and cheap copper of electric conductivity.Also, institute
Stating seal member 13 can be used transparent or semitransparent plastics.As an example, the seal member 13 can be for as made of plastics
Adhesive tape.In this way, there is the movement for being capable of fixing the semiconductor packages 100 by the way that seal member 13 is used adhesive tape, and
And the effect that can prevent moulding compound 150 from overflowing.
Fig. 4 is the schematic diagram in the molding face of the semiconductor chip according to the present invention re-molded, is indicated in 10 mould of fixture
The state diagram of molding plastics 150, Fig. 5 are the sectional views of the line A-A along Fig. 4, and Fig. 6 is to see before soldered ball 140 through this hair
The engineering of a bright embodiment loads the schematic diagram of the fixture of the state of semiconductor packages 100.
Fig. 6 is the semiconductor packages 100 re-molded in the state of re-molding and recycling semiconductor packages 100
Cut the status diagram before (S260) engineering.
Moreover, the step of re-molding the one side of the semiconductor packages 100 is in a manner of in the face moulded overlapping
The step of carrying out 2 moldings.At this point, thickness slightly thickens than the thickness of initial semiconductor packages 100.But mould again at this time
The thickness of system is abundant as long as the initial molding face that can cover defective semiconductor's chip 110, so, it will not occur to become because of thickness
Problem caused by thickness.Defective semiconductor's encapsulation 100 of the i.e. described recycling is when laser marking has mistake, as long as can solve this
Problem.
As described above, ceramics, metal, plastics etc. can be used in moulding part, still, used in one embodiment of the invention
In the EMC of the inorganic material and various auxiliary materials (hardened material, fire proofing, release agent etc.) such as epoxy resin addition silicon
(Epoxy Molding Compound)。
After the semiconductor packages 100 of the recycling is on the fixture 10 by bar shaped known to one embodiment of the invention
It is molded again.Therefore, the fixture 10 is the fixture 10 for multiple semiconductor packages 100, can be named as common fixture 10,
Multiple opening portions 14 mutually separate to be formed at a predetermined interval.In this way, in one embodiment of this invention, by the way that benefit will be being recycled
Multiple 100 continuous arrangements of semiconductor packages re-mold after fixture 10 is formed as bar shaped, thus, it is possible in a short time
The a large amount of semiconductor packages of automatic processing.
Above-described detailed description is to illustrate, and does not limit the present invention.The scope of the present invention should be wanted by right
It asks the reasonable explanation of range and determines, having altered in full scope of equivalents of the invention is all contained in the scope of the present invention.
Claims (10)
1. a kind of semiconductor packages recoverying and utilizing method characterized by comprising
The step of recycling the semiconductor packages to be recycled；
Multiple semiconductor packages of the recycling are loaded in and are formed with multiple sizes opening portion corresponding with semiconductor packages
The step of fixture；
The step of re-molding the molding face for the semiconductor packages being loaded on the fixture；And
The step of semiconductor packages re-molded described in cutting,
50 to 1000 μm are increased via the thickness of the semiconductor packages re-molded.
2. semiconductor packages recoverying and utilizing method according to claim 1, which is characterized in that described the step of re-molding
It is executed at 170 DEG C to 180 DEG C.
3. semiconductor packages recoverying and utilizing method according to claim 1, which is characterized in that the fixture by metal plate and
It is formed, is being attached with the seal member opposite with the another side of the semiconductor packages on one side.
4. semiconductor packages recoverying and utilizing method according to claim 1, which is characterized in that in the loading step,
The semiconductor packages continuous arrangement of the recycling is on the fixture.
5. semiconductor packages recoverying and utilizing method according to claim 1, which is characterized in that recycle the semiconductor packages
The step of, comprising:
The laminated semiconductor package formed from lamination 2 or more semiconductor packages isolates the semiconductor package to be recycled
The step of dress；And
The step of removing the soldered ball for the another side for being formed in the isolated semiconductor packages.
6. semiconductor packages recoverying and utilizing method according to claim 1, which is characterized in that re-molded for described
The glass transition temperature of epoxy molding material is 180 DEG C or more.
7. semiconductor packages recoverying and utilizing method according to claim 5, which is characterized in that further comprise:
The step of soldered ball is adhered to the another side of the semiconductor packages to be recycled after step is re-molded described；With
And
After the attachment soldered ball the step of, the step of face carries out laser marking is re-molded to described.
8. a kind of recycling semiconductor packages, which is characterized in that the recycling semiconductor packages to be recycled re-molds described
The molding face of the semiconductor packages of recycling, the thickness of the semiconductor packages re-molded increase 50 to 1000 μm.
9. it is a kind of for recycling the fixture of semiconductor packages, to be formed with the half of moulded parts on one side for recycling
The fixture of conductor encapsulation characterized by comprising
Metal plate is formed with multiple opening portions, the size of the multiple opening portion for loading multiple semiconductor packages of recycling
It is corresponding with the semiconductor packages；And
Seal member is oppositely disposed at the one side of the metal plate with the another side of the semiconductor packages.
10. according to claim 9 for recycling the fixture of semiconductor packages, which is characterized in that the metal plate
It is formed by copper sheet, the multiple opening portion is formed continuously at a predetermined interval.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20170144604 | 2017-11-01 | ||
| KR10-2017-0144604 | 2017-11-01 | ||
| KR1020180006027A KR101992263B1 (en) | 2017-11-01 | 2018-01-17 | Recycling method for semiconductor package and recycling semiconductor package |
| KR10-2018-0006027 | 2018-01-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109755105A true CN109755105A (en) | 2019-05-14 |
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ID=66402351
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810321341.7A Pending CN109755105A (en) | 2017-11-01 | 2018-04-11 | Semiconductor packages recoverying and utilizing method recycles semiconductor packages and fixture |
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| JP2007273546A (en) * | 2006-03-30 | 2007-10-18 | Disco Abrasive Syst Ltd | Jig for semiconductor package and receiving method of semiconductor package |
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| JP2007273546A (en) * | 2006-03-30 | 2007-10-18 | Disco Abrasive Syst Ltd | Jig for semiconductor package and receiving method of semiconductor package |
| TW201016468A (en) * | 2007-06-21 | 2010-05-01 | Gen Electric | Method for making an interconnect structure and low-temperature interconnect component recovery process |
| TW201247093A (en) * | 2011-05-02 | 2012-11-16 | Powertech Technology Inc | Semiconductor packaging method to form double side electromagnetic shielding layers and device fabricated from the same |
| CN105164179A (en) * | 2013-03-06 | 2015-12-16 | Dic株式会社 | Epoxy resin composition, cured product, heat radiating material, and electronic member |
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Application publication date: 20190514 |