TW201917837A - Semiconductor package - Google Patents

Abstract

A semiconductor package includes: a semiconductor chip having connection pads; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface and including an insulating member and a redistribution layer formed on the insulating member and electrically connected to the connection pads; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; and a barrier layer disposed on the second surface of the connection member and including an organic layer containing fluorine.

Description

Semiconductor package

This disclosure relates to a semiconductor package. [Cross-reference to related applications]

This application claims the right of priority of Korean Patent Application No. 10-2017-0136062 filed in the Korean Intellectual Property Office on October 19, 2017, and the disclosure of the Korean patent application is cited in full. Incorporated herein.

Semiconductor packages are continuously required to be thinner and lighter in shape, and are required to be implemented in the form of a system in package (SiP) that requires complexity and versatility in functionality. With this development trend, a fan-out wafer level package (FOWLP) has recently prevailed, and attempts have been made to meet the requirements of semiconductor packaging by applying several technologies to FOWLP.

For the purpose of making the semiconductor package thin and light, it is urgent to reduce both the thickness of the circuit pattern transmitting the electrical signals and the thickness of the insulating layer covering the circuit pattern. As the thickness of the insulating layer decreases, reliability related to such characteristics as close adhesion, chemical resistance, heat resistance, moisture permeability, etc. It has become more difficult to be satisfied.

Aspects of the present disclosure can provide a semiconductor package that can solve the cause of reduced reliability (such as corrosion of a circuit pattern) by improving the water vapor permeability and air permeability of an insulating member.

According to aspects of the present disclosure, a semiconductor package can be provided in which a new barrier layer is introduced onto the surface of an insulating member for a rewiring structure to improve the reliability of the semiconductor package.

According to an aspect of the present disclosure, a semiconductor package may include: a semiconductor wafer having a connection pad; a connection member having a first surface on which the semiconductor wafer is disposed and a second surface opposite to the first surface, and including An insulating member and a redistribution layer disposed in the insulating member and electrically connected to the connection pad; an encapsulation body disposed on the first surface of the connection member and encapsulating the semiconductor wafer; and The barrier layer is disposed on the second surface of the connection member and includes an organic layer containing fluorine.

According to another aspect of the present disclosure, a semiconductor package may include: a semiconductor wafer having a connection pad; and a connection member having a first surface on which the semiconductor wafer is disposed and a second surface opposite to the first surface, And includes an insulating member, a redistribution layer disposed in the insulating member and electrically connected to the connection pad, and a sub-bump metallurgy connected to the redistribution layer and providing a connection region on the second surface (Underbump metallurgy, UBM) layer; an encapsulation body disposed on the first surface of the connection member and encapsulating the semiconductor wafer; an electrical connection structure disposed on the second surface of the connection member The connection region which is connected to the metallurgical layer below the bump; and a multilayer barrier having an organic layer disposed on the second surface of the connection member and an inorganic layer disposed on the organic layer.

Hereinafter, exemplary embodiments in the present disclosure will be explained with reference to the drawings. In the drawings, the shape, size, etc. of each component may be exaggerated or reduced for clarity.

Herein, the lower side, the lower portion, the lower surface, etc. are used to refer to the direction toward the mounting surface of the fan-out type semiconductor package with respect to the cross section of the figure, and the upper side, upper portion, upper surface, etc. are used to Refers to a direction opposite to that. However, these directions are defined for convenience of explanation, and the scope of the patent of this application is not particularly limited by the directions defined above.

In the description, the meaning of "connection" between a component and another component includes an indirect connection via an adhesive layer and a direct connection between two components. In addition, the concept of "electrical connection" includes physical connection and physical disconnection. It will be understood that when referring to elements such as "first" and "second", the elements are not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the element from other elements, and does not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the patentable scope set forth herein. Similarly, the second element may also be referred to as the first element.

The term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be able to be implemented by being combined with each other in whole or in part. For example, even if an element set forth in a particular exemplary embodiment is not set forth in another exemplary embodiment, the element is also provided unless an opposite or contradictory description is provided in another exemplary embodiment. It can be understood as a description related to another exemplary embodiment.

The terminology used herein is for the purpose of illustrating exemplary embodiments only and is not a limitation on the present disclosure. In this case, the singular includes the plural unless otherwise explained in context. Electronic device

FIG. 1 is a block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 can house a motherboard 1010. The motherboard 1010 may include a chip-related component 1020, a network-related component 1030, and other components 1040, which are physically or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip, such as a volatile memory (such as dynamic random access memory (DRAM)), a non-volatile memory (such as read only memory, ROM)), flash memory, etc .; application processor chips, such as central processing units (such as central processing unit (CPU)), graphics processors (such as graphics processing unit (GPU)), Digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc .; and logic chips such as analog-to-digital converters (ADCs), application-specific integrated circuits (applications) -specific integrated circuit (ASIC). However, the wafer-related component 1020 is not limited to this, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related component 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), global interoperable microwave access ( worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access ( code division multiple access (CDMA) , Time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G and any other designations specified after the above Wireless and wired protocols. However, the network related component 1030 is not limited to this, but may include various other wireless standards or protocols or wired standards or protocols. In addition, the network related components 1030 may be combined with each other together with the chip related components 1020 described above.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic, LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited to this, but may include passive components and the like for various other purposes. In addition, other components 1040 may be combined with each other together with the wafer-related component 1020 or the network-related component 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected or electrically connected to the motherboard 1010, or other components that may not be physically connected or electrically connected to the motherboard 1010. These other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), Compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (such as a hard drive) (not shown), compact disc (compact disk (CD) drive (not shown), digital versatile disk (DVD) drive (not shown), and the like. However, the other components are not limited to this, but may include other components for various purposes depending on the type of the electronic device 1000 and the like.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, and a notebook. Personal computers, netbook PCs, TVs, video game machines, smart watches, car components, etc. However, the electronic device 1000 is not limited to this, but may be any other electronic device that processes data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, a semiconductor package may be used for various purposes in various electronic devices 1000 as described above. For example, the motherboard 1110 can be accommodated in the body 1101 of the smart phone 1100, and various electronic components 1120 can be physically connected to or electrically connected to the motherboard 1110. In addition, other components (such as the camera module 1130) that can be physically connected or electrically connected to the main board 1010 or can not be physically or electrically connected to the main board 1010 can be housed in the body 1101. Some electronic components in the electronic component 1120 may be chip-related components, and the semiconductor package 100 may be, for example, an application processor among the chip-related components, but is not limited thereto. The electronic device is not limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor package

Generally speaking, many precision circuits are integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot serve as a finished semiconductor product and may be damaged due to external physical or chemical influences. Therefore, the semiconductor wafer is not used alone, but is packaged in an electronic device or the like and used in a packaged state.

Because there is a difference in circuit width in terms of electrical connection between the semiconductor chip and the motherboard of the electronic device, a semiconductor package is required. In detail, the size of the connection pads of the semiconductor wafer and the spacing between the connection pads of the semiconductor wafer are extremely precise, but the size of the component mounting pads of the motherboard used in electronic devices and the interval between the component mounting pads of the motherboard are significantly larger than The size and spacing of the connection pads of the semiconductor wafer. Therefore, it may be difficult to directly mount a semiconductor wafer on a motherboard, and a packaging technology for buffering a difference in circuit width between the semiconductor and the motherboard may be required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package manufactured by the packaging technology can be classified as a fan-in semiconductor package or a fan-out semiconductor package.

Hereinafter, the fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail with reference to the drawings. Fan-in semiconductor package

3A and 3B are schematic cross-sectional views showing a state of the fan-in semiconductor package before and after packaging, and FIG. 4 is a schematic cross-sectional view showing a packaging process of the fan-in semiconductor package.

Referring to FIGS. 3A to 4, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in an exposed state. The semiconductor wafer 2220 includes a body 2221 including silicon (Si), germanium (Ge), and gallium arsenide. (GaAs), etc .; a connection pad 2222 formed on one surface of the body 2221 and including a conductive material such as aluminum (Al); and a passivation layer 2223 such as an oxide film, a nitride film, and the like, and formed on the body 2221 On one surface and covering at least part of the connection pad 2222. In this case, since the connection pad 2222 may be significantly small, it may be difficult to mount an integrated circuit (IC) on an intermediate printed circuit board (PCB), a motherboard of an electronic device, and the like.

Therefore, depending on the size of the semiconductor wafer 2220, a connection member 2240 is formed on the semiconductor wafer 2220 to rewire the connection pads 2222. The connection member 2240 can be formed by the following steps: an insulating layer 2241 is formed on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin, and a through hole 2243h is formed to open the connection pad 2222, and then A wiring pattern 2242 and a through hole 2243 are formed. Next, a passivation layer 2250 for protecting the connection member 2240 may be formed, an opening 2251 may be formed, and a metal layer 2260 under the bump may be formed. That is, the fan-in type semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under bump metal layer 2260 may be manufactured through a series of processes.

As described above, a fan-in semiconductor package may have a package form in which all connection pads (such as input / output (I / O) terminals) of the semiconductor wafer are arranged in the semiconductor wafer, and may have excellent electrical properties. Sexual properties and can be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components mounted in a smart phone have been developed for fast signal transmission while being compact in size.

However, since all the input / output terminals in the fan-in type semiconductor package need to be arranged inside the semiconductor chip, the space limitation of the fan-in type semiconductor package is significant. Therefore, it is difficult to apply such a structure to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a small size. In addition, due to the disadvantages described above, a fan-in semiconductor package may not be directly mounted and used on a motherboard of an electronic device. The reason is that even in a case where the size of the input / output terminals of the semiconductor wafer and the interval between the input / output terminals of the semiconductor wafer are increased by the rewiring process, the size of the input / output terminals of the semiconductor wafer and the semiconductor wafer are increased. The interval between the input / output terminals of the device is still not enough for the fan-in semiconductor package to be directly mounted on the motherboard of the electronic device.

FIG. 5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device, and FIG. 6 is a diagram illustrating a fan-in semiconductor package embedded in the interposer substrate and finally mounted on an electronic device. A schematic cross-sectional view of the situation on the motherboard of the device.

5 and 6, in the fan-in type semiconductor package 2200, the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 can be re-routed again via the interposer substrate 2301, and the fan-in type semiconductor package 2200 can In a state of being mounted on the interposer substrate 2301, it is finally mounted on the main board 2500 of the electronic device. In this case, the solder balls 2270 and the like can be fixed by underfill resin 2280 and the like, and the outside of the semiconductor wafer 2220 can be covered with the encapsulation body 2290 and the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be in a state where the fan-in semiconductor package 2200 is embedded in the interposer substrate 2302. The interposer substrate 2302 is rewired again, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly mount and use a fan-in semiconductor package on a motherboard of an electronic device. Therefore, the fan-in type semiconductor package can be mounted on a separate interposer substrate and then mounted on the main board of the electronic device through a packaging process; or the fan-in type semiconductor package can be in a state where the fan-in semiconductor package is embedded in the interposer Install and use on the motherboard of the electronic device. Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view showing a fan-out type semiconductor package.

Referring to FIG. 7, in the fan-out type semiconductor package 2100, for example, the outside of the semiconductor wafer 2120 may be protected by the encapsulation body 2130, and the connection pad 2122 of the semiconductor wafer 2120 may be directed outside the semiconductor wafer 2120 by the connection member 2140. Perform rewiring. In this case, a passivation layer 2150 may be further formed on the connection member 2140, and an under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, a passivation layer (not shown), and the like. The connection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a through hole 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

In this manufacturing process, the connection member 2140 may be formed after the encapsulation body 2130 is formed on the outside of the semiconductor wafer 2120. In this case, the process of connecting members 2140 is performed by the through-holes connecting the redistribution layer and the connection pad 2122 of the semiconductor wafer 2120 to each other, and thus the width of the through-holes 2143 can be changed with it. Semiconductor wafers (see enlarged area).

As described above, the fan-out type semiconductor package may have a form in which the input / output terminals of the semiconductor wafer are rewired and arranged outside the semiconductor wafer by the connection member formed on the semiconductor wafer. As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer need to be arranged in the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls must be reduced, thereby making standardized ball layouts unusable in fan-in semiconductor packages. On the other hand, as described above, the fan-out type semiconductor package has a form in which the input / output terminals of the semiconductor wafer are rewired and arranged outside the semiconductor wafer by the connection member formed on the semiconductor wafer. Therefore, even in the case where the size of the semiconductor wafer is reduced, the standardized ball layout can still be used in a fan-out semiconductor package, so that the fan-out semiconductor package can be installed on the motherboard of an electronic device without using a separate interposer substrate. As described below.

FIG. 8 is a schematic cross-sectional view showing a state in which a fan-out semiconductor package is mounted on a motherboard of an electronic device.

Referring to FIG. 8, the fan-out type semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device via a solder ball 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of rewiring the connection pad 2122 to a fan-out area outside the size of the semiconductor wafer 2120, thereby making The standardized ball layout can still be used in the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As described above, since a fan-out semiconductor package can be mounted on a main board of an electronic device without using a separate interposer, the thickness of the fan-out semiconductor package can be smaller than that of a fan-in semiconductor package using an interposer. Next implementation. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, making the fan-out semiconductor package particularly suitable for mobile products. Therefore, the fan-out semiconductor package can be implemented in a more compact form than a general package-on-package (POP) type using a printed circuit board (PCB), and can solve the problem caused by warpage. And the problems that arise.

Fan-out type semiconductor package means a packaging technology for mounting a semiconductor wafer on a motherboard of an electronic device or the like as described above and protecting the semiconductor wafer from external influences, and it is in contact with a printed circuit board (PCB) such as an interposer It is conceptually different. The printed circuit board has a specification, purpose, etc. different from that of the fan-out type semiconductor package, and a fan-in type semiconductor package is embedded therein.

Hereinafter, a semiconductor wafer for improving high-temperature / high-humidity reliability by forming a barrier layer capable of reducing the penetration of water vapor and gas on the surface of an insulating member will be described in detail with reference to the attached drawings.

FIG. 9 is a side sectional view showing a semiconductor package according to an exemplary embodiment in the present disclosure, and FIGS. 10A and 10B are a plan view and a bottom view showing the semiconductor package shown in FIG. 9, respectively.

9 and 10A, a semiconductor package 100A according to this exemplary embodiment may include: a core member 110 having a cavity 110H; and a connection member 140 having a first surface on which the core member 110 is disposed and the first surface A second surface opposite to each other and including a redistribution layer 145; a semiconductor wafer 120 disposed in the cavity 110H of the core member 110 and having a connection pad 122 connected to the redistribution layer 145; and an encapsulation body 130 that encloses the core Component 110 and semiconductor wafer 120.

As shown in FIG. 9, an electrical connection structure 170 may be disposed on the second surface of the connection member 140. The connection member 100 may include a UBM layer 160 that connects the electrical connection structure 170 and the redistribution layer 145 to each other.

A barrier layer 180 may be disposed on the second surface of the connection member 140. The barrier layer 180 may be disposed on the outermost surface of the insulating member 141, and may effectively prevent water vapor and gas (such as oxygen) from penetrating into the inside.

The barrier layer 180 used in this exemplary embodiment may have a multilayer barrier structure including an organic layer 181 and an inorganic layer 185 disposed on the organic layer 181.

The organic layer 181 may be formed of an organic material containing fluorine. The inorganic layer 185 itself can be used not only to prevent penetration of water vapor and oxygen, but also to protect the organic layer 181 in a high-temperature environment such as a reflow process.

For example, the fluorine-containing organic layer 181 may include at least one selected from the group consisting of CF ₄ , C ₄ F _8, and fluoroalkylsilane. The fluoroalkylsilane which may be used as a material of the organic layer 181 may include, but is not limited to, a fluoroalkylsilane having one or more fluorine atoms and about 1 to about 12 carbon atoms. For example, the organic layer 181 may include an organic material satisfying R-Si-F _x C _y OH. Here, the functional group represented by R may include an alkyl group, a fluoroalkyl group, an acrylic group, a methacrylic group, a vinyl group, an epoxy group, an amine group, and an aniline group, but is not limited thereto. In another example, the organic layer 181 may include perylene.

For example, the inorganic layer 185 may include at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. The inorganic layer 185 may be formed by chemical vapor deposition (CVD), sputtering, or evaporation.

Examples of the oxygen barrier layer 180 used in the present exemplary embodiment may be from 0.01 cc / square meter / day (cc / m ² / day) or less than 0.01 cc / m² / day, preferably a 0.001 cm3 / m2 / day or less. Here, the oxygen permeability may be a value measured at a temperature of 35 ° C. and a relative humidity of 0% using OX-TRAN 2/20, which is commercially available from the MOCON Company.

The water vapor permeability of the barrier layer 180 used in this exemplary embodiment may be 0.1 g / m ² / day (g / m ² / day) or less, preferably 0.01. G / m2 / day or less than 0.01 g / m2 / day. Here, the water vapor permeability may be a value measured for 48 hours at a temperature of 37.8 ° C and a relative humidity of 100% using PERMATRAN-W3 / 31, which is commercially available from Markem.

The thickness t1 of the organic layer 181 may be in a range from 0.01 micrometer (μm) to 0.5 micrometer, and the thickness t2 of the inorganic layer 182 may be in a range from 0.01 micrometer to 0.5 micrometer. That is, the entire thickness of the barrier layer 180 may be in a range from 0.02 micrometers to 2 micrometers. In an example, the thickness t1 of the organic layer may be greater than the thickness t2 of the inorganic layer.

As shown in FIGS. 9 and 10B, the barrier layer 180 may be disposed in a region other than the electrical connection structure 170 on the second surface of the connection member 140. The barrier layer 180 may be formed on a region equal to or larger than 50% of an area other than the electrical connection structure 170 of the second surface of the connection member 140 to achieve a sufficient effect.

In this exemplary embodiment, the connection member 140 may have a three-layer redistribution structure including a first wiring layer having a first wiring pattern 142a and a first through-hole 143a; a second The wiring layer includes a second wiring pattern 142b and a second through hole 143b; and the third wiring layer includes a third wiring pattern 142c and a third through hole 143c.

In detail, the connection member 140 may include: a first insulating layer 141a disposed on the first surface of the core member 110 and the semiconductor wafer 120; a first wiring pattern 142a disposed on the first insulating layer 141a; a first through hole 143a, which connects the first insulating layer 141a and the connection pad 122 of the semiconductor wafer 122 to each other; the second insulating layer 141b, which is disposed on the first insulating layer 141a and covers the first wiring pattern 142a; On the two insulating layers 141b; the second through holes 143b penetrate the second insulating layer 141b and connect the first wiring pattern 142a and the second wiring pattern 142b to each other; A second wiring pattern 142b; a third wiring pattern 142c disposed on the third insulating layer 141c; and a third through hole 143c penetrating the third insulating layer 141c and electrically connecting the second wiring pattern 142b and the third wiring pattern 142c to each other connection.

Hereinafter, each component included in the semiconductor package 100A according to the present exemplary embodiment will be explained in more detail.

The core member 110 can maintain the rigidity of the semiconductor package 100A and can be used to ensure the thickness uniformity of the encapsulation body 130. A redistribution layer 145 such as a wiring pattern and a via hole may be introduced on the core member 110. In this case, the semiconductor package 100A can be used as a package-on-package (POP) type fan-out type package (see FIGS. 11 and 13). The semiconductor wafer 120 may be disposed in the cavity 110H so that the semiconductor wafer 120 and the sidewall of the core member 110 are separated by a predetermined distance. A side surface of the semiconductor wafer 120 may be surrounded by the core member 110. However, this form is merely an example, and may be variously modified to have another form, and the core component 110 may perform another function in this form. In some exemplary embodiments, the core component 110 may be omitted.

The core member 110 may include an insulating layer. The material of the insulating layer may be a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; a resin in which a thermosetting resin or a thermoplastic resin is mixed with an inorganic filler; or a thermosetting resin or a thermoplastic resin and an inorganic filler are impregnated together, for example Resin in core materials such as glass fiber (or glass cloth, or glass fiber cloth), such as prepreg, Ajinomoto Build up Film (ABF), FR-4, double malay Bismaleimide Triazine (BT) and so on. When a material having high rigidity (for example, a prepreg including glass fiber or the like) is used as the material of the insulating layer, the core member 110 may be used as a supporting member for controlling the warpage of the semiconductor package 100A.

The semiconductor wafer 120 may be an integrated circuit (IC) provided to integrate hundreds to millions or more of components in a single wafer. In this case, for example, the integrated circuit may be a processor chip (more specifically, an application processor (AP)), such as a central processing unit (such as a central processing unit), a graphics processor (such as Graphics processing unit), field programmable gate array (FPGA), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc., but not limited to this. That is, the integrated circuit may be a logic chip, such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like, or may be a memory chip such as a volatile memory (such as a dynamic random access memory). ), Non-volatile memory (such as read-only memory), flash memory, etc. In addition, the above-mentioned elements may be arranged in combination with each other.

The semiconductor wafer 120 may be formed on the basis of an active wafer. In this case, the base material of the body 121 of the semiconductor wafer 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body 121. The connection pad 122 can electrically connect the semiconductor wafer 120 to other components. The material of each of the connection pads 122 may be a conductive material such as aluminum (Al). A passivation layer 123 exposing the connection pad 122 may be formed on the body 121, and the passivation layer 123 may be an oxide film, a nitride film, or the like, or a double layer composed of an oxide layer and a nitride layer. With the passivation layer 123, the lower surface of the connection pad 122 may have a step relative to the lower surface of the encapsulation body 130. Therefore, the phenomenon that the encapsulation body 130 penetrates into the lower surface of the connection pad 122 can be prevented to a certain extent. An insulation layer (not shown) and the like may be further disposed at other required positions. The semiconductor wafer 120 may be a bare die. A redistribution layer (not shown) may be further formed on the first surface (the surface on which the connection pad 122 is formed) of the semiconductor wafer 120, and a bump ( Not shown) or the like is connected to the connection pad 122.

An encapsulation body 130 may be provided to protect the core member 110 and electronic components such as the semiconductor wafer 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be a form in which the encapsulation body 130 surrounds at least a part of the core member 110, the semiconductor wafer 120, and the like. For example, the encapsulation body 130 may cover the core member 110 and the upper surface of the semiconductor wafer 120, and may fill the space between the wall of the cavity 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulation body 130 may also fill at least a part of a space between the passivation layer 123 of the semiconductor wafer 120 and the connection member 140. At the same time, the encapsulation body 130 may fill the cavity 110H, thereby acting as an adhesive, and reducing buckling of the semiconductor wafer 120 depending on a specific material.

For example, the following materials can be used as the material of the encapsulation body 130: a thermosetting resin, such as an epoxy resin; a thermoplastic resin, such as a polyimide resin; a resin that mixes a thermosetting resin and a thermoplastic resin with an inorganic filler; or a thermosetting resin And thermoplastic resin and inorganic filler are dipped into core materials such as glass fiber, such as prepreg, Ajinomoto film, FR-4, bismaleimide triazine, etc. In some exemplary embodiments, a photosensitive imaging dielectric resin may also be used as a material of the encapsulation body 130.

The connection member 140 may rewire the connection pads 122 of the semiconductor wafer 120. The tens to hundreds of connection pads 122 of the semiconductor wafer 120 having various functions can be rewired by the connection member 140, and depending on the function, the electrical connection structure 170 can be used for physical or electrical connection with the outside.

The connection member 140 may be disposed on the first surface of the core member 110 and the semiconductor wafer 120, and may have another multi-layer redistribution structure in addition to the three-layer wiring structure according to the exemplary embodiment, and in some exemplary embodiments, In an embodiment, the redistribution structure may include a single layer (ie, a wiring pattern + a via).

The insulating member 141 used in the connection member 140 may include a first insulating layer 141a, a second insulating layer 141b, a third insulating layer 141c, and a fourth insulating layer 141d. In addition to the insulating materials described above, the first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth insulating layer 141d may be formed of a photosensitive insulating material such as a photosensitive imaging dielectric resin. When the first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth insulating layer 141d have photosensitive properties, the first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the first Each of the four insulating layers 141d may be formed to have a smaller thickness, and it may be easier to achieve a precise pitch of each of the first through hole 143a, the second through hole 143b, and the third through hole 143c. . However, as the thickness of each of the first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth insulating layer 141d decreases, water vapor permeability and / or oxygen permeability may be Relatively increased. Therefore, problems such as ion migration or generation of an oxide film may occur in the redistribution layer 145 which may be formed of a metal such as copper. To prevent such a problem, the barrier layer 180 used in this exemplary embodiment may reduce adverse effects caused by oxygen, water vapor, and the like penetrating through the insulating member.

The first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth insulating layer 141d may be a photosensitive insulating layer including an insulating resin and an inorganic filler. For example, the content of the inorganic filler in each of the insulating layers may be 10% by weight (wt%) or less based on the insulating material. When the first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth insulating layer 141d are multiple layers, the first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth The materials of the insulating layers 141d may be the same as each other, or may be different from each other. The first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth insulating layer 141d may be integrated with each other depending on the process used, so that the boundaries between the insulating layers may be inconspicuous.

Between the patterns other than the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c, the first insulating layer 141a, the second insulating layer 141b, the third insulating layer 141c, and the fourth insulating layer 141d Each of these may have a thickness of about 1 to 10 microns.

The first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c may be used to rewire the connection pad 122 together with the first through hole 143a, the second through hole 143b, and the third through hole 143c. The first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c may perform various functions depending on the design of the corresponding layer. For example, the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal. In addition, the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c may include a through-hole pad pattern, an electrical connection structure pad pattern, and the like. Each of the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c may have a thickness of about 0.5 to 15 micrometers.

The first through hole 143a, the second through hole 143b, and the third through hole 143c may be used to connect the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c, which are formed on different layers, in a vertical direction. The pads 122 and the like are connected to each other. Each of the first through hole 143a, the second through hole 143b, and the third through hole 143c may include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first through hole 143a, the second through hole 143b, and the third through hole 143c may be completely filled with a conductive material, or the conductive material may be formed along the wall of each of the through hole holes. In addition, each of the first through hole 143a, the second through hole 143b, and the third through hole 143c may have any shape known in the related art, such as a tapered shape, a cylindrical shape, or the like.

In this exemplary embodiment, a passivation layer for protecting the connection member 140 from external physical or chemical damage, etc. may be omitted, and the barrier layer 180 may be introduced to the surface of the fourth insulating layer 141d (which is formed thereon) There are bumps below the outermost metallurgical layer 160), but this exemplary embodiment is not limited to this.

The under-bump metallurgical layer 160 can improve the connection reliability of the electrical connection structure 170 to improve the board-level reliability of the semiconductor package 100A. The under bump metallurgical layer 160 may be connected to the redistribution layer 145 of the connection member 140 exposed through the opening h of the fourth insulating layer 141d. The under-bump metallurgical layer 160 may be formed in the opening h by any conventional metallization method using any conventional conductive material (such as metal), but it is not limited thereto.

The electrical connection structure 170 may be externally physically connected or electrically connected to the semiconductor package 100A. For example, the semiconductor package 100A can be mounted on a motherboard of an electronic device through the electrical connection structure 170. Each of the electrical connection structures 170 may be formed of a conductive material, such as solder or the like. However, this is only an example, and the material of each of the electrical connection structures 170 is not particularly limited thereto. Each of the electrical connection structures 170 may be a pin, a ball, a pin, or the like. The electrical connection structure 170 may be formed as a multilayer structure or a single-layer structure. When the electrical connection structure 170 is formed as a multilayer structure, the electrical connection structure 170 may include copper (Cu) pillars and solder. When the electrical connection structure 170 is formed as a single-layer structure, the electrical connection structure 170 may include tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structure 170 is not limited to this. The number, interval, and configuration of the electrical connection structures 170 are not particularly limited, but can be fully modified by those skilled in the art depending on design details. For example, the electrical connection structure 170 may be set to a number of tens to thousands, or a number of tens to thousands or more or tens to thousands or Less quantity.

At least one of the electrical connection structures 170 may be disposed in the fan-out area. The fan-out region refers to a region other than a region where the semiconductor wafer 120 is arranged. The fan-out package can have superior reliability compared to the fan-in package, can implement multiple input / output (I / O) terminals, and can facilitate 3D interconnection. In addition, compared to a ball grid array (BGA) package, a land grid array (LGA) package, and the like, a fan-out package can be manufactured to have a smaller thickness.

Meanwhile, although not shown in the drawings, when necessary, a metal thin film may be formed on the wall of the cavity 110H to dissipate or block electromagnetic waves. In some exemplary embodiments, when necessary, a plurality of semiconductor wafers 120 that perform the same or different functions from each other may be configured in the cavity 110H. In some exemplary embodiments, separate passive components such as inductors, capacitors, etc. may be configured in the cavity 110H. In some exemplary embodiments, a passive component such as a surface mounting technology (SMT) component including an inductor, a capacitor, and the like may be configured on the surface of the passivation layer 150.

FIG. 11 is a side sectional view showing a semiconductor package according to another exemplary embodiment in the present disclosure.

11, it can be understood that, except that the semiconductor package 100B includes a core member 110 having a wiring structure and the barrier layer is formed as a single layer all the way to the surface of the electrical connection structure, the semiconductor package 100B according to the exemplary embodiment has A structure similar to that shown in FIG. 9. Unless explicitly stated to the contrary, the components according to the present exemplary embodiment may be understood with reference to the description of the same components or similar components of the semiconductor package 100A shown in FIG. 9.

In this exemplary embodiment, the core member 110 may include: a first dielectric layer 111a, which contacts the connection member 140; a first wiring layer 112a, which contacts the connection member 140 and is embedded in the first dielectric layer 111a; a second wiring layer 112b is disposed on the other surface of the first dielectric layer 111a, and the other surface is opposite to one surface of the first dielectric layer 111a having the first wiring layer 112a embedded therein; the second dielectric layer 111b is disposed on The first dielectric layer 111a covers the second wiring layer 112b; and the third wiring layer 112c is disposed on the second dielectric layer 111b. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be electrically connected to the connection pad 122. Respectively, the first wiring layer 112a and the second wiring layer 112b may be electrically connected to each other through the first through hole 113a penetrating the first dielectric layer 111a, and the second wiring layer 112b and the third wiring layer 112c may be connected via The second through holes 113b passing through the second dielectric layer 111b are electrically connected to each other.

When the first wiring layer 112a is embedded in the first dielectric layer 111a as in this exemplary embodiment, the step due to the thickness of the first wiring layer 112a can be significantly reduced, and the insulation distance of the connection member 140 can be reduced. Therefore, it becomes constant. That is, the distance from the first wiring pattern 142a of the connection member 140 to the lower surface of the first dielectric layer 111a and the distance from the first wiring pattern 142a of the connection member 140 to the connection pad 122 of the semiconductor wafer 120, both The difference between them may be smaller than the thickness of the first wiring layer 112a. Therefore, a high-density wiring design of the connection member 140 can be easily achieved.

A lower height of the lower surface of the first wiring layer 112 a of the core member 110 may be higher than a lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, a distance between the first wiring pattern 142 a of the connection member 140 and the first wiring layer 112 a of the core member 110 may be greater than a distance between the first wiring pattern 142 a of the connection member 140 and the connection pad 122 of the semiconductor wafer 120. The reason is that the first wiring layer 112a can be recessed in the first dielectric layer 111a.

As described above, when the first wiring layer 112a is recessed in the first dielectric layer 111a, so that there is a step between the lower surface of the first dielectric layer 111a and the lower surface of the first wiring layer 112a, encapsulation can be prevented. A phenomenon that the material of the body 130 penetrates and contaminates the first wiring layer 112a. The horizontal height of the second wiring layer 112 b of the core member 110 may be between the active surface and the non-active surface of the semiconductor wafer 120. The core member 110 may be formed in a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the horizontal height of the second wiring layer 112 b formed in the core member 110 may be between the active surface and the non-active surface of the semiconductor wafer 120.

The thickness of the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c of the core member 110 may be greater than the thickness of the wiring pattern 142a, the wiring pattern 142b, and the wiring pattern 142c of the connection member 140. Since the thickness of the core member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the wiring layer 112a, the wiring layer 112b, and the wiring layer 112c may be formed to have a large size depending on the specifications of the core member 110. On the other hand, in consideration of thinness, the size of the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c of the connection member 140 may be formed relatively smaller than those of the first wiring layer 112a and the second wiring. The dimensions of the layer 112b and the third wiring layer 112c.

The material of each of the first dielectric layer 111a and the second dielectric layer 111b is not particularly limited, but may be, for example, the following materials: a thermosetting resin such as an epoxy resin; a thermoplastic resin such as a polyimide resin; A resin in which a thermosetting resin and a thermoplastic resin are mixed with an inorganic filler or a resin in which a thermosetting resin and a thermoplastic resin and an inorganic filler are immersed in a core material such as glass fiber, such as a prepreg, Ajinomoto build-up film, FR- 4, bismaleimide imine triazine and so on. In some exemplary embodiments, a photosensitive imaging dielectric resin may also be used as a material of each of the first dielectric layer 111a and the second dielectric layer 111b.

The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be used to rewire the connection pads 122 of the semiconductor wafer 120. For example, the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may perform various functions depending on the design of the corresponding layer. For example, the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, such as a data signal. In addition, the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may include through-hole pads, wiring pads, electrical connection structure pads, and the like.

The first through-hole 113a and the second through-hole 113b may electrically connect the first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c formed on different layers to each other, thereby forming electricity in the core member 110. Sexual path (electrical path). The material of each of the first through hole 113a and the second through hole 113b may be a conductive material.

Each of the first through hole 113a and the second through hole 113b may be completely filled with a conductive material, or the conductive material may be formed along the wall of each of the through hole holes. In addition, each of the first through hole 113a and the second through hole 113b may have any shape known in the related art, such as a cone shape, a cylindrical shape, or the like. When the holes of the first through hole 113a are formed, some pads of the first wiring layer 112a may serve as termination elements. Making each of the first through holes 113a have a tapered shape with an upper surface width greater than a lower surface width may facilitate the manufacturing process. In this case, the first through hole 113a may be integrated with the pad pattern of the second wiring layer 112b. In addition, when the holes of the second through hole 113b are formed, some of the pads of the second wiring layer 112b can serve as termination elements, and therefore, each of the second through holes 113b has an upper surface width greater than a lower surface width. The tapered shape can facilitate the process. In this case, the second through hole 113b may be integrated with the pad pattern of the third wiring layer 112c.

The barrier layer 181 used in this exemplary embodiment may have a single-layer structure different from the above-described exemplary embodiment, and when the barrier layer 181 has a single-layer structure, the barrier layer 181 may be an organic barrier layer 181 containing fluorine.

For example, the organic barrier layer 181 containing fluorine may include at least one selected from the group consisting of CF ₄ , C ₄ F ₈ and fluoroalkylsilane. The fluoroalkylsilane which may be used as a material of the organic barrier layer 181 may include, but is not limited to, a fluoroalkylsilane having one or more fluorine atoms and about 1 to about 12 carbon atoms. In another example, the organic barrier layer 181 may include erbium.

Unlike the above exemplary embodiment, the organic barrier layer 181 may be formed on the second surface of the connection member to cover the surface of the electrical connection structure 170. The process of forming the organic barrier layer 181 may be performed after the electrical connection structure 170 is formed.

In this exemplary embodiment, although the organic barrier layer 181 is formed of an insulating material, the portion of the organic barrier layer 181 disposed on the electrical connection structure 170 can be controlled during the reflow process by controlling the thickness of the organic barrier layer 181. Medium thermal decomposition.

12A and 12B are cross-sectional views illustrating a process of mounting the semiconductor package shown in FIG. 11 on a motherboard.

First, as shown in FIG. 12A, a semiconductor package 100B according to this exemplary embodiment may be mounted on a motherboard 250 of an electronic device to connect an electrical connection structure 170 to a circuit pattern 220. The circuit pattern 220 may include first patterns 220a and second patterns 220b respectively disposed on the upper and lower surfaces of the board body 210, and conductive vias connecting the first patterns 220a and the second patterns 220b to each other. 220c. The organic barrier layer 181 may be formed on the lower surface of the connection member 140 and extends to the surface of the electrical connection structure 170 disposed on the circuit pattern 220.

Next, as shown in FIG. 12B, a reflow process may be performed. In the re-soldering process, the electrical connection structure 170 can be melted and attached to the first pattern 220a. In this melting process, the organic barrier layer 181 existing on the surface of the electrical connection structure 170 can be thermally decomposed And removed. On the other hand, the organic barrier layer 181 may remain on the lower surface of the connection member 140 to effectively prevent oxygen and / or water vapor from penetrating into the connection member 140.

The organic barrier layer 181 used in the exemplary embodiment may be formed at a thickness of 0.2 micrometers or less, so as to effectively remove the organic barrier layer 181 existing on the surface of the electrical connection structure 170 without causing residuals. The impact of things. Meanwhile, the organic barrier layer 181 retained on the lower surface of the connection member 140 may be formed with a thickness of 0.02 micrometers or more to maintain resistance to oxygen and / or water vapor.

FIG. 13 is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring to FIG. 13, it can be understood that, in addition to using the core member 110 having a wiring structure and forming a passivation layer 150 on a lower surface of the connection member 140, the semiconductor package 100C according to this exemplary embodiment has the same structure as that shown in FIG. 9. Structure similar structure. Unless explicitly stated to the contrary, the components according to the present exemplary embodiment may be understood with reference to the description of the same components or similar components of the semiconductor package 100A shown in FIG. 9.

In the semiconductor package 100C according to this exemplary embodiment, the core member 110 may include: a first dielectric layer 111a; a first wiring layer 112a and a second wiring layer 112b, which are respectively disposed on opposite surfaces of the first dielectric layer 111a On; the second dielectric layer 111b is disposed on the first dielectric layer 111a and covers the first wiring layer 112a; the third wiring layer 112c is disposed on the second dielectric layer 111b; the third dielectric layer 111c is disposed The first dielectric layer 111a covers the second wiring layer 112b; and the fourth wiring layer 112d is disposed on the third dielectric layer 111c. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may be electrically connected to the connection pad 122.

Since the core member 110 may include a large number of wiring layers 112a, 112b, 112c, and 112d, the connection member 140 may be further simplified. Therefore, the problem of a decrease in the yield due to a defect occurring in the process of forming the connection member 140 can be suppressed. Meanwhile, the first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may pass through the first dielectric layer 111a, the second dielectric layer 111b, and the third dielectric layer, respectively. The first through hole 113a, the third through hole 113b, and the third through hole 113c of 111c are electrically connected to each other.

The first dielectric layer 111a may have a thickness greater than that of the second dielectric layer 111b and the thickness of the third dielectric layer 111c. The first dielectric layer 111a may be relatively thick to maintain rigidity, and the second dielectric layer 111b and the third dielectric layer 111c may be introduced to form a larger number of wiring layers 112c and 112d. The first dielectric layer 111a may include an insulating material different from an insulating material of the second dielectric layer 111b and an insulating material of the third dielectric layer 111c. For example, the first dielectric layer 111a may be, for example, a prepreg including a core material, a filler, and an insulating resin, and the second dielectric layer 111b and the third dielectric layer 111c may be a flavor including a filler and an insulating resin. Element buildup film or photosensitive imaging dielectric film. However, the material of the first dielectric layer 111a, the material of the second dielectric layer 111b, and the material of the third dielectric layer 111c are not limited thereto. Similarly, the first via hole 113a penetrating the first dielectric layer 111a may have a diameter larger than the diameter of the second via hole 113b penetrating the second dielectric layer 111b and the third via hole 113c penetrating the third dielectric layer 111c. diameter of.

The lower surface of the third wiring layer 112 c of the core member 110 may be disposed at a level lower than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, a distance between the first wiring pattern 142 a of the connection member 140 and the third wiring layer 112 c of the core member 110 may be smaller than a distance between the first wiring pattern 142 a of the connection member 140 and the connection pad 122 of the semiconductor wafer 120.

The reason is that the third wiring layer 112c may be disposed on the second dielectric layer 111b in a protruding form so as to contact the connection member 140. The first wiring layer 112 a and the second wiring layer 112 b of the core member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120. Since the thickness of the core member 110 may be formed corresponding to the thickness of the semiconductor wafer 120, the first wiring layer 112a and the second wiring layer 112b formed in the core member 110 may be disposed between the active surface and the non-active surface of the semiconductor wafer 120. Level.

The thicknesses of the first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d of the core member 110 may be greater than the thicknesses of the first wiring pattern 142a, the second wiring pattern 142b, and the first wiring layer 142 of the connection member 140. The thickness of the three wiring patterns 142c. Since the core member 110 may have a thickness equal to or greater than the thickness of the semiconductor wafer 120, the first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d may also be formed with larger sizes. . On the other hand, considering the thinness, the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c of the connection member 140 having a relatively small size can be formed.

The connection member 140 'used in this exemplary embodiment may further include a passivation layer 150 disposed on the lower surface of the insulating member 141' and partially embedded in the metallurgical layer 160 under the bump.

The passivation layer 150 may protect the semiconductor wafer from external physical or chemical damage. The passivation layer 150 may have an opening h that exposes at least part of the first wiring pattern 142a, the second wiring pattern 142b, and the third wiring pattern 142c of the connection member 140 '. The number of the openings h formed in the passivation layer 150 may be tens to thousands. For example, the passivation layer 150 may include at least one of a prepreg, an Ajinomoto build-up film, FR-4, bismaleimide triazine, and a solder resist.

The barrier layer 180 used in this exemplary embodiment may have a multilayer structure similar to the barrier layer shown in FIG. 9, and the barrier layer 180 may be disposed on the passivation layer 150.

The barrier layer 180 may have a multilayer barrier structure including an organic layer 181 and an inorganic layer 185 disposed on the organic layer 181. The organic layer 181 may be formed of an organic material containing fluorine. For example, the fluorine-containing organic layer 181 may include at least one selected from the group consisting of CF ₄ , C ₄ F _8, and fluoroalkylsilane. For example, the inorganic layer 185 may include at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. The oxygen permeability of the barrier layer 180 used in this exemplary embodiment may be 0.01 cm3 / m2 / day or less, and preferably 0.001 cm3 / m2 / day. Or less than 0.001 cubic centimeter / square meter / day, and the water vapor permeability of the barrier layer 180 used in this exemplary embodiment may be 0.1 g / square meter / day or less than 0.1 g / square meter / day, It is preferably 0.01 g / m2 / day or less.

The thickness t1 of the organic layer 181 may be in a range of 0.01 μm to 0.5 μm, and the thickness t2 of the inorganic layer 182 may be in a range of 0.01 μm to 0.5 μm. That is, the entire thickness of the barrier layer 180 may be in a range of 0.02 μm to 2 μm. In an example, the thickness t1 of the organic layer may be greater than the thickness t2 of the inorganic layer.

The under bump metallurgical layer 160 may be connected to the third wiring pattern 143c of the connection member 140 'exposed through the opening h of the passivation layer 150. The under-bump metallurgy layer 160 may be formed in the opening h of the passivation layer 150 by any conventional metallization method using any conventional conductive metal (eg, metal), but it is not limited thereto.

As described above, according to the exemplary embodiments in the present disclosure, it is possible to provide a reliability caused by the penetration of oxygen or gas by introducing an organic barrier layer containing organic fluorine or an organic / inorganic barrier layer onto the surface of an insulating member. A semiconductor package that reduces the problem of reliability and maintains excellent reliability in high temperature / high humidity environments.

Although exemplary embodiments have been shown and described above, it should be apparent to those skilled in the art that retouching and changes can be made without departing from the scope of the invention as defined by the scope of the accompanying patent application. .

100, 100A, 100B, 100C‧‧‧ semiconductor package

110‧‧‧Core components

110H‧‧‧ Cavity

111‧‧‧ Insulation

111a‧‧‧first dielectric layer

111b‧‧‧Second dielectric layer

111c‧‧‧Third dielectric layer

112a‧‧‧wiring layer / first wiring layer

112b‧‧‧wiring layer / second wiring layer

112c‧‧‧Wiring layer / Third wiring layer

112d‧‧‧wiring layer / fourth wiring layer

113a, 143a‧‧‧First through hole

113b, 143b‧‧‧Second through hole

113c, 143c‧‧‧Third through hole

120, 2120, 2220‧‧‧ semiconductor wafer

121, 1101, 2121, 2221‧‧‧ Ontology

122, 2122, 2222‧‧‧ connecting pads

123, 150, 2150, 2223, 2250 ‧‧‧ passivation layer

130, 2130, 2290‧‧‧ envelope

140, 140 ’, 2140, 2240‧‧‧ connecting members

141, 141’‧‧‧ insulating members

141a‧‧‧First insulation layer

141b‧‧‧Second insulation layer

141c‧‧‧Third insulation layer

141d‧‧‧Fourth insulation layer

142a‧‧‧wiring pattern / first wiring pattern

142b‧‧‧wiring pattern / second wiring pattern

142c‧‧‧wiring pattern / third wiring pattern

145, 2142‧‧‧ Redistribution layer

160‧‧‧Under bump metallurgical (UBM) layer

170‧‧‧electrical connection structure

180‧‧‧ The barrier layer

181‧‧‧Organic layer / Barrier layer / Organic barrier layer

185‧‧‧ inorganic layer

210‧‧‧ plate body

220‧‧‧Circuit pattern

220a‧‧‧The first pattern

220b‧‧‧Second pattern

220c‧‧‧ conductive via

250, 1010, 2500‧‧‧ motherboards

1000‧‧‧ electronic device

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050, 1130‧‧‧ Camera Module

1060‧‧‧antenna

1070‧‧‧Display device

1080‧‧‧ battery

1090‧‧‧Signal line

1100‧‧‧Smartphone

1110‧‧‧Motherboard

1120‧‧‧Electronic components

2100‧‧‧fan-out semiconductor package

2141, 2241‧‧‧ Insulation

2143, 2243‧‧‧through hole

2160, 2260‧‧‧ metal layer under bump

2170, 2270‧‧‧ solder balls

2200‧‧‧fan-in semiconductor package

2242‧‧‧Wiring pattern

2243h‧‧‧Through Hole

2251, h‧‧‧ opening

2280‧‧‧ underfill resin

2301, 2302‧‧‧ interposer

I-I’‧‧‧ line

t0, t1, t2‧‧‧thickness

The above and other aspects, features, and advantages of the present disclosure will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings. In the drawings: FIG. 1 is a block diagram illustrating an example of an electronic device system. FIG. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating a state of the fan-in semiconductor package before and after the package. FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package. FIG. 5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device. FIG. 6 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device. FIG. 7 is a schematic cross-sectional view showing a fan-out type semiconductor package. FIG. 8 is a schematic cross-sectional view showing a state in which a fan-out semiconductor package is mounted on a motherboard of an electronic device. FIG. 9 is a side cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure. 10A and 10B are a plan view and a bottom view, respectively, showing the semiconductor package shown in FIG. 9. FIG. 11 is a side sectional view showing a semiconductor package according to another exemplary embodiment in the present disclosure. 12A and 12B are cross-sectional views illustrating a process of mounting the semiconductor package shown in FIG. 11. FIG. 13 is a side sectional view showing a semiconductor package according to another exemplary embodiment in the present disclosure.

Claims (20)

A semiconductor package includes: a semiconductor wafer having a connection pad; a connection member having a first surface on which the semiconductor wafer is disposed and a second surface opposite to the first surface, and including an insulating member and formed on the A redistribution layer electrically connected to the connection pad in the insulating member; an encapsulation body disposed on the first surface of the connection member and encapsulating the semiconductor wafer; and a barrier layer disposed on the The second surface of the connection member includes an organic layer containing fluorine. The semiconductor package according to item 1 of the scope of patent application, wherein the organic layer includes at least one selected from the group consisting of CF ₄ , C ₄ F ₈ and fluoroalkylsilane. The semiconductor package according to item 1 of the scope of patent application, wherein the barrier layer further includes an inorganic layer disposed on the organic layer. The semiconductor package according to item 3 of the scope of patent application, wherein the inorganic layer includes at least one selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. The semiconductor package according to item 3 of the scope of patent application, wherein the thickness of the organic layer is in a range from 0.01 micrometer to 0.5 micrometer, and the thickness of the inorganic layer is in a range from 0.01 micrometer to 0.5 micrometer. The semiconductor package according to item 3 of the scope of patent application, wherein a thickness of the organic layer is greater than a thickness of the inorganic layer. The semiconductor package according to item 1 of the scope of patent application, further comprising an electrical connection structure disposed on the second surface of the connection member, wherein the connection member includes an under bump metallurgical (UBM) layer. The under bump metallurgical layer connects the electrical connection structure and the redistribution layer to each other. The semiconductor package according to item 7 of the scope of patent application, wherein the barrier layer is disposed in a region on the second surface of the connection member other than the electrical connection structure. The semiconductor package according to item 1 of the scope of patent application, wherein the thickness of the barrier layer is in a range from 0.02 μm to 1 μm. The semiconductor package according to item 7 of the scope of patent application, wherein the barrier layer covers a surface of the electrical connection structure. The semiconductor package according to item 10 of the scope of patent application, wherein the thickness of the barrier layer is in a range from 0.02 μm to 0.2 μm. The semiconductor package according to item 1 of the scope of patent application, wherein the insulating member is formed of a photosensitive organic material. The semiconductor package according to item 1 of the scope of patent application, further includes a core member disposed on the first surface of the connection member and having a cavity, and the semiconductor wafer is accommodated in the cavity. The semiconductor package according to item 13 of the patent application scope, wherein the core member has a wiring structure that connects an upper surface of the core member and a lower surface of the core member to each other and is electrically connected to the redistribution layer . The semiconductor package according to item 1 of the scope of patent application, wherein the organic layer further comprises rhenium. A semiconductor package includes: a semiconductor wafer having a connection pad; a connection member having a first surface on which the semiconductor wafer is disposed and a second surface opposite to the first surface, and including an insulating member disposed on the surface A redistribution layer electrically connected to the connection pad in the insulating member, and a metallurgical layer under the bump electrically connected to the redistribution layer and providing a connection region on the second surface; An electrical connection structure is disposed on the second surface of the connection member and is connected to a metallurgical layer under the bump; The connection region; and a multilayer barrier having an organic layer disposed on the second surface of the connection member and an inorganic layer disposed on the organic layer. The semiconductor package according to item 16 of the scope of patent application, wherein the organic layer is an organic layer containing fluorine, and the inorganic layer includes a group selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. At least one. The semiconductor package according to item 16 of the scope of patent application, wherein the oxygen permeability of the multilayer barrier is 0.01 cubic centimeter / square meter / day or less. The semiconductor package according to item 16 of the scope of patent application, wherein the multilayer barrier has a water vapor permeability of 0.1 g / m2 / day or less. The semiconductor package according to item 17 of the patent application scope, wherein the organic layer includes an organic material satisfying R-Si-F _x C _y OH, wherein R is an alkyl group, a fluoroalkyl group, an acrylic group, or a methacrylic group , Vinyl, epoxy, amine, or aniline.