TWI658554B - Fan-out semiconductor package module - Google Patents

Abstract

The invention provides a fan-out type semiconductor package module, including a fan-out type semiconductor package, including: a first interconnecting member having a through hole and a semiconductor wafer, arranged in the through hole, an encapsulation body, and covering the first interconnect At least part of the component and at least part of the semiconductor wafer, the second interconnection member is disposed on the first interconnection member and the semiconductor wafer, the third interconnection member is disposed on the encapsulation body, the first connection terminal is disposed on the first The two interconnecting members and the second connection terminal are disposed on the third interconnecting member; the first interconnecting member to the third interconnecting member respectively include a redistribution layer electrically connected to the semiconductor wafer connection pad; and installed on the fan The component package on the outgoing semiconductor package includes a wiring substrate connected to the second interconnection member via a first connection member and a plurality of mounting components mounted on the wiring substrate.

Description

Fan-out semiconductor package module [Cross-reference to related applications]

This application claims the priority of Korean Patent Application No. 10-2016-0078580, filed with the Korean Intellectual Property Office on June 23, 2016, and South Korea, which filed with the Korean Intellectual Property Office on July 29, 2016 The priority of Patent Application No. 10-2016-0097123, the disclosure content of each of the Korean patent applications mentioned herein is incorporated in its entirety for reference.

The present invention relates to a semiconductor package, and more particularly, to a fan-out type semiconductor package module in which a connection terminal can extend outside a configuration area of a semiconductor wafer.

Components are commonly installed in mobile devices, such as memory, fundamental frequency integrated circuits (ICs), radio frequency (RF) ICs (RFICs), power management integrated circuits (PMICs) , RF matching components, power terminal shunt group Components (power terminal bypass component) and the like. However, where such components are implemented in a separate module, the thickness and size of the module can be significantly larger.

In some modules, in order to solve this problem, components are installed on the upper and lower surfaces of the wiring substrate, a sub-wiring substrate is introduced, and an electronic device is formed on the main wiring substrate to mount the electronic device on the main board. Of pads. However, the IC mounted on the lower surface of the wiring substrate is limited in form and has reliability problems.

One aspect of the present disclosure can provide a miniature fan-out type semiconductor package module with improved functionality and improved reliability.

According to an aspect of the present disclosure, a micro fan-out type semiconductor package module can be provided. The wiring substrate is stacked on the fan-out type semiconductor package. Components are mounted in the wiring substrate. Face-up form configuration.

According to an aspect of the present disclosure, a fan-out semiconductor package module may include: a fan-out semiconductor package and a component package. The fan-out semiconductor package includes a first interconnection member having a through hole, a semiconductor wafer, and an encapsulation body. , A second interconnection member, a first connection terminal, and a second connection terminal. The semiconductor wafer is disposed in the through hole of the first interconnection member and has an active surface and a non-active surface opposite to the active surface, and a connection pad is disposed on the active surface. The encapsulation body covers at least part of the first interconnection member and At least part of the non-active surface of the semiconductor wafer, the second interconnection member is disposed on the first connection member and the active surface of the semiconductor wafer, the first connection terminal is disposed on the second interconnection member, and the second connection terminal is disposed on the package. On the body. The first interconnecting member and the second interconnecting member each include: a redistribution layer electrically connected to a connection pad of the semiconductor wafer, and the component package includes a second interconnecting member configured to be connected to the second interconnector via the first connection terminal. A wiring substrate connecting the members and at least one member arranged on the wiring substrate.

100‧‧‧Semiconductor Package

100A, 100B, 100C, 2100‧‧‧fan-out semiconductor packages

110, 110C‧‧‧First interconnecting component

110H‧‧‧through hole

111‧‧‧ Insulation

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧Third insulation layer

112a‧‧‧First redistribution layer

112b‧‧‧Second redistribution layer

112c‧‧‧ Third wiring layer

113, 113a, 113b, 113c, 133, 143, 213, 2143, 2243

120, 2120, 2220‧‧‧ semiconductor wafer

120C‧‧‧Semiconductor wafer

121, 1101, 2121, 2221‧‧‧ Ontology

122, 2122, 2222‧‧‧ connecting pad

123‧‧‧ passivation layer

130, 130C, 2130‧‧‧ Encapsulation bodies

140, 140C‧‧‧Second interconnecting component

141, 141a, 141b, 211, 2141, 2241‧‧‧ insulation

142, 152, 212, 2142‧‧‧ Redistribution layers

145, 155, 215, 215a‧‧‧ metal layer under bump

150, 150B, 150C

151‧‧‧Insulation

152P‧‧‧Connection terminal pad

160, 160B, 160C‧‧‧First connection terminal

170, 170B, 170C‧‧‧Second connection terminal

180, 180B, 180C‧‧‧Third connection terminal

200A, 200B, 200C‧‧‧component package

210, 210B, 210C‧‧‧ wiring substrate

210Ca‧‧‧First wiring substrate

210Cb‧‧‧Second wiring board

211A‧‧‧First insulation layer

211B‧‧‧Second insulation layer

211C‧‧‧Third insulation layer

218, 2280‧‧‧ underfill resin

220, 220B, 220C‧‧‧ components

221‧‧‧Memory Chip

222, 223‧‧‧ Passive components

230, 230C, 2150, 2223, 2250‧‧‧

300A, 300B, 300C‧‧‧fan-out semiconductor package module

500, 1010, 1110, 2500‧‧‧ motherboards

1000‧‧‧ electronic device

1020‧‧‧Chip-related components

1030‧‧‧Network related components

1040‧‧‧Other components

1050, 1130‧‧‧ Camera Module

1060‧‧‧antenna

1070‧‧‧ display device

1080‧‧‧ battery

1090‧‧‧Signal cable

1100‧‧‧Smartphone

2140, 2240‧‧‧ interconnecting components

2251‧‧‧ opening

2270‧‧‧Solder Ball

2200‧‧‧fan-in semiconductor package

2242‧‧‧Wiring pattern

2243h‧‧‧through hole

2290‧‧‧Molding material

2301, 2302‧‧‧ interposer

A‧‧‧Area

I-I'‧‧‧ hatch

P-1, P-2, P-3, P-4, P-5, P-6‧‧‧electrical pathways

R1‧‧‧fan-in area

R2‧‧‧fan-out area

The embodiments are exemplified below and described in detail in conjunction with the accompanying drawings. The above and other aspects, features, and advantages of the present invention will be more obvious and understandable. In the attached drawings: FIG. 1 is a diagram illustrating an electronic device system. A block schematic diagram of an example; FIG. 2 is a perspective schematic diagram illustrating an example of an electronic device; and FIGS. 3A and 3B are cross-sectional schematic diagrams illustrating a state of a fan-in semiconductor package before and after packaging.

4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package; FIG. 5 is a cross-sectional schematic view illustrating a situation in which a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device; A cross-sectional view of a fan-in type semiconductor package embedded in an interposer and finally mounted on a main board of an electronic device; FIG. 7 is a cross-sectional view illustrating a fan-out type semiconductor package; FIG. 8 is a view illustrating a fan-out type semiconductor package mounted on Love on the motherboard of an electronic device 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package module; FIG. 10 is a plane taken along a section line II ′ of the fan-out type semiconductor package module shown in FIG. 9 11 is a schematic plan view taken along the section line II ′ of the fan-out semiconductor package module shown in FIG. 9; FIG. 12 is a plan view of the fan-out semiconductor package module shown in FIG. 9 viewed from the direction a; 13 is a schematic plan view of the fan-out semiconductor package module of FIG. 9 viewed from the direction b; FIG. 14 is a schematic plan view of the fan-out semiconductor package module of FIG. 9 viewed from the direction c; An enlarged cross-sectional view; FIG. 16 is an enlarged cross-sectional view of area A modified in FIG. 9; FIG. 17 is an enlarged cross-sectional view of area A modified in FIG. 9; FIG. 18 is a modified view of FIG. An enlarged cross-sectional view of region A; FIG. 19 is a cross-sectional view illustrating another example of a fan-out semiconductor package module; FIG. 20 is an enlarged cross-sectional view of region B in FIG. 19; A schematic cross-sectional view of another example of a semiconductor package module; and FIG. 22 is a diagram of FIG. 21 C is an enlarged sectional view of the region.

Hereinafter, exemplary embodiments in the present invention will be explained with reference to the drawings. In the drawings, the shape, size, and the like of each component may be exaggerated or omitted for clarity.

The term "exemplary embodiment" used herein does not refer to the same exemplary embodiment, but is provided to emphasize a specific feature or characteristic that is different from a specific feature or characteristic of another exemplary embodiment. However, the exemplary embodiments provided herein are considered to be capable of being implemented by combining each other in whole or in part. For example, even if an element set forth in a particular exemplary embodiment is not set forth in another exemplary embodiment, the element is not described unless an opposite or contradictory description is provided in another exemplary embodiment. It can also be understood as a description related to another exemplary embodiment.

The meaning of "connection" between a component and another component in the description includes an indirect connection via a third component and a direct connection between two components. In addition, "electrical connection" means the concept of physical connection and physical disconnection. It should be understood that when an element is referred to by "first" and "second", the element is not limited thereby. The use of "first" and "second" may only be used for the purpose of distinguishing the elements from other elements, and may not limit the order or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the patentable scope set forth herein. Likewise, the second element may be referred to as a first element.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Inventions, anyone with ordinary knowledge in the technical field to which they belong can make minor changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the attached patent application as follows: quasi.

Herein, the upper part, the lower part, the upper side, the lower side, the upper surface, the lower surface, and the like are illustrated in the attached drawings. For example, the first interconnection member may be configured higher than the horizontal height of the redistribution layer. However, the scope of this application patent is not limited to this. In addition, the vertical direction refers to the above upward and downward directions, and the horizontal direction refers to the directions perpendicular to the above upward and downward directions. In this case, the vertical cross-section means a case of being taken along a plane in the vertical direction, and an example of the vertical cross-section may be a cross-sectional view shown in a drawing. In addition, the horizontal cross section refers to a case of being taken along a plane in the horizontal direction, and an example of the horizontal cross section may be a plan view shown in a drawing.

The terminology used herein is for the purpose of illustrating the exemplary embodiments only and not limiting the present invention. In this case, the singular includes the plural unless otherwise explained in context.

Electronic device

FIG. 1 is a block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, a motherboard 1010 can be accommodated in the electronic device 1000. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, and similar components that are physically or electrically connected to the motherboard 1010. These components can be connected to other components described below to form various signal lines 1090.

The chip-related component 1020 may include a memory chip, such as a volatile memory Memory (such as dynamic random access memory (DRAM)), non-volatile memory (such as read only memory (ROM)), flash memory, or the like; application processor Chips, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor (cryptographic processor ), Microprocessor, microcontroller or similar; and logic chips, such as analog-to-digital converter (ADC), application-specific integrated circuit (ASIC) or similar By. However, the wafer-related component 1020 is not limited thereto, and may include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related component 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, etc.), worldwide interoperable microwave access (worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access + (HSPA +), high speed downlink packet access + (HSDPA +), high speed uplink packet access + (HSUPA +), enhanced data GSM environment (EDGE ), Global system for mobile communications, GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement, 4G agreement, 5G agreement, and any other wireless and wired agreement specified after the above agreement. However, the network related component 1030 is not limited thereto, and may include various other wireless standards or protocols or wired standards or protocols. In addition, the network related components 1030 may be combined with each other together with the chip related components 1020 described above.

Other components 1040 may include a high-frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, and a low temperature co-fired ceramic; (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), combinations thereof, or the like. However, the other components 1040 are not limited thereto, and may include passive components and the like used for various other purposes. In addition, other components 1040 may be combined with each other together with the chip-related component 1020 or the network-related component 1030 described above.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may be physically connected or electrically connected to the motherboard 1010 or may not be physically connected or electrically connected to the motherboard 1010. The other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), Compass (Shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage unit (e.g. hard drive) (not shown), compact disk (CD) ) Drive (not shown), digital versatile disk (DVD) drive (not shown), etc. However, the other components are not limited thereto, but may include other components for various purposes depending on the type of the electronic device 1000 or the like.

The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, and a notebook. Personal computer (laptop PC), portable netbook PC, television, video game machine, smart watch, car component, or the like. However, the electronic device 1000 is not limited thereto, and may be any other electronic device that processes data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, the semiconductor package may be used for various purposes in the electronic device 1000 described above. For example, the motherboard 1110 can be accommodated in the body 1101 of the smart phone 1100, and various electronic components 1120 can be physically connected to or electrically connected to the motherboard 1110. In addition, other components (such as the camera module 1130) that can be physically connected or electrically connected to the main board 1110 or not or not electrically connected to the main board 1110 can be housed in the body 1101. Some electronic components in the electronic component 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor between chip related components, but is not limited thereto. The electronic device need not be It is limited to the smart phone 1100, but may be other electronic devices as described above.

Semiconductor package

Generally speaking, a plurality of different circuits can be integrated in a semiconductor wafer. However, the semiconductor wafer itself cannot serve as a completed semiconductor product, and may be damaged due to external physical or chemical influences. Therefore, the semiconductor wafer cannot be used alone, but can be packaged in an electronic device or the like and used in a packaged state in the electronic device or the like.

Here, a semiconductor package is required due to a difference in circuit width in terms of electrical connection between the semiconductor wafer and the motherboard of the electronic device. In detail, the size of the connection pads of the semiconductor wafer and the spacing between the connection pads of the semiconductor wafer are extremely fine, but the size of the component rmounting pads of the motherboard used in electronic devices and the size of the component mounting pads of the motherboard The interval is significantly larger than the size and interval of the connection pads of the semiconductor wafer. Therefore, it may be difficult to mount a semiconductor wafer directly on the motherboard, and a packaging technology for buffering a difference in circuit width between the semiconductor wafer and the motherboard may be required.

Depending on the structure and purpose of the semiconductor package, the semiconductor package manufactured by the packaging technology can be classified into a fan-in semiconductor package or a fan-out semiconductor package.

The fan-in type semiconductor package and the fan-out type semiconductor package will be explained in more detail below with reference to the drawings.

Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after packaging.

FIG. 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state. The semiconductor wafer 2220 includes a body 2221, a connection pad 2222, and a protective layer 2223. The body 2221 includes silicon (Si ), Germanium (Ge), gallium arsenide (GaAs), etc .; the connection pad 2222 is formed on one surface of the body 2221 and includes a conductive material such as aluminum (Al); the protective layer 2223 is, for example, an oxide film, A nitride film or the like, a protective layer 2223 is formed on one surface of the body 2221 and covers at least a part of the connection pad 2222. In this case, since the connection pad 2222 is significantly small, it is difficult to mount the integrated circuit on an intermediate level printed circuit board (PCB) and a motherboard or the like of an electronic device.

Therefore, the interconnection member 2240 may be formed on the semiconductor wafer 2220 according to its size to redistribute the connection pads 2222. The interconnection member 2240 may be formed by the following steps: forming an insulating layer 2241 on the semiconductor wafer 2220 using an insulating material such as a photoimagable dielectric (PID) resin; forming a through hole 2243h of the open connection pad 2222; and then A wiring pattern 2242 and a through hole 2243 are formed. Next, a protective layer 2250 may be formed to protect the interconnection member 2240, an opening 2251 may be formed, and a metal layer 2260 under the bump may be formed. That is, the fan-in semiconductor package 2200 including, for example, the semiconductor wafer 2220, the interconnect member 2240, the protective layer 2250, and the under bump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a packaging form in which all connection pads such as input / output (I / O) terminals of the semiconductor wafer are arranged in the semiconductor wafer, and Can have excellent electrical characteristics and can be produced at low cost. Therefore, many components mounted in a smart phone have been manufactured in the form of a fan-in semiconductor package. In detail, many components installed in a smart phone have been developed to implement fast signal transmission while having a small size.

However, since all the input / output terminals need to be arranged inside the semiconductor wafer in the fan-in semiconductor package, the fan-in semiconductor package has a relatively large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of input / output terminals or a semiconductor wafer having a small size. In addition, due to the above disadvantages, a fan-in semiconductor package cannot be directly mounted and used on a motherboard of an electronic device. Here, even if the size of the input / output terminals of the semiconductor wafer and the interval between the input / output terminals of the semiconductor wafer are increased by the rewiring process, in this case, the size of the input / output terminals of the semiconductor wafer and the semiconductor The interval between the input / output terminals of the chip may still not be enough for the fan-in semiconductor package to be directly mounted on the motherboard of the electronic device.

5 is a schematic cross-sectional view illustrating a case where a fan-in semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a situation where a fan-in semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawings, in a fan-in type semiconductor package 2200, a connection pad 2222 (that is, an input / output terminal) of a semiconductor wafer 2220 may pass through an interposer substrate 2301 Redistribution again, and in a state where the fan-in semiconductor package 2200 is mounted on the interposer substrate 2301, the fan-in semiconductor package 2200 can finally be mounted on the motherboard 2500 of the electronic device. In this case, the solder balls 2270 and the like may be fixed by an underfill resin 2280 or the like, and the outer surface of the semiconductor wafer 2220 may be covered with a molding material 2290 or the like. The fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pads 2222 (ie, input / output terminals) of the semiconductor wafer 2220 may be in a state where the fan-in semiconductor package 2200 is embedded in the interposer substrate 2302. The interposer substrate 2302 is redistributed again, and the fan-in semiconductor package 2200 can be finally mounted on the motherboard 2500 of the electronic device.

As described above, it may be difficult to mount and use a fan-in semiconductor package directly on a motherboard of an electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate interposer substrate and then mounted on the motherboard of the electronic device through a packaging process; or, the fan-in semiconductor package can be embedded in the interposer substrate in the fan-in semiconductor package. Installed and used on the motherboard of the electronic device in the state.

Fan-out semiconductor package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out type semiconductor package 2100, for example, the outer surface of the semiconductor wafer 2120 is protected by the encapsulation body 2130, and the connection pad 2122 of the semiconductor wafer 2120 may be formed on the semiconductor wafer 2120 by the interconnection member 2140. Redistribution outside. In this case, a protective layer 2150 may be further formed on the interconnection member 2140, and an under bump metal layer may be further formed in the opening of the protective layer 2150. 2160. The solder ball 2170 may be further formed on the under bump metal layer 2160. The semiconductor wafer 2120 may be an integrated circuit including a body 2121, a connection pad 2122, a protective layer (not shown in the drawings), and the like. The interconnection member 2140 may include an insulating layer 2141, a redistribution layer 2142 formed on the insulating layer 2141, and a through hole 2143 for electrically connecting the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which input / output terminals of a semiconductor wafer are redistributed and arranged toward the outside of the semiconductor wafer via a connection member formed on the semiconductor wafer. As described above, in a fan-in type semiconductor package, all input / output terminals of a semiconductor wafer need to be arranged in the semiconductor wafer. Therefore, when the size of a semiconductor wafer is reduced, it is necessary to reduce the size and pitch of the balls, thereby making it impossible to use a standardized ball layout in a fan-in semiconductor package. On the other hand, the fan-out type semiconductor package has a form in which input / output terminals of a semiconductor wafer are redistributed and disposed outside the semiconductor wafer by an interconnect member formed on the semiconductor wafer, as described above . Therefore, even when the size of the semiconductor wafer is reduced, the standardized ball layout can still be used in a fan-out semiconductor package, so that the fan-out semiconductor package can be mounted on the motherboard of an electronic device without using a separate interposer substrate. As described below.

8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a motherboard of an electronic device.

Referring to the drawings, the fan-out type semiconductor package 2100 may be mounted on a motherboard 2500 of an electronic device via a solder ball 2170 or the like. That is, as described above, the fan-out type semiconductor package 2100 includes the interconnection member 2140 formed on the semiconductor device. The body wafer 2120 can be redistributed to the fan-out area outside the area of the semiconductor wafer 2120, so that the standardized ball layout can actually be used in the fan-out semiconductor package 2100. Therefore, the fan-out type semiconductor package 2100 can be mounted on the motherboard 2500 of the electronic device without using a separate interposer or the like.

As described above, since a fan-out type semiconductor package can be mounted on a motherboard of an electronic device without using a separate interposer, the fan-out type semiconductor package can have a thickness smaller than that of a fan-in type semiconductor package using an interposer. Next implementation. Therefore, the fan-out type semiconductor package can be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal and electrical characteristics, which makes the fan-out semiconductor package particularly suitable for mobile products. Therefore, a fan-out type semiconductor package module can be implemented in a more compact form than a general stacked-type semiconductor package (POP) type using a printed circuit board (PCB), and the fan-out type Type semiconductor packages can solve problems caused by the occurrence of a warpage phenomenon.

Meanwhile, a fan-out type semiconductor package means a packaging technology, as described above, for mounting a semiconductor wafer on a motherboard or the like of an electronic device, and the semiconductor wafer is protected from external impact, and interacts with a substrate such as an interposer or A similar printed circuit board (PCB) is different in concept. The PCB has a different specification, purpose, and the like from a fan-out semiconductor package, and is embedded in a fan-in semiconductor package.

Semiconductor package module

FIG. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package module.

FIG. 10 is a schematic plan view taken along the line I-I 'of the fan-out semiconductor package module shown in FIG. 9.

11 is a schematic plan view taken along a line I-I 'of the fan-out semiconductor package module shown in FIG. 9.

Referring to the drawings, a fan-out type semiconductor package module 300A according to an exemplary embodiment of the present invention may include a fan-out type semiconductor package 100A and a component package 200A disposed on the fan-out type semiconductor package 100A. The fan-out type semiconductor package 100A may include a first interconnection member 110, a semiconductor wafer 120, an encapsulation body 130, a second interconnection member 140, a third interconnection member 150, a first connection terminal 160, and a second connection terminal 170. The first interconnecting member 110 has a through-hole 110H, the semiconductor wafer 120 is disposed in the through-hole 110H and has an active surface on which the connection pad 122 is disposed and an inactive surface opposite to the active surface, and the encapsulation body 130 covers the first At least part of the inactive surfaces of the interconnection member 110 and the semiconductor wafer 120, the second interconnection member 140 is disposed on the active surfaces of the first interconnection member 110 and the semiconductor wafer 120, and the third interconnection member 150 is disposed on the encapsulation body On 130, the first connection terminal 160 is disposed on and connected to the second interconnection member 140, and the second connection terminal 170 is connected to the third interconnection member 150 and connected to the third interconnection member 150. The component package 200A may include a wiring substrate 210, a plurality of components 220 disposed on the wiring substrate 210, and a protective layer 230 that protects the plurality of components 220. The wiring substrate 210 is disposed above the second interconnection member 140 and is connected through the first connection. The terminal 160 is connected to the second interconnection member 140.

Implement components used in current mobile devices in separate modules, such as memory, baseband integrated circuits, radio frequency (RF) integrated circuits (RFICs), and power management integrated circuits integrated circuits (PMICs), RF matching components, power terminal bypass components, and the like. In this case, the thickness and size of the module are significantly larger. In some modules, in order to solve this problem, components are installed on the upper and lower surfaces of the wiring substrate, a sub wiring substrate is introduced, and a pad for mounting an electronic device on the motherboard is formed on the sub wiring substrate. However, the form of the IC mounted on the lower surface of the wiring substrate is limited and has a problem of reliability. Therefore, there is a need for a novel miniature module with improved functionality and improved reliability.

The fan-out type semiconductor package module 300A according to an exemplary embodiment may have a structure in which a fan-out type semiconductor package 100A is introduced, and a main semiconductor chip 120 (eg, IC) is mounted in the fan-out type semiconductor package 100A. Various components can be installed in the component package 200A, and the component package 200A is stacked on the fan-out semiconductor package 100A. Therefore, a micro fan-out type semiconductor package module with improved functionality and improved reliability can be provided. In this case, the semiconductor wafer 120 may be configured to face up, and the semiconductor wafer 120 may be electrically connected to the wiring substrate via the second interconnection member 140 and the first connection terminal 160 connected to the second interconnection member 140. 210 and the component 220 of the component package 200A to generate a very short signal transmission path and the like. In the fan-out type semiconductor package 100A, the redistribution layer 112a and the redistribution layer formed in the first interconnection member 110 are formed. The wire layer 112b and the like are introduced around the semiconductor wafer 120 to introduce the second connection terminal 170 electrically connected to the third interconnection member 150 below the encapsulation body 130, so that the fan-out type semiconductor package The module 300A can be stably mounted on the motherboard 500 of the electronic device.

The respective components included in the fan-out type semiconductor package module according to the exemplary embodiment will be explained in further detail below.

The first interconnection member 110 can maintain the rigidity of the fan-out type semiconductor package 100A and can be used to ensure the thickness uniformity of the encapsulation body 130. In addition, the first interconnection member 110 may provide a routing region for forming the redistribution layer 112a and the redistribution layer 112b, thereby reducing the number of the second interconnection members 140 and solving the formation of the second interconnection members 140. Defects in the manufacturing process. The first interconnection member 110 may have a through hole 110H. The semiconductor wafer 120 may be disposed in the through hole 110H such that the through hole 110 and the first interconnection member 110 are spaced apart from each other by a predetermined distance. That is, the first interconnection member 110 may surround a side surface of the semiconductor wafer 120. However, the form of the first interconnection member 110 is not limited thereto, and may be variously modified to have other forms. The first interconnection member 110 may include an insulating layer 111, a redistribution layer 112a, a redistribution layer 112b, and a through hole 113. The redistribution layer 112a and the redistribution layer 112b are respectively disposed on opposite surfaces of the insulating layer 111, and the through hole 113 penetrates the insulation. The layer 111 electrically connects the redistribution layer 112a and the redistribution layer 112b, which are respectively disposed on the opposite surfaces of the insulating layer 111.

An insulating material may be used as a material of the insulating layer 111. In this case, the insulating material may be: a thermosetting resin (for example, epoxy resin), a thermoplastic resin (for example, fluorene imine resin), having, for example, immersion in the thermosetting resin and the heat Resins for reinforcing materials such as glass fibers and / or inorganic fillers in plastic resins, such as prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (Bismaleimide Triazine, BT) or similar. Alternatively, a photosensitive imaging dielectric (PID) resin may be used as the insulating material.

The redistribution layer 112a and the redistribution layer 112b may be used as a redistribution pattern, and each of the redistribution layer 112a and the redistribution layer 112b may be a conductive material, such as copper (Cu), aluminum (Al), and silver (Ag). , Tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution layer 112a and the redistribution layer 112b may have various functions depending on the design of the corresponding layers. For example, the redistribution layer 112a and the redistribution layer 112b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, the redistribution layer 112a and the redistribution layer 112b may include via pads, connection terminal pads, and the like.

The through hole 113 can electrically connect the redistribution layer 112 a and the redistribution layer 112 b formed on different layers to each other, thereby forming an electrical path in the first interconnection member 110. The material of each of the through holes 113 may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium ( Ti) or a conductive material such as an alloy thereof. The conductive material may completely fill each of the through holes 113, or the conductive material may be formed along the hole wall of each through hole, which is different from that shown in the drawings. In addition, each of the through holes 113 may have any conventional cross-sectional shape, such as tapered, cylindrical, and the like.

The semiconductor wafer 120 may be an integrated circuit in a bare state, and is configured to integrate hundreds to millions or more components in a single wafer. For example, the integrated circuit may be an application processor chip, such as a central processing unit (such as a central processing unit), a graphics processor (such as a graphics processing unit), a digital signal processor, a cryptographic processor, a microprocessor, Microcontroller, etc., but not limited to this.

The semiconductor wafer 120 may include a body 121, a connection pad 122 formed on a surface of the body 121, and a passivation layer 123 formed on the body 121 and covering a part of the connection pad 122. The body 121 may be formed on a substrate of an active wafer, for example. In this case, the basic material of the body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The connection pad 122 can electrically connect the semiconductor wafer 120 to other components, and each of the connection pad 122 materials can be a conductive material, such as aluminum (Al) or the like. The connection pads 122 may be redistributed by the first interconnection member 110, the second interconnection member 140, the third interconnection member 150, the wiring substrate 210, and the like. The surface of the semiconductor wafer 120 on which the connection pad 122 is disposed may be an active surface, and the surface of the semiconductor wafer 120 opposite to the active surface may be an inactive surface. The semiconductor wafer 120 may be configured to face up as an example. That is, the active surface on which the connection pad 122 is disposed may be disposed in an upward direction in which the first interconnection member 110 is disposed. The passivation layer 123 can be used to protect the body 121 from external impact, and the passivation layer 123 can be, for example, an oxide film formed of silicon monoxide (SiO), etc., a nitride film formed of silicon nitride (SiN), or the like , Or a double layer including an oxide layer and a nitride layer. In addition, a silicon oxide (SiO) or the like The edge film and the like (not shown in the figure) may be further disposed between the body 121 and the connection pad 122 or between the body 121 and the passivation layer 123.

The encapsulation body 130 may be used to protect the first interconnection member 110 and / or the semiconductor wafer 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but the form may be that the encapsulation body 130 surrounds at least a portion of the first interconnection member 110 and / or at least a portion of the semiconductor wafer 120. For example, the encapsulation body 130 may cover the lower surfaces of the first interconnecting member 110 and the semiconductor wafer 120 and fill the gap between the wall surface of the through hole 110H and the side surface of the semiconductor wafer 120. At the same time, the encapsulation body 130 can fill the through hole 110H as an adhesive, and reduce buckling of the semiconductor wafer 120 depending on its material.

The material of the encapsulation body 130 is not particularly limited, but may be, for example, an insulating material. In more detail, the material of the encapsulation body 130 may be, for example, ABF or the like, which includes an inorganic filler and an insulating resin, but does not include glass cloth. In the case where a material including the inorganic filler and an insulating resin but not containing glass cloth is used as the material of the encapsulation body 130, problems such as voids or delamination can be solved. Meanwhile, the inorganic filler may be a conventional inorganic filler, and the insulating resin may be a conventional epoxy resin or the like.

The second interconnection member 140 may be used to substantially redistribute the connection pads 122 of the semiconductor wafer 120. The second interconnection member 140 can be used to redistribute tens to hundreds of connection pads 122 having various functions. The second interconnection member 140 may be disposed above the first interconnection member 110 and the semiconductor wafer 120. The second interconnection member 140 may include an insulating layer 141, a redistribution layer 142, and a through hole 143. The redistribution layer 142 is disposed on the insulating layer 141, the through hole 143 penetrates the insulating layer 141 and connects the redistribution layers 142 to each other.

An insulating material may be used as a material of the insulating layer 141. In this case, a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin may be used as the insulating material. In this case, the insulating layer 141 may have a smaller thickness, and the fine pitch of the through holes 143 may be more easily achieved. When necessary, when the insulating layer 141 is a plurality of layers, the materials of the insulating layers 141 may be the same as or different from each other. When the insulating layer 141 is a plurality of layers, the insulating layers 141 may be integrated with each other according to a manufacturing process, so that the boundaries between the insulating layers 141 may be inconspicuous.

The redistribution layer 142 may be used to substantially redistribute the connection pads 122. The material of each of the redistribution layers 142 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Titanium (Ti), or an alloy thereof. Depending on the design of the layer corresponding to the redistribution layer 142, the redistribution layer 142 may have various functions. For example, the redistribution layer 142 may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, the redistribution layer 142 may include a via pad, a connection terminal pad, and the like.

The through-holes 143 can electrically connect the redistribution layers 142, the connection pads 122, or the like formed on different layers to each other, thereby generating an electrical path in the fan-out semiconductor package 100A. The material of each of the through holes 143 may be, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti ) Or its alloy and other conductive materials. The conductive material may be completely filled in the through holes 143, or the conductive material may be formed along the wall surface of each of the through holes. In addition, each of the through holes 143 may have any conventional shape, such as a tapered shape, a cylindrical shape, or the like.

In the case shown in the drawings, the second interconnection member 140 has a redistribution layer 142 and a through hole 143, but the second interconnection member 140 is not limited thereto. That is, the second interconnection member 140 may include a large number of insulating layers depending on its design, and thus includes a large number of distribution layers and vias. That is, the second interconnection member 140 may be formed of a plurality of layers.

The third interconnection member 150 may be used to redistribute the connection pads 122 of the semiconductor wafer 120 and provide mounting pads for mounting the fan-out type semiconductor package module 300A on the motherboard 500. The third interconnection member 150 may include an insulating layer 151 and a redistribution layer 152. The third interconnection member 150 may penetrate the encapsulation body 130 to connect to the redistribution layer 112 b of the first interconnection member 110 via the through hole 133.

The material of the insulating layer 151 is not particularly limited, but may be a photosensitive insulating material such as a photosensitive imaging dielectric (PID) resin. Alternatively, a solder resist may be used as a material of the insulating layer 151. Alternatively, an insulating material containing an inorganic filler and an insulating resin but not containing glass cloth may be used as the material of the insulating layer 151, such as ABF or the like. When necessary, when the insulating layer 151 is a plurality of layers, the materials of the insulating layers 151 may be the same as each other, and may also be different from each other. When the insulating layer 151 is a plurality of layers, the insulating layers 151 may be integrated with each other according to a manufacturing process, so that the boundaries between the insulating layers may be inconspicuous.

The material of each of the redistribution layers 152 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Titanium (Ti), or an alloy thereof. Depending on the design of the layers corresponding to the redistribution layer 152, the redistribution layer 142 may have various functions. For example, the redistribution layer 152 may include a ground pattern, a power pattern, a signal pattern, and the like. In addition, the redistribution layer 152 may include Including through-hole pads, connection terminal pads, etc. When the insulating layer 151 is a plurality of layers, the redistribution layer 152 may also be a plurality of layers, and the redistribution layers 152 formed on different layers may be electrically connected to each other through through holes or the like penetrating the insulating layer 151.

The first connection terminal 160 may be used to connect the fan-out semiconductor package 100A and the component package 200A to each other. The second connection terminal 160 may be connected to a portion of the redistribution layer 142 exposed by an opening formed in the third interconnection member 140. The first connection terminal 160 may be, for example, a solder ball, a copper cored ball, a copper pillar, or the like, but is not limited thereto. The size of the first connection terminal 160 may be smaller than that of the second connection terminal 170.

The second connection terminal 170 may be used to connect the fan-out type semiconductor package module 300A to the motherboard 500 or the like of the electronic device. The second connection terminal 170 may be connected to a portion of the redistribution layer 152 exposed by an opening formed in the third interconnection member 150. Each of the second connection terminals 170 may be formed of a conductive material such as solder. However, this is merely an example, and the material of each of the second connection terminals 170 is not limited thereto. The second connection terminal 170 may be a land, a solder ball, a pin, or the like. The second connection terminal 170 may form a multi-layer structure or a single-layer structure. When the second connection terminal 170 is formed into a multilayer structure, the second connection terminal 170 may include copper (Cu) pillars and solder. When the second connection terminal 170 forms a single-layer structure, the connection terminal 170 may include tin-silver solder or copper (Cu). However, this is merely an example, and the second connection terminal 170 is not limited thereto.

Although not shown in the drawings, if necessary, a metal layer may be further disposed on an inner sidewall of the through hole 110H of the first interconnection member 110. That is, there can also be metal The layer surrounds a side surface of the semiconductor wafer 120. The heat generated by the semiconductor wafer 120 can effectively dissipate heat above or below the fan-out semiconductor package 100A through the metal layer, and the metal layer can effectively block electromagnetic waves. In addition, when necessary, a plurality of semiconductor wafers may be arranged in the through-holes 110H of the first interconnecting member 110, and the number of the through-holes 110H of the first interconnecting member 110 may be multiple and the semiconductor wafers may be respectively arranged in the through-holes. in. In addition, separate passive components such as capacitors and inductors may be disposed in the through hole 110H together with the semiconductor wafer.

The wiring substrate 210 may be a conventional printed circuit board (PCB), such as an interposer. The wiring substrate 210 may include an insulating layer 211 and a redistribution layer 212 formed on the insulating layer 211. Although not shown in the drawings, different types of redistribution layers 212 may be formed in the insulating layer 211.

The insulating layer 211 may include an insulating material. In this case, the insulating material may be a thermosetting resin (for example, epoxy resin), a thermoplastic resin (for example, fluorene imine resin), and glass fibers having, for example, immersed in the thermosetting resin and the thermoplastic resin. And / or resins of reinforcing materials such as inorganic fillers, such as prepreg, Ajinomoto Build Up Film (ABF), FR-4, bismaleimide triazine (BT), and the like. Alternatively, a photosensitive imaging dielectric (PID) resin may be used as the insulating material.

The redistribution layer 212 may function as a redistribution pattern. The material of each of the redistribution layers 212 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Titanium (Ti), or an alloy thereof. Depending on the design of the layers corresponding to the redistribution layer 212, the redistribution layer 142 may have various functions. For example, the redistribution layer 212 may include a ground pattern, a power pattern, a signal pattern, and the like. Here, the signal pattern may include various signals other than a ground pattern, a power pattern, and the like, such as a data signal. In addition, the redistribution layer 212 may include a via pad, a connection terminal pad, and the like.

The component 220 may be a variety of different electronic components. For example, the component 220 may be various active components, passive components, or the like. In some cases, the chip component may be configured as a component 220, such as a memory chip and the like. That is, a specific kind of the component 220 is not particularly limited. The number of the components 220 is not particularly limited, and the plurality of components 220 may be configured in different forms.

A protection layer 230 may be used to protect the component 220 disposed on the wiring substrate 210, and the protection layer 230 may be a conventional metal cover in which the component 220 is housed or a molding material covering the component 220. Different from what is shown in the drawing. The material of the metal cover or the molding material is not particularly limited, but may be a material known to those having ordinary knowledge in this technical field.

FIG. 12 is a schematic plan view of the fan-out semiconductor package module of FIG. 9 viewed from the direction a.

FIG. 13 is a schematic plan view of the fan-out semiconductor package module of FIG. 9 viewed from the direction b.

FIG. 14 is a schematic plan view of the fan-out semiconductor package module of FIG. 9 viewed from the direction c.

Referring to the drawings, the connection terminal pads 212P exposed from the insulation layer 211 of the wiring substrate 210 and the insulation layer 141 of the second interconnection member 140 are exposed to the outside. The connection terminal pads 142P can be connected to each other through the first connection terminal 160. Therefore, the number, position, form, and the like of the connection terminal pads 212P of the wiring substrate 210 and the connection terminal pads 142P of the second interconnection member 140 may correspond to each other. In addition, a connection terminal pad 152P exposed from the insulating layer 151 of the redistribution layer 152 of the third interconnection member 150 may be connected to the second connection terminal 170. Therefore, the number, position, form, and the like of the connection terminal pads 152P of the third interconnection member 150 may correspond to the number, position, and form of the second connection terminal 170.

Meanwhile, when the arrangement area corresponding to the semiconductor wafer 120 is a fan-in area and the area surrounding the fan-in area is a fan-out area, the connection terminal pads 212P of the wiring substrate 210 and the connection terminal connection of the second interconnection member 140 are connected. The pad 142P may be disposed in both the fan-in area and the fan-out area to connect a plurality of input / output terminals to each other, but is not limited thereto. In addition, the connection terminal pads 152P of the third interconnection member 150 may be disposed only in the fan-out area or at a boundary between the fan-in area and the fan-out area. Therefore, the number of connection terminal pads 142P of the second interconnection member 140 connected to the first connection terminal 160 may be greater than the number of connection terminal pads 152P of the third interconnection member 150, but is not limited thereto. At the same time, various different surface mount technology (SMT) components (not shown in the drawings) can be configured in different forms in the fan-in area formed by the connection terminal pads 152P without the insulating layer 151, but are not limited thereto.

Meanwhile, the first connection terminal 160 may have a bump shape instead of a ball shape, and the connection terminal pad 212P of the wiring substrate 210 and the connection terminal pad 142P of the second interconnection member 140 may thus form a bump pad. Rather than a ball pad, and the bump pad has a smaller size than the ball pad. In this case, in areas without pads Power plane design is performed to ensure power integrity (PI).

FIG. 15 is a schematic enlarged sectional view of a region A in FIG. 9.

Referring to the drawings, at least one of the connection pad 122 and the second connection terminal 170 may be connected to each other by passing through the wiring substrate 210 and the electrical path P-1 of the first interconnection member 110. For example, at least one of the connection pads 122 of the semiconductor wafer 120 may be electrically connected to at least one of the second connection terminals 170, and traversing the second interconnection through the electrical path P-1 in order or in reverse order. The member 140, the first connection terminal 160, the wiring substrate 210, the first connection terminal 160, the second interconnection member 140, and the first interconnection member 110. The second connection terminal 170 connected to the electrical path P-1 may be disposed in the fan-in region R1, the fan-out region R2, or between the fan-in region R1 or the fan-out region R2. When the number of circuits is multiple, the multiple circuits can be arranged in the fan-in area R1 and the fan-out area R2.

When the connection pad 122 and the second connection terminal 170 are connected to each other through the wiring substrate 210 and the first interconnection member 110 through the electrical path P-1, both the wiring substrate 210 and the first interconnection member 110 are connected to each other. Any of them can be used for redistribution of the connection pads 122, and thus the second interconnection member 140 can be simplified. Therefore, problems occurring in the process of forming the second interconnection member 140, such as the yield of the semiconductor wafer 120, can be solved. For example, the connection pad 122 connected to the electrical path P-1 may be a power connection pad or a ground connection pad. In this case, when the redistribution layer 212a and the redistribution layer 212b of the wiring substrate 210 provided with the electrical path P-1 include a power supply pattern or a ground pattern, the The redistribution layer 212a and the redistribution layer 212b are used to redistribute the power connection pad or the ground connection pad. Therefore, the number of power supply patterns or ground patterns in the second interconnection member 140 can be significantly reduced. Therefore, the second interconnection member 140 can be simplified, and the remaining area can be used for another purpose.

In addition, since the connection pad 122 and the second connection terminal 170 are connected to each other by a meandering electrical path P-1, the stress transferred through the second connection terminal 170 can be resisted by the electrical path P-1. An offset makes it possible to improve the connection reliability of the through hole 143 and the like connected to the connection pad 122. In addition, since the semiconductor wafer 120 is configured to face up, even if the underfill process of the second connection terminal 170 is performed to improve the reliability when the semiconductor package module 300A is mounted on the motherboard of the electronic device, it is included in the underfill material. The chloride ion (Cl-) is difficult to corrode the connection pad 122 of the semiconductor wafer 120.

Meanwhile, the second interconnection member 140 may include a plurality of insulating layers 141a and 141b. The plurality of insulating layers 141a and 141b may include the same insulating material or different insulating materials. An opening exposing at least a part of the pattern may be formed in the upper insulating layer 141b as a connection terminal pad in the redistribution layer 142, and a lower bump metal layer 145 may be formed in the opening. The wiring substrate 210 may include a plurality of insulation layers 211a, 211b, and 211c, a plurality of redistribution layers 212a, a redistribution layer 212b, and a redistribution layer 212c, a plurality of through holes 213a and 213b, and a plurality of insulation The layers 211a, 211b, and 211c may include the same insulating material or different insulating materials. An opening exposing at least a part of the pattern may be formed in the lower insulating layer 211a as a connection terminal pad in the redistribution layer 212a, and a bump may be formed in the opening Lower metal layer 215. An opening exposing at least a part of the pattern may be formed in the third interconnection member 150 as a connection terminal pad in the redistribution layer 152, and an under bump metal layer 155 may be formed in the opening.

FIG. 16 is a schematic enlarged cross-sectional view of the modified area A in FIG. 9.

Referring to the drawings, the third interconnection member 150 may be omitted. That is, the second connection terminal 170 may be directly disposed on the redistribution layer 112 b of the first interconnection member 110, and the second connection terminal 170 may utilize a metal layer under the bump formed in the opening in the lower surface of the encapsulation body 130. 135 is connected to the redistribution layer 112b. Therefore, the connection pads 122 can be redistributed to the fan-out area via the electrical path P-2. If necessary, an underfill resin 401 may be formed between the second interconnection member 140 and the wiring substrate 210 to surround the first connection terminal 160. Therefore, the reliability of the first connection terminal 160 can be increased. Other configurations may overlap with the above, so descriptions are omitted.

FIG. 17 is an enlarged cross-sectional view of the modified region A in FIG. 9.

Referring to the drawings, the first interconnection member 110 may include a first insulation layer 111a, a first redistribution layer 112a, a second redistribution layer 112b, a second insulation layer 111b, and a third redistribution layer 112c. The layer 111a contacts the second interconnection member 140, the first redistribution layer 112a contacts the second interconnection member 140 and is embedded in the first insulation layer 111a, and the second redistribution layer 112b is disposed on the other surface of the first insulation layer 111a And the other surface is opposite to the surface having the first redistribution layer 112a embedded therein, the second insulating layer 111b is disposed on the first insulating layer 111a and covers the second redistribution layer 112b, and the third redistribution layer 112c is disposed On the second insulating layer 111b. Since the first interconnection member 110 may include a large number of redistribution layers 112a, redistribution layers 112b, and redistributions Layer 112c, so the second interconnection member 140 can be further simplified. Therefore, a decrease in the yield due to a defect occurring in a process of forming the second interconnection member 140 can be improved. Since the first redistribution layer 112a is embedded in the first insulation layer 111a, the insulation distance of the insulation layer 141a of the second interconnection member 140 may be relatively constant. The first redistribution layer 112a may be recessed in the insulating layer 111, so that there is a step between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Therefore, the phenomenon that the encapsulation body 130 penetrates into the first redistribution layer 112a can be prevented. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to each other through the first through hole 113a and the second through hole 113b, and penetrate the first insulating layer 111a and the second Insulating layer 111b. At least one of the connection pads 122 may be redistributed to the fan-in area and / or the fan-out area via the electrical path P-3 passing through the first interconnection member 110.

Meanwhile, an upper surface of the first redistribution layer 112 a of the first interconnecting member 110 may be disposed lower than a horizontal height of an upper surface of the connection pad 122 of the semiconductor wafer 120. In addition, a distance between the redistribution layer 142 of the second interconnection member 140 and the first redistribution layer 112 a of the first interconnection member 110 may be greater than a connection between the redistribution layer 142 of the second interconnection member 140 and the semiconductor wafer 120. The distance between the pads 122. Here, the first redistribution layer 112a may be recessed in the first insulating layer 111a. The second redistribution layer 112 b of the first interconnection member 110 may be disposed at a horizontal height between the active surface and the non-active surface of the semiconductor wafer 120. The thickness of the formed first interconnection member 110 may correspond to the thickness of the semiconductor wafer 120. Therefore, the second redistribution layer 112 b formed in the first interconnection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120.

In addition, the thickness of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first interconnection member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnection member 140. Since the thickness of the first interconnection member 110 may be equal to or larger than the thickness of the semiconductor wafer 120, depending on the specifications of the first interconnection member 110, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may have a relatively large size. On the other hand, the redistribution layer 142 formed on the second interconnection member 140 may have a relatively small thickness. Other configurations may overlap with those described above, so descriptions are omitted.

FIG. 18 is a schematic enlarged cross-sectional view of the modified region A in FIG. 9.

Referring to the drawings, the first interconnection member 110 may include a first insulation layer 111a, a first redistribution layer 112a, a second redistribution layer 112b, a second insulation layer 111b, a third redistribution layer 112c, and a third insulation layer 111c. And a fourth redistribution layer 112d. The first redistribution layer 112a and the second redistribution layer 112b are respectively disposed on a surface opposite to the first insulation layer 111a, and the second insulation layer 111b is disposed on the first insulation layer 111a and covers the first redistribution layer 112a. The triple wiring layer 112c is disposed on the second insulation layer 111b, the third insulation layer 111c is disposed on the second insulation layer 111b and covers the second wiring layer 112b, and the fourth wiring layer 112d is disposed on the third insulation layer 111c on. The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to each other through the first via 113a, the second via 113b, and the third via 113c. The first through hole 113a, the second through hole 113b, and the third through hole 113c pass through the first insulating layer 111a, the second insulating layer 111b, and the third insulating layer 111c, respectively. Since the first interconnection member 110 may include a large number of redistribution layers 112a, 112b, 112c, and 112d can further simplify the second interconnecting member 140, so that the problem of yield reduction during the process of forming the second interconnecting member 140 can be improved. At least one of the connection pads 122 may be redistributed to the fan-in area and / or the fan-out area via the electrical path P-4 passing through the first interconnection member 110.

At the same time, the thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be configured to form a larger number of redistribution layers 112c and 112d. The insulating material included in the first insulating layer 111a may be different from the insulating materials included in the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be formed of a prepreg such as glass cloth, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be ABF or photosensitive insulating including an inorganic filler and an insulating resin. Film. However, the material of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

In addition, an upper surface of the redistribution layer 112 of the first interconnection member 110 may be disposed higher than a horizontal height of an upper surface of the connection pad 122 of the semiconductor wafer 120. The distance between the redistribution layer 142 of the second interconnection member 140 and the third redistribution layer 112c of the first interconnection member 110 may be smaller than the redistribution layer 142 of the second interconnection member 140 and the connection pad 122 of the semiconductor wafer 120 the distance between. Here, the third redistribution layer 112c may be disposed on the second insulating layer 111b in a protruding form so as to contact the second interconnection member 140. The formed first interconnection member 110 may have a thickness corresponding to the thickness of the semiconductor wafer 120. Therefore, the first layer formed in the first interconnection member 110 The wiring layer 112 a and the second redistribution layer 112 b may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120.

The thicknesses of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first interconnection member 110 may be greater than the thickness of the redistribution layer 142 of the second interconnection member 140. Since the thickness of the first interconnection component 110 may be equal to or larger than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also have relative thicknesses. Larger size. On the other hand, the redistribution layer 142 of the second interconnection member 140 may be formed to have a relatively small thickness. Other configurations may overlap with those described above, so descriptions are omitted.

19 is a schematic cross-sectional view of another example of a fan-out type semiconductor package module.

FIG. 20 is an enlarged sectional view of a region B in FIG. 19.

Referring to the drawings, a fan-out type semiconductor package module 300B according to an exemplary embodiment of the present invention may include a fan-out type semiconductor package 100B and a component package 200B disposed on the fan-out type semiconductor package 100B. The fan-out type semiconductor package 100B may include a first interconnection member 110B having a through hole 110H, a semiconductor wafer 120B, an encapsulation body 130B, a second interconnection member 140B, a third interconnection member 150B, a first connection terminal 160B, and a first Two connecting ends 170B. The semiconductor wafer 120B is disposed in the through hole 110H and has an active surface on which the connection pad 122 is disposed and an inactive surface opposite to the active surface. The encapsulation body 130B covers the inactive of the first interconnection member 110B and the semiconductor wafer 120B. At least part of the surface, the second interconnection member 140B is disposed on the active surfaces of the first interconnection member 110B and the semiconductor wafer 120B, and the third interconnection member 150B The first connection terminal 160B is disposed on the second interconnection member 140B and is connected to the second interconnection member 140B, and the second connection end 170B is connected to the third interconnection member 150B and also connected to the second interconnection member 140B. Motherboard 500. The component package 200B may include a wiring substrate 210B, a plurality of components 220B, and a protective layer 230B. The wiring substrate 210B is disposed above the second interconnection member 140B and connected to the second interconnection member 140B via the first connection terminal 160B. A plurality of components 220B are disposed on or embedded in the wiring substrate 210B, and the protective layer 230B protects A memory wafer 221 and the like arranged on the wiring substrate 210B.

The fan-out type semiconductor package module 300B according to an exemplary embodiment of the present invention may have a structure in which a fan-out type semiconductor package 100B is introduced. A main semiconductor wafer 120B (eg, IC) is installed in the fan-out type semiconductor package 100B, and may be The component package 200B mounted with the memory chip 221 and the like is stacked on the fan-out type semiconductor package 100B. Therefore, a micro fan-out type semiconductor package module having improved functionality and improved reliability can be provided. In this case, the semiconductor wafer 120B may be configured to face up, and the semiconductor wafer 120B is electrically connected to the component package 200B via the second interconnection member 140B and the first connection terminal 160B connected to the second interconnection member 140B. Wiring the substrate 210B and the component 220B to produce a very short signal transmission path or the like. In addition, in the fan-out type semiconductor package 100B, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the like formed in the first interconnection member 110B are introduced around the semiconductor wafer 120B, so that The second connection terminal 170B electrically connected to the third interconnection member 150B is introduced to a position lower than the encapsulation body 130B, so that the fan-out type semiconductor package module 300B can be stably mounted on The motherboard 500 of the electronic device.

Individual components included in the fan-out type semiconductor package module according to an exemplary embodiment of the present invention will be described in more detail below, but descriptions that overlap with those described above will be omitted.

Referring to the drawings, at least one connection pad 122 and at least one second connection terminal 170B may be connected to each other through an electrical path P-5 through the wiring substrate 210B and the first interconnection member 110B. For example, at least one of the connection pads 122 of the semiconductor wafer 120B can pass through the second interconnection member 140B, the first connection terminal 160B, the wiring substrate 210B, the first connection terminal 160B, and the second via the electrical path P-5. The order of the interconnection member 140B and the first interconnection member 110B or the reverse order thereof is electrically connected to at least one of the second connection terminals 170B. In this case, the electrical path P-5 may be connected to a passive component 222 in the embedded wiring substrate 210B, such as an embedded capacitor, an embedded power inductor, or the like. As described above, the semiconductor wafer 120B may be connected to the embedded passive component 222 via the electrical path P-5, which is short and is beneficial to maintaining power integrity (PI) characteristics. At the same time, the semiconductor wafer 120B does not need to be electrically connected to the passive component 222 only through the electrical path P-5 described above, but can also be electrically connected to the passive component 222 through another path. In addition, in the case where the aforementioned passive component 222 is embedded in the wiring substrate 210B and connected to the semiconductor wafer 120B, it is not necessary to configure a separate land side capacitor (LSC) below the fan-out semiconductor package 100B, Therefore, the height of the second connection terminal 170B is reduced. In addition, the memory signal of the semiconductor wafer 120B arranged in a face-up form can be within a short distance The connection to the memory chip 221 via the wiring substrate 210B facilitates the characteristics of the memory.

The second interconnection member 140B may include a plurality of insulating layers 141a and 141b. The plurality of insulating layers 141a and 141b may include the same insulating material or different insulating materials. An opening exposing at least a part of the pattern may be formed in the upper insulating layer 141b as a connection terminal pad in the redistribution layer 142, and a lower bump metal layer 145 may be formed in the opening. The wiring substrate 210B may include a first insulating layer 211A, a second insulating layer 211B, and a third insulating layer 211C. The first insulating layer 211A has a cavity embedded in the passive component 222, the second insulating layer 211B covers one surface of the first insulating layer 211A, and the third insulating layer 211C covers the other surface of the first insulating layer 211A. In addition, the wiring substrate 210B may include a redistribution layer 212 formed on the first insulating layer 211A and the second insulating layer 211B, and a through hole 213 formed in the first insulating layer 211A and the second insulating layer 211B. The first insulation layer 211A may be a conventional core layer formed by a prepreg or the like, the second insulation layer 211B may be a conventional insulation layer formed by an ABF or the like, and the third insulation The layer 211C may be a conventional photosensitive imaging dielectric (PID) film formed by a solder resist or the like. However, the first to third insulating layers are not limited thereto. The wiring substrate 210B may include a under bump metal layer 215 connected to the other first connection terminals 160B. The second connection terminal 170B may be disposed in both the fan-in area and the fan-out area via the third interconnection member 150B, but is not limited thereto.

Although not shown in the drawings, various modifications may be made to the fan-out type semiconductor package module 300B according to an exemplary embodiment of the present invention, such as the aforementioned modification of the fan-out type semiconductor package module 300A according to the exemplary embodiment Instance.

21 is a schematic cross-sectional view of another example of a fan-out semiconductor package module.

FIG. 22 is an enlarged sectional view of a region C in FIG. 21.

Referring to the drawings, a fan-out semiconductor package module 300C according to an exemplary embodiment of the present invention may include a fan-out semiconductor package 100C and a component package 200C disposed on the fan-out semiconductor package 100C. The fan-out type semiconductor package 100C may include a first interconnection member 110C having a through hole 110H, a semiconductor wafer 120C, an encapsulation body 130C, a second interconnection member 140C, a third interconnection member 150C, a first connection terminal 160C, and a first Two connection terminals 170C. The semiconductor wafer 120C is disposed in the through hole 110H and has an active surface on which the connection pad 122 is disposed and an inactive surface opposite to the active surface. The encapsulation body 130C covers the inactive of the first interconnection member 110C and the semiconductor wafer 120C. At least part of the surface, the second interconnection member 140C is disposed on the first interconnection member 110C and the active surface of the semiconductor wafer 120C, the third interconnection member 150C is disposed on the encapsulation body 130C, and the first connection terminal 160C is disposed on The second interconnection member 140C is connected to the second interconnection member 140C, and the second connection terminal 170C is connected to the third interconnection member 150C and also connected to the motherboard 500. The component package 200C may include a first wiring substrate 210Ca, a second wiring substrate 210Cb, a component 220C, and a protective layer 230C. The first wiring substrate 210Ca is disposed on the second interconnection member 140C, and is connected to the second interconnection member 140C via the first connection terminal 160C. The second wiring substrate 210Cb is disposed on the first wiring substrate 210Ca, and via the first The three connection terminals 180C are connected to the first wiring substrate 210Ca, the component 220C is disposed on the first wiring substrate 210Ca or the second wiring substrate 210Cb, and the protective layer 230C protects the memory chip 221 and the like disposed on the wiring substrate 210Cb.

The fan-out type semiconductor package module 300C according to an exemplary embodiment of the present invention may have a structure that introduces a fan-out type semiconductor package 100C. The main semiconductor wafer 120C (for example, IC) is installed in the fan-out type semiconductor package 100C, and many Each of the component packages 200Ca and 200Cb is stacked on the fan-out semiconductor package 100C, and a memory chip and the like can be installed in the component packages. Therefore, a micro fan-out type semiconductor package module with improved functionality and improved reliability can be provided. In this case, the semiconductor wafer 120C of the fan-out type semiconductor package 100C may be configured to face up, and the semiconductor wafer 120C may be electrically connected via the second interconnection member 140C and the first connection terminal 160C connected to the second interconnection member 140C. To the component package 200C to produce a very short signal transmission path or the like. In addition, in the fan-out semiconductor package 100C, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the like formed in the first interconnection member 110C are introduced around the semiconductor wafer 120C, and are electrically conductive. The second connection terminal 170C connected to the third interconnection member 150C is introduced at a position lower than the encapsulation body 130C, so that the fan-out type semiconductor package module 300C can be stably mounted on the motherboard 500 of the electronic device.

Individual components included in the fan-out type semiconductor package module according to an exemplary embodiment of the present invention will be described in more detail below, but descriptions that overlap with those described above will be omitted.

Referring to the drawings, one of the connection pads 122 and the second connection terminal 170C may be connected to each other through an electrical path P-6 through the first wiring substrate 210Ca and the first interconnection member 110C. For example, at least one of the connection pads 122 of the semiconductor wafer 120C may pass through the second interconnection member 140C and the first connection terminal via the electrical path P-6. The sub 160C, the wiring substrate 210C, the first connection terminal 160C, the second interconnection member 140C, and the first interconnection member 110C are electrically connected to at least one of the second connection terminals 170C in the order or the reverse order. In this case, the electrical path P-6 may be connected to the passive component 223 disposed on the first wiring substrate 210Ca using an underfill resin 218 or the like, such as a surface mounted capacitor, a surface mount A type of surface mounted thin film inductor or the like. As described above, the semiconductor wafer 120C can be connected to the surface-mounted passive component 223 via a relatively short electrical path P-6, which is beneficial to maintaining power integrity (PI) characteristics. At the same time, the semiconductor chip 120C does not need to be electrically connected to the passive component 223 only through the electrical path P-6 described above, but can also be electrically connected to the passive component 223 through another path. Meanwhile, in the case where the aforementioned passive component 223 is mounted on the first wiring substrate 210C and connected to the semiconductor wafer 120C, the individual pin-side capacitor (LSC) need not be configured lower than the fan-out type semiconductor package 100C, and thus can be reduced The height of the second connection terminal 170C. In addition, the memory signal of the semiconductor wafer 120C that can be arranged in a face-up form is connected to the memory wafer 221 via the wiring substrate 210C within a short distance, which can be beneficial to the characteristics of the memory.

The second interconnection member 140C may include a plurality of insulating layers 141a and 141b. The plurality of insulating layers 141a and 141b may include the same insulating material or different insulating materials. An opening exposing at least a part of the pattern may be formed in the upper insulating layer 141b as a connection terminal pad in the redistribution layer 142, and a lower bump metal layer 145 may be formed in the opening. The first wiring substrate 210Ca may include a first insulating layer 211A And a third insulating layer 211C, which covers two opposite surfaces of the first insulating layer 211A. In addition, the first wiring substrate 210Ca may include a redistribution layer 212 formed on the first insulating layer 211A and a through hole 213 formed in the first insulating layer 211A. The first insulating layer 211A may be a conventional core layer formed by a prepreg or the like, and the third insulating layer 211C may be a conventional photosensitive imaging dielectric formed by a solder resist or the like (PID) film. However, the first insulating layer and the third insulating layer are not limited to this. The first wiring substrate 210Ca may include an under bump metal layer 215a connected to the other first connection terminals 160C. The second wiring substrate 210Cb may include a plurality of insulating layers, a plurality of redistribution layers formed on the insulating layer, and a plurality of through holes formed in the insulating layer. The second wiring substrate 210Cb may include a metal layer under the bump connected to the third connection terminal 180C. The third connection terminal 180C may be a solder ball, a copper core ball, a copper pillar, or the like, but is not limited thereto. The second connection terminal 170C may be disposed in both the fan-in area and the fan-out area via the third interconnection member 150C, but is not limited thereto. However, the second connection terminal 170C is not limited to this.

Although not shown in the drawings, various modifications may be made to the fan-out type semiconductor package module 300C according to the exemplary embodiment of the present invention, as the above-mentioned modification of the fan-out type semiconductor package module 300A according to the exemplary embodiment Instance.

As mentioned above, according to the exemplary embodiments of the present invention, a micro fan-out type semiconductor package module having improved functionality and improved reliability can be provided.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention.

Claims (15)

A fan-out type semiconductor package module includes a fan-out type semiconductor package including a first interconnection member, a semiconductor wafer, an encapsulation body, a second interconnection member, a first connection terminal, and a second connection terminal. An interconnection member has a through hole, and the semiconductor wafer is disposed in the through hole of the first interconnection member and has an active surface and a non-active surface opposite to the active surface, and the active surface is provided with A connection pad, the encapsulation body covering at least part of the first interconnecting member and at least part of the non-active surface of the semiconductor wafer, and the second interconnecting member is disposed on the first interconnecting member and On the active surface of the semiconductor wafer, the first connection terminal is disposed on the second interconnection member, the second connection terminal is disposed on the encapsulation body, and the first interconnection member And the second interconnecting member respectively includes a redistribution layer electrically connected to the connection pad of the semiconductor wafer; and a component package including a portion disposed above the second interconnecting member and passing through the first Connected with terminals A wiring substrate to the second interconnection member and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate, wherein the second interconnection member is disposed on the semiconductor wafer. Between the active surface and the wiring substrate, and the active surface of the semiconductor wafer faces the first connection terminal and the wiring substrate, and the non-active surface of the semiconductor wafer faces the second connection terminal The first connection terminal and the second connection terminal are electrically connected to each other through the first interconnection member, and at least one connection pad and at least one second connection terminal pass through the wiring substrate and the first An interconnection member is electrically connected to each other through electrical paths, and the electrical paths at least sequentially pass through the connection pad, the first redistribution pattern of the redistribution layer of the second interconnection member, and the first A first terminal of a connection terminal, a wiring layer of the wiring substrate, a second terminal of the first connection terminal spaced from the first terminal, and the first terminal spaced from the first redistribution pattern. two A second wiring pattern connected to the weight member rewiring layer, the first interconnection layer redistribution member and the second connection terminal. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the wiring substrate has a passive component embedded therein, and the electrical path is connected to the passive component. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the wiring substrate includes a first wiring substrate connected to the first connection member, and a second wiring substrate disposed on the first wiring substrate. A wiring substrate and a third connection terminal, the third connection terminal being disposed between the first wiring substrate and the second wiring substrate and connecting the first wiring substrate and the second wiring substrate to each other, and mounting A passive component on the first wiring substrate is disposed between the first wiring substrate and the second wiring substrate, and the electrical path is connected to the passive component mounted on the first wiring substrate. Components. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the component package includes a memory chip electrically connected to the semiconductor chip. The fan-out type semiconductor package module according to item 1 of the scope of patent application, wherein the first connection terminal is surrounded by an underfill resin formed between the second interconnection member and the wiring substrate. The fan-out type semiconductor package module according to item 1 of the patent application scope, wherein the fan-out type semiconductor package further includes a third interconnecting member disposed on the encapsulation body and having the second connection terminal. Connected to the third interconnection member, wherein the number of first connection terminal pads of the second interconnection member connected to the first connection terminal is greater than the third connection terminal connected to the second connection terminal The number of the second connection terminal pads of the interconnection member. A fan-out type semiconductor package module includes a fan-out type semiconductor package including a first interconnection member, a semiconductor wafer, an encapsulation body, a second interconnection member, a first connection terminal, and a second connection terminal. An interconnection member has a through hole, and the semiconductor wafer is disposed in the through hole of the first interconnection member and has an active surface and a non-active surface opposite to the active surface, and the active surface is provided with A connection pad, the encapsulation body covering at least part of the first interconnecting member and at least part of the non-active surface of the semiconductor wafer, and the second interconnecting member is disposed on the first interconnecting member and On the active surface of the semiconductor wafer, the first connection terminal is disposed on the second interconnection member, the second connection terminal is disposed on the encapsulation body, and the first interconnection member And the second interconnecting member respectively includes a redistribution layer electrically connected to the connection pad of the semiconductor wafer; and a component package including a portion disposed above the second interconnecting member and passing through the first Connected with terminals A wiring substrate to the second interconnection member and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate, wherein the second interconnection member is disposed on the semiconductor wafer. Between the active surface and the wiring substrate, and the active surface of the semiconductor wafer faces the first connection terminal and the wiring substrate, and the non-active surface of the semiconductor wafer faces the second connection terminal The first connection terminal and the second connection terminal are electrically connected to each other via the first interconnection member, and the first interconnection member includes a first insulation layer, a first rewiring layer, and a second reconnection layer; A wiring layer, a first via hole, a second insulation layer, a third redistribution layer, and a second via hole, the first insulation layer is in contact with the second interconnect member, and the first redistribution layer is in contact with the A second interconnecting member contacts and is embedded in the first surface of the first insulating layer, and the second redistribution layer is disposed on the first insulating layer opposite to the first surface of the first insulating layer On the second surface, the first pass Penetrating the first insulating layer and electrically connecting the first redistribution layer and the second redistribution layer, the second insulating layer is disposed on the second surface of the first insulating layer and The second redistribution layer is embedded in a first surface of the second insulation layer, and the third redistribution layer is disposed in the second insulation opposite to the first surface of the second insulation layer. On the second surface of the layer, the second through-hole penetrates the second insulating layer and electrically connects the second redistribution layer and the third redistribution layer, and the first through-hole and The second redistribution layer is integrated, and the second via is integrated with the third redistribution layer. The fan-out type semiconductor package module according to item 7 of the patent application scope, wherein a distance between the redistribution layer and the first redistribution layer of the second interconnection member is greater than the second interconnection member. A distance between the redistribution layer and the connection pad of the connecting member. The fan-out type semiconductor package module according to item 7 of the patent application scope, wherein a thickness of the first redistribution layer is greater than a thickness of the redistribution layer of the second interconnection member. The fan-out type semiconductor package module according to item 7 of the scope of patent application, wherein the upper surface of the first redistribution layer is arranged below the horizontal height of the lower surface of the connection pad. According to the fan-out type semiconductor package module according to item 7 of the patent application scope, wherein the second redistribution layer is disposed on a horizontal level between the active surface and the non-active surface of the semiconductor wafer. A fan-out type semiconductor package module includes a fan-out type semiconductor package including a first interconnection member, a semiconductor wafer, an encapsulation body, a second interconnection member, a first connection terminal, and a second connection terminal. An interconnection member has a through hole, and the semiconductor wafer is disposed in the through hole of the first interconnection member and has an active surface and a non-active surface opposite to the active surface, and the active surface is provided with A connection pad, the encapsulation body covering at least part of the first interconnecting member and at least part of the non-active surface of the semiconductor wafer, and the second interconnecting member is disposed on the first interconnecting member and On the active surface of the semiconductor wafer, the first connection terminal is disposed on the second interconnection member, the second connection terminal is disposed on the encapsulation body, and the first interconnection member And the second interconnecting member respectively includes a redistribution layer electrically connected to the connection pad of the semiconductor wafer; and a component package including a portion disposed above the second interconnecting member and passing through the first Connected with terminals A wiring substrate to the second interconnection member and at least one component disposed on the wiring substrate and electrically connected to the wiring substrate, wherein the second interconnection member is disposed on the semiconductor wafer. Between the active surface and the wiring substrate, and the active surface of the semiconductor wafer faces the first connection terminal and the wiring substrate, and the non-active surface of the semiconductor wafer faces the second connection terminal The first connection terminal and the second connection terminal are electrically connected to each other via the first interconnection member, and the first interconnection member includes a first insulation layer, a first rewiring layer, and a second reconnection layer; A wiring layer, a second insulating layer, a first through hole, a third redistribution layer, a second through hole, a third insulating layer, a fourth redistribution layer, and a third through hole, the first redistribution layer and the third redistribution layer A second redistribution layer is disposed on an opposite surface of the first insulating layer, the second insulating layer is disposed on the first insulating layer and covers the first redistribution layer, and the first through hole Penetrate the first insulating layer and connect the A redistribution layer is electrically connected to the second redistribution layer, the third redistribution layer is disposed on the second insulation layer, the second through hole penetrates the second insulation layer and connects the first redistribution layer to the second insulation layer. A redistribution layer is electrically connected to the third redistribution layer, the third insulation layer is disposed on the first insulation layer and covers the second redistribution layer, and the fourth redistribution layer is disposed on On the third insulation layer, the third through hole penetrates the third insulation layer and electrically connects the second redistribution layer and the fourth redistribution layer, and the thickness of the first insulation layer Greater than the thickness of the second insulating layer and the third insulating layer. According to the fan-out type semiconductor package module according to item 12 of the application scope, the thickness of the third redistribution layer is greater than the thickness of the redistribution layer of the second interconnection member. According to the fan-out type semiconductor package module according to item 12 of the application, wherein the first redistribution layer is disposed at a horizontal height between the active surface and the non-active surface of the semiconductor wafer. According to the fan-out type semiconductor package module according to item 12 of the patent application scope, wherein an upper surface of the third redistribution layer is higher than a horizontal height of an upper surface of the connection pad.