TW201917802A - Wafer level testing structure for multi-sites solution - Google Patents

Wafer level testing structure for multi-sites solution Download PDF

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Publication number
TW201917802A
TW201917802A TW106135627A TW106135627A TW201917802A TW 201917802 A TW201917802 A TW 201917802A TW 106135627 A TW106135627 A TW 106135627A TW 106135627 A TW106135627 A TW 106135627A TW 201917802 A TW201917802 A TW 201917802A
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circuit board
secondary circuit
wafer
socket
slot
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TW106135627A
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Chinese (zh)
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TWI639205B (en
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洪乾耀
陳銘賢
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漢民科技股份有限公司
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Priority to TW106135627A priority Critical patent/TWI639205B/en
Priority to CN201810617966.8A priority patent/CN109683077A/en
Priority to KR1020180079804A priority patent/KR102146158B1/en
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Publication of TWI639205B publication Critical patent/TWI639205B/en
Publication of TW201917802A publication Critical patent/TW201917802A/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2601Apparatus or methods therefor
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

A wafer-level testing structure for multi-sites solution is disclosed. The wafer-level testing structure for multi-sites solution includes a printed circuit board (PCB); at least two socket assemblies set side by side on the PCB, wherein each socket assembly comprises a bottom plate and a positioning stiffener combined to form a socket; one of at least two sub PCB assemblies set on the socket, wherein each sub PCB assembly includes a sub PCB and a final testing substrate; a fixing ring set on the PCB and said fixing ring is provided with a hollow portion, wherein said socket assembly and sub PCB assembly is positioned on the hollow portion; and a probe head assembly set above said sub PCB assembly, and is fixed on the fixing ring. A plurality of final testing substrates arranged side by side are utilized for a wafer-level testing process with multi-sites to improve the testing efficiency. In addition, the socket design is utilized to achieve a function of good accessibility for replacement and good accessibility for testing.

Description

晶圓級多點測試結構Wafer-level multipoint test structure

本發明是有關一種探針測試結構,特別是有關一種晶圓級多點測試的測試結構。The invention relates to a probe test structure, in particular to a wafer-level multi-point test structure.

於半導體產品製造過程中,晶圓(wafer)測試是指對晶圓上的半導體積體電路進行電路測試的技術以確保電路正常運作並得知產品的良率。其中,利用自動測試設備(automatic test equipment,ATE) 於晶圓上的積體電路間形成暫時電性連接用來驗證積體電路正常的電性特性。晶圓測試時,利用探針卡裝置傳遞訊號至積體電路。In the manufacturing process of semiconductor products, wafer testing refers to the technology of performing circuit testing on semiconductor integrated circuits on a wafer to ensure the normal operation of the circuit and to know the yield of the product. Among them, automatic test equipment (ATE) is used to form a temporary electrical connection between the integrated circuits on the wafer to verify the normal electrical characteristics of the integrated circuits. During wafer testing, a probe card device is used to pass signals to the integrated circuit.

請參照圖1所示,一般傳統電路測試探針卡結構1主要包括:一電路板10、一探針基板12、一探針頭組14。此外,因應不同結構設計設置一固定環16與一加強墊18分別結合於電路板之兩側用以穩固並增加電路板強度避免其於高溫或外力環境下產生變形。探針基板12設置於固定環16之鏤空部內,探針基板12其一側表面設有複數錫球122分別對應於電路板10的接點102,其中錫球122可經過迴焊程序與各接點102焊合。基板10之另側表面則設有複數內接點124,且於探針基板12內設有複數導電線路銜接於各內接點124與錫球122間。探針頭組14係固定於固定環16之另一側,複數個探針以一端分別穿過探針固定器上定位孔使各探針之端部保持一適當外凸長度,供抵觸於探針基板12之內接點124。各探針之另一端可通過探針固定器下通孔向外延伸並保持一壓縮彈性以用於與外部電路測試點形成電連接。惟,現有技術之探針基板為整片式基板,除因其組裝方式使之不易更換之外,測試效率亦有限,此外測試不同產品時,無法直接只置換探針基板,極為不便。而提供更有效率、更方便操作、可符合多樣產的的多點測試裝置為此業界相當重要的一課題。Referring to FIG. 1, a conventional conventional circuit test probe card structure 1 mainly includes a circuit board 10, a probe substrate 12, and a probe head group 14. In addition, according to different structural designs, a fixing ring 16 and a reinforcing pad 18 are respectively combined on both sides of the circuit board to stabilize and increase the strength of the circuit board to avoid deformation under high temperature or external force environment. The probe substrate 12 is disposed in the hollow portion of the fixing ring 16. A plurality of solder balls 122 on one side surface of the probe substrate 12 are respectively corresponding to the contacts 102 of the circuit board 10. Point 102 is welded. A plurality of internal contacts 124 are provided on the other surface of the substrate 10, and a plurality of conductive lines are provided in the probe substrate 12 to connect between the internal contacts 124 and the solder balls 122. The probe head group 14 is fixed on the other side of the fixing ring 16, and one end of each of the plurality of probes passes through the positioning hole on the probe holder so that the ends of each probe maintain a proper convex length for resistance to the probe. The inner contact point 124 of the pin substrate 12. The other end of each probe can extend outward through the lower hole of the probe holder and maintain a compression elasticity for forming an electrical connection with an external circuit test point. However, the probe substrate of the prior art is a monolithic substrate. In addition to the difficulty in replacing the probe substrate due to its assembly method, the test efficiency is also limited. In addition, when testing different products, it is impossible to directly replace the probe substrate only, which is extremely inconvenient. It is a very important issue in the industry to provide a multi-point test device that is more efficient, more convenient to operate, and can meet various production requirements.

本發明提供一種晶圓級多點測試結構,其利用多片最終測試基板並排對位設置對晶圓同時進行多點測試,不僅可增加測試效益,可插拔式設計更可達到方便測試、方便置換之功效。The invention provides a wafer-level multi-point test structure, which uses multiple final test substrates to be aligned side-by-side to perform multi-point test on a wafer at the same time, which not only increases test efficiency, but also enables pluggable design to achieve convenient testing and The effect of replacement.

本發明一實施例之一種晶圓級多點測試結構,包含:一印刷電路板,其具有一測試側與跟測試側相對的一晶圓側;至少二插槽座組件設置於印刷電路板的晶圓側上,且每一插槽座組件具有一槽孔,其中每一插槽座組件包含一插槽座底板與一定位加強板,且定位加強板環設固定於插槽座底板的週邊以形成槽孔;至少二次要電路板組件,一該次要電路板組件係可移除地設置於一槽孔內,其中每一次要電路板組件包含:一次要電路板;及一最終測試基板固設於次要電路板上,其中次要電路板位於最終測試基板與槽孔之間;一固定環設置於印刷電路板上,且固定環具有一露空部,其中插槽座組件及次要電路板組件位於露空部內;以及一探針頭組件設置於次要電路板組件上方,並固定設置於固定環上。A wafer-level multi-point test structure according to an embodiment of the present invention includes: a printed circuit board having a test side and a wafer side opposite to the test side; at least two socket seat components are disposed on the printed circuit board. On the wafer side, each slot seat assembly has a slot hole, wherein each slot seat assembly includes a slot seat bottom plate and a positioning reinforcement plate, and the positioning reinforcement plate ring is fixed on the periphery of the slot seat bottom plate. To form a slot; at least a secondary circuit board component, one of which is removably disposed in a slot, wherein each primary circuit board component includes: a primary circuit board; and a final test The substrate is fixed on the secondary circuit board, wherein the secondary circuit board is located between the final test substrate and the slot; a fixing ring is arranged on the printed circuit board, and the fixing ring has an exposed part, wherein the socket seat assembly and the The secondary circuit board component is located in the exposed part; and a probe head component is disposed above the secondary circuit board component and fixedly disposed on the fixing ring.

以下藉由具體實施例配合所附的圖式詳加說明,當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。In the following, detailed description will be given through specific embodiments in conjunction with the accompanying drawings to make it easier to understand the purpose, technical content, characteristics and effects achieved by the present invention.

本發明主要提供一種晶圓級多點測試結構,利用多個最終測試電路板並排設置以完成晶圓的多點測試。以下將詳述本案的各實施例,並配合圖式作為例示。除了這些詳細描述之外,本發明還可以廣泛地施行在其他的實施例中,任何所述實施例的輕易替代、修改、等效變化都包含在本案的範圍內,並以之後的專利範圍為準。在說明書的描述中,為了使讀者對本發明有較完整的瞭解,提供了許多特定細節;然而,本發明可能在省略部分或全部這些特定細節的前提下,仍可實施。此外,眾所周知的步驟或元件並未描述於細節中,以避免造成本發明不必要之限制。圖式中相同或類似之元件將以相同或類似符號來表示。特別注意的是,圖式僅為示意之用,並非代表元件實際的尺寸或數量,不相關的細節未完全繪出,以求圖式的簡潔。The invention mainly provides a wafer-level multi-point test structure, and a plurality of final test circuit boards are arranged side by side to complete the multi-point test of the wafer. Hereinafter, the embodiments of the present invention will be described in detail, and illustrated with the drawings. In addition to these detailed descriptions, the present invention can also be widely implemented in other embodiments, and easy replacements, modifications, and equivalent changes of any of the embodiments are included in the scope of this case, and the scope of subsequent patents is quasi. In the description of the specification, in order to provide the reader with a more complete understanding of the present invention, many specific details are provided; however, the present invention may be implemented without omitting some or all of these specific details. In addition, well-known steps or elements are not described in detail to avoid unnecessary limitations of the present invention. The same or similar elements in the drawings will be represented by the same or similar symbols. It is particularly noted that the drawings are for illustrative purposes only and do not represent the actual size or number of components, and irrelevant details have not been completely drawn in order to simplify the drawings.

請先參考圖2,圖2為本發明一實施例之晶圓級多點測試結構的組立示意圖。如圖所示,本發明一實施例之晶圓級多點測試結構2包含一印刷電路板20、至少二插槽座組件22、至少二次要電路板組件24、一固定環26、及一探針頭組件28。於圖2之實施例中,插槽座組件22之數量包含但不限於兩個,且次要電路板組件24之數量亦包含但不限於兩個。印刷電路板20具有一測試側201與跟測試側201相對的一晶圓側202。插槽座組件22並排設置於印刷電路板20的晶圓側202上,且每一插槽座組件22具有一槽孔221。而每一次要電路板組件24可移除地對應設置於槽孔221內,其中每一次要電路板組件24包含:一次要電路板241;及一最終測試基板242固設於次要電路板241上,其中次要電路板241會位於最終測試基板242與槽孔221之間,因測試機台的高度固定,故可利用次要電路板241讓最終測試基板242變厚(也就是增加次要電路板組件24的整體厚度),以符合機台高度。於一實施例中,最終測試基板242係以適當形式設置於次要電路板241上,例如表面黏著技術(SMT,Surface Mount Technology)或其他黏合方式。於一實施例中,如待測試晶圓之每單位晶粒區域大小為10公釐(mm) x 10公釐(mm),則最終測試基板242之大小包含但不限於17公釐(mm) x 17公釐(mm) ,此外,每一最終測試基板242可定義為一個單元測試區域(1 site),本發明同一時間最少可同時測試兩個單元測試區域(2 site),因此有效解決測試效率問題。於又一實施例中,次要電路板組件24的次要電路板241包含複數固定部2412,次要電路板組件24可利用該複數固定部2412定位於插槽座組件22上。承上,於再一實施例中,複數固定部2412包含但不限於固定孔,其係利用適當方式,例如以螺絲螺合方式固定於插槽座組件22上。固定環26設置於印刷電路板20上,且固定環26具有一露空部261,其中插槽座組件22及次要電路板組件24位於露空部261內。探針頭組件28設置於次要電路板組件24上方,並固定設置於固定環26上。一實施例中,次要電路板組件24與插槽座組件22組立於印刷電路板後的結構如圖3所示。Please refer to FIG. 2 first, which is an assembly schematic diagram of a wafer-level multi-point test structure according to an embodiment of the present invention. As shown in the figure, a wafer-level multi-point test structure 2 according to an embodiment of the present invention includes a printed circuit board 20, at least two socket seat assemblies 22, at least secondary circuit board assemblies 24, a fixing ring 26, and a Probe head assembly 28. In the embodiment of FIG. 2, the number of the socket seat components 22 includes but is not limited to two, and the number of the secondary circuit board components 24 also includes but is not limited to two. The printed circuit board 20 has a test side 201 and a wafer side 202 opposite to the test side 201. The socket base assemblies 22 are arranged side by side on the wafer side 202 of the printed circuit board 20, and each socket base assembly 22 has a slot hole 221. Each of the secondary circuit board components 24 is removably disposed in the slot 221. Each of the secondary circuit board components 24 includes: a secondary circuit board 241; and a final test substrate 242 is fixed on the secondary circuit board 241. Above, the secondary circuit board 241 is located between the final test substrate 242 and the slot 221. Because the height of the test machine is fixed, the secondary circuit board 241 can be used to thicken the final test substrate 242 (that is, increase the secondary The overall thickness of the circuit board assembly 24) to match the height of the machine. In one embodiment, the final test substrate 242 is disposed on the secondary circuit board 241 in an appropriate form, such as Surface Mount Technology (SMT) or other bonding methods. In an embodiment, if the size of each die area of the wafer to be tested is 10 mm (mm) x 10 mm (mm), the size of the final test substrate 242 includes, but is not limited to, 17 mm (mm) x 17 mm (mm). In addition, each final test substrate 242 can be defined as a unit test area (1 site). The invention can test at least two unit test areas (2 site) at the same time at the same time. Efficiency issues. In yet another embodiment, the secondary circuit board 241 of the secondary circuit board assembly 24 includes a plurality of fixing portions 2412. The secondary circuit board assembly 24 can be positioned on the socket base assembly 22 using the plurality of fixing portions 2412. In another example, in another embodiment, the plurality of fixing portions 2412 include, but are not limited to, fixing holes, which are fixed to the socket seat assembly 22 by a suitable method, for example, by screwing. The fixing ring 26 is disposed on the printed circuit board 20, and the fixing ring 26 has an exposed portion 261. The slot seat component 22 and the secondary circuit board component 24 are located in the exposed portion 261. The probe head assembly 28 is disposed above the secondary circuit board assembly 24 and is fixedly disposed on the fixing ring 26. In one embodiment, the structure of the secondary circuit board assembly 24 and the socket seat assembly 22 after being assembled on the printed circuit board is shown in FIG. 3.

接續上述,為清楚解釋插槽座組件之結構,請繼續參考圖2及圖4A及圖4B,其中圖4A、圖4B分別為插槽座組件組立前及組立後的結構俯視示意圖。如圖所示,每一插槽座組件22包含一插槽座底板222與一定位加強板224,且定位加強板224環設固定於插槽座底板222的週邊以形成槽孔221。而次要電路板組件24可移除地對應設置於槽孔221內,其中次要電路板組件24藉由複數固定部2412達到可輕易更換之功效,此外,可利用更換不同設計的次要電路板組件24以適用多樣產品,從而減少成本。Continuing the above, in order to clearly explain the structure of the socket seat assembly, please continue to refer to FIG. 2 and FIG. 4A and FIG. 4B, wherein FIG. 4A and FIG. As shown in the figure, each slot seat assembly 22 includes a slot seat bottom plate 222 and a positioning reinforcement plate 224, and the positioning reinforcement plate 224 is fixed around the periphery of the slot seat bottom plate 222 to form a slot hole 221. The secondary circuit board assembly 24 is removably correspondingly disposed in the slot 221. The secondary circuit board assembly 24 can be easily replaced by a plurality of fixing parts 2412. In addition, the secondary circuit of a different design can be replaced by using The board assembly 24 is applicable to various products, thereby reducing costs.

承上,於一實施例中,插槽座組件22更包含至少一止付螺絲226設置於定位加強板224的週邊以依需求控制設置於其上之次要電路板組件24的水平位移。於又一實施例中,請一併參考圖2、圖5A及圖5B,如圖所示,插槽座組件22更可包含一聚脂薄膜墊片228設置於插槽座組件22與印刷電路板20之間,亦或者,聚脂薄膜墊片228可設置於插槽座組件22與次要電路板組件24之間,以依需求調整次要電路板組件24的高度與平整度。利用微調次要電路板組件24的水平位移、高度及平整度,除可提高測試機台的準確度之外,亦可依據不同待測物或待測產品的測試需求作細部調整。According to an embodiment, in one embodiment, the socket seat assembly 22 further includes at least one set screw 226 disposed on the periphery of the positioning reinforcing plate 224 to control the horizontal displacement of the secondary circuit board assembly 24 disposed thereon as required. In another embodiment, please refer to FIG. 2, FIG. 5A and FIG. 5B together. As shown in the figure, the socket base assembly 22 may further include a polyester film gasket 228 disposed on the socket base assembly 22 and the printed circuit. Between the boards 20, or alternatively, a polyester film gasket 228 may be disposed between the socket seat assembly 22 and the secondary circuit board assembly 24 to adjust the height and flatness of the secondary circuit board assembly 24 as required. By fine-tuning the horizontal displacement, height, and flatness of the secondary circuit board assembly 24, in addition to improving the accuracy of the test machine, detailed adjustments can also be made according to the test needs of different objects or products to be tested.

根據上述,本發明之晶圓級多點測試結構,利用多個最終測試電路板並排以完成晶圓的多點測試,以增加測試效益。此外,一般最終測試電路板無空間做額外的固定,故本發明利用次要電路板結合最終測試電路板有效增加鎖附空間;而利用插槽座組件的插接組裝方式,方便作業人員操作、置換及對位。再者,次要電路板組件藉由複數固定部可輕易置換,以適用多樣產品,從而減少測試機台開發成本。更者,依需求於插槽座組件上使用止付螺絲及/或聚脂薄膜墊片,可有效調整多組並排之次要電路板組件的垂直高度與水平位置,以符合不同待測產品之需求。According to the above, the wafer-level multi-point test structure of the present invention utilizes multiple final test circuit boards side by side to complete the multi-point test of the wafer to increase test efficiency. In addition, the final test circuit board generally has no space for additional fixing, so the present invention uses a secondary circuit board in combination with the final test circuit board to effectively increase the locking space; and the plug-in assembly method of the socket seat assembly is convenient for operators to operate Replacement and alignment. In addition, the secondary circuit board components can be easily replaced by a plurality of fixing parts to apply to various products, thereby reducing the development cost of the test machine. Furthermore, the use of stop screws and / or polyester film gaskets on the socket seat components can effectively adjust the vertical height and horizontal position of multiple sets of side-by-side secondary circuit board components to meet the requirements of different products under test. demand.

綜合上述,本發明之晶圓級多點測試結構,其利用多片最終測試基板並排對位設置對晶圓同時進行多點測試,不僅可增加測試效益,可插拔式設計更可達到方便測試、方便置換之功效。To sum up, the wafer-level multi-point test structure of the present invention utilizes multiple final test substrates to be aligned side-by-side to perform multi-point test on the wafer at the same time, which not only increases test efficiency, but also enables pluggable design for convenient testing. The effect of convenient replacement.

以上所述之實施例僅是為說明本發明之技術思想及特點,其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施,當不能以之限定本發明之專利範圍,即大凡依本發明所揭示之精神所作之均等變化或修飾,仍應涵蓋在本發明之專利範圍內。The above-mentioned embodiments are only for explaining the technical ideas and characteristics of the present invention. The purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. When the scope of the patent of the present invention cannot be limited, That is, any equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered by the patent scope of the present invention.

1‧‧‧電路測試探針卡結構1‧‧‧Circuit test probe card structure

10‧‧‧電路板10‧‧‧Circuit Board

102‧‧‧接點102‧‧‧Contact

12‧‧‧探針基板12‧‧‧ Probe substrate

122‧‧‧錫球122‧‧‧ solder ball

124‧‧‧內接點124‧‧‧Internal contact

14‧‧‧探針頭組14‧‧‧ Probe Head Set

16‧‧‧固定環16‧‧‧ fixed ring

18‧‧‧加強墊18‧‧‧ Reinforcement pad

2‧‧‧晶圓級多點測試結構2‧‧‧ Wafer-level multi-point test structure

20‧‧‧印刷電路板20‧‧‧printed circuit board

201‧‧‧測試側201‧‧‧Test side

202‧‧‧晶圓側202‧‧‧Wafer side

22‧‧‧插槽座組件22‧‧‧Slot Block Assembly

221‧‧‧槽孔221‧‧‧Slot

222‧‧‧插槽座底板222‧‧‧Slot base plate

224‧‧‧定位加強板224‧‧‧Positioning plate

226‧‧‧止付螺絲226‧‧‧stop screw

228‧‧‧聚脂薄膜墊片228‧‧‧Polyester film gasket

24‧‧‧次要電路板組件24‧‧‧ secondary circuit board components

241‧‧‧次要電路板241‧‧‧ secondary circuit board

2412‧‧‧固定部2412‧‧‧Fixed section

242‧‧‧最終測試基板242‧‧‧Final test substrate

26‧‧‧固定環26‧‧‧Fixed ring

261‧‧‧露空部261‧‧‧ Open Air Department

28‧‧‧探針頭組件 28‧‧‧ Probe head assembly

圖1為習知之傳統電路測試探針卡結構之示意圖。 圖2為本發明一實施例之晶圓級多點測試結構的待組立示意圖。 圖3本發明一實施例之晶圓級多點測試結構的局部組立後的示意圖。 圖4A、圖4B為本發明一實施例之插槽座組件之示意圖。 圖5A為本發明又一實施例之插槽座組件之示意圖。 圖5B為圖5A的局部放大示意圖。FIG. 1 is a schematic diagram of a conventional conventional circuit test probe card structure. FIG. 2 is a schematic diagram to be assembled of a wafer-level multi-point test structure according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a partially assembled wafer-level multi-point test structure according to an embodiment of the present invention. 4A and 4B are schematic diagrams of a socket base assembly according to an embodiment of the present invention. FIG. 5A is a schematic diagram of a socket seat assembly according to another embodiment of the present invention. FIG. 5B is a partially enlarged schematic diagram of FIG. 5A.

Claims (6)

一種晶圓級多點測試結構,包含: 一印刷電路板,具有一測試側與跟該測試側相對的一晶圓側; 至少二插槽座組件,其並排設置於該印刷電路板的該晶圓側上,且每一該插槽座組件具有一槽孔,其中每一該插槽座組件包含一插槽座底板與一定位加強板,且該定位加強板環設固定於該插槽座底板的週邊以形成該槽孔; 至少二次要電路板組件,一該次要電路板組件係可移除地設置於一該槽孔內,其中每一該次要電路板組件包含:一次要電路板;及一最終測試基板,固設於該次要電路板上,其中該次要電路板位於該最終測試基板與該槽孔之間; 一固定環,設置於該印刷電路板上,且該固定環具有一露空部,其中該插槽座組件及該次要電路板組件位於該露空部內;以及 一探針頭組件,設置於該次要電路板組件上方,並固定設置於該固定環上。A wafer-level multi-point test structure includes: a printed circuit board having a test side and a wafer side opposite to the test side; at least two socket seat components arranged side by side on the crystal of the printed circuit board On the round side, and each of the slot seat components has a slot hole, wherein each of the slot seat components includes a slot seat bottom plate and a positioning reinforcing plate, and the positioning reinforcing plate ring is fixed to the slot seat A periphery of the bottom plate to form the slot; at least a secondary circuit board component, one of the secondary circuit board components is removably disposed in one of the slot holes, and each of the secondary circuit board components includes: a primary A circuit board; and a final test substrate, fixed on the secondary circuit board, wherein the secondary circuit board is located between the final test substrate and the slot; a fixing ring, disposed on the printed circuit board, and The fixing ring has an exposed part, wherein the socket seat component and the secondary circuit board component are located in the exposed part; and a probe head component is disposed above the secondary circuit board component and is fixedly disposed on the secondary circuit board component. On the retaining ring. 如請求項1所述之晶圓級多點測試結構,其中該次要電路板組件的該次要電路板包含複數固定部,該次要電路板組件利用該複數固定部定位於該插槽座組件。The wafer-level multi-point test structure according to claim 1, wherein the secondary circuit board of the secondary circuit board assembly includes a plurality of fixing parts, and the secondary circuit board assembly is positioned on the socket base using the plurality of fixing parts. Components. 如請求項2所述之晶圓級多點測試結構,其中該複數固定部為固定孔。The wafer-level multi-point test structure according to claim 2, wherein the plurality of fixing portions are fixing holes. 如請求項1所述之晶圓級多點測試結構,更包含至少一止付螺絲設置於該定位加強板上以控制該次要電路板組件的水平位移。The wafer-level multi-point test structure according to claim 1, further comprising at least one stop screw disposed on the positioning reinforcing plate to control the horizontal displacement of the secondary circuit board component. 如請求項1所述之晶圓級多點測試結構,更包含一聚脂薄膜墊片設置於該插槽座組件與該印刷電路板之間,以調整該次要電路板組件的高度與平整度。The wafer-level multi-point test structure as described in claim 1, further comprising a polyester film gasket disposed between the socket seat assembly and the printed circuit board to adjust the height and flatness of the secondary circuit board assembly degree. 如請求項1所述之晶圓級多點測試結構,更包含一聚脂薄膜墊片設置於該插槽座組件與該次要電路板組件之間,以調整該次要電路板組件的高度與平整度。The wafer-level multi-point test structure as described in claim 1, further comprising a polyester film gasket disposed between the socket seat component and the secondary circuit board component to adjust the height of the secondary circuit board component. With flatness.
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