TW201916040A - Resistive memory device - Google Patents

Abstract

Provided is a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell and a reference cell; a reference resistance circuit configured to be electrically connected to the reference cell; an offset current source circuit configured to add or draw an offset current to or from a read current provided to the reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell. The resistive memory device of the invention accurately reads a value stored in a memory cell by compensating for variations in the resistance of the memory cell.

Description

Resistive memory device

The present invention relates to a resistive memory device, and more particularly to a resistive memory device including a reference unit and a method of operating a resistive memory device.

The resistive memory device stores data in a storage unit including a variable resistance element. To detect data stored in the storage unit of the resistive memory device, for example, a read current can be supplied to the storage unit, and a voltage caused by the read current and the variable resistance element of the storage unit can be detected.

In a memory cell in which a specific value is stored, the resistance of the variable resistance element may be dispersed, and the dispersion may fluctuate due to a process voltage temperature (PVT) or the like. Such variations in resistance dispersion may interfere with accurate reading of values stored in the storage unit.

The inventive concept provides a resistive memory device and a method of operating the memory device to accurately read a value stored in a storage unit by compensating for changes in resistance of the storage unit.

According to an aspect of the present invention, a resistive memory device is provided, the resistive memory device being configured to output a value stored in a storage unit in response to a read command, the resistive memory device comprising: a cell array including the storage unit and a reference unit; a reference resistance circuit configured to be electrically connected to the reference unit; and an offset current source circuit configured to add a read current supplied to the reference resistance circuit And shifting current or extracting the offset current from the read current supplied to the reference resistor circuit; and a control circuit configured to control the offset current source circuit to compensate for resistance of the storage unit The change.

According to another aspect of the inventive concept, a resistive memory device is provided, the resistive memory device being configured to output a value stored in a storage unit in response to a read command, the resistive memory device comprising a cell array including the storage unit and a reference unit, a first read current flowing through the storage unit, a reference current flowing through the reference unit, and a current source circuit configured to generate the first read current and a second read current; an offset current source circuit configured to generate the reference current by adding an offset current to the second read current or extracting the offset current from the second read current And a control circuit configured to control the offset current source circuit to compensate for a change in resistance of the storage unit.

According to another aspect of the inventive concept, a resistive memory device is provided, the resistive memory device being configured to output a value stored in a storage unit in response to a read command, the resistive memory device comprising a cell array including the storage unit and a reference unit, a first read current flowing through the storage unit, a second read current flowing through the reference unit; and an offset current source circuit configured to pass the a second read current plus an offset current or a reference current drawn from the second read current to generate a reference current; a reference resistor circuit electrically connected to the reference unit, and the reference current flowing through a reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a change in resistance of the storage unit.

Exemplary embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings. FIG.

FIG. 1 is a block diagram of a memory device 100 and a controller 200, in accordance with an exemplary embodiment.

Referring to FIG. 1, the memory device 100 can communicate with the controller 200. The memory device 100 can receive commands CMD (such as write commands and read commands) and the address ADDR from the controller 200 and receive the data DATA from the controller 200 (ie, the data to be written) or transfer the data DATA to the controller. (ie, the material to be read). Although FIG. 1 illustrates the command CMD, the address ADDR, and the data DATA, respectively, according to some exemplary embodiments, at least two of the command CMD, the address ADDR, and the data DATA may be transmitted through the same channel. As shown in FIG. 1, the memory device 100 can include a cell array 110, a current source circuit 120, a reference resistance circuit 130, an offset current circuit 140, an amplification circuit 150, and/or a control circuit 160.

The cell array 110 can include a plurality of memory cells M. The storage unit M may include a variable resistance element (for example, a magnetic tunnel junction (MTJ) in FIG. 2), and the variable resistance element may have a resistance corresponding to a value stored in the storage unit M. Therefore, the memory device 100 can be referred to as a resistive memory device or a resistive random access memory (ReRAM) device. For example, as an unrestricted example, the memory device 100 may include a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM). The cell array 110 of the same structure may include a cell array 110 having a structure such as a spin-transfer torque magnetic random access memory (STT-MRAM), Magnetic random access memory such as spin torque transfer magnetization switching RAM (Spin-PRAM) and spin momentum transfer RAM (SMT-RAM) Magnetic random access memory (MRAM) structure. As will be explained below with reference to FIG. 2, the exemplary embodiments will be mainly explained with reference to the MRAM, but the exemplary embodiments are not limited thereto.

The cell array 110 may include a reference cell R for determining a value stored in the storage unit M. For example, as shown in FIG. 1, the cell array 110 may include a plurality of memory cells M and a reference cell R that are commonly connected to the word line WLi, and thus may be simultaneously selected to be commonly connected to each other through the word line WLi being activated. The plurality of storage units M of the word line WLi and the reference unit R. Although only one reference cell R is illustrated in FIG. 1, in some exemplary embodiments, cell array 110 may include two or more reference cells R connected to word line WLi. In some exemplary embodiments, the reference unit R may be a shorted cell that does not include a resistive element (eg, a variable resistive element) as explained below with reference to FIGS. 4-6.

The current source circuit 120 can provide the first read current I_RD1 and the second read current I_RD2 to the cell array 110. For example, in response to the read command, current source circuit 120 can provide first read current I_RD1 to storage unit M and provide at least a portion of second read current I_RD2 to reference unit R. In some exemplary embodiments, current source circuit 120 may generate first read current I_RD1 and second read current I_RD2 having the same magnitude. In addition, in some exemplary embodiments, the current source circuit 120 may adjust the magnitude of the first read current I_RD1 and/or the magnitude of the second read current I_RD2 under the control of the control circuit 160.

In response to the read command, the reference resistor circuit 130 can be electrically coupled to the reference unit R and provide a resistor for the reference current I_REF to flow through. As explained below, the reference current I_REF may be obtained by subtracting the offset current I_OFF from the second read current I_RD2 generated by the current source circuit 120 or the second read current I_RD2 generated by the current source circuit 120. Current generated by I_OFF. For example, as shown in FIG. 1, the reference resistance circuit 130 may provide a resistance having a reference resistance R _REF between the first node N1 to which the reference current I_REF is supplied and the second node N2 to which the reference current I_REF is supplied. Additionally, in some exemplary embodiments, the reference resistance circuit 130 may adjust the reference resistance R _REF under the control of the control circuit 160. The resistance of the reference resistance circuit 130 may have characteristics different from those of the resistance formed inside the cell array 110 (for example, the MTJ in FIG. 2). For example, the resistance of the reference resistance circuit 130 may have better characteristics than the characteristics of the resistance formed inside the cell array 110. For example, the resistance of reference resistor circuit 130 may be less sensitive to PVT variations.

The offset current circuit 140 may generate the reference current I_REF by adding the offset current I_OFF to the second read current I_RD2 or the offset current I_OFF from the second read current I_RD2. The offset current circuit 140 may include at least one current source for generating an offset current I_OFF, and the magnitude of the offset current I_OFF may be adjusted according to a control signal CTRL provided from the control circuit 160. As explained below, the offset current I_OFF may have a magnitude and a direction corresponding to a change in the variable resistance element included in the storage unit M. In some exemplary embodiments, the second read current I_RD2 may flow through the reference unit R as explained below with reference to FIG. 4, or in some exemplary embodiments, the reference current I_REF may be as described below with reference to FIGS. 5 and 6. Explain the flow through the reference unit R.

The amplifying circuit 150 can receive the read voltage V_RD and the reference voltage V_REF and can determine the value stored in the storage unit M based on the read voltage V_RD and the reference voltage V_REF. For example, the amplifying circuit 150 may output a signal corresponding to the value stored in the storage unit M by comparing the read voltage V_RD with the reference voltage V_REF. The read voltage V_RD may include a voltage drop due to the first read current I_RD1 supplied from the current source circuit 120 flowing through the memory cell M. In addition, the read voltage V_RD may include not only the voltage drop caused by the memory cell M but also the path through which the first read current I_RD1 flows (eg, the row decoder 170a, the source line SLj, and the bit line BLj). The voltage drop caused by the parasitic resistance in ).

Similar to the read voltage V_RD, the reference voltage V_REF may include not only the voltage drop caused by the reference cell R but also the path through which the second read current I_RD2 or the reference current I_REF provided by the current source circuit 120 flows (for example) The voltage drop caused by the parasitic resistance in the row decoder 170a, the short-circuit source line SSL, and the short-circuit bit line SBL in FIG. The reference voltage V_REF may also include a voltage drop caused by the reference resistance R _REF provided by the reference resistance circuit 130. Therefore, the reference voltage V_REF can be adjusted by controlling the reference current I_REF of the reference resistance circuit 130 and the reference resistance R _REF , and thus the criteria for determining the value stored in the storage unit M can be adjusted.

Control circuit 160 can control offset current circuit 140 by control signal CTRL. In some exemplary embodiments, the control circuit 160 may generate the control signal CTRL based on the PVT variation or the like to compensate for variations in the resistance of the variable resistance element included in the memory element M. For example, when the variable resistance element included in the storage unit M has a resistance proportional to temperature (ie, a positive temperature coefficient), the control circuit 160 may reduce the read current I_RD2 from the second by the control signal CTRL. The magnitude of the extracted offset current I_OFF is such that the reference current I_REF supplied to the reference resistance circuit 130 is increased, or the magnitude of the offset current I_OFF applied to the second read current I_RD2 is increased. On the other hand, when the variable resistance element included in the storage unit M has a resistance inversely proportional to temperature (ie, a negative temperature coefficient), the control circuit 160 can increase the read current I_RD2 from the second by the control signal CTRL. The magnitude of the extracted offset current I_OFF or the magnitude of the offset current I_OFF added to the second read current I_RD2 is decreased such that the reference current I_REF supplied to the reference resistance circuit 130 is decreased.

In some exemplary embodiments, control circuit 160 may receive information regarding offset current I_OFF from controller 200. For example, the controller 200 may estimate the magnitude of the offset current I_OFF for compensating for the process variation of the memory device 100 in the operation of reading the memory device 100, and will report the estimated offset current I_OFF The information is provided to the memory device 100. The information about the estimated offset current I_OFF may be stored in a non-volatile memory (NVM) device (for example, NVM in FIG. 7B) included in the memory device 100, and the control circuit The 160 may generate the control signal CTRL based on the information of the estimated offset current I_OFF stored in the non-volatile memory device.

When the reference resistance R _REF of the reference resistance circuit 130 is adjusted to compensate for variations in the resistance of the variable resistance element included in the memory cell M due to a change in PVT or the like, the resistance can be quantized due to the limited resistance of the adjustable, And thus the accuracy of the compensation can be degraded. In addition, to provide a plurality of adjustable reference resistors, the reference resistor circuit 130 can include a plurality of resistors and switching devices, and thus the space consumption and power consumption caused by the reference resistor circuit 130 can be increased. On the other hand, in the case where the variation of the resistance of the variable resistance element included in the storage unit M is compensated by the offset current I_OFF of the offset current circuit 140, due to the offset current I_OFF based on the simple structure as described below Continuous characteristics, so it is expected to achieve very accurate compensation.

2 is a diagram illustrating an example of the storage unit M illustrated in FIG. 1 according to an exemplary embodiment, and FIG. 3 is a diagram illustrating a dispersion of resistance provided by the storage unit M illustrated in FIG. 2, according to an exemplary embodiment. Figure. More specifically, FIG. 2 illustrates a memory cell M' including a magnetic tunnel junction (MTJ) element as a variable resistance element, and FIG. 3 illustrates dispersion of resistance of the variable resistance element MTJ of FIG.

As shown in FIG. 2, the memory cell M' may include a variable resistance element MTJ and a cell transistor CT which are connected in series to each other between the bit line BLj and the source line SLj. In some exemplary embodiments, the variable resistance element MTJ and the unit transistor CT may be connected between the bit line BLj and the source line SLj in the stated order, as shown in FIG. 2, and in some exemplary embodiments. The order of the unit cell transistor CT and the variable resistance element MTJ is connected to each other between the bit line BLj and the source line SLj as shown in FIG.

The variable resistance element MTJ may include a free layer FL and a pinned layer PL, and may include a barrier layer BL between the free layer FL and the pinned layer PL. As indicated by the arrows in FIG. 2, the magnetization direction of the pinned layer PL may be fixed, and the free layer FL may have the same or opposite magnetization direction as the magnetization direction of the pinned layer PL. When the pinned layer PL has the same magnetization direction as the free layer FL, the variable resistance element MTJ may be referred to as being in the parallel state P. Meanwhile, when the pinned layer PL and the free layer FL have opposite magnetization directions, the variable resistance element MTJ may be referred to as being in the anti-parallel state AP. In some exemplary embodiments, the variable resistance element MTJ may further include an antiferromagnetic layer such that the pinned layer PL has a fixed magnetization direction.

The variable resistance element MTJ may have a relatively low resistance R _P in the parallel state _P and a relatively high resistance R _AP in the anti-parallel state _AP . In the present specification, it is assumed that the memory cell M' stores '0' when the variable resistance element MTJ in the parallel state P has a low resistance R _P , and the variable resistance element MTJ in the anti-parallel state AP has a high resistance R _AP The storage unit M' stores '1'. Further, in the present specification, the resistor R _P corresponding to '0' may be referred to as a parallel resistor R _P , and the resistor R _AP corresponding to '1' may be referred to as an anti-parallel resistor R _AP .

The unit transistor CT may include a gate connected to the word line WLi and a source and a drain connected to the source line SLj and the variable resistance element MTJ. The unit transistor CT can electrically and disconnect the variable resistance element MTJ and the source line SLj in accordance with a signal applied to the word line WLi. For example, to write '0' to the memory cell M' in a write operation, the cell transistor CT can be turned on, and the current from the bit line BLj to the source line SLj can flow through the variable resistor. Element MTJ and unit transistor CT. In addition, to write '1' to the memory cell M', the cell transistor CT can be turned on, and current from the source line SLj to the bit line BLj can flow through the cell transistor CT and the variable resistance element MTJ. In the read operation, the cell transistor CT may be turned on and the current from the bit line BLj to the source line SLj or the current from the source line SLj to the bit line BLj (ie, the first read current I_RD1) may be The unit transistor CT and the variable resistance element MTJ flow through. It is assumed herein that the first read current I_RD1 flows from the source line SLj to the bit line BLj.

Referring to FIG. 3, the resistance of the variable resistance element MTJ may be dispersed. For example, as shown in FIG. 3, there may be a distributed parallel resistance R _P having an average value of R _P ' in a storage unit storing '0', and an average value may exist in a storage unit storing '1'. a dispersed antiparallel resistance R _{AP of} R _AP ' or R _AP ". In addition, there may be a dispersion of the average value between the dispersed parallel resistance R _P and the dispersed antiparallel resistance R _AP 'R _REF ' Resistor R _REF . As shown in FIG. 3, due to the characteristics of the reference resistor circuit 130, the reference resistor R _REF may have a relatively good dispersion, that is, a relatively low dispersion of the resistances R _P and R _{AP of the} variable resistance element MTJ. In some exemplary embodiments, as shown in FIG. 3, the anti-parallel resistance R _AP may have a relatively degraded dispersion, that is, a dispersion that is relatively higher than a dispersion of the parallel resistance R _P .

In the example shown in FIG. 3, the anti-parallel resistance R _AP of the variable resistance element MTJ may decrease as the temperature of the variable resistance element MTJ rises. Additionally, this variation can be more pronounced for the anti-parallel resistance R _AP than for the parallel resistance R _P . For example, as indicated by the arrow in FIG. 3, the dispersion of the antiparallel resistance R _AP at a low temperature may shift to the left toward the dispersion of the antiparallel resistance R _AP at a high temperature as the temperature increases, and the antiparallel resistance The average value of the R _AP can be shifted from R _AP ' to R _AP '. Therefore, the sensing margin for detecting the anti-parallel resistance R _AP using the reference resistor R _REF at a high temperature can be reduced, and for example, As indicated by the broken line in FIG. 3, the dispersion of the reference resistance R _REF may partially overlap with the dispersion of the anti-parallel resistance R _AP .

The dispersion of the reference resistance R _REF can be shifted to the left at a high temperature, so that the '1' stored in the storage unit M' can be accurately read even at a high temperature. As set forth above with reference to FIG. 1, the dispersion of the reference resistor R _REF is shifted to the left at a high temperature, the reference resistor R _REF reference resistor circuit 130 can be reduced, and the magnitude of the reference current according to the I_REF offset current I_OFF And decrease. In other words, since the value stored in the memory cell M' is determined based on the read voltage V_RD and the reference voltage V_REF, a decrease in the reference voltage V_REF due to a decrease in the reference current I_REF may be caused and will be referred to The effect of the dispersion of the resistance R _REF shifting to the left has the same effect. Although FIG. 3 exemplifies a change in resistance of the variable resistance element MTJ with temperature, it is also possible to compensate for the resistance of the variable resistance element MTJ by adjusting the reference current I_REF in a manner similar to the case of temperature. Other factors of change (for example, process and supply voltage).

Hereinafter, with reference to FIGS. 4 to 6, an example of the memory device 100 shown in FIG. 1 in the reading operation will be explained. In the examples shown in FIGS. 4 to 6, the offset current I_OFF may have a positive value or a negative value. In other words, the reference current I_REF may be equal to the sum of the second read current I_RD2 and the offset current I_OFF, as shown in Equation 1 below. [Equation 1] I_REF = I_RD2 + I_OFF

Therefore, the positive offset current I_OFF may indicate that the reference current I_REF is generated as a current corresponding to the magnitude of the second read current I_RD2 plus the offset current I_OFF (ie, I_REF > I_RD2). Meanwhile, the negative offset current I_OFF may indicate that the reference current I_REF is generated as a current corresponding to the magnitude of the offset current I_OFF extracted from the second read current I_RD2 (ie, I_REF < I_RD2). In addition, the magnitude of the offset current I_OFF can be zero according to the control signal CTRL.

FIG. 4 is a block diagram showing an example of the memory device 100 of FIG. 1 according to an exemplary embodiment. In detail, FIG. 4 illustrates the memory device 100a including the offset current circuit 140a between the reference unit R and the reference resistor circuit 130a. As shown in FIG. 4, the memory device 100a may include a cell array 110a, a current source circuit 120a, a reference resistance circuit 130a, an offset current circuit 140a, an amplification circuit 150a, and a row decoder 170a.

The cell array 110a may include a memory cell M and a reference cell R that are commonly connected to the word line WLi. The storage unit M can be connected to the bit line BLj and the source line SLj, and the reference unit R can be connected to the shorted bit line SBL and the shorted source line SSL. The bit line BLj, the source line SLj, the shorted bit line SBL, and the shorted source line SSL may extend to the row decoder 170a. The storage unit M may include a variable resistance element MTJ and a unit transistor CT connected in series between the bit line BLj and the source line SLj, and the reference unit R may include a connection to the short-circuit bit line SBL and the short-circuit source line SSL Unit transistor CT. Therefore, the short-circuit bit line SBL and the short-circuit source line SSL can be electrically short-circuited or disconnected by the unit transistor CT of the reference unit R, and such a reference unit R having no resistor can be referred to as a short-circuit unit.

To compensate for the voltage drop caused by the bit line BLj and the source line SLj connected to the memory cell M, a reference cell R connected to the short bit line SBL and the short source line SSL may be provided in the cell array 110a. As shown in FIG. 4, the reference unit R may be a short-circuit unit, and thus, the voltage drop caused by the variable resistance element MTJ of the memory unit M may be compared with the voltage drop caused by the reference resistance circuit 130a outside the unit array 110a. . The reference resistor circuit 130a located outside the cell array 110a can provide a reference resistor R _REF that is insensitive to PVT variations or the like due to space limitations and structural limitations of the cell array 110a, and thus can accurately adjust the reference by the reference current I_REF. Voltage V_REF.

The row decoder 170a can route the bit line BLj, the source line SLj, the short-circuit bit line SBL, and the short-circuit source line SSL in accordance with the row address COL. The row address COL can be generated from the address ADDR received from the controller 200 shown in FIG. 1, and the row decoder 170a can select the selected in the cell array 110a according to the row address COL to be selected according to the row address COL. At least some of the storage unit and the reference unit and the reference unit. For example, as shown in FIG. 4, the row decoder 170a may connect the bit line BLj of the memory cell M to the negative supply voltage VSS and the source line SLj to the current source circuit 120a. In addition, the row decoder 170a may connect the short-circuited bit line SBL of the reference unit R to a node connected to the reference resistance circuit 130a and the offset current circuit 140a, and connect the short-circuit source line SSL to the current source circuit 120a. Therefore, the first read current I_RD1 can flow to the negative power supply voltage VSS via the source line SLj, the memory unit M, and the bit line BLj, and the second read current I_RD2 can flow through the short-circuit source line SSL, the reference unit R, and the short circuit. The bit line SBL, and the reference current I_REF as the sum of the second read current I_RD2 and the offset current I_OFF may flow to the negative power supply voltage VSS via the reference resistance circuit 130a.

The amplifying circuit 150a is connectable to a node that outputs the first read current I_RD1 and the second read current I_RD2 from the current source circuit 120a and generates an output signal according to the voltage of the node (ie, the read voltage V_RD and the reference voltage V_REF) Q. The read voltage V_RD may be determined based on the resistance value of the variable resistance element MTJ of the memory cell M and the first read current I_RD1, and the reference voltage V_REF may be determined based on the reference resistance value R _REF and the reference current I_REF. The amplifying circuit 150a may generate an output signal Q corresponding to '1' when the read voltage V_RD is higher than the reference voltage V_REF, and may generate an output signal Q corresponding to '0' when the read voltage V_RD is lower than the reference voltage V_REF.

The offset current circuit 140a may include a first current source 141a for providing a source current I_SC and a second current source 142a for providing a sink current I_SK. Therefore, the offset current I_OFF can be equal to the difference between the source current I_SC and the sink current I_SK, as shown in Equation 2 below. [Equation 2] I_OFF = I_SC - I_SK

The first current source 141a and/or the second current source 142a may adjust the source current I_SC and/or the sink current I_SK according to the control signal CTRL to adjust the offset current I_OFF. In some exemplary embodiments, the offset current circuit 140a may include only one of the first current source 141a and the second current source 142a, as explained below with reference to FIGS. 8B and 8C.

FIG. 5 is a block diagram illustrating an example of the memory device 100 of FIG. 1 in accordance with an exemplary embodiment. In detail, FIG. 5 illustrates the memory device 100b including the offset current circuit 140b between the current source circuit 120b and the reference unit R. As shown in FIG. 5, the memory device 100b may include a cell array 110b, a current source circuit 120b, a reference resistance circuit 130b, an offset current circuit 140b, an amplification circuit 150b, and a row decoder 170b. Hereinafter, the same description as that of FIG. 4 will be omitted.

Since the offset current circuit 140b is provided between the current source circuit 120b and the reference unit R, the reference current I_REF generated when the offset current I_OFF is reflected to the second read current I_RD2 can be via the short-circuit source line SSL, reference The cell R, the short-circuit bit line SBL, and the reference resistance circuit 130b flow to the negative power supply voltage VSS. The offset current circuit 140b may include a first current source 141b for supplying the source current I_SC and a second current source 142b for providing the sink current I_SK, and the offset current I_OFF may be determined as shown in Equation 2. The first current source 141b and/or the second current source 142b may adjust the source current I_SC and/or the sink current I_SK according to the control signal CTRL to adjust the offset current I_OFF. In some exemplary embodiments, unlike the one shown in FIG. 5, the offset current circuit 140b may include only one of the first current source 141b and the second current source 142b.

FIG. 6 is a block diagram showing an example of the memory device 100 of FIG. 1 according to an exemplary embodiment. In detail, FIG. 6 illustrates the memory device 100c including the offset current circuit 140c between the reference unit R and the reference resistance circuit 130c. Compared with the memory device 100b shown in FIG. 5, the reference resistance circuit 130c may be disposed between the current source circuit 120c and the reference unit R instead of between the reference unit R and the negative power supply voltage VSS. As shown in FIG. 6, the memory device 100c may include a cell array 110c, a current source circuit 120c, a reference resistance circuit 130c, an offset current circuit 140c, an amplification circuit 150c, and a row decoder 170c. Hereinafter, the same description as that of FIGS. 4 and 5 will be omitted.

Since the offset current circuit 140c is provided between the current source circuit 120c and the reference resistance circuit 130c, the reference current I_REF generated when the offset current I_OFF is reflected to the second read current I_RD2 can be short-circuited via the reference resistance circuit 130c. The source line SSL, the reference unit R, and the shorted bit line SBL flow to the negative power supply voltage VSS. The offset current circuit 140c may include a first current source 141c for supplying the source current I_SC and a second current source 142c for providing the sink current I_SK, and the offset current I_OFF may be determined as shown in Equation 2. The first current source 141c and/or the second current source 142c may adjust the source current I_SC and/or the sink current I_SK according to the control signal CTRL, thereby adjusting the offset current I_OFF. In some exemplary embodiments, unlike the one shown in FIG. 6, the offset current circuit 140c may include only one of the first current source 141c and the second current source 142c.

7A through 7D are block diagrams showing an example of the control circuit 160 of Fig. 1 in accordance with an exemplary embodiment. As explained above with reference to FIG. 1, the control circuits 160a, 160b, 160c, and 160d shown in FIGS. 7A through 7D can respectively generate the control signal CTRL, and the offset current I_OFF generated by the offset current circuit 140 can be based on the control signal CTRL. Take control. Hereinafter, FIGS. 7A to 7D will be explained with reference to FIG. 1.

Referring to FIG. 7A, the control circuit 160a may include a first signal generator 161a, a second signal generator 162a, and a combination circuit 163a and may be based on a signal whose magnitude may vary with changes in PVT (eg, voltage, current, etc.). A control signal CTRL is generated. In some exemplary embodiments, the first signal generator 161a may generate a first signal SIG1 whose magnitude is proportional to temperature, and the second signal generator 162a may generate a second signal SIG2 whose magnitude is inversely proportional to temperature. In some exemplary embodiments, the first signal generator 161a may generate a first signal SIG1 whose magnitude is proportional to a supply voltage (eg, a positive supply voltage VDD), and the second signal generator 162a may generate a magnitude and a positive value The power supply voltage VDD is inversely proportional to the second signal SIG2. The combining circuit 163a may generate the control signal CTRL as a weighted sum of the first signal SIG1 and the second signal SIG2 according to the first weight w1 and the second weight w2. The first weight w1 and the second weight w2 of the combination circuit 163a may be determined according to the variation characteristics of the resistance of the storage unit M.

Referring to FIG. 7B, the control circuit 160b may include the non-volatile memory 161b and may receive the process information P_INFO. For example, the process information P_INFO can be generated from the process of manufacturing the memory device 100 shown in FIG. 1, and the process information P_INFO can be provided during the process of manufacturing the memory device 100. The control circuit 160b can store the process information P_INFO in the non-volatile memory 161b and can generate the control signal CTRL based on the process information P_INFO stored in the non-volatile memory 161b during the operation of reading the memory device 100. . In some exemplary embodiments, the process information P_INFO may include information about the offset current I_OFF, and the control circuit 160b may generate the control signal CTRL based on the information about the offset current I_OFF.

Referring to FIG. 7C, the control circuit 160c may include a lookup data table 161c and may receive the sensing signal SEN. The sensing signal SEN is a signal generated by sensing an operating environment of the memory device 100 and may be an analog signal or a digital signal. For example, the sensing signal SEN may be generated when a temperature sensor included in the memory device 100 senses the temperature of the memory device 100, or provided by a voltage sensor pair included in the memory device 100. This is generated when the power supply voltage of the memory device 100 is sensed. The lookup data table 161c may include mapping information on the sensing signal SEN and the control signal CTRL, and thus the control circuit 160c generates a control signal CTRL corresponding to the received sensing signal SEN by referring to the lookup data table 161c.

Referring to FIG. 7D, the control circuit 160d may include a signal processing circuit 161d and may receive the sensing signal SEN. As explained above with reference to FIG. 7C, the sense signal SEN may be a signal generated by sensing an operating environment of the memory device 100. In some exemplary embodiments, the sense signal SEN may be an analog signal and the signal processing circuit 161d may generate the control signal CTRL by amplifying or attenuating the sense signal SEN. In some exemplary embodiments, the sense signal SEN may be a digital signal and the signal processing circuit 161d may generate the control signal CTRL by calculating or converting the sense signal SEN.

8A, 8B, and 8C are block diagrams illustrating an example of the offset current circuit 140 of FIG. 1 in accordance with an exemplary embodiment. As explained above with reference to FIG. 1, the offset current circuit 140d shown in FIG. 8A, the offset current circuit 140e shown in FIG. 8B, and the offset current circuit 140f shown in FIG. 8C can respectively generate magnitudes that are adjusted according to the control signal CTRL. Offset current I_OFF. Hereinafter, FIG. 8A, FIG. 8B, and FIG. 8C will be explained with reference to FIG. 1.

Referring to FIG. 8A, in some exemplary embodiments, the offset current circuit 140d can include two current sources. For example, as shown in FIG. 8A, the offset current circuit 140d may include a PMOS transistor PT for generating a source current I_SC and an NMOS transistor NT for generating a sink current I_SK. The PMOS transistor PT may include a gate for receiving the first control signal CTRL1 from the control circuit 160e, a source connected to the positive supply voltage VDD, and a drain connected to the NMOS transistor NT. In addition, the NMOS transistor NT may include a gate for receiving the second control signal CTRL2 from the control circuit 160e, a source connected to the negative supply voltage VSS, and a drain connected to the PMOS transistor PT. The offset current I_OFF can be output through a node connected to the drain of the PMOS transistor PT and the drain of the NMOS transistor NT, and therefore, as shown in FIG. 8A, the offset current I_OFF can be the same as the source current I_SC and the sink current I_SK. Difference. The control circuit 160e may generate a reference current I_REF greater than the positive offset current I_OFF (ie, the second read current I_RD2) based on the first control signal CTRL1 and the second control signal CTRL2, and may also generate a negative offset current I_OFF (ie, , a reference current I_REF) smaller than the second read current I_RD2.

Referring to Figure 8B, in some exemplary embodiments, the offset current circuit 140e can include a current source. For example, as shown in FIG. 8B, the offset current circuit 140e may include a PMOS transistor PT for generating a source current I_SC. The PMOS transistor PT may include a gate for receiving the control signal CTRL from the control circuit 160f, a source connected to the positive power supply voltage VDD, and a drain for outputting the offset current I_OFF. Therefore, the offset current I_OFF can be the same as the source current I_SC. In some exemplary embodiments, when the variable resistance element included in the storage unit M has a positive temperature coefficient and the reference resistance R _REF is configured to have a variable resistance element suitable for determining at a low temperature (eg, room temperature) At the magnitude of the resistance, the control circuit 160f can increase the magnitude of the offset current I_OFF by decreasing the voltage of the control signal CTRL as the temperature rises. Therefore, the magnitude of the reference current I_REF can be increased at a high temperature and thus the reference voltage V_REF can be increased.

Referring to Figure 8C, in some exemplary embodiments, the offset current circuit 140f can include a current source. For example, as shown in FIG. 8C, the offset current circuit 140f may include an NMOS transistor NT for generating a sink current I_SK. The NMOS transistor NT may have a gate for receiving the control signal CTRL from the control circuit 160g, a source connected to the negative power supply voltage VSS, and a drain for outputting the offset current I_OFF. Therefore, the offset current I_OFF may have the same magnitude as the sink current I_SK and may have a direction opposite to the direction of the sink current I_SK. In some exemplary embodiments, when the variable resistance element included in the storage unit M has a negative temperature coefficient and the reference resistance R _REF is configured to have a variable resistance element suitable for determining at a low temperature (eg, room temperature) At the magnitude of the resistance, the control circuit 160g can increase the magnitude of the offset current I_OFF by increasing the voltage of the control signal CTRL as the temperature increases. Therefore, the magnitude of the reference current I_REF can be reduced at a high temperature and thus the reference voltage V_REF can be lowered.

FIG. 9 is a flowchart of a method of operating a memory device, according to an exemplary embodiment. In detail, FIG. 9 illustrates an example of a read operation performed by the memory device in response to a read command. In some exemplary illustrated examples, the method illustrated in FIG. 9 may be performed by the memory device 100 illustrated in FIG. 1, and hereinafter, FIG. 9 will be illustrated with reference to FIG.

In operation S200, an operation of generating the first read current I_RD1 and the second read current I_RD2 may be performed. For example, the current source circuit 120 of the memory device 100 can generate the first read current I_RD1 and the second read current I_RD2 in response to the read command. The first read current I_RD1 may be supplied to the memory cell M of the cell array 110 and at least a portion of the second read current I_RD2 may be provided to the reference cell R of the cell array 110. In some exemplary embodiments, the first read current I_RD1 and the second read current I_RD2 may have substantially the same magnitude.

In operation S400, an operation for generating an offset current I_OFF according to a change in resistance of the storage unit M may be performed. For example, the control signal CTRL may be generated based on the process of manufacturing the memory device 100, the operating environment of the memory device 100 (eg, power supply voltage and temperature), etc. to compensate for variations in the resistance of the memory cell M, and offset. The current circuit 140 can generate the offset current I_OFF according to the control signal CTRL. The reference current I_REF can be generated by increasing or decreasing the second read current I_RD2 with the offset current I_OFF.

In operation S600, an operation for generating the read voltage V_RD and the reference voltage V_REF may be performed. For example, when the first read current I_RD1 flows through the memory cell M, the read voltage V_RD can be generated. In addition, in some exemplary embodiments, the reference voltage V_REF may be generated when the second read current I_RD2 flows through the reference cell R and the reference current flows through the reference resistance circuit 130. In some exemplary embodiments, the reference voltage V_REF may be generated when the reference current I_REF flows through the reference unit R and the reference resistance circuit 130.

In operation S800, an operation for determining a value stored in the storage unit M may be performed. For example, the amplifying circuit 150 can receive the read voltage V_RD and the reference voltage V_REF, compare the read voltage V_RD with the reference voltage V_REF, and generate an output corresponding to the value stored in the storage unit M. When the change in the resistance of the memory cell M is reflected to the reference voltage V_REF by the offset current I_OFF, the value stored in the memory cell M can be accurately read.

FIG. 10 is a block diagram showing a system die (SoC) 300 including a memory device in accordance with an exemplary embodiment. System wafer 300 may refer to an integrated circuit that integrates elements of a computing system or elements of other electronic systems. For example, as an example of system wafer 300, an application processor (AP) can include a processor and components for other functions. As shown in FIG. 10, the system chip 300 can include a core 310, a digital signal processor (DSP) 320, a graphics processing unit (GPU) 330, internal memory 340, a communication interface 350, and/or The storage interface 360. The various components of system wafer 300 can communicate with each other through bus bar 370.

Core 310 can process the instructions and can control the operation of the various components included in system wafer 300. For example, core 310 can drive an operating system and execute applications on the operating system by processing a series of instructions. The DSP 320 can generate useful data by processing digital signals (e.g., digital signals provided by the communication interface 350). The GPU 330 can generate or encode image data of an image to be output through the display device from image data supplied from the internal memory 340.

Internal memory 340 can store data for running core 310, DSP 320, and GPU 330. The internal memory 340 may include a resistive memory device according to an exemplary embodiment, and thus the internal memory 340 may exhibit high operational reliability by compensating for variations in the variable resistive element.

Communication interface 350 can provide a communication network or interface for one-to-one communication. The storage interface 360 can provide an interface for external memory (eg, dynamic random access memory (DRAM), flash memory, etc.) of the system chip 300.

FIG. 11 is a block diagram showing a memory system 400 including a memory device in accordance with an exemplary embodiment. As shown in FIG. 11, the memory system 400 can communicate with the host 500 and can include a controller 410 and a memory device 420.

The interface 600 used by the memory system 400 and the host 500 to communicate with each other may use electrical signals and/or optical signals, and may include, but is not limited to, a serial advanced technology attachment (SATA) interface, SATA fast ( SATA express, SATAe) serial attached small computer system interface (serial attached SCSI; SAS), peripheral component interconnect express (PCIe) interface, non-volatile storage fast (non - volatile memory express, NVMe) interface, advanced host controller interface (AHCI) or a combination thereof.

In some exemplary embodiments, memory system 400 can communicate with host 500 by being removably coupled to host 500. As a resistive memory, the memory device 420 can be a non-volatile memory, and the memory system 400 can be referred to as a storage system. For example, the memory system 400 can include, but is not limited to, a solid state drive or a solid state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded multimedia card. (embedded multimedia card, eMMC) and so on.

Controller 410 can control memory device 420 in response to a request received from host 500 via interface 600. For example, in response to the write request, the controller 410 can write the data received in association with the write request to the memory device 420, and the data stored in the memory device 420 in response to the read request. Provided to the host 500.

The memory system 400 can include at least one memory device 420 and the memory device 420 can include a reference unit and a storage unit having variable resistance elements. As explained above with reference to the exemplary embodiments, the manufacturing process by the memory device 420 and the memory device 420 or the memory system can be simply and accurately compensated by adjusting the reference current flowing through the reference resistor connected to the reference cell. A change in the resistance of the storage unit caused by the operating environment of 400. Therefore, the memory device 420 can accurately supply the value stored in the storage unit to the controller 410 in response to the read command of the controller 410, thereby improving the operational reliability of the memory system 400.

While the present invention has been particularly shown and described with reference to the exemplary embodiments of the embodiments of the present invention, it is understood that various forms and details may be made herein without departing from the spirit and scope of the claims change.

100, 100a, 100b, 100c, 420‧‧‧ memory devices

110, 110a, 110b, 110c‧‧‧ unit array

120, 120a, 120b, 120c‧‧‧ current source circuit

130, 130a, 130b, 130c‧‧‧ reference resistance circuit

140, 140a, 140b, 140c, 140d, 140e, 140f‧‧‧ offset current circuit

141a, 141b, 141c‧‧‧ first current source

142a, 142b, 142c‧‧‧ second current source

150, 150a, 150b, 150c‧‧‧ amplifying circuit

160, 160a, 160b, 160c, 160d, 160e, 160f, 160g‧‧‧ control circuit

161a‧‧‧First signal generator

161b‧‧‧Non-volatile memory

161c‧‧‧Check the data sheet

161d‧‧‧Signal Processing Circuit

162a‧‧‧Second signal generator

163a‧‧‧Combined circuit

170a, 170b, 170c‧‧‧ row decoder

200‧‧‧ controller

300‧‧‧System Chip

310‧‧‧nuclear

320‧‧‧Digital Signal Processor (DSP)

330‧‧‧Graphical Processing Unit (GPU)

340‧‧‧ internal memory

350‧‧‧Communication interface

360‧‧‧ Storage interface

370‧‧ ‧ busbar

400‧‧‧ memory system

410‧‧‧ Controller

500‧‧‧Host

600‧‧‧ interface

ADDR‧‧‧ address

BL‧‧‧ barrier layer

BLj‧‧‧ bit line

CMD‧‧‧ Order

CT‧‧‧ unit transistor

CTRL‧‧‧ control signal

CTRL1‧‧‧ first control signal

CTRL2‧‧‧second control signal

COL‧‧‧ address

DATA‧‧‧Information

FL‧‧‧ free layer

I_RD1‧‧‧First read current

I_RD2‧‧‧second read current

I_REF‧‧‧reference current

I_SC‧‧‧ source current

I_SK‧‧‧ sink current

I_OFF‧‧‧Offset current / positive offset current / negative offset current

M, M'‧‧‧ storage unit

MTJ‧‧‧Variable Resistive Components

N1‧‧‧ first node

N2‧‧‧ second node

NT‧‧‧NMOS transistor

PL‧‧‧ pinned layer

PT‧‧‧PMOS transistor

P_INFO‧‧‧Process Information

Q‧‧‧Output signal

R‧‧‧ reference unit

RAP‧‧‧antiparallel resistance / resistance / high resistance

RAP', RAP'', RP', RREF'‧‧‧ average

RP‧‧‧parallel resistance/resistance/low resistance

RREF‧‧‧reference resistor/reference resistor value

S200, S400, S600, S800‧‧‧ operations

SBL‧‧‧Short bit line

SEN‧‧‧Sensor signal

SIG1‧‧‧ first signal

SIG2‧‧‧ second signal

SLj‧‧‧ source line

SSL‧‧‧Short-circuit source line

VDD‧‧‧ positive supply voltage

V_RD‧‧‧Read voltage

V_REF‧‧‧reference voltage

VSS‧‧‧negative supply voltage

W1‧‧‧ first weight

W2‧‧‧ second weight

WLi‧‧‧ character line

BRIEF DESCRIPTION OF THE DRAWINGS Exemplary embodiments of the present invention will be more clearly understood from the following detailed description of the embodiments of the invention. FIG. 1 is a block diagram showing a memory device and a controller according to an exemplary embodiment. 2 is a block diagram illustrating an example of the storage unit of FIG. 1 in accordance with an exemplary embodiment. FIG. 3 is a graph illustrating dispersion of resistance provided by the storage unit of FIG. 2, according to an exemplary embodiment. FIG. 4 is a block diagram showing an example of the memory device of FIG. 1 according to an exemplary embodiment. FIG. 5 is a block diagram showing an example of the memory device of FIG. 1 according to an exemplary embodiment. FIG. 6 is a block diagram showing an example of the memory device of FIG. 1 according to an exemplary embodiment. 7A, 7B, 7C, and 7D are block diagrams showing an example of the control circuit of Fig. 1 according to an exemplary embodiment. 8A, 8B, and 8C are block diagrams showing an example of the offset current circuit of FIG. 1 according to an exemplary embodiment. FIG. 9 is a flowchart of a method of operating a memory device, according to an exemplary embodiment. FIG. 10 is a block diagram showing a system-on-chip (SoC) including a memory device according to an exemplary embodiment. 11 is a block diagram showing a memory system including a memory device in accordance with an exemplary embodiment.

Claims (10)

A resistive memory device configured to output a value stored in a storage unit in response to a read command, the resistive memory device comprising: a cell array including the storage unit and a reference unit; a reference resistance circuit, Configuring to be electrically connected to the reference unit; an offset current source circuit configured to add an offset current to a read current supplied to the reference resistor circuit or from a portion supplied to the reference resistor circuit The read current draws the offset current; and a control circuit configured to control the offset current source circuit to compensate for a change in resistance of the storage unit. The resistive memory device of claim 1, wherein the control circuit is further configured to adjust a magnitude of the offset current based on a temperature of the resistive memory device. The resistive memory device of claim 2, wherein the offset current source circuit is further configured to adjust the magnitude of the offset current according to a control signal, the control circuit comprising: a first signal generator configured to generate a first signal proportional to temperature; a second signal generator configured to generate a second signal inversely proportional to temperature; and a combination circuit configured to convert the control signal Generating a weighted sum of the first signal and the second signal; wherein the weight of the weighted sum is determined according to a temperature change characteristic of the resistance of the storage unit. The resistive memory device of claim 2, wherein the offset current source circuit is further configured to adjust the magnitude of the offset current according to a control signal, and the control circuit A lookup data sheet is included and is further configured to generate the control signal from the temperature signal based on the temperature of the resistive memory device by reference to the lookup data table. The resistive memory device of claim 1, further comprising: a non-volatile memory configured to be accessed by the control circuit and to store processing information, wherein the control circuit is further configured The magnitude of the offset current is adjusted based on the processing information. The resistive memory device of claim 1, wherein the control circuit is further configured to adjust the amount of the offset current based on a magnitude of a positive power supply voltage of the resistive memory device. value. A resistive memory device configured to output a value stored in a storage unit in response to a read command, the resistive memory device comprising: a cell array including the storage unit and a reference unit, a first read a current flows through the storage unit, a reference current flows through the reference unit; a current source circuit configured to generate the first read current and a second read current; and an offset current source circuit configured to pass The second read current plus an offset current or the offset current is drawn from the second read current to generate the reference current; and a control circuit configured to control the offset current source circuit Compensating for changes in the resistance of the storage unit. The resistive memory device of claim 7, further comprising: a reference resistor circuit electrically connected to the reference unit, and the reference current flows through the reference resistor circuit. The resistive memory device of claim 7, wherein the first read current and the second read current are the same. A resistive memory device configured to output a value stored in a storage unit in response to a read command, the resistive memory device comprising: a cell array including the storage unit and a reference unit, a first read a current flows through the storage unit, a second read current flows through the reference unit; an offset current source circuit configured to add an offset current to the second read current or read from the second Taking a current to draw the offset current to generate a reference current; a reference resistance circuit configured to be electrically connected to the reference unit, and the reference current flowing through the reference resistance circuit; and a control circuit configured to control the An offset current source circuit is provided to compensate for variations in the resistance of the storage unit.