JP6660745B2 - Reference current generation circuit and memory device - Google Patents

Description

  The present invention relates to a reference current generation circuit that generates a reference current, and a memory device including the reference current generation circuit.

  2. Description of the Related Art A nonvolatile semiconductor memory device capable of storing data of three or more values in each memory cell of a nonvolatile semiconductor memory is known (for example, see Patent Document 1). In this nonvolatile semiconductor memory device, by comparing the magnitude of the current read from the memory cell with a plurality of reference currents having different current values, the value of the read multi-value data is determined, The read data having that value is output. Therefore, such a nonvolatile semiconductor memory device is provided with a reference current generator for generating a plurality of reference currents having different current values.

  Here, if the reference current fluctuates due to a change in the environmental temperature, a normal data value cannot be determined.

  Therefore, a first current generator that generates a first current with a positive temperature characteristic in which the current value increases as the temperature rises, and generates a second current with a negative temperature characteristic in which the current value decreases as the temperature rises. A current source circuit has been proposed in which a second current generating unit is provided, and a current having a desired temperature characteristic can be generated by combining the first and second currents (for example, Patent Document 2). reference).

JP 2004-241083 A JP 2004-30041 A

  In the above-described current source circuit, the rate of change (increase rate, decrease rate) of the current value with the temperature increase is determined by the resistance elements provided in each of the first and second current generating units. Therefore, if the resistance value of the resistance element varies due to a variation in manufacturing or the like, the rate of change of the current value due to the temperature increase will have an error with respect to the desired rate of change, and the desired temperature characteristic will be reduced. Current cannot be generated.

  Therefore, according to the present invention, even if the current read from a memory cell fluctuates due to a temperature change, it is possible to acquire read data from the memory cell with high read accuracy, and regardless of manufacturing variations, It is an object to provide a reference current generation circuit capable of generating a reference current having a desired temperature characteristic and a memory device including the reference current generation circuit.

The reference current generation circuit according to the present invention includes a positive temperature coefficient current source that generates a first current having an output current value that increases with a rise in temperature, and a second current source that outputs a second current that decreases with a rise in temperature. A negative temperature coefficient current source that generates a current, a first current adjustment unit that generates a current obtained by changing a current value of the first current according to a first adjustment set value as a positive temperature characteristic current, A second current adjustment unit that generates a current obtained by changing the current value of the second current according to the second adjustment set value as a negative temperature characteristic current, and the positive temperature characteristic current and the negative temperature characteristic current are combined. An output unit that outputs a current as a reference current.

  Further, the reference current generating circuit according to the present invention has a positive temperature coefficient current source that generates a first current whose current value increases as the temperature rises, and a negative current source that generates a second current whose current value decreases as the temperature rises. A temperature coefficient current source, a first current adjusting unit that generates a current obtained by adjusting the current value of the first current according to a first adjustment set value as a first positive temperature characteristic current, and the second current A second current adjusting unit that generates a current obtained by adjusting the current value of the first current according to the second adjustment set value as a first negative temperature characteristic current; and a current value of the first current that is adjusted according to a third adjustment signal. A third current adjusting unit that generates the adjusted current as a second positive temperature characteristic current; and a current that adjusts the current value of the second current according to a fourth adjustment signal as a second negative temperature characteristic current. A fourth current adjusting unit that generates the first positive temperature characteristic current and A first output unit that outputs a current obtained by combining the first negative temperature characteristic current as a first reference current, and a second output unit that outputs the current obtained by combining the second positive temperature characteristic current and the second negative temperature characteristic current. And a second output unit for outputting the reference current as a reference current.

In addition, a memory device according to the present invention includes a memory cell array in which a plurality of memory cells are formed, a reference current generation circuit that generates a reference current, and a read current read from the memory cell and the reference current. A sense amplifier that determines a value of read data based on a result of the magnitude comparison, wherein the reference current generation circuit generates a first current having an output current value that increases with a rise in temperature. A positive temperature coefficient current source, a negative temperature coefficient current source that generates a second current having an output current value that decreases in accordance with the temperature rise, and a current value of the first current according to a first adjustment set value. the generating a first current adjusting unit for generating a current of changing a positive temperature coefficient current, the current is varied in accordance with the current value of the second current to the second adjustment setting value as a negative temperature characteristic current 2 current adjuster and front PTC current and having an output unit for outputting the synthesized current the negative temperature characteristic current as a reference current.

  The reference current generation circuit according to the present invention includes first and second current adjustments for individually adjusting current values for a current whose current value increases as the temperature rises and a current whose value decreases as the temperature rises. And a reference current is generated by combining the currents whose current values have been adjusted by the first and second current adjustment units. According to the first and second current adjustment units, it is possible to adjust the combined ratio of the current whose current value increases as the temperature rises and the current whose current value decreases as the temperature rises, and the current value of the reference current. Become.

  Therefore, according to such a configuration, even if a current source that generates a current whose current value increases as the temperature rises and a current whose current value decreases as the temperature rises has a manufacturing variation, the first and second current sources can be manufactured after manufacturing. By adjusting the current value in the second current adjustment unit, it is possible to obtain a reference current having a desired temperature characteristic and a desired current value for each product. Further, according to the memory device equipped with the reference current generation circuit, it is possible to acquire read data from the memory cell with high read accuracy even if the current read from the memory cell fluctuates due to a temperature change. Becomes

1 is a block diagram illustrating a schematic configuration of a memory device 200 including a reference current generation circuit 100 according to the present invention. FIG. 2 is a block diagram showing an example of an internal configuration of a reference current generation circuit 100. FIG. 3 is a circuit diagram showing a configuration of a positive temperature coefficient current source 11 including a band gap reference circuit having a positive temperature coefficient. It is a figure showing transition of current value to temperature change of current IP1, IP2, and Ir1. FIG. 3 is a circuit diagram showing a configuration of a negative temperature coefficient current source 12 including a band gap reference circuit having a negative temperature coefficient. It is a figure which shows transition of the current value with respect to the temperature change of current IM1, IM2, Ir2. FIG. 3 is a circuit diagram showing an internal configuration of current adjustment units 13 and 14 and a current amplification unit 16. FIG. 4 is a block diagram showing another example of the internal configuration of the reference current generation circuit 100.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a memory device 200 including a reference current generation circuit 100 according to the present invention. As shown in FIG. 1, the memory device 200 includes a reference current generation circuit 100, a memory cell array 101, a controller 102, a row driver 103, a column driver 104, and a sensor amplifier 105.

  In the memory cell array 101, a plurality of memory cells MC are arranged in a matrix along with n (n is an integer of 2 or more) word lines W1 to Wn and m (m is an integer of 2 or more) bit lines B1 to Bm. It is arranged and formed. Each memory cell MC is connected to one or two bit lines and one word line at each intersection of the word lines W1 to Wn and the bit lines B1 to Bm. The memory cell MC is, for example, a MOS (Metal Oxide Semiconductor) transistor having a control gate and a floating gate, and is a storage element that can write and read binary, ternary or higher multi-level data. For example, at the time of reading data, the memory cell MC connected to the bit line B1 sends a read current having a current value corresponding to the multi-value data stored therein to the bit line B1.

  The controller 102 generates a control signal for driving the word lines W1 to Wn and the bit lines B1 to Bm of the memory cell array 101 based on various memory control commands CMD including a read command or a write command. The controller 102 supplies the control signal to the row driver 103 and the column driver 104.

  The row driver 103 responds to the storage address specified by the address signal AD among the word lines W1 to Wn of the memory cell array 101 according to the address signal AD specifying the storage address and the control signal supplied from the controller 102. A word line voltage for selecting this word line is supplied to the selected word line.

  In response to the address signal AD and the control signal supplied from the controller 102, the column decoder 104, for example, sets a data read voltage for data read, a data write voltage for data write, a data write voltage for data erase, and a data erase voltage for the memory cell array 101. To the bit lines B1 to Bm.

The reference current generation circuit 100 generates one or two or more reference currents for determining multi-valued data of two or more values from the read current. For example, when the memory cell MC is a storage element that stores binary data, the reference current generating circuit 100 determines that the read current sent from the memory cell MC is one of the data values [0] and [1]. The reference current Iref1 is supplied to the sense amplifier 105 as a threshold value for determining which value corresponds. Further, for example, when the memory cell MC is a storage element capable of storing quaternary data, the reference current generation circuit 100 sets the read current to a data value of [00], [01], [10], and [11]. The reference currents Iref1 to Iref3 having different current values are supplied to the sense amplifier 105 as thresholds for determining which one of the two corresponds. The current values of the reference currents Iref1 to Iref3 have, for example, the following magnitude relationship.
Iref1 <Iref2 <Iref3
When the memory cell MC is, for example, a storage element for storing binary data, the sense amplifier 105 compares the read current flowing through the bit lines B1 to Bm of the memory cell array 101 with the reference current Iref1. At this time, for example, when the read current is larger than the reference current Iref1, the sense amplifier 105 outputs the read data DT indicating the data value [0]. The read data DT representing [1] is output.

  When the memory cell MC is a storage element that stores, for example, quaternary data, the sense amplifier 105 compares the read current with each of the reference currents Iref1 to Iref3. At this time, for example, when the read current is larger than the reference current Iref3, the sense amplifier 105 outputs the read data DT representing the data value [00]. When the read current is larger than reference current Iref2 and equal to or smaller than Iref3, sense amplifier 105 outputs read data DT representing data value [01]. When the read current is larger than reference current Iref1 and equal to or smaller than Iref2, sense amplifier 105 outputs read data DT representing data value [10]. When the read current is equal to or smaller than reference current Iref1, sense amplifier 105 outputs read data DT representing data value [11].

  Hereinafter, the reference current generation circuit 100 will be described in detail.

  FIG. 2 is a block diagram showing an internal configuration of the reference current generation circuit 100 employed when generating a single reference current Iref1. The configuration shown in FIG. 2 uses, for example, a reference current for determining which of the logical levels 0 and 1 the read current read from the memory cell MC storing the binary data has. It is used as a reference current generating circuit to generate.

  As shown in FIG. 2, the reference current generation circuit 100 includes a positive temperature coefficient current source 11, a negative temperature coefficient current source 12, current adjustment units 13 and 14, a current control unit 15, and a current amplification unit 16.

  The positive temperature coefficient current source 11 is configured by, for example, a band gap reference circuit having a positive temperature coefficient.

  FIG. 3 is a circuit diagram showing a configuration of the positive temperature coefficient current source 11 composed of a band gap reference circuit having a positive temperature coefficient. As shown in FIG. 3, the band gap reference circuit includes PNP transistors Q1 and Q2, n-channel MOS (metal-oxide semiconductor) transistors N1 to N4, p-channel MOS transistors P1 to P4, and a resistor R1. To R4.

  In FIG. 3, a ground voltage is applied to the base terminal and the collector terminal of the transistor Q1, and the emitter terminal is connected to one end of the resistor R1 and the source terminal of the transistor N1. A ground voltage is applied to the other end of the resistor R1. The drain terminal of the transistor N1 is connected to the source terminal of the transistor N2, and the gate terminal of the transistor N1 is connected to the drain terminal of the transistor N2 and the gate terminal of the transistor N3. The drain end of the transistor N2 is connected to one end of the resistor R2, and the gate end is connected to the other end of the resistor R2, the gate end of the transistor N4, and the drain end of the transistor P1. The source terminal of the transistor P1 is connected to the drain terminal of the transistor P2, and the gate terminal of the transistor P1 is connected to the line L1. The power supply voltage VCC is applied to the source terminal of the transistor P2, and the gate terminal thereof is connected to the line L2.

  In FIG. 3, a ground voltage is applied to the base terminal and the collector terminal of the transistor Q2, and the emitter terminal is connected to one end of the resistor R4. The other end of the resistor R4 is connected to the source end of the transistor N3 and one end of the resistor R3. A ground voltage is applied to the other end of the resistor R3. The drain end of the transistor N3 is connected to the source end of the transistor N4. The drain end of the transistor N4 is connected to the line L1 and one end of the resistor R5. The other end of the resistor R5 is connected to the drain end of the transistor P3 and the line L2. The source end of the transistor P3 is connected to the drain end of the transistor P4, and the gate end of the transistor P3 is connected to the line L1. A power supply voltage VCC is applied to a source terminal of the transistor P4, and a gate terminal thereof is connected to the line L2.

Note that the magnitude relationship between the resistance values of R1, R3 and R4 among the resistors R1 to R5 shown in FIG.
R1 = R4> R3
It is.

  As a result, the positive temperature coefficient current source 11 generates a pair of currents IP1 and IP2 whose current values increase as the environmental temperature increases, as shown in FIG. 4, and supplies the pair of currents IP1 and IP2 via the lines L1 and L2, respectively. To supply.

  The negative temperature coefficient current source 11 is configured by, for example, a band gap reference circuit having a negative temperature coefficient.

  FIG. 5 is a circuit diagram showing a configuration of the negative temperature coefficient current source 11 composed of a band gap reference circuit having a negative temperature coefficient.

  As shown in FIG. 5, the band gap reference circuit includes PNP transistors Q3 and Q4, n-channel MOS transistors N11 to N14, p-channel MOS transistors P11 to P14, and resistors R6 to R10.

  In FIG. 5, a ground voltage is applied to the base terminal and the collector terminal of the transistor Q3, and the emitter terminal is connected to one end of the resistor R6 and the source terminal of the transistor N11. A ground voltage is applied to the other end of the resistor R6. The drain terminal of the transistor N11 is connected to the source terminal of the transistor N12, and the gate terminal of the transistor N11 is connected to the drain terminal of the transistor N12 and the gate terminal of the transistor N13. The drain end of the transistor N12 is connected to one end of the resistor R7, and the gate end is connected to the other end of the resistor R7, the gate end of the transistor N14, and the drain end of the transistor P11. The source end of the transistor P11 is connected to the drain end of the transistor P12, and the gate end of the transistor P11 is connected to the line L11. A power supply voltage VCC is applied to a source terminal of the transistor P12, and a gate terminal thereof is connected to the line L2.

  In FIG. 5, a ground voltage is applied to the base terminal and the collector terminal of the transistor Q4, and the emitter terminal is connected to one end of the resistor R9. The other end of the resistor R9 is connected to the source end of the transistor N13 and one end of the resistor R8. A ground voltage is applied to the other end of the resistor R8. The drain terminal of the transistor N13 is connected to the source terminal of the transistor N14. The drain end of the transistor N14 is connected to the line L11 and one end of the resistor R10. The other end of the resistor R10 is connected to the drain end of the transistor P13 and the line L12. The source terminal of the transistor P13 is connected to the drain terminal of the transistor P14, and the gate terminal of the transistor P13 is connected to the line L11. The power supply voltage VCC is applied to the source terminal of the transistor P14, and the gate terminal is connected to the line L12.

The magnitude relationship between the resistance values of R6, R8 and R9 among the resistors R6 to R10 shown in FIG.
R6 = R8 = R9
It is.

  As a result, the negative temperature coefficient current source 12 generates a pair of currents IM1 and IM2 whose current values increase as the environmental temperature increases, as shown in FIG. 6, and respectively supplies the currents IM1 and IM2 via the lines L11 and L12. To supply.

  The current control unit 15 calculates the positive temperature coefficient current adjustment data indicating the adjustment set values for adjusting the current values of the currents IP1 and IP2 sent from the positive temperature coefficient current source 11, and the current sent from the negative temperature coefficient current source 12. A built-in register (not shown) for storing negative temperature coefficient current adjustment data indicating an adjustment set value for adjusting the current values of IM1 and IM2 is included. The current control unit 15 generates 4-bit current adjustment signals TP0 to TP3 corresponding to the adjustment set value indicated by the positive temperature coefficient current adjustment data stored in the internal register. Each of the current adjustment signals TP0 to TP3 is a binary signal having a logic level 0 or a logic level 1.

  For example, when the adjustment set value indicated by the positive temperature coefficient current adjustment data indicates a current value of zero, the current control unit 15 sets all of the current adjustment signals TP0 to TP3 to the logic level 1 and indicates a maximum current value. , All the current adjustment signals TP0 to TP3 are set to the logic level 0. When the adjustment set value represents a first adjustment current value that is one step larger than the current value of zero, the current control unit 15 sets only one of the current adjustment signals TP0 to TP3 to a logic level. When it is set to 0 and represents a second adjustment current value that is one step larger than the first adjustment current value, only two of the current adjustment signals TP0 to TP3 are set to the logic level 0. When the adjustment set value indicated by the positive temperature coefficient current adjustment data represents a third adjustment current value that is one step larger than the second adjustment current value, the current control unit 15 sets the current adjustment signal TP0 Only three of TP3 are set to logic level 0.

  The current control unit 15 supplies the current adjustment signals TP0 to TP3 described above to the current adjustment unit 13.

  Further, the current control unit 15 generates 4-bit current adjustment signals TM0 to TM3 based on the adjustment set value indicated by the negative temperature coefficient current adjustment data stored in the internal register.

  For example, when the adjustment set value indicated by the negative temperature coefficient current adjustment data indicates a current value of zero, the current control unit 15 sets all of the current adjustment signals TM0 to TM3 to the logic level 1 and indicates the maximum current value. , All the current adjustment signals TM0 to TM3 are set to the logic level 0. When the adjustment setting value represents the above-described first adjustment current value, the current control unit 15 sets only one of the current adjustment signals TM0 to TM3 to the logic level 0, and sets the first adjustment current When representing the second adjustment current value that is larger by one level than the value, only two of the current adjustment signals TM0 to TM3 are set to the logic level 0. When the adjustment set value indicated by the negative temperature coefficient current adjustment data represents a third adjustment current value that is one step larger than the second adjustment current value, the current control unit 15 outputs the current adjustment signals TM0 to TM0. Only three of TM3 are set to logic level 0.

  The current control unit 15 supplies the current adjustment signals TM0 to TM3 described above to the current adjustment unit 14.

  FIG. 7 is a circuit diagram showing the internal configurations of the current adjustment units 13 and 14 and the current amplification unit 16.

  The current adjustment unit 13 includes mirror current output units MP0 to MP3 that form a four-output current mirror circuit in combination with the transistors P3 and P4 of the positive temperature coefficient current source 11. The mirror current output units MP0 to MP3 have the same circuit configuration, that is, each has a current mirror unit including p-channel MOS transistors PQ1 and PQ2 and a mirror current synthesis unit including p-channel MOS transistor PQ3. .

  In each of the mirror current output units MP0 to MP3, the power supply voltage VCC is applied to the source terminal of the transistor PQ1, and the drain terminal is connected to the source terminal of the transistor PQ2. In each of the mirror current output units MP0 to MP3, the drain terminal of the transistor PQ2 is connected to the source terminal of the transistor PQ3. The gate terminal of the transistor PQ1 of each of the mirror current output units MP0 to MP3 is commonly connected to a line L2 of the positive temperature coefficient current source 11. The gate terminal of the transistor PQ2 of each of the mirror current output units MP0 to MP3 is commonly connected to the line L1 of the positive temperature coefficient current source 11. Further, the drain terminal of the transistor PQ3 of each of the mirror current output units MP0 to MP3 is commonly connected to the current combining line LM.

  The current adjustment signal TP0 is supplied to the gate terminal of the transistor PQ3 of the mirror current output unit MP0, and the current adjustment signal TP1 is supplied to the gate terminal of the transistor PQ3 of the mirror current output unit MP1. Have been. The current adjustment signal TP2 is supplied to the gate terminal of the transistor PQ3 of the mirror current output unit MP2, and the current adjustment signal TP3 is supplied to the gate terminal of the transistor PQ3 of the mirror current output unit MP3.

  At this time, the transistor PQ3 of the mirror current output unit MP0 is turned off when the current adjustment signal TP0 indicates the logic level 1, and is turned on when the current adjustment signal TP0 indicates the logic level 0. A mirror current Ia having a current value corresponding to a combined current of IP1 and current IP2 is sent to current combining line LM. The transistor PQ3 of the mirror current output unit MP1 is turned off when the current adjustment signal TP1 indicates the logic level 1, while it is turned on when the current adjustment signal TP1 indicates the logic level 0, and the mirror current Ia is sent to the current combining line LM. The transistor PQ3 of the mirror current output unit MP2 is turned off when the current adjustment signal TP2 indicates the logic level 1, and turned on when the current adjustment signal TP2 indicates the logic level 0, and the mirror current Ia is sent to the current combining line LM. The transistor PQ3 of the mirror current output unit MP3 is turned off when the current adjustment signal TP3 indicates the logic level 1, while it is turned on when the current adjustment signal TP3 indicates the logic level 0, and the mirror current Ia is sent to the current combining line LM.

  Therefore, of the mirror current output units MP0 to MP3, only the mirror current output unit whose transistor PQ3 is turned on in response to the current adjustment signals TP0 to TP3 sends out the mirror current Ia to the current combining line LM. . At this time, of the mirror current output units MP0 to MP3, no current is transmitted from the mirror current output unit whose transistor PQ3 is turned off. Accordingly, a current obtained by combining the mirror currents Ia sent from the mirror current output units MP0 to MP3, that is, a combined current of k · Ia (k: the number of transistors PQ3 in the on state) is supplied to the current combining line LM. It flows as the positive temperature characteristic current Ir1.

  That is, in the current adjustment unit 13, the current mirror unit including the transistors PQ1 and PQ2 of each of the mirror current output units MP0 to MP3 has a current (hereinafter referred to as a positive temperature characteristic) having a characteristic that the current value increases as the temperature increases. Four mirror currents Ia corresponding to (IP1 + IP2) are generated. Then, the mirror current synthesizing unit including the transistors PQ3 of the mirror current output units MP0 to MP3 corresponds to the adjustment setting value indicated by the first adjustment setting value (TP0 to TP3) among the four mirror currents Ia. A current obtained by combining a number of mirror currents Ia is generated as a positive temperature characteristic current Ir1.

  With the above-described configuration, the current adjusting unit 13 adjusts the current value of the current (IP1 + IP2) having the positive temperature characteristic generated by the positive temperature coefficient current source 11 according to the current adjustment signals TP0 to TP3. The positive temperature characteristic current Ir1 is sent to the current synthesis line LM.

  The current adjustment unit 14 includes mirror current output units MN0 to MN3 that form a four-output type current mirror circuit in combination with the transistors P13 and P14 of the negative temperature coefficient current source 12. The mirror current output units MN0 to MN3 have the same circuit configuration, that is, each includes p-channel MOS transistors NQ1 to NQ3.

  In each of the mirror current output units MN0 to MN3, the power supply voltage VCC is applied to the source terminal of the transistor NQ1, and the drain terminal is connected to the source terminal of the transistor NQ2. In each of the mirror current output units MN0 to MN3, the drain terminal of the transistor NQ2 is connected to the source terminal of the transistor NQ3. The gate terminal of the transistor NQ1 of each of the mirror current output units MN0 to MN3 is commonly connected to the line L12 of the negative temperature coefficient current source 12. The gate terminal of the transistor NQ2 of each of the mirror current output units MN0 to MN3 is commonly connected to the line L11 of the negative temperature coefficient current source 12. Further, the drain terminal of the transistor NQ3 of each of the mirror current output units MN0 to MN3 is commonly connected to a current combining line LM.

  The current adjustment signal TM0 is supplied to the gate terminal of the transistor NQ3 of the mirror current output unit MN0, and the current adjustment signal TM1 is supplied to the gate terminal of the transistor NQ3 of the mirror current output unit MN1. Have been. The current adjustment signal TM2 is supplied to the gate terminal of the transistor NQ3 of the mirror current output unit MN2, and the current adjustment signal TM3 is supplied to the gate terminal of the transistor NQ3 of the mirror current output unit MN3.

  At this time, the transistor NQ3 of the mirror current output unit MN0 is turned off when the current adjustment signal TM0 indicates the logic level 1, whereas it is turned on when the current adjustment signal TM0 indicates the logic level 0. A mirror current Ib having a current value corresponding to the combined current of IM1 and current IM2 is sent to the current combining line LM. Further, the transistor NQ3 of the mirror current output unit MN1 is turned off when the current adjustment signal TM1 indicates the logic level 1, while it is turned on when the current adjustment signal TM1 indicates the logic level 0, and the mirror current Ib is sent to the current combining line LM. Also, the transistor NQ3 of the mirror current output unit MN2 is turned off when the current adjustment signal TM2 indicates the logic level 1, and is turned on when the current adjustment signal TM2 indicates the logic level 0, so that the mirror current Ib is sent to the current combining line LM. Further, the transistor NQ3 of the mirror current output unit MN3 is turned off when the current adjustment signal TM3 indicates the logic level 1, and turned on when the current adjustment signal TM3 indicates the logic level 0, and the mirror current Ib is sent to the current combining line LM.

  Therefore, of the mirror current output units MN0 to MN3, only the mirror current output unit whose transistor NQ3 is turned on in response to the current adjustment signals TM0 to TM3 sends out the mirror current Ib to the current combining line LM. . At this time, of the mirror current output units MN0 to MN3, no current is sent from the mirror current output unit whose transistor NQ3 is turned off. Therefore, in the current combining line LM, a combined current of the mirror currents Ib sent from the mirror current output units MN0 to MN3, that is, a combined current of k · Ib (k: the number of transistors NQ3 turned on). It flows as a negative temperature characteristic current Ir2.

  That is, in the current adjustment unit 14, the current mirror unit including the transistors NQ1 and NQ2 of each of the mirror current output units MN0 to MN3 has a current (hereinafter referred to as a negative temperature characteristic) having a characteristic that the current value decreases as the temperature increases. Four mirror currents Ib corresponding to (IM1 + IM2) are generated. Then, the mirror current synthesizing unit including the transistors NQ3 of the mirror current output units MN0 to MN3 corresponds to the adjustment setting value indicated by the second adjustment setting value (TM0 to TM3) among the four mirror currents Ib. A current obtained by combining a number of mirror currents Ib is generated as a negative temperature characteristic current Ir2.

  With the above-described configuration, the current adjustment unit 14 adjusts the current value of the current (IM1 + IM2) having the negative temperature characteristic generated by the negative temperature coefficient current source 12 according to the current adjustment signals TM0 to TM3. The negative temperature characteristic current Ir2 is sent to the current synthesis line LM.

  Therefore, a combined current of the positive temperature characteristic current Ir1 sent from the current adjusting unit 13 and the negative temperature characteristic current Ir2 sent from the current adjusting unit 14 is supplied to the current amplifying unit 16 via the current combining line LM. Is done.

  As shown in FIG. 7, the current amplifying unit 16 includes n-channel MOS transistors NA1 to NA3 and p-channel MOS transistors PA1 and PA2. A ground voltage is applied to the source terminal of the transistor NA1, and the drain terminal and the gate terminal are connected to the current combining line LM and the gate terminal of the transistor NA2. The ground voltage is applied to the source terminal of the transistor NA2, and the drain terminal is connected to the drain terminal and the gate terminal of the transistor PA1. The gate terminals of the transistors PA1 and PA2 are connected to each other, and the power supply voltage VCC is applied to the source terminals of both. The drain end of the transistor PA2 is connected to the drain end of the transistor NA3 and the output line LO. A ground voltage is applied to the source terminal of the transistor NA3, and the gate terminal is connected to the output line LO.

  With the above configuration, the current amplifying unit 16 amplifies the current supplied through the current combining line LM, that is, the current value of the combined current of the positive temperature characteristic current Ir1 and the negative temperature characteristic current Ir2, and And output via the output line LO.

  As described above, in the reference current generation circuit 100 having the configuration shown in FIG. 2, the positive temperature coefficient current source 11 generates the first currents (IP1, IP2) having the positive temperature characteristic in which the current value increases with the temperature rise. And the negative temperature coefficient current source 12 generates the second currents (IM1, IM2) having negative temperature characteristics in which the current value decreases as the temperature increases. Here, the current adjusting unit 13 obtains the positive temperature characteristic current Ir1 by adjusting the current value of the first current having the positive temperature characteristic according to the first adjustment setting values (TP0 to TP3). Further, the current adjusting unit 14 obtains the negative temperature characteristic current Ir2 by adjusting the current value of the second current having the negative temperature characteristic according to the second adjustment setting value (TM0 to TM3). Then, the output section (LM, 16) outputs a current obtained by combining the positive temperature characteristic current Ir1 and the negative temperature characteristic current Ir2 as the reference current Iref1.

  In other words, in the reference current generation circuit 100, when a current obtained by combining a current having the positive temperature characteristic and a current having the negative temperature characteristic is output as the reference current Iref1, the current adjusting units 13 and 14 use the current adjusting units 13 and 14 to output the current having the positive temperature characteristic. This makes it possible to adjust the combined ratio of the reference current Iref1 and the current having the negative temperature characteristic and the current value of the reference current Iref1.

According to such a configuration, even if a manufacturing variation occurs in the positive temperature coefficient current source 11 or the negative temperature coefficient current source 12, by adjusting the current value using the current adjusting units 13 and 14 after the manufacturing, It is possible to obtain a reference current Iref1 having a desired temperature coefficient and current value for each product.
Therefore, according to the memory device 200 including the reference current generation circuit 100, even if the current read from the memory cell MC fluctuates due to a temperature change, the read data DT can be obtained from the memory cell with high read accuracy. Becomes possible.

  FIG. 8 is a block diagram showing a configuration of a reference current generation circuit 100 employed when generating three reference currents Iref1 to Iref3 having different current values. In the configuration shown in FIG. 8, for example, the read current sent from the memory cell MC storing four-valued data is one of four data values [00], [01], [10], and [11]. Is used as a reference current generation circuit for generating three reference currents for determining which of the above is represented.

  In the configuration shown in FIG. 8, the reference current generation circuit 100 includes a positive temperature coefficient current source 11, a negative temperature coefficient current source 12, current adjustment units 13a to 13c, current adjustment units 14a to 14c, current amplification units 16a to 16c, and a current The control unit 150 is included.

  The positive temperature coefficient current source 11 shown in FIG. 8 is the same as the positive temperature coefficient current source 11 shown in FIG. 2, and has, for example, a circuit configuration shown in FIG. However, the positive temperature coefficient current source 11 shown in FIG. 8 supplies currents IP1 and IP2 having positive temperature characteristics as shown in FIG. 4 to the current adjusting units 13a to 13c via lines L1 and L2, respectively. .

  The negative temperature coefficient current source 12 shown in FIG. 8 is the same as the negative temperature coefficient current source 12 shown in FIG. 2, and has, for example, a circuit configuration shown in FIG. However, the negative temperature coefficient current source 12 shown in FIG. 8 supplies currents IM1 and IM2 having negative temperature characteristics as shown in FIG. 6 to the current adjusting units 14a to 14c via the lines L11 and L12, respectively. .

  The current control unit 150 includes first to third positive temperature coefficient current adjustment data indicating adjustment setting values for adjusting the current values of the currents (IP1, IP2) having the positive temperature characteristic, and the current (IM1) having the negative temperature characteristic. , IM2), and a built-in register (not shown) for storing first to third negative temperature coefficient current adjustment data indicating an adjustment set value for adjusting the current value. At this time, the first positive temperature coefficient current adjustment data is data indicating an adjustment set value of the current adjustment applied to the currents (IP1, IP2) when the reference current Iref1 is generated. Further, the second positive temperature coefficient current adjustment data is data indicating an adjustment set value of current adjustment applied to the currents (IP1, IP2) when generating the reference current Iref2. Further, the third positive temperature coefficient current adjustment data is data indicating an adjustment set value of the current adjustment applied to the currents (IP1, IP2) when generating the reference current Iref3. Further, the first negative temperature coefficient current adjustment data is data indicating an adjustment set value of the current adjustment applied to the currents (IM1, IM2) when generating the reference current Iref1. The second negative temperature coefficient current adjustment data is data indicating an adjustment set value of current adjustment applied to the currents (IM1, IM2) when generating the reference current Iref2. The third negative temperature coefficient current adjustment data is data indicating an adjustment set value of current adjustment applied to the currents (IM1, IM2) when generating the reference current Iref3.

  The current control unit 150 outputs the current adjustment signals TPa0 to TPa3, TPb0 to TPb3, and TPc0 to TPc3 based on the adjustment set values indicated by the first to third positive temperature coefficient current adjustment data stored in the internal register. Generate. Each of the current adjustment signals TPa0 to TPa3, TPb0 to TPb3, and TPc0 to TPc3 is a binary signal having a logic level 0 or a logic level 1.

  For example, when the adjustment set value indicated by the first positive temperature coefficient current adjustment data indicates a current value of zero, the current control unit 150 sets all of the current adjustment signals TPa0 to TPa3 to the logic level 1 and sets the current value to the maximum. , All the current adjustment signals TPa0 to TPa3 are set to the logic level 0. If the adjustment set value represents a first adjustment current value that is one step larger than the current value of zero, the current control unit 150 sets only one of the current adjustment signals TPa0 to TPa3 to a logic level. When the second adjustment current value is set to 0 and is larger by one step than the first adjustment current value, only two of the current adjustment signals TPa0 to TPa3 are set to the logic level 0. If the adjustment set value indicated by the first positive temperature coefficient current adjustment data represents a third adjustment current value that is larger by one step than the second adjustment current value, the current control unit 150 sets the current Only three of the adjustment signals TPa0 to TPa3 are set to the logic level 0.

  The current control unit 150 supplies the current adjustment signals TPa0 to TPa3 to the current adjustment unit 13a.

  Note that the current control unit 150 similarly generates current adjustment signals TPb0 to TPb3 representing the adjustment set values indicated by the second positive temperature coefficient current adjustment data, and adjusts the current adjustment signals TPb0 to TPb3 to current adjustment. To the unit 13b. Further, the current control unit 150 generates current adjustment signals TPc0 to TPc3 representing the adjustment set values indicated by the third positive temperature coefficient current adjustment data, and supplies the current adjustment signals TPc0 to TPc3 to the current adjustment unit 13c. I do.

  Further, the current control unit 150 controls the current adjustment signals TMa0 to TMa3, TMb0 to TMb3, TMc0 based on the adjustment set values indicated by the first to third negative temperature coefficient current adjustment data stored in the internal register. Generate TMc3. Each of the current adjustment signals TMa0 to TMa3, TMb0 to TMb3, and TMc0 to TMc3 is a binary signal having a logic level 0 or a logic level 1.

  For example, when the adjustment setting value indicated by the first negative temperature coefficient current adjustment data indicates a current value of zero, the current control unit 150 sets all the current adjustment signals TMa0 to TMa3 to the logic level 1 and sets the current value to the maximum. , The current adjustment signals TMa0 to TMa3 are all set to the logic level 0. When the adjustment set value represents the first adjustment current value that is one step larger than the current value of zero, the current control unit 150 sets only one of the current adjustment signals TMa0 to TMa3 to the logic level. When the second adjustment current value is set to 0 and is larger than the first adjustment current value by one step, only two of the current adjustment signals TMa0 to TMa3 are set to the logic level 0. If the adjustment set value indicated by the first negative temperature coefficient current adjustment data represents a third adjustment current value that is one step larger than the second adjustment current value, the current control unit 150 Only three of the adjustment signals TMa0 to TMa3 are set to the logic level 0.

  The current control unit 150 supplies the current adjustment signals TMa0 to TMa3 to the current adjustment unit 14a.

  The current control unit 150 similarly generates current adjustment signals TMb0 to TMb3 representing the adjustment set values indicated by the second negative temperature coefficient current adjustment data, and adjusts the current adjustment signals TMb0 to TMb3 to current adjustment. To the unit 14b. Further, current control section 150 generates current adjustment signals TMc0 to TMc3 representing the adjustment set values indicated by the third negative temperature coefficient current adjustment data, and supplies the current adjustment signals TMc0 to TMc3 to current adjustment section 14c. I do.

Here, each of the current adjustment units 13a to 13c has the circuit configuration illustrated in FIG. 7 similarly to the current adjustment unit 13 illustrated in FIG. Further, each of the current adjustment units 14a to 14c has the circuit configuration illustrated in FIG. 7 similarly to the current adjustment unit 14 illustrated in FIG. Further, each of the current amplifying sections 16a to 16c shown in FIG. 8 has the circuit configuration shown in FIG. 7, similarly to the current amplifying section 16 shown in FIG.
Therefore, the current of the current obtained by combining the positive temperature characteristic current Ir1 whose current value has been adjusted by the current adjustment unit 13a and the negative temperature characteristic current Ir2 whose current value has been adjusted by the current adjustment unit 14a. The value is amplified by the current amplifier 16a and output as the reference current Iref1. The current of the current obtained by combining the positive temperature characteristic current Ir1 whose current value has been adjusted by the current adjusting unit 13b and the negative temperature characteristic current Ir2 whose current value has been adjusted by the current adjusting unit 14b. The value is amplified in the current amplifier 16b and output as the reference current Iref2. Furthermore, the current value of the current obtained by combining the positive temperature characteristic current Ir1 whose current value has been adjusted by the current adjusting unit 13c and the negative temperature characteristic current Ir2 whose current value has been adjusted by the current adjusting unit 14c. Is amplified in the current amplifying unit 16c and output as the reference current Iref3.

  Here, in the configuration shown in FIG. 8, in synthesizing the currents (IP1, IP2) having the positive temperature characteristics and the currents (IM1, IM2) having the negative temperature characteristics, the current adjustment unit ( The reference currents Iref1 to Iref3 having different current values are obtained by individually adjusting the current values of both at 13a to 13c and 14a to 14c).

  According to such a configuration, even if the positive temperature coefficient current source 11 or the negative temperature coefficient current source 12 has a manufacturing variation, the current value by the current adjusting units (13a to 13c, 14a to 14c) after the manufacturing. , It is possible to individually adjust each of the reference currents Iref1 to Iref3 to a current having a desired current value and temperature characteristics for each product.

  Further, in each of the current adjusting units 13a to 13c shown in FIG. 8, mirror currents corresponding to the currents (IP1, IP2) generated by the positive temperature coefficient current source 11 are output by the mirror current output units MP0 to MP3 shown in FIG. Ia is generated for four systems. Then, in each of the current adjustment units 13a to 13c, the mirror current Ia is synthesized by the number corresponding to the adjustment setting value indicated by the current adjustment signals (TPa0 to TPa3, TPb0 to TPb3, TPc0 to TPc3). Thus, a positive temperature characteristic current Ir1 whose current value has been adjusted is generated.

  In each of the current adjusting units 14a to 14c shown in FIG. 8, the mirror current output units MN0 to MN3 shown in FIG. 7 use the mirror currents corresponding to the currents (IM1, IM2) generated by the negative temperature coefficient current source 12. Ib is generated for four systems. Then, in each of the current adjustment units 14a to 14c, the mirror current Ib is combined by the number corresponding to the adjustment setting value indicated by the current adjustment signals (TMa0 to TMa3, TMb0 to TMb3, TMc0 to TMc3). As a result, the negative temperature characteristic current Ir2 whose current value has been adjusted is generated.

  As described above, each of the current adjustment units 13a to 13c does not change the current value of the current (IP1, IP2) itself generated by the positive temperature coefficient current source 11, and similarly, the current adjustment units 14a to 14c Does not change the current value of the current (IM1, IM2) itself generated by the negative temperature coefficient current source 12.

  Therefore, in the reference current generation circuit 100 having the configuration shown in FIGS. 7 and 8, when generating three reference currents Iref1 to Iref3 having different current values from each other, the positive temperature coefficient current source 11 and the negative temperature coefficient current source 12 Need only be prepared for one system. As a result, the circuit scale can be significantly reduced as compared with a case where a dedicated positive temperature coefficient current source 11 and a negative temperature coefficient current source 12 are provided for each of the reference currents Iref1 to Iref3. It becomes possible. Therefore, according to the memory device 200 including the reference current generating circuit 100 having the configuration shown in FIGS. 7 and 8, even if the current read from the memory cell MC fluctuates due to a temperature change, the read accuracy is high. The read data DT can be obtained from the memory cell.

  In the embodiment shown in FIG. 8, three reference currents Iref1 to Iref3 for generating four-value data from the read current are shown. However, in the embodiment shown in FIG. It is also possible to generate more than three reference currents. At this time, it is necessary to add the current adjusting units (13, 14) and the current amplifying unit 16 as much as the number of reference currents increases, but the positive temperature coefficient current source 11 and the negative temperature coefficient current source 12 are newly added. Therefore, the increase in the circuit size can be minimized.

  In the embodiment shown in FIG. 7, a four-stage output type current mirror circuit is employed as each of the current adjustment units 13 and 14. However, by increasing the number of output stages, the temperature coefficient of the reference current and the current The value can be finely adjusted. If fine adjustment is not required for each of the current adjustment units 13 and 14, a two-stage output type current mirror circuit may be employed.

  In short, the current adjusting unit 13 generates the first to Nth (N is an integer of 2 or more) mirror currents (Ia) corresponding to the first currents (IP1 and IP2) having the positive temperature characteristics. A current obtained by combining the sections (PQ1 and PQ2) and the mirror currents of the first to Nth mirror currents corresponding to the first adjustment set values (TP0 to TP3) is output as the positive temperature characteristic current (Ir1). And a mirror current combining section (PQ3). Further, as the current adjusting unit 14, current mirror units (NQ1, NQ2) for generating first to N-th mirror currents (Ib) corresponding to the second currents (IM1, IM2) having negative temperature characteristics, A mirror current synthesizing unit (NQ3) that outputs a current obtained by synthesizing a number of mirror currents corresponding to the second adjustment setting values (TM0 to TM3) among the first to Nth mirror currents as a negative temperature characteristic current (Ir2); May be used as long as it has

11 Positive temperature coefficient current source 12 Negative temperature coefficient current sources 13, 14 Current adjustment unit 15 Current control unit 100 Reference current generation circuit

Claims (9)

A positive temperature coefficient current source for generating a first current having an output current value that increases with a rise in temperature;
A negative temperature coefficient current source for generating a second current having an output current value that decreases in accordance with the temperature rise;
A first current adjustment unit that generates a current obtained by changing a current value of the first current according to a first adjustment set value as a positive temperature characteristic current;
A second current adjustment unit that generates a current obtained by changing a current value of the second current according to a second adjustment set value as a negative temperature characteristic current;
A reference current generation circuit, comprising: an output unit that outputs a current obtained by combining the positive temperature characteristic current and the negative temperature characteristic current as a reference current. The first current adjustment unit includes:
A first current mirror unit that generates first to Nth (N is an integer of 2 or more) mirror currents corresponding to the first current;
A first mirror current combining unit that outputs a current obtained by combining a number of mirror currents corresponding to the first adjustment setting value among the first to N-th mirror currents as the positive temperature characteristic current,
The second current adjustment unit includes:
A second current mirror unit that generates first to N-th mirror currents corresponding to the second current;
Outputting a current obtained by combining mirror currents of a number corresponding to the second adjustment setting value among the first to N-th mirror currents generated by the second current mirror unit as the negative temperature characteristic current; 2. The reference current generation circuit according to claim 1, further comprising: a mirror current synthesis unit. 3. The reference current generating circuit according to claim 1, wherein the positive temperature coefficient current source and the negative temperature coefficient current source are configured by a band gap reference circuit. A positive temperature coefficient current source that generates a first current whose current value increases as the temperature rises;
A negative temperature coefficient current source for generating a second current whose current value decreases as the temperature increases,
A first current adjustment unit that generates a current obtained by adjusting the current value of the first current according to a first adjustment set value as a first positive temperature characteristic current;
A second current adjustment unit that generates a current obtained by adjusting the current value of the second current according to a second adjustment set value as a first negative temperature characteristic current;
A third current adjustment unit that generates a current obtained by adjusting the current value of the first current according to a third adjustment set value as a second positive temperature characteristic current;
A fourth current adjusting unit that generates a current obtained by adjusting the current value of the second current according to a fourth adjustment set value as a second negative temperature characteristic current;
A first output unit that outputs a current obtained by combining the first positive temperature characteristic current and the first negative temperature characteristic current as a first reference current;
A second output unit that outputs a current obtained by combining the second positive temperature characteristic current and the second negative temperature characteristic current as a second reference current. The first current adjustment unit includes:
A first current mirror unit that generates first to Nth (N is an integer of 2 or more) mirror currents corresponding to the first current, and the first adjustment among the first to Nth mirror currents A first mirror current synthesis unit that outputs a current obtained by synthesizing a number of mirror currents corresponding to the set value as the first positive temperature characteristic current,
The second current adjustment unit includes:
A second current mirror unit that generates first to N-th mirror currents corresponding to the second current, and the first to N-th mirror currents generated by the second current mirror unit. A second mirror current synthesis unit that outputs a current obtained by synthesizing a number of mirror currents corresponding to the second adjustment set value as the first negative temperature characteristic current,
The third current adjustment unit includes:
A third current mirror unit that generates first to N-th mirror currents corresponding to the first current, and the first to N-th mirror currents generated by the third current mirror unit. A third mirror current synthesis unit that outputs a current obtained by synthesizing a number of mirror currents corresponding to the third adjustment set value as the second positive temperature characteristic current,
The fourth current adjustment unit includes:
A fourth current mirror unit that generates first to N-th mirror currents corresponding to the second current, and the first to N-th mirror currents generated by the fourth current mirror unit. The reference according to claim 4, further comprising: a fourth mirror current combining unit that outputs a current obtained by combining a number of mirror currents corresponding to a fourth adjustment set value as the second negative temperature characteristic current. Current generation circuit. 6. The reference current generation circuit according to claim 4, wherein the positive temperature coefficient current source and the negative temperature coefficient current source are configured by a band gap reference circuit. A memory cell array in which a plurality of memory cells are formed; a reference current generation circuit for generating a reference current; and a value of read data based on a comparison result between the read current read from the memory cell and the reference current. A sense amplifier for determining
The reference current generation circuit,
A positive temperature coefficient current source for generating a first current having an output current value that increases with a rise in temperature;
A negative temperature coefficient current source for generating a second current having an output current value that decreases in accordance with the temperature rise;
A first current adjustment unit that generates a current obtained by changing a current value of the first current according to a first adjustment set value as a positive temperature characteristic current;
A second current adjustment unit that generates a current obtained by changing a current value of the second current according to a second adjustment set value as a negative temperature characteristic current;
A memory configured to output a current obtained by combining the positive temperature characteristic current and the negative temperature characteristic current as a reference current. The first current adjustment unit includes:
A first current mirror unit that generates first to Nth (N is an integer of 2 or more) mirror currents corresponding to the first current;
A first mirror current combining unit that outputs a current obtained by combining a number of mirror currents corresponding to the first adjustment setting value among the first to N-th mirror currents as the positive temperature characteristic current,
The second current adjustment unit includes:
A second current mirror unit that generates first to N-th mirror currents corresponding to the second current;
Outputting a current obtained by combining mirror currents of a number corresponding to the second adjustment setting value among the first to N-th mirror currents generated by the second current mirror unit as the negative temperature characteristic current; 8. The memory device according to claim 7, further comprising a mirror current synthesizing unit. 9. The memory device according to claim 7, wherein the positive temperature coefficient current source and the negative temperature coefficient current source are configured by a band gap reference circuit.

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