JP2004030041A - Current source circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current source circuit which can optionally set the temperature coefficient of an output current while suppressing an increase in circuit scale. <P>SOLUTION: A control part 10 controls an npn transistor Q11 and an npn transistor Q12 so that their currents are equal and their emitter potentials are equal to each other, so a potential difference having a positive temperature coefficient corresponding to differences in size and shape between those npn transistors Q11 and Q12 is generated between the bases of those transistors. A current I1 generated by a first current generation part 20 corresponding to the potential difference has a positive temperature coefficient. Further, the base-emitter voltage of the npn transistor Q11 has a negative temperature coefficient, so a current I2 generated by a second current generation part 30 corresponding to it has a negative temperature coefficient. The temperature coefficient of a current Iref composed of those currents is therefore set to a desired value. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a current source circuit, and more particularly, to a current source circuit that outputs a reference current with reduced influence of a temperature change.
[0002]
[Prior art]
FIG. 7 is a circuit diagram showing a configuration of a current source circuit generally used conventionally.
This current source circuit has an n-type MOS transistor M1, an n-type MOS transistor M2, and a resistor R1.
[0003]
As shown in FIG. 7, the n-type MOS transistor M1 has a drain connected to the power supply voltage line VDD via the resistor R1, a source connected to the reference voltage line VSS, and a gate connected to the drain.
The n-type MOS transistor M2 has a gate connected to the gate of the n-type MOS transistor M1, and a source connected to the reference voltage line VSS.
[0004]
Since a common voltage is supplied between the gate and the source of the n-type MOS transistor M1 and the n-type MOS transistor M2, if the shapes and sizes of both transistors are formed to be equal, the drain currents thereof are also substantially equal. In this case, the current Ir1 output from the drain of the n-type MOS transistor M2 becomes equal to the current flowing through the resistor R1, and the following relationship is established.
[0005]
(Equation 1)
Ir1 = (Vdd−Vss−Vgs1) / r1 (1)
[0006]
In the equation (1), the symbol Vdd represents the voltage of the power supply voltage line VDD, the symbol Vss represents the voltage of the reference voltage line VSS, the symbol Vgs1 represents the gate-source voltage of the n-type MOS transistor M1 and the n-type MOS transistor M2, The symbol r1 indicates the resistance value of the resistor R1.
[0007]
The current source circuit shown in FIG. 7 has a very simple circuit configuration, and is therefore generally used as a circuit for supplying a DC bias current, for example. However, as can be seen from equation (1), the output current Ir1 is directly affected by the fluctuation of the gate-source voltage Vgs1 due to the temperature and the fluctuation of the power supply voltage VDD, so that the output current Ir1 is used for applications requiring a stable current. Is an unsuitable circuit.
[0008]
FIG. 8 is a circuit diagram showing a configuration of another general current source circuit.
This current source circuit has a differential amplifier circuit U1, an n-type MOS transistor M3, and a resistor R2.
[0009]
The source of the n-type MOS transistor M3 is connected to the reference voltage line VSS via the resistor R2.
The differential amplifier U1 inputs the source voltage of the n-type MOS transistor M3 to the negative input terminal, inputs the reference voltage Vref to the positive input terminal, and amplifies the potential difference between the positive input terminal and the negative input terminal. Output to the gate of n-type MOS transistor M3.
[0010]
When the amplification factor of the differential amplifier circuit U1 is sufficiently large, the source voltage of the n-type MOS transistor M3 becomes substantially equal to the reference voltage Vref. Therefore, the current Ir2 output from the collector of the n-type MOS transistor M3 is expressed by the following equation. expressed.
[0011]
(Equation 2)
Ir2 = (Vref−Vss) / r2 (2)
[0012]
However, in equation (2), the symbol r2 indicates the resistance value of the resistor R2.
As can be seen from the equation (2), the output current Ir2 is not affected by the temperature characteristics of the n-type MOS transistor M3. Therefore, the current source circuit of FIG. 8 has a more stable output current than the current source circuit of FIG. There is an advantage that the property is increased. However, the current source circuit in FIG. 8 uses a differential amplifier circuit having a large number of elements and additionally requires a circuit for generating a reference voltage Vref compensated for temperature. However, there is a problem that the circuit scale becomes large. There is also a problem that the output current Ir2 fluctuates directly due to the influence of the temperature characteristics of the resistor R2.
[0013]
Therefore, as a current source circuit capable of outputting a temperature-compensated current without using a circuit for generating a reference voltage or a differential amplifier circuit, for example, Japanese Unexamined Patent Application Publication No. 7-191969 The circuit shown in FIG. 5 is known.
[0014]
FIG. 9 is a circuit diagram showing a schematic configuration of the current source circuit shown in the above-mentioned document.
This current source circuit includes npn transistors Q1 to Q7, p-type MOS transistors M4 to M6, resistors R3 and R4.
[0015]
These components have the following connection relationship.
The p-type MOS transistor M4 has a source connected to the power supply voltage line VDD, a gate connected to the gate of the p-type MOS transistor M5, and a drain connected to the reference voltage line VSS via a series circuit of npn transistors Q1 to Q3. Connected.
The bases and collectors of the npn transistors Q1 to Q3 are connected.
The npn transistor Q4 has a collector connected to the power supply voltage line VDD, a base connected to the drain of the p-type MOS transistor M4, and an emitter connected to the collector of the npn transistor Q5 via the resistor R3.
The npn transistor Q5 has a base connected to its collector and an emitter connected to the reference voltage line VSS.
The p-type MOS transistor M5 has a source connected to the power supply voltage line VDD, a gate connected to its drain, and a drain connected to the collectors of the npn transistor Q6 and the npn transistor Q7.
The npn transistor Q6 has a base connected to the base of the npn transistor Q5, and an emitter connected to the reference voltage line VSS.
The npn transistor Q7 has a base connected to the base of the npn transistor Q5, and an emitter connected to the reference voltage line VSS via the resistor R4.
The p-type MOS transistor M6 has a source connected to the power supply voltage line VDD and a gate connected to the gate of the p-type MOS transistor M5.
[0016]
When the base-emitter voltages of the npn transistors Q1 to Q5 are the voltages Vbe1 to Vbe5, respectively, and the resistor R3 has the resistance value r3, the current Iq5 flowing through the npn transistor Q5 can be approximately expressed by the following equation. Is represented as
[0017]
[Equation 3]
Iq5 = (Vbe1 + Vbe2 + Vbe3-Vbe4-Vbe5) / r3 (3)
[0018]
Assuming that the shape and the size of the npn transistor Q5 and the npn transistor Q6 are equal, the current Iq6 flowing through the npn transistor Q6 is substantially equal to the current Iq5 shown in the equation (3).
[0019]
When the npn transistor Q7 has a base-emitter voltage Vbe7 and the resistor R4 has a resistance value r4, the current Iq7 flowing through the npn transistor Q7 is represented by the following equation.
[0020]
(Equation 4)
Iq7 = (Vbe5-Vbe7) / r4 (4)
[0021]
A current obtained by combining the current Iq7 and the current Iq6 flows through the p-type MOS transistor M5. Assuming that the shapes and sizes of the p-type MOS transistor M6 and the p-type MOS transistor M5 are equal, the drain current Ir3 of the p-type MOS transistor M6 becomes equal to this combined current, and is expressed by the following equation. You.
[0022]
(Equation 5)
Ir3 = Iq5 + Iq7 (5)
[0023]
Since the voltage between the base and the emitter of the npn transistor has a negative temperature coefficient of about −2 mV / ° C., assuming that the shapes and sizes of the npn transistors Q1 to Q5 are equal, the equation (3) The term of the voltage difference (Vbe1 + Vbe2 + Vbe3-Vbe4-Vbe5) in ()) has a negative temperature coefficient as a whole.
[0024]
On the other hand, assuming that the emitter area of npn transistor Q7 is formed to be larger than the emitter area of npn transistor Q5, the temperature change of voltage Vbe7 becomes larger in the negative direction than the temperature change of voltage Vbe5. The term of the voltage difference (Vbe5-Vbe7) at has a positive temperature coefficient.
[0025]
Therefore, the output current Ir3 of the current source circuit is generated by combining the current Iq7 having a positive temperature coefficient and the current Iq5 having a negative temperature coefficient. It is possible to make the temperature coefficient in the vicinity close to zero.
[0026]
[Problems to be solved by the invention]
By the way, in the power supply circuit of FIG. 9, when the resistances of the resistors R3 and R4 vary, the current values of the npn transistors Q5 to Q7 change and the npn transistors Q5 to Npn Since the base-emitter voltage of the transistor Q7 changes, there is a problem that the temperature coefficient of the current Ir3 shifts from the design value.
[0027]
Further, since the resistance values of the resistors R3 and R4 also change depending on the temperature, if the base-emitter voltages of the npn transistors Q5 to Q7 change in accordance with the temperature change, the temperature coefficient of the current Ir3 is changed. There is a problem that it is difficult to design a desired value.
[0028]
Further, when the resistance value of the resistor R4 is adjusted, the current flowing through the npn transistor Q7 changes accordingly. Therefore, the temperature coefficient of the current Iq7 should be proportionally changed according to the resistance value of the resistor R4. Can not. When the resistance value of the resistor R3 is adjusted, the currents of the npn transistors Q5 to Q7 change, so that both the temperature coefficients of the current Iq6 and the current Iq7 change. Thus, there is a problem that it is difficult to set an arbitrary temperature coefficient for the current Ir3 by adjusting the resistance values of the resistors R3 and R4.
[0029]
The present invention has been made in view of such circumstances, and an object of the present invention is to provide a current source circuit that can arbitrarily set a temperature coefficient of an output current while suppressing an increase in circuit scale.
[0030]
[Means for Solving the Problems]
In order to achieve the above object, a current source circuit according to the present invention comprises a first transistor and a second transistor having different sizes or shapes to which a common voltage is supplied to a collector, the first transistor and the second transistor having different sizes or shapes. Control means for controlling the currents flowing through the two transistors to be equal and the emitter potentials to be equal to each other; and a first means for controlling a potential difference between a base potential of the first transistor and a base potential of the second transistor. First current generating means for generating the first current, second current generating means for generating a second current corresponding to a potential difference between the base potential and the emitter potential of the first transistor, and the first current And a current output means for combining and outputting the second current.
Preferably, the first transistor has a collector and a base connected to a first voltage supply line, the second transistor has a collector connected to the first voltage supply line, and the first current The generating means includes a first resistor inserted between the first voltage supply line and the base of the second transistor.
[0031]
According to the current source circuit of the present invention, the control means controls the currents flowing through the first transistor and the second transistor to be equal and controls the emitter potentials to be equal to each other. Between the base potential of the first transistor and the base potential of the second transistor, a potential difference having a positive temperature coefficient corresponding to the size or shape of these transistors is generated. Therefore, a first current having a positive temperature coefficient flows through the first resistor of the first current generating means. On the other hand, since the potential difference between the base potential and the emitter potential of the first transistor has a negative temperature coefficient, the second current generated by the second current generating means accordingly becomes negative. Has a temperature coefficient of The first current and the second current are combined, and the temperature coefficient of the current output from the current output means is set to a desired value.
[0032]
Further, the control means includes two transistors to which a common control voltage is supplied to the current control terminals of each other, and the control means includes an emitter between the first transistor and the second transistor and a second voltage supply line. And one or a plurality of first transistor pairs inserted in series with each other, and two transistors whose current control terminals are connected to each other. The emitters of the first transistor and the second transistor and the first transistor And a second transistor pair having the current control terminal connected to one of connection nodes with the first transistor pair. The means includes a third transistor whose current control terminal is connected to a current control terminal of the second transistor pair, the third transistor and the first transistor. It may include a second resistor inserted between the pressure supply line.
Further, the current output means includes a node connecting the current output terminal of the first current generation means and the current output terminal of the second current generation means, and outputs a current corresponding to a combined current flowing from the node. And a current mirror circuit.
This current mirror circuit includes two transistors whose current control terminals are connected to each other, and one of the two transistors is inserted between the node and the second voltage supply line, and the second voltage The first transistor pair connected to the supply line may have a current control terminal connected to a current control terminal of a current mirror circuit of the current output means.
[0033]
Alternatively, the control means includes two transistors whose current control terminals are supplied with a common control voltage, and connects between the emitters of the first transistor and the second transistor and a second voltage supply line. And one or more first transistor pairs inserted in series with the first transistor pair or the emitter line of the first transistor or the emitter line of the second transistor and the first transistor pair. A fifth transistor, and a first differential amplifier for outputting a voltage corresponding to a potential difference between an emitter potential of the first transistor and an emitter potential of the second transistor to a current control terminal of the fifth transistor. And the second current generating means receives the output voltage from the first differential amplifier circuit at its current control terminal. A third transistor may include a second resistor inserted between the third transistor and the first voltage supply line.
[0034]
BEST MODE FOR CARRYING OUT THE INVENTION
Three embodiments of the present invention will be described with reference to the drawings.
(1st Embodiment)
FIG. 1 is a schematic block diagram illustrating a configuration example of a current source circuit according to an embodiment of the present invention.
The current source circuit shown in FIG. 1 has an npn transistor Q11, an npn transistor Q12, a control unit 10, a first current generation unit 20, a second current generation unit 30, and a current output unit 40.
The npn transistor Q11 is an embodiment of the first transistor of the present invention.
The npn transistor Q12 is an embodiment of the second transistor of the present invention.
The control unit 10 is an embodiment of the control means of the present invention.
The first current generator 20 is one embodiment of the first current generator of the present invention. The second current generator 30 is one embodiment of the second current generator of the present invention.
The current output unit 40 is an embodiment of the current output unit of the present invention.
[0035]
The collectors of the npn transistor Q11 and the npn transistor Q12 are both connected to the power supply voltage line VDD. In the example of FIG. 1, the base of npn transistor Q11 is also connected to power supply voltage line VDD.
Also, the npn transistor Q11 and the npn transistor Q12 have different sizes or shapes such as an emitter region and a base region, and therefore have different base-emitter voltages when the same current flows.
[0036]
The control unit 10 determines that the current I3 flowing through the npn transistor Q11 is equal to the current I4 flowing through the npn transistor Q12, and the potential of the node N1 connected to the emitter of the npn transistor Q11 and the potential of the node N2 connected to the emitter of the npn transistor Q12. Are controlled to be equal to each other.
[0037]
The first current generator 20 generates a current I1 according to the base potential of the npn transistor Q11, that is, the potential difference between the potential of the power supply voltage line VDD and the base potential of the npn transistor Q12 in the example of FIG.
The second current generator 30 generates a current I2 according to the potential difference between the base potential and the emitter potential of the npn transistor Q11.
[0038]
Current output unit 40 combines current I1 generated in first current generation unit 20 and current I2 generated in second current generation unit 30, and outputs reference current Iref.
[0039]
According to the above-described configuration, the same current flows through npn transistor Q11 and npn transistor Q12 and the voltage between the collector and the emitter is controlled to be equal. The voltage is different depending on the size or shape of the transistor. Since the voltage difference between the base-emitter voltage has a positive temperature coefficient as described later, the first current generator 20 generates a current I1 having a positive temperature coefficient. On the other hand, since the base-emitter voltage of npn transistor Q11 has a negative temperature coefficient, current I2 generated by second current generating section 30 according to the base-emitter voltage has a negative temperature coefficient. have. Since the current I1 having a positive temperature coefficient and the current I2 having a negative temperature coefficient are combined in the current output unit 40, the output current Iref can have an arbitrary temperature coefficient.
[0040]
Here, an example of a more detailed configuration of the current source circuit of FIG. 1 will be described.
FIG. 2 is a block diagram showing a configuration example of the current source circuit according to the first embodiment of the present invention, and the same reference numerals in FIGS. 2 and 1 indicate the same components.
[0041]
In the example of FIG. 2, the control unit 10 includes n-type MOS transistors M21 to M24, n-type MOS transistor M28, n-type MOS transistor M29, p-type MOS transistor M11, p-type MOS transistor M12, and resistor R14. Including.
The transistor pair of the n-type MOS transistor M21 and the n-type MOS transistor M22 and the transistor pair of the n-type MOS transistor M23 and the n-type MOS transistor M24 are embodiments of the first transistor pair of the present invention.
The transistor pair of the p-type MOS transistor M11 and the p-type MOS transistor M12 is an embodiment of the second transistor pair of the present invention.
[0042]
The first current generator 20 includes a resistor R11, a resistor R13, and a p-type MOS transistor M14.
The resistor R11 is an embodiment of the first resistor of the present invention.
The resistor R13 is an embodiment of the third resistor of the present invention.
The p-type MOS transistor M14 is an embodiment of the fourth transistor of the present invention.
[0043]
Second current generator 30 includes a resistor R12 and a p-type MOS transistor M13.
The resistor R12 is an embodiment of the second resistor of the present invention.
The p-type MOS transistor M13 is an embodiment of the third transistor of the present invention.
[0044]
Current output unit 40 includes an n-type MOS transistor M30 and an n-type MOS transistor M31.
The circuit constituted by the n-type MOS transistor M30 and the n-type MOS transistor M31 is an embodiment of the current mirror circuit of the present invention.
[0045]
These components of the current source circuit shown in FIG. 2 have the following connection relationship. One end of the resistor R14 is connected to the power supply voltage line VDD, and the other end is connected to the reference voltage line VSS via a series circuit of an n-type MOS transistor M28 and an n-type MOS transistor M29. The n-type MOS transistor M28 has a gate connected to its drain and to the other end of the resistor R14. The n-type MOS transistor M29 has a gate connected to the drain thereof, a source connected to the n-type MOS transistor M28, and a source connected to the reference voltage line VSS.
[0046]
The gates of the n-type MOS transistor M23 and the n-type MOS transistor M24 are commonly connected to the gate of the n-type MOS transistor M29, and the sources are commonly connected to the reference voltage line VSS. The drain of the n-type MOS transistor M23 is connected to the source of the n-type MOS transistor M21, and the drain of the n-type MOS transistor M24 is connected to the source of the n-type MOS transistor M22.
[0047]
The gates of the n-type MOS transistor M21 and the n-type MOS transistor M22 are commonly connected to the gate of the n-type MOS transistor M28. The drain of the n-type MOS transistor M21 is connected to a node N3 connected to the drain of the p-type MOS transistor M11, and the drain of the n-type MOS transistor M22 is connected to a node N4 connected to the drain of the p-type MOS transistor M12.
[0048]
The gates of the p-type MOS transistor M11 and the p-type MOS transistor M12 are commonly connected to a node N4. The source of p-type MOS transistor M11 is connected to node N1 connected to the emitter of npn transistor Q11, and the source of p-type MOS transistor M12 is connected to node N2 connected to the emitter of npn transistor Q12.
[0049]
The collector and base of npn transistor Q11 and the collector of npn transistor Q12 are commonly connected to power supply voltage line VDD. The base of npn transistor Q12 is connected to power supply voltage line VDD via resistor R11 and to the source of p-type MOS transistor M14 via resistor 13.
[0050]
The p-type MOS transistor M14 has a gate connected to the node N3 and a drain connected to a node N5 connected to the drains of the p-type MOS transistor M13 and the n-type MOS transistor M30. The p-type MOS transistor M13 has a gate connected to the node N4, and a source connected to the power supply voltage line VDD via the resistor R12.
[0051]
The gates of the n-type MOS transistors M30 and M31 are commonly connected to the node N5, and the sources are commonly connected to the reference voltage line VSS. The reference current Iref is output from the drain of the n-type MOS transistor M31.
[0052]
In the current source circuit of FIG. 2 having the above-described configuration, a transistor pair of n-type MOS transistor M23 and n-type MOS transistor M24, a transistor pair of n-type MOS transistor M21 and n-type MOS transistor M22, and p-type MOS transistor M11 and Assuming that the transistor pair of the p-type MOS transistor M12 is composed of transistors having the same characteristics, the magnitude of the drain current flowing through each transistor of the transistor pair and the magnitude of the drain-source voltage of each other are They are almost equal. As a result, the current values of the current I3 and the current I4 become substantially equal, and the potentials of the nodes N1 and N2 also become substantially equal. Therefore, the base-emitter voltages of npn transistor Q11 and npn transistor Q12 are different voltages according to the difference in size or shape of both transistors, and the voltage difference ΔVbe is expressed by the following equation.
[0053]
(Equation 6)
ΔVbe = (k · T / q) · ln {J1 / J2} (6)
[0054]
In Equation (6), the symbol k indicates the Boltzmann constant, the symbol T indicates the absolute temperature, the symbol J1 indicates the current density of the npn transistor Q11, and the symbol J2 indicates the current density of the npn transistor Q12.
As can be seen from the equation (6), the voltage difference ΔVbe has a positive temperature coefficient proportional to the temperature. Since the voltage difference ΔVbe is applied to the resistor R11, the current I1 flowing to the node N5 via the resistor R13 and the p-type MOS transistor M14 is substantially expressed by the following equation.
[0055]
(Equation 7)
I1 = ΔVbe / r11 = (k · T / q · r11) · ln {J1 / J2} (7)
[0056]
In the equation (7), a symbol r11 indicates a resistance value of the resistor R11.
On the other hand, the voltage Vn4 generated at the node N4 is a value obtained by subtracting the base-emitter voltage Vbe11 of the npn transistor Q11 and the gate-source voltage Vgs11 of the p-type MOS transistor M11 from the power supply voltage Vdd, and is expressed by the following equation. You.
[0057]
(Equation 8)
Vn4 = Vdd-Vss- (Vbe11 + Vgs11) (8)
[0058]
Using the voltage Vn4 of the node N4 shown in Expression (8), the gate-source voltage Vgs13 of the p-type MOS transistor M13, and the resistance value r12 of the resistor R12, the current I2 is expressed by the following expression.
[0059]
(Equation 9)
I2 = (Vdd-Vn4-Vss-Vgs13) / r12
= (Vbe11 + Vgs11-Vgs13) / r12 (9)
[0060]
If the characteristics of the p-type MOS transistor M13 are adjusted so that the voltage Vgs11 and the voltage Vgs13 become equal, the following equation is established.
[0061]
(Equation 10)
I2 = Vbe11 / r12 (10)
[0062]
The base-emitter voltage Vbe11 can be approximately expressed by the following equation.
[0063]
[Equation 11]
Vbe11 = Vgo + (T / T0) · (Vbe0−Vgo)
+ (M−1) · (k · T / q) · ln {T0 / T} (11)
[0064]
In the equation (11), the sign Vgo indicates a band gap voltage, the sign m indicates a constant independent of temperature, the sign T0 indicates absolute zero degree, and the sign Vbe0 indicates a base-emitter voltage at absolute zero degree.
In equation (11), if the bandgap voltage Vgo is higher than the base-emitter voltage Vbe0, the second term on the right side has a negative slope proportional to the temperature T. Therefore, if the temperature change in the third term on the right side of the equation (11) is negligible, it can be understood that the base-emitter voltage Vbe11 has a negative temperature coefficient proportional to the temperature T.
[0065]
The n-type MOS transistor M30 and the n-type MOS transistor M31 form a current mirror circuit. If the n-type MOS transistor M30 and the n-type MOS transistor M31 have the same shape and size, the drain of both The currents almost match. Therefore, the reference current Iref is expressed by the following equation.
[0066]
(Equation 12)
Iref = I1 + I2 = (ΔVbe / r11) + (Vbe11 / r12) (12)
[0067]
Assuming that the resistors R11 and R12 do not have a temperature coefficient, the relationship of the equation (12) becomes equivalent to the well-known principle of generating a bandgap reference voltage. That is, the first term on the right side of the equation (12) has a positive temperature coefficient proportional to temperature, and the second term on the right side has a negative temperature coefficient proportional to temperature. By adjusting the resistance value, a temperature coefficient near room temperature can be set.
[0068]
FIG. 3 is a diagram illustrating an example of changes in the current I1, the current I2, and the reference current Iref with temperature.
In the example of FIG. 3, the current I1 generated in the first current generating section 20 has a positive slope proportional to the temperature T as shown by a curve C1. On the other hand, the current I2 generated in the second current generator 30 has a negative slope proportional to the temperature T as shown by the curve C2. Since the slopes of the curves C1 and C2 are set to have substantially the same magnitude near room temperature (300K), the current Iref generated by combining these currents is equal to the room temperature as shown by the curve C3. It is almost zero near (300K).
[0069]
Further, in the current source circuit of FIG. 2, since the current values of npn transistor Q11 and npn transistor Q12 are kept constant even if the resistance values of resistors R11 and R12 are changed, the voltage difference ΔVbe and the difference between base-emitter There is an advantage that the voltage Vbe11 is not affected by a change in the resistance value. Therefore, the temperature coefficient of the reference current Iref can be adjusted to be positive or negative in accordance with the resistance ratio between the resistors R11 and R12, so that an arbitrary temperature coefficient can be easily set.
[0070]
Generally, the resistance values of the resistors R11 and R12 have a constant temperature coefficient. For example, when a resistance is formed of polycrystalline silicon, the temperature coefficient becomes a negative value. By adjusting the resistance ratio between the resistors R11 and R12 in consideration of the above, it becomes possible to set the temperature coefficient near room temperature to a desired value.
[0071]
When the resistance values of the resistors R11 and R12 vary due to the influence of the manufacturing process, the ratios of the variations in the resistance values within the same chip generally become equal, so that the resistance ratio of the resistors R11 and R12 tends to be maintained. It is in. Therefore, in the current source circuit of FIG. 2, even if the resistance value varies due to the influence of the manufacturing process, the deviation of the temperature coefficient of the reference current Iref is effectively suppressed.
[0072]
Since the node N3 is a node where the drains of the n-type MOS transistor M21 and the p-type MOS transistor M11 are connected to each other, the impedance thereof is extremely high, and the potential is the gate-source of the n-type MOS transistor M14. It is affected by the voltage between On the other hand, since the currents (current I3 and current I4) flowing through p-type MOS transistor M11 and p-type MOS transistor M12 need to be equal to each other, it is required that nodes N3 and N4 have the same potential. . Therefore, as shown in FIG. 2, a resistor R13 is inserted between the resistor R11 and the p-type MOS transistor M14. By adjusting the resistance value so that the potentials of the node N3 and the node N4 become equal, the current I3 and the current I4 can be more accurately matched.
[0073]
Further, in the example of FIG. 2, the n-type MOS transistor M23 and the n-type MOS transistor M24 are connected in series to the n-type MOS transistor M23 and the n-type MOS transistor M24. Is to prevent the drain voltage of the transistor pair from greatly changing due to the change in the bias voltage supplied to the gate. In the example of FIG. 2, two pairs of transistor pairs are connected in series. However, more transistor pairs may be connected in series, and if the variation of the output current Iref due to the variation of the drain voltage is within an allowable range. Alternatively, only one transistor pair may be used.
[0074]
(Second embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 4 is a schematic block diagram illustrating a configuration example of a current source circuit according to the second embodiment of the present invention, and the same reference numerals in FIGS. 2 and 4 indicate the same components. In the current source circuit of FIG. 4, the control unit 10 in FIG. 2 is replaced with a control unit 10a.
[0075]
The control unit 10a has the same components as the control unit 10, and differs from the control unit 10 in the method of supplying a bias voltage to the gates of the n-type MOS transistor M23 and the n-type MOS transistor M24.
That is, in the control unit 10a, the gate bias voltages of the n-type MOS transistors M23 and M24 are supplied from the gate of the n-type MOS transistor M30 in the current output unit 40.
[0076]
In the control unit 10 in FIG. 2, when the power supply voltage Vdd fluctuates, the drain-source voltage of the n-type MOS transistor M28 and the n-type MOS transistor M29 fluctuates, and the drain current also slightly fluctuates accordingly. Would. Therefore, each transistor pair (n-type MOS transistor M23 and n-type MOS transistor M24, n-type MOS transistor M21 and n-type MOS transistor) to which a bias voltage is supplied from the gates of n-type MOS transistor M28 and n-type MOS transistor M29. M22) also fluctuates, and as a result, the output current Iref fluctuates. Also, the drain current of the n-type MOS transistor M28 and the n-type MOS transistor M29 fluctuates due to the temperature change of the resistance value of the resistor R14, and thus the output current Iref similarly fluctuates.
[0077]
On the other hand, in the control unit 10a in FIG. 4, the gate bias voltage of the transistor pair (the n-type MOS transistor M23 and the n-type MOS transistor M24) connected to the reference voltage line VSS is the current mirror circuit of the current output unit 40. (N-type MOS transistor M30 and n-type MOS transistor M31) are supplied from the gate voltage that determines the output current Iref, so that the power supply voltage dependency and the temperature dependency of the gate bias voltage as in the control unit 10 are reduced. You. Therefore, the stability of the output current Iref can be further improved.
[0078]
In the control unit 10a in FIG. 4, the gate bias voltage of the transistor pair (the n-type MOS transistor M23 and the n-type MOS transistor M24) connected to the reference voltage line VSS is stabilized. As shown in FIG. 5, similar stabilization can be achieved for the other transistor pair (n-type MOS transistor M21 and n-type MOS transistor M22) connected in series with this transistor pair.
[0079]
FIG. 5 is a schematic block diagram illustrating another configuration example of the current source circuit according to the second embodiment of the present invention, and the same reference numerals in FIGS. 5 and 4 indicate the same components.
In the current source circuit of FIG. 5, the control unit 10a in FIG. 4 is replaced with a control unit 10b, and the current output unit 40 in FIG. 4 is replaced with a current output unit 40a.
[0080]
In current output unit 40a, n-type MOS transistor M32 is inserted in series between node N5 and current mirror circuit (n-type MOS transistor M30 and n-type MOS transistor M31) in current output unit 40 in FIG. I have. The gate of the n-type MOS transistor M32 is connected to its drain. The gate bias voltage of the transistor pair of the n-type MOS transistor M21 and the n-type MOS transistor M22 in the control unit 10b is supplied from the gate of the n-type MOS transistor M32.
[0081]
As described above, in the current source circuit of FIG. 5, the gate bias voltage of the transistor pair included in the control unit 10b is generated based on the output current Iref with reduced power supply voltage dependency and temperature dependency, As a result, the stability of the output current Iref can be improved.
[0082]
In the example of FIG. 5, the control unit 10b receiving the bias current from the current output unit 40a has two stages of transistor pairs. However, if more transistor pairs are connected in series, the node N5 and the node N5 are connected in series. The number of transistors inserted in series with the n-type MOS transistor M30 may be increased accordingly, and a gate bias voltage may be supplied from each gate to each transistor pair of the control unit.
[0083]
In the current source circuits of FIGS. 4 and 5, when the magnitude of the current flowing in the transistor pair of the n-type MOS transistor M23 and the n-type MOS transistor M24 is different from the magnitude of the current flowing in the n-type MOS transistor M30 in design. For example, by adjusting the ratio between the channel length and the channel width of these transistors, the ratio between the current values of the two can be adjusted.
[0084]
(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 6 is a schematic block diagram showing a configuration example of a current source circuit according to the third embodiment of the present invention. The same reference numerals in FIGS. 4 and 6 indicate the same components. In the current source circuit of FIG. 6, the control unit 10a in FIG. 4 is replaced with a control unit 10c.
[0085]
In the example of FIG. 6, the control unit 10c includes an n-type MOS transistor M23, an n-type MOS transistor M24, an n-type MOS transistor M26 to an n-type MOS transistor M29, a p-type MOS transistor M15, a resistor R14, a differential amplifier circuit U11, Includes a differential amplifier circuit U12.
The transistor pair of the n-type MOS transistor M23 and the n-type MOS transistor M24 is an embodiment of the first transistor pair of the present invention.
The p-type MOS transistor M15 is an embodiment of the fifth transistor of the present invention.
The n-type MOS transistor M26 is an embodiment of the sixth transistor of the present invention.
The n-type MOS transistor M27 is an embodiment of the seventh transistor of the present invention.
The differential amplifier U11 is an embodiment of the first differential amplifier of the present invention.
The differential amplifier circuit U12 is an embodiment of the second differential amplifier circuit of the present invention.
[0086]
These components of the control unit 10c have the following connection relationship.
One end of the resistor R14 is connected to the power supply voltage line VDD, and the other end is connected to the reference voltage line VSS via a series circuit of an n-type MOS transistor M28 and an n-type MOS transistor M29. The n-type MOS transistor M28 has a gate connected to its drain and to the other end of the resistor R14. The n-type MOS transistor M29 has a gate connected to the drain thereof, a source connected to the n-type MOS transistor M28, and a source connected to the reference voltage line VSS.
[0087]
The gates of the n-type MOS transistors M23 and M24 are commonly connected to the node N5 of the current output unit 40, and the sources are commonly connected to the reference voltage line VSS. The drain of the n-type MOS transistor M23 is connected to the node N1 via the source-drain terminal of the n-type MOS transistor M27, and the drain of the n-type MOS transistor M24 is connected via the source-drain terminal of the n-type MOS transistor M26. It is connected to the drain of p-type MOS transistor M15 and the gate of p-type MOS transistor M14. The gate of the n-type MOS transistor M26 is connected to the gate of the n-type MOS transistor M28. The source of p-type MOS transistor M15 is connected to node N2.
[0088]
The positive input terminal of the differential amplifying circuit U12 receives the voltage of a node N7 to which the drain of the n-type MOS transistor M24 and the source of the n-type MOS transistor M26 are connected. The voltage at the node N6 where the drain of the transistor M23 and the source of the n-type MOS transistor M27 are connected is input. The output voltage of the differential amplifier U12 obtained by amplifying the potential difference between the nodes N7 and N6 is input to the gate of the n-type MOS transistor M27.
The voltage of the node N1 is input to the positive input terminal of the differential amplifier circuit U11, and the voltage of the node N2 is input to its negative input terminal. The output voltage of the differential amplifier U11 that has amplified the potential difference between the nodes N1 and N2 is input to the gate of the p-type MOS transistor M15 and the gate of the p-type MOS transistor M13.
[0089]
According to the above-described configuration, the drain-source voltage of the n-type MOS transistor M27 is controlled so that the potentials of the node N6 and the node N7 become equal, and thereby the drains of the n-type MOS transistor M23 and the n-type MOS transistor M24 are controlled. Since the source-to-source voltages become equal, the current I3 and the current I4 match with higher accuracy. In addition, since the drain-source voltage of p-type MOS transistor M15 is controlled such that the potentials of node N1 and node N2 become equal, the emitter current and collector-emitter voltage of npn transistor Q11 and npn transistor Q12 become , More precisely. Therefore, the voltage difference ΔVbe applied to the resistor R11 accurately satisfies the relationship of Expression (6), so that the temperature coefficient of the output current Iref can be set more accurately.
Further, the current balance between the currents I3 and I4 and the voltage balance between the nodes N1 and N2 are less likely to fluctuate under the influence of the power supply voltage Vdd and the temperature, so that the stability of the output current Iref can be further improved. .
[0090]
In the example shown in FIG. 6, the gate bias voltage of the n-type MOS transistor M26 is supplied from the gate of the n-type MOS transistor M28. The power may be supplied from the gate of a transistor inserted in series between N5 and the n-type MOS transistor M30.
[0091]
The invention is not limited to the embodiments described above.
That is, the above-described circuit configuration is merely an example given in describing the embodiment of the present invention, and the present invention can be realized by another circuit having an equivalent function.
For example, in the above-described circuit, a p-type MOS transistor and an n-type MOS transistor are mainly used, but the present invention can be realized by replacing these with various other transistors. Also, the present invention can be realized by replacing the npn transistor used in the above-described circuit with a pnp transistor.
[0092]
【The invention's effect】
According to the present invention, the temperature coefficient of the output current can be set arbitrarily while suppressing an increase in the circuit scale.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram illustrating a configuration example of a current source circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration example of a current source circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram illustrating examples of currents generated in a first current generating unit and a second current generating unit, and a change in an output current obtained by combining the currents with temperature;
FIG. 4 is a schematic block diagram illustrating a configuration example of a current source circuit according to a second embodiment of the present invention.
FIG. 5 is a schematic block diagram illustrating another configuration example of the current source circuit according to the second embodiment of the present invention.
FIG. 6 is a schematic block diagram illustrating a configuration example of a current source circuit according to a third embodiment of the present invention.
FIG. 7 is a first circuit diagram illustrating a configuration of a conventional current source circuit.
FIG. 8 is a second circuit diagram showing a configuration of a conventional current source circuit.
FIG. 9 is a third circuit diagram showing a configuration of a conventional current source circuit.
[Explanation of symbols]
Q1 to Q7, Q11, Q12 ... npn transistors, M1 to M3, M21 to M32 ... n-type MOS transistors, M4 to M6, M11 to M15 ... pnp transistors, R1 to R4, R11 to R14 ... resistors, U1, U11, U12 .. A differential amplifier circuit, 10, 10a, 10b, 10c a control unit, 20 a first current generating unit, 30 a second current generating unit, 40, 40a a current output unit.

Claims (10)

A first transistor and a second transistor having different sizes or shapes, supplied with a common voltage to a collector;
Control means for controlling the currents flowing through the first transistor and the second transistor to be equal and the emitter potentials to be equal to each other;
First current generating means for generating a first current according to a potential difference between a base potential of the first transistor and a base potential of the second transistor;
Second current generating means for generating a second current according to a potential difference between a base potential and an emitter potential of the first transistor;
A current source circuit having current output means for combining and outputting the first current and the second current. The first transistor has a collector and a base connected to a first voltage supply line,
The second transistor has a collector connected to the first voltage supply line,
The first current generating means includes a first resistor inserted between the first voltage supply line and a base of the second transistor.
The current source circuit according to claim 1. The control means includes:
A first transistor and a second transistor which are inserted in series between emitters of the second transistor and a second voltage supply line; One or more first transistor pairs;
The first transistor pair includes two transistors whose current control terminals are connected to each other, and is inserted in series between the first transistor pair and the emitters of the second transistor and the first transistor pair. A second transistor pair in which the current control terminal is connected to one of connection nodes with
The second current generating means includes:
A third transistor whose current control terminal is connected to the current control terminal of the second transistor pair;
A second resistor inserted between the third transistor and the first voltage supply line;
The current source circuit according to claim 2. The first current generating means includes:
A fourth transistor having a current control terminal connected to one of connection nodes between the first transistor pair and the second transistor pair;
A third resistor inserted between the fourth transistor and the first resistor;
The current source circuit according to claim 3. The current output means,
A node connecting the current output terminal of the first current generation means and the current output terminal of the second current generation means,
A current mirror circuit that outputs a current corresponding to the combined current flowing from the node,
The current source circuit according to claim 3. The current mirror circuit of the current output means includes two transistors whose current control terminals are connected to each other, and one of the two transistors is inserted between the node and the second voltage supply line;
The first transistor pair connected to the second voltage supply line has a current control terminal connected to a current control terminal of a current mirror circuit of the current output means.
The current source circuit according to claim 5. The current output means includes one or more transistors inserted in series between the node and the current mirror circuit, and each current control terminal of the transistor is connected to the node or a preceding stage of the node. Connected to the connection node with the transistor,
At least a part of the first transistor pair cascaded in the control means has a current control terminal connected to a current control terminal of the cascade-connected transistor in the current output means.
The current source circuit according to claim 6. The control means includes:
A first transistor and a second transistor which are inserted in series between emitters of the second transistor and a second voltage supply line; One or more first transistor pairs;
A fifth transistor inserted in series on a connection line between the emitter of the first transistor or the emitter of the second transistor and the first transistor pair;
A first differential amplifier circuit that outputs a voltage corresponding to a potential difference between the emitter potential of the first transistor and the emitter potential of the second transistor to a current control terminal of the fifth transistor;
The second current generating means includes:
A third transistor having its current control terminal supplied with the output voltage from the first differential amplifier circuit;
A second resistor inserted between the third transistor and the first voltage supply line;
The current source circuit according to claim 2. The current output means,
A node connecting the current output terminal of the first current generation means and the current output terminal of the second current generation means,
It includes two transistors whose current control terminals are connected to each other, and one of the two transistors is inserted between the node and the second voltage supply line to supply a current corresponding to a combined current flowing from the node. Output current mirror circuit,
The first transistor pair connected to the second voltage supply line has a current control terminal connected to a current control terminal of a current mirror circuit of the current output means.
A current source circuit according to claim 8. The control means includes:
A sixth transistor inserted in series on a connection line between the emitter of the first transistor or the second transistor and the first transistor pair and having a predetermined control voltage supplied to a current control terminal;
A seventh transistor inserted in series on a connection line between the emitter of the first transistor or the second transistor and the first transistor pair and not including the sixth transistor. Transistors and
A second differential amplifier circuit that outputs a voltage corresponding to a potential difference between a connection node between the sixth transistor and the seventh transistor and the first transistor pair to a current control terminal of the seventh transistor; including,
The current source circuit according to claim 9.

Images