JP4491405B2 - Bias current generation circuit without resistance element - Google Patents

Bias current generation circuit without resistance element Download PDF

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JP4491405B2
JP4491405B2 JP2005324173A JP2005324173A JP4491405B2 JP 4491405 B2 JP4491405 B2 JP 4491405B2 JP 2005324173 A JP2005324173 A JP 2005324173A JP 2005324173 A JP2005324173 A JP 2005324173A JP 4491405 B2 JP4491405 B2 JP 4491405B2
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connected
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transistor
nmos transistor
current
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JP2006146906A (en
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ウェイ チェン チャン
▲セン▼ 勳 李
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三星電子株式会社Samsung Electronics Co.,Ltd.
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Priority to US11/225,587 priority patent/US7227401B2/en
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Description

The present invention relates to an integrated circuit device, and more particularly to a circuit for providing a bias current in an integrated circuit device.
The bias current generator is a circuit that provides a bias current using an externally applied power source in an integrated circuit device. Here, an ideal bias current generator should provide a constant bias current independently of changes in power supply, process parameters or operating temperature.

  A bias current generator according to the prior art is disclosed in Japanese Patent Application Laid-Open No. H10-228707. Conventional bias current generators include a temperature proportional (PTAT) current providing circuit that provides a current that increases as the operating temperature increases, and a temperature inverse proportional (IPTAT) current that provides a current that decreases as the operating temperature increases. There are a providing circuit and a circuit that provides a bias current obtained by adding a temperature proportional current and a temperature inverse proportional current that are less affected by changes in temperature and power supply.

Prior art temperature proportional current providing circuits and temperature inverse proportional current providing circuits use resistance elements to generate temperature proportional current and temperature inverse proportional current, respectively. Since the characteristic of the resistance element is drastically changed by a process change or a temperature change, the bias current generated by the conventional technique is also affected by the process or the temperature change.
US Pat. No. 6,201,436

  SUMMARY OF THE INVENTION An object of the present invention to solve the above-described problems is to provide a current generator that generates a stable and constant bias current regardless of changes in power supply, process, and operating temperature supplied without a resistance element. Is to provide.

  According to one aspect of the present invention for achieving the above object, a temperature proportional current generator including an active circuit element that generates a first current proportional to an operating temperature and a second current inversely proportional to the operating temperature are generated. There is provided a bias current generator, comprising: a temperature inversely proportional current generating unit including an active circuit element; and an adding unit generating the bias current by adding the first current and the second current.

  According to still another aspect of the present invention for achieving the above object, a first current path including a plurality of transistors and a second current path including a plurality of transistors are generated to generate a first current proportional to an operating temperature. A temperature proportional current generator, a third current path including a plurality of transistors, a temperature inverse proportional current generator that generates a second current that is inversely proportional to the operating temperature, and the first current and the second current are added. An adder for generating a bias current, wherein at least one of the plurality of transistors in the second current path corresponds to one of the plurality of transistors in the first current path, and the first current path And at least a pair of the transistors corresponding to the second current path have different transistor sizes, and the first current has the different transistor sizes. The second current is generated based on the voltage generated by the temperature proportional current generation unit, the voltage is divided by the transistors in the third current path, and the second current is generated. A bias current generator is provided.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, reference numerals of constituent elements in the drawings are given the same reference numerals as much as possible even if they are shown in other drawings. In the description of the present invention, if it is determined that a specific description of a related known configuration or function hinders the gist of the present invention, a detailed description thereof will be omitted.

FIG. 1 is a circuit diagram of a bias current generator according to an embodiment of the present invention.
Referring to FIG. 1, the bias current generator includes a temperature proportional current generator 200, a temperature inverse proportional current generator 400, and an adder 500.
The temperature proportional current generating unit 200 and the temperature inverse proportional current generating unit 400 include only active elements such as NMOS or PMOS transistors and bipolar junction transistors (BJT), and do not include passive elements such as resistors.

  The temperature proportional current generator 200 generates a first sub-current (I1) that increases as the temperature increases and decreases as the temperature decreases. The temperature inverse proportional current generator 400 generates a second sub-current (I2) that decreases as the temperature increases and increases as the temperature decreases. The adding unit 500 adds the first sub current (I1) and the second sub current (I2) to generate an addition current (I3). Since the temperature proportional current generator 200 and the temperature inverse proportional current generator 400 do not include passive elements such as resistors, the bias current generator of FIG. 1 is substantially unaffected by changes in the process, power supply, and temperature.

The temperature proportional current generator 200 includes a PMOS cascode current mirror 211, an NMOS cascode current mirror 220, and two BJTs 209 and 210.
The PMOS cascode current mirror 211 includes four PMOS transistors 205, 206, 207 and 208.

  The first PMOS transistor 208 and the second PMOS transistor 206 are connected in series between the first reference voltage (VDD) and the first node 240, and the third PMOS transistor 207 and the fourth PMOS transistor 205 are connected to the first reference voltage (VDD). And the second node 242 are connected in series. The gates of the first PMOS transistor 208 and the third PMOS transistor 207 are connected to the first node 240, and the gates of the second PMOS transistor 206 and the fourth PMOS transistor 205 are connected to the first bias voltage (Vcasp).

The NMOS cascode current mirror 220 includes four NMOS transistors 201, 202, 203, 204.
The first NMOS transistor 204 and the second NMOS transistor 202 are connected in series between the first node 240 and the third node 244, and the third NMOS transistor 203 and the fourth NMOS transistor 201 are connected to the second node 242 and the fourth node 246, respectively. Are connected in series. The gates of the first NMOS transistor 204 and the third NMOS transistor are connected to the second bias voltage (Vcasn), and the gates of the second NMOS transistor 202 and the fourth NMOS transistor 201 are connected to the second node 242.

  The first BJT 210 is diode-coupled between the third node 244 and the second reference voltage (GND). The base and collector of the first BJT 210 are connected to the second reference voltage (GND), and the emitter is connected to the source of the second NMOS transistor 202.

  The second BJT 209 is diode-coupled between the fourth node 246 and the second reference voltage (GND). The base and collector of the second BJT 109 are connected to the second reference voltage (GND), and the emitter is connected to the source of the fourth NMOS transistor 201.

  The third PMOS transistor 207 and the first PMOS transistor 208 are the same pair, and the fourth PMOS transistor 205 and the second PMOS transistor 206 are the same pair. Accordingly, the first sub-current (I1) and the first mirror sub-current (I1 ') are substantially the same.

  Since the gates of the NMOS transistors 201 and 202 are connected to each other, the gate voltage of the fourth NMOS transistor 201 based on the second reference voltage (GND) and the second NMOS based on the second reference voltage (GND). The gate voltage of the transistor 202 is the same. Therefore, it can be expressed as Equation 1 below.

In Equation 1, V be1 and V be2 are the emitter-base voltages of the BJT (209, 210), respectively, and V gs201 and V gs202 are the gate-source voltages of the NMOS transistors (201, 202), respectively.
The base-emitter voltage of BJT is shown as the following formula 2.

V be in Equation 2 is the base-emitter voltage of the BJT, V T is the thermal voltage, I c is the collector current, I s is the saturation current of the BJT.
Further, the gate-source voltage of the MOS transistor is represented by the following Equation 3.

V gs in Equation 3 is the gate-source voltage of the MOS transistor, I D is a drain current of the MOS transistor, U n is the electron mobility, C OX is a capacitor formed by the gate electrode and the channel is the capacitance per unit area of, W / L is the transistor size of the MOS transistor, V th is the threshold voltage of the MOS transistor.
When the base current of BJT is ignored and Equations 2 and 3 are applied to Equation 1, the following Equation 4 is obtained.

In Equation 4, I 1 ′ is a mirror subcurrent (I1 ′), I S209 is the saturation current of the second BJT 209 , (W / L) 201 is the transistor size of the fourth NMOS transistor 201, and V th201 is the fourth NMOS transistor. A threshold voltage of 201. Also, I 1 is the first sub-current (I 1), I S 210 is the saturation current of the first BJT 210 , (W / L) 202 is the transistor size of the second NMOS transistor 202, and V th 202 is the second NMOS 2 is the threshold voltage of the NMOS transistor 202. Such expressions in mathematical formulas apply to all future mathematical formulas.

If the body effect is ignored, V th201 = V th202 can be obtained, and the first sub-current (I1) is the same as the first mirror sub-current (I1 ′).

When Equation 5 is rewritten with respect to the first sub-current (I1), the following Equation 6 is obtained.

Equation 6, the V T kT / q (k is the Boltzmann constant, T is the absolute temperature, q the electron of the charge) illustrates in. The above symbols will be used in future mathematical formulas as well.
In Formula 6, I S210 / I S209 is indicated by m, and (W / L) 201 / (W / L) 202 is indicated by n. M and n are all real numbers larger than 1. For example, m may be 7 and n may be 2.

The first BJT 210 shown in FIG. 1 can be realized by a single transistor having a m-fold saturation current than the second BJT 209. However, if m is a natural number, the first BJT 210 may be realized by connecting the second BJT 209m in parallel. You can also.
U n C OX in circuit using MOS transistors is proportional to T -1.5. Therefore, in Equation 6, the first sub-current (I1) is proportional to T 0.5 , and the first sub-current (I1) is approximately linearly proportional to the temperature in a temperature range of interest such as −55 ° C. to 125 ° C. To do.

Hereinafter, an operation in which the temperature proportional current generator 200 provides a bias current that decreases as the temperature increases and increases as the temperature decreases will be described.
Here, the temperature proportionality includes all cases where the temperature increases as the temperature increases and decreases as the temperature decreases.
The gate voltage (Vgn) of the fourth NMOS transistor 201 with the second reference voltage (GND) as a reference is expressed as Equation 7 below.

In Formula 7, V th is a threshold voltage of the fourth NMOS transistor 201.
When the left / right side is partially differentiated with respect to the temperature T in Expression 2, the following Expression 8 is obtained.

Neglecting the base current of BJT, I C209 can be regarded as substantially the same as the first sub-current (I1), and as described above, the first sub-current (I1) is proportional to T 0.5 . Therefore, I C209 is expressed as Equation 9 below.

In Equation 9, c is a proportional constant, and T indicates temperature.
Also, IS 209 is expressed as in Equation 10 below.

In Equation 10, b is a proportional constant, and Eg represents band gap energy. The band gap energy Eg is known as about 1.12 eV. k and T are as described above.
From Equation 9 and Equation 10, the following Equations 11 to 14 are obtained.

  When Expressions 11 to 14 are applied to Expression 8, the following Expression 15 is obtained.

For example, V be1 = 0.8 V, V T = 26 mV, Eg / q = 1.12 V, T = 300 K, and a temperature coefficient (TC) of about −1.2 mV / ° C. is obtained through Equation 15.

As the temperature increases, the threshold voltage of the MOS transistor decreases. Therefore, in Formula 7, V th also has a negative temperature coefficient.
For example, V th has a temperature coefficient of about −2.5 mV / ° C.

  For example, the third term on the right side of Equation 7 is proportional to the temperature, but is relatively less affected than the first and second terms in the temperature range of interest. For example, the third term on the right side of Equation 7 has a temperature coefficient of about 0.4 mV / ° C. Therefore, the right side of Equation 7 decreases as the temperature increases, and increases as the temperature decreases. Eventually, the reference voltage (Vgn) decreases as the temperature increases and increases as the temperature decreases. In particular, in the temperature range of interest, such as −55 ° C. to 125 ° C., the reference voltage decreases almost linearly with increasing temperature.

The temperature inverse proportional current generation unit 400 includes a control voltage providing unit 410 and a second sub current generation unit 412.
The control voltage providing unit 410 includes a fifth PMOS transistor 401 and a sixth PMOS transistor 402 connected in series between the first reference voltage (VDD) and the fifth node 414. The gate of the fifth PMOS transistor 401 is connected to the first node 240, and the gate of the sixth PMOS transistor 402 is connected to the first bias voltage (Vcasp).

  The control voltage providing unit 410 includes a fifth NMOS transistor 403 and a sixth NMOS transistor 404 connected in series between the fifth node 414 and the second reference voltage (GND). The gates of the fifth NMOS transistor 403 and the sixth NMOS transistor 404 are respectively connected to the source, so that the fifth NMOS transistor 403 and the sixth NMOS transistor 404 are diode-connected and operate like a diode.

  The second sub current generator 412 includes a seventh PMOS transistor 407 connected in series between the first reference voltage (VDD) and the sixth node 416. The gate of the seventh PMOS transistor 407 is connected to the sixth node 416.

  The second sub-current generator 412 includes a seventh NMOS transistor 405 and an eighth NMOS transistor 406 connected in series between the sixth node 416 and the second reference voltage (GND). The gate of the seventh NMOS transistor 405 is connected to the gate of the fourth NMOS transistor 201, and the gate of the eighth NMOS transistor 406 is connected to the fifth node 414.

  The control voltage provider 410 provides the gate of the eighth NMOS transistor 406 with a control voltage (Vg 406) that allows the eighth NMOS transistor 406 to operate in a linear region. The eighth NMOS transistor 406 operates as a resistance element by operating in a linear region.

  As described above, although the gate voltage Vgn of the fourth NMOS transistor 201 is inversely proportional to the temperature, the second voltage increases as the temperature increases and decreases as the temperature decreases as Vgn is input to the gate of the seventh NMOS transistor 405. A sub-current (I2) is generated.

Hereinafter, how the temperature inversely proportional current generation unit 400 generates the second sub-current (I2) that decreases as the temperature increases and increases as the temperature decreases will be described.
Here, the temperature inverse proportion includes all cases where the temperature decreases as the temperature increases and increases as the temperature decreases.
The drain current of the eighth NMOS transistor 406 is expressed as Equation 16 below.

In Equation 16, I 2 is the drain current of the eighth NMOS transistor 406, and this current becomes the second sub-current (I2). Also, G M405 is a transconductance of the 7NMOS transistor 405, r ds406 is an equivalent resistance of the 8NMOS transistor 406 which operates in a linear region. Approximation in Equation 16 is obtained by assuming that r Ds406 is greater than 1 / g m405. Actually, the transconductance of the NMOS transistor is a very large value, and the transistor size (aspect ratio or W / L) of the eighth NMOS transistor 406 can be reduced to increase the r ds 406. Can be
The equivalent resistance of the eighth NMOS transistor 406 is expressed as Equation 17 below.

In Expression 17, V g406 is the control voltage (Vg406) shown in FIG.
Here, the control voltage (Vg 406) is expressed by the following Equation 18.

When the body effect of the fifth NMOS transistor 403 is ignored and Equation 18 is applied to Equation 17, the following Equation 19 is obtained.

On the right side of Equation 19, the first term in the brackets increases with increasing temperature, and the second term decreases with increasing temperature. Conversely, the first term in the square brackets on the right side of Equation 19 decreases with decreasing temperature, and the second term increases with decreasing temperature. Accordingly, the transistor values of the fifth PMOS transistor 401 and the NMOS transistors (403, 404, 406) can be adjusted so that the resistance value can be maintained constant regardless of the temperature change. In particular, it is important to use two NMOS transistors (403, 404) in order to generate the control voltage (Vg 406). When one NMOS transistor is omitted, the right-hand side in the result of Expression 18 The second term is changed from 2Vth to Vth, and as a result, the second term on the right side in the result of Equation 19 is removed. In such a case, the resistance value of the r ds 406 changes with a change in temperature.

  Since the reference voltage (Vgn) generated by the temperature proportional current generator 200 decreases as the temperature increases and increases as the temperature decreases, the second sub-current increases as a result of approximation of Equation 16. Then it decreases and increases as the temperature decreases.

The adding unit 500 includes a first mirror unit 520, a second mirror unit 530, and a third mirror unit 540.
The first mirror unit 520 includes an eighth PMOS transistor 508 and a ninth PMOS transistor 509 connected in series between the first reference voltage (VDD) and the seventh node 514. The gate of the eighth PMOS transistor 508 is connected to the first node 240, and the gate of the ninth PMOS transistor 509 is connected to the first bias voltage (Vcasp). The first mirror unit 520 provides the seventh node 514 with the mirror current of the first sub-current (I1).

  The second mirror unit 530 includes a tenth PMOS transistor 510 connected between the first reference voltage (VDD) and the seventh node 514. The gate of the tenth PMOS transistor 510 is connected to the sixth node 416. The second mirror unit 530 provides a mirror current of the second sub-current (I2) to the seventh node 514.

  At the seventh node 514, the mirror current of the first subcurrent (I1) and the mirror current of the second subcurrent (I2) are added to generate an addition current (I3). Although the addition current (I3) is applied to the third mirror unit 540, the third mirror unit 540 includes two NMOS transistors (511, 512). The ninth NMOS transistor 511 is connected between the seventh node 514 and the second reference voltage (GND), and the tenth NMOS transistor 512 is connected between the bias node 516 and the second reference voltage (GND). The gates of the ninth NMOS transistor 511 and the tenth NMOS transistor 512 are connected to each other and connected to the seventh node 514, respectively. The addition current (I3) flows to the ninth NMOS transistor 511, and the addition current 1 (I3) is replicated by the tenth NMOS transistor 512, thereby generating a bias current (Ibias).

  As described above, the mirror current of the first sub-current (I1) is proportional to the temperature, and the mirror current of the second sub-current (I2) is inversely proportional to the temperature. Therefore, the bias current (Ibias), which is the mirror current of the addition current (I3), is expressed by the following Equation 20.

In Equation 20, I bias is the bias current (Ibias), I 1 is the first sub-current (I1), I 2 is the second sub-current (I2). As the temperature increases in Equation 20, the first sub-current (I1) increases and the second sub-current (I2) decreases. Further, as the temperature decreases, the first sub-current (I1) decreases and the second sub-current (I2) increases. Accordingly, the bias current (Ibais) can be maintained constant by appropriately adjusting the transistor size of the transistor. In addition, the size of the bias current (Ibais) can be adjusted by adjusting the transistor sizes of the ninth NMOS transistor 511 and the tenth NMOS transistor 512.

FIG. 2 is a circuit diagram of a bias current generator according to an embodiment of the present invention.
Referring to FIG. 2, the bias current generator according to an embodiment of the present invention includes a temperature proportional current generator 200, a temperature inverse proportional current generator 400, an adder 500, a bias voltage generator 300, and a starter 100.

  The temperature proportional current generation unit 200, the temperature inverse proportional current generation unit 400, and the addition unit 500 shown in FIG. 2 are the same as those shown in FIG.

Hereinafter, the bias voltage generating unit 300 and the starting unit 100 will be described.
The bias voltage generator 300 provides the temperature proportional current generator 200 with a first bias voltage (Vcasp) and a second bias voltage (Vcasn).
The bias voltage generator 300 includes a first voltage generator 320 and a second voltage generator 330. The first voltage generator 320 provides the first bias voltage (Vcasp) to the PMOS cascode current mirror 211 of the temperature proportional current generator 200. The second voltage generator 330 provides a second bias voltage (Vcasn) to the NMOS cascode current mirror 220 of the temperature proportional current generator 200.

  The first voltage generator 320 includes PMOS transistors (307, 311, 312, 313) and NMOS transistors (308, 309, 310).

  The eleventh PMOS transistor 307 and the eleventh NMOS transistor 308 are connected in series between the first reference voltage (VDD) and the second reference voltage (GND). The twelfth PMOS transistor 311 and the twelfth NMOS transistor 309 are connected in series between the first reference voltage (VDD) and the second reference voltage (GND). The thirteenth PMOS transistor 312, the fourteenth PMOS transistor 313, and the thirteenth NMOS transistor 310 are connected in series between the first reference voltage (VDD) and the second reference voltage (GND). The gate of the eleventh NMOS transistor 307 is connected to the first node 240. The gate of the eleventh NMOS transistor 308 is connected to a junction node between the eleventh PMOS transistor 307 and the eleventh NMOS transistor 308 and is connected to the gates of the twelfth NMOS transistor 309 and the thirteenth NMOS transistor 310. The gate of the twelfth PMOS transistor 311 is connected to the node of the junction between the twelfth PMOS transistor 311 and the twelfth NMOS transistor 309 and is connected to the gate of the thirteenth PMOS transistor 312. The gate of the fourteenth PMOS transistor 313 is connected to a junction node between the fourteenth PMOS transistor 313 and the thirteenth NMO transistor 310, and the first bias voltage (Vcasp) is supplied to the starter 100, the temperature proportional current generator 200, and the temperature inverse proportional current generator. 400.

The second voltage generator 330 includes a PMOS transistor (301, 302), an NMOS transistor (303, 304, 305), and a BJT 306.
The fifteenth PMOS transistor 301 and the fifteen NMOS transistor 305 are connected in series between the first reference voltage (VDD) and the eighth node 518. The sixteenth PMOS transistor 302, the fourteenth NMOS transistor 303, and the sixteenth NMOS transistor 304 are connected in series between the first reference voltage (VDD) and the eighth node 518. The third BJT 306 is diode-connected between the eighth node 518 and the second reference voltage (GND). The gates of the fifteenth PMOS transistor 301 and the sixteenth PMOS transistor 302 are connected to the first node 240. The gate of the fifteenth NMOS transistor 305 is connected to the junction node between the fifteenth PMOS transistor 301 and the fifteenth NMOS transistor 305 and is connected to the gate of the sixteenth NMOS transistor 304. The gate of the fourteenth NMOS transistor 303 is connected to a junction node between the sixteenth PMOS transistor 302 and the fourteenth NMOS transistor 303 and provides the second bias voltage (Vcasn) to the temperature proportional current generator 200 and the starter 100. The base of the third BJT 306 is connected to the second reference voltage (GND).

Hereinafter, how the second voltage generator 330 generates the second bias voltage (Vcasn) will be described.
In the second voltage generator 330, the second bias voltage (Vcasn) can be expressed as the sum of the emitter-base voltage of the third BJT 306, the drain-source voltage of the sixteenth NMOS transistor 304, and the gate-source voltage of the fourteenth NMOS transistor 303. Therefore, the following formula 21 is obtained.

  In order to set the emitter-base voltage (Vbe3) of the third BJT 306 to an appropriate value, the sum of the currents flowing through the fifteenth PMOS transistor 301 and the sixteenth PMOS transistor 302 should be p times the current flowing through the third PMOS transistor 207. . Here, p is a value obtained by dividing the saturation current of the third BJT 306 by the saturation current of the second BJT 209 and may be a positive real number including one. The third BJT 306 can be realized by one transistor having a saturation current that is m times that of the second BJT 209. If m is a natural number, the third BJT 306 can also be realized by a system in which the second BJT 209m are connected in parallel. Therefore, the following formula 22 is obtained.

  In order to set the drain-source voltage of the sixteenth NMOS transistor 304 to an appropriate value, the following Expressions 23 and 24 can be satisfied.

  In order to set the gate-source voltage of the fourteenth NMOS transistor 303 to an appropriate value, the following Expression 25 can be satisfied.

After that, how the first voltage generator 320 generates the first bias voltage (Vcasp) will be described.
In the first voltage generator 320, the first bias voltage (Vcasp) is expressed as a voltage obtained by subtracting the source / drain voltage of the thirteenth PMOS transistor 312 and the source / gate voltage of the fourteenth PMOS transistor 313 from the first reference voltage (VDD). Can do. Therefore, the following mathematical formula 26 is obtained.

In Equation 26, V ds 312 is a drain-source voltage of the thirteenth PMOS transistor 312 and has a negative value. V gs 313 is a gate-source voltage of the fourteenth PMOS transistor 313 and has a negative value.

  In order to set the drain-source voltage of the thirteenth PMOS transistor 312 and the gate-source voltage of the fourteenth PMOS transistor 313 to appropriate values, the following Expressions 27 and 28 may be satisfied.

Accordingly, the second bias voltage (Vcasn) of the appropriate first bias voltage (Vcasp) can be generated by adjusting the transistor size of the transistor.

  The starter 100 causes the temperature proportional current generator 200 to deviate from the degenerate bias point when power is applied. The degenerate bias point means a state where all transistors do not pass current when power is applied.

  The starting unit 100 is a startup circuit including a PMOS transistor (101, 102) and an NMOS transistor (103, 104, 105, 106).

  The seventeenth PMOS transistor 101, the eighteenth PMOS transistor 102, the nineteenth NMOS transistor 105, and the twentieth NMOS transistor 106 are connected in series between the first reference voltage (VDD) and the second reference voltage (GND). The seventeenth NMOS transistor 103 is connected between the first node 240 and the second reference voltage (GND). The eighteenth NMOS transistor 104 is connected between the first bias voltage (Vcasp) and the second reference voltage (GND). The gates of the seventeenth PMOS transistor 101 and the eighteenth PMOS transistor 102 are connected to the second reference voltage (GND). The gates of the seventeenth NMOS transistor 103 and the eighteenth NMOS transistor 104 are connected to a junction node between the sixteenth PMOS transistor 102 and the nineteenth NMOS transistor 105. The gate of the nineteenth NMOS transistor 105 is connected to the second bias voltage (Vcasn). The gate of the twentieth NMOS transistor 106 is connected to the second node 242.

  If the NMOS transistors (202, 204) do not flow current at the initial stage of power application, the NMOS transistors (105, 106) also do not flow current. The PMOS transistors (101, 102) also do not pass current. Accordingly, the voltage (Vst) at the drain node of the nineteenth NMOS transistor 105 is high enough to turn on the NMOS transistors (103, 104). Accordingly, the gate voltage (Vgp) of the first PMOS transistor 208 and the first bias voltage (Vcasp) which is the gate voltage of the second PMOS transistor 206 are all close to the second reference voltage (GND). Accordingly, the PMOS transistors (206, 208) are turned on, and current flows through the NMOS transistors (202, 204). As a result, the second bias voltage (Vcasn), which is the gate voltage of the first NMOS transistor 204, and the second voltage are supplied. 2 The gate voltage (Vgn) of the NMOS transistor 202 rises. When the NMOS transistors (201, 202, 203, 204) are turned on, the NMOS transistors (105, 106) are also turned on.

  When the PMOS transistor (101, 102) is turned on with a small transistor size (W / L) of the PMOS transistor (101, 102), the drain node voltage (Vst) of the 19th NMOS transistor (105) is changed to NMOS. It can be made lower than the threshold voltage of the transistors (103, 104). Therefore, when the NMOS transistor (201, 202, 203, 204) flows current, the NMOS transistor (103, 104) is turned off. As a result, the bias current generator transistor sets an appropriate bias point. After searching, the starter 100 does not affect the operation of the bias current generator.

  FIG. 3 is a circuit diagram of a bias current generator according to an embodiment of the present invention. Referring to FIG. 3, as shown in FIG. 2, the bias current generator according to an embodiment of the present invention includes a starter 100A, a temperature proportional current generator 200A, a bias voltage generator 300A, an inverse temperature proportional current generator 400A, and an adder. Includes 500A.

  The functions and operations of the starter 100A, the temperature proportional current generator 200A, the bias voltage generator 300A, the temperature inverse proportional current generator 400A, and the adder 500A in FIG. 3 are equivalent to the circuits in FIGS. However, in the starting unit 100A, PMOS transistors (103A, 104A) are used instead of the seventeenth NMOS transistor 103 and the eighteenth NMOS transistor 104. In the temperature proportional current generator 200A, the NPN BJT (210A, 209A) is positioned in series between the first reference voltage (VDD) and the PMOS cascode current mirror. In the second voltage generator 330A, an NPN BJT (306A), PMOS transistors (303A, 304A, 305A), and NMOS transistors (301A, 302A) are applied. In the first voltage generator 320A, a PMOS transistor (309A, 301A) and an NMOS transistor (307A, 308A, 311A, 312A, 313A) are applied. In the temperature inversely proportional current generation unit 400A, PMOS transistors (403A, 404A, 405A, 406A) and NMOS transistors (401A, 402A) are applied. In the adding unit 500A, the first mirror unit 520A includes NMOS transistors (508A and 509A), the second mirror unit 530A includes an NMOS transistor 510A, and the third mirror unit 540A includes PMOS transistors (511A and 512A).

  In this manner, as shown in FIGS. 1 and 2, the bias current generator according to an embodiment of the present invention includes a first sub-current (I1) proportional to temperature and a second sub-current (I2) inversely proportional to temperature. ) Is added to generate a bias current (Ibias) that is less affected by temperature and process changes.

  As mentioned above, although the technique of this invention was demonstrated through the Example shown in FIG. 1 thru | or FIG. 3, the technique of this invention is not restricted to the Example shown in FIG. For example, in the embodiments described with reference to FIGS. 1 to 3, the NMOS transistor is used as the transistor operating in the linear region, but the technique of the present invention can be realized by operating the PMOS transistor in the linear region. In addition, as long as the bias voltage generation unit 300 and the start unit 100 illustrated in FIG. 2 provide an appropriate bias voltage to the temperature proportional current generation unit 200 so that an appropriate bias point can be found when applying power, It can be realized by various methods.

  As described above, since the current providing circuit of the present invention does not use a resistance element, it is possible to provide a bias current that is less affected by changes in the process, temperature, or power supply. In particular, the use of a cascode current mirror has a strong characteristic against changes in the power supply. Further, since the MOS transistor operating in the linear region plays a role of a resistance element, a resistance value with little influence of temperature change can be obtained, so that a bias current can be effectively provided. Further, the chip size and the power consumption can be reduced by realizing the bias current generator using a smaller number of transistors than in the prior art without using a resistance element.

The present invention has been described in detail with reference to the embodiments. However, the present invention is not limited to this embodiment, and the present invention is not limited to this, as long as it has ordinary knowledge in the technical field to which the present invention belongs. The present invention can be modified or changed.

It is a circuit diagram of the bias current generator by one Example of this invention (the 1). It is a circuit diagram of the bias current generator by one Example of this invention (the 2). FIG. 6 is a circuit diagram of a bias current generator according to an embodiment of the present invention (No. 3).

Explanation of symbols

200 Temperature proportional current generation unit 211 PMOS cascode current mirror 220 NMOS cascode current mirror 400 Temperature inversely proportional current generation unit 410 Control voltage providing unit 500 Adder 520 First mirror unit 530 Second mirror unit 540 Third mirror unit

Claims (37)

  1. A temperature-proportional current generation unit composed of only active circuit elements that generate a first current proportional to the operating temperature;
    A temperature inversely proportional current generation unit composed of only active circuit elements that generate a second current inversely proportional to the operating temperature;
    An adder comprising only active circuit elements for generating the bias current by adding the first current and the second current, the A-containing Muba bias current generator,
    The bias current is generated substantially independent of the operating temperature;
    The temperature proportional current generator is
    The first PMOS transistor and the second PMOS transistor are connected in series between a first reference voltage and a first node, and the third PMOS transistor and the fourth PMOS transistor are: The first and third PMOS transistors are connected in series between the first reference voltage and the second node, the gates of the first and third PMOS transistors are connected to the first node, and the gates of the second and fourth PMOS transistors are connected to the first node. A PMOS cascode current mirror coupled to one bias voltage;
    The first NMOS transistor and the second NMOS transistor are connected in series between the first node and the third node, and the third NMOS transistor and the fourth NMOS transistor are: The second node and the fourth node are connected in series, the gates of the first NMOS transistor and the third NMOS transistor are connected to a second bias voltage, and the gates of the second NMOS transistor and the fourth NMOS transistor are connected to the second node. An NMOS cascode current mirror coupled to two nodes;
    A first diode connected in series between the third node and a second reference voltage;
    A second diode connected in series between the fourth node and the second reference voltage;
    The temperature inversely proportional current generator is
    A fifth PMOS transistor and a sixth POS transistor connected in series between the first reference voltage and a fifth node;
    A fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage;
    A seventh PMOS transistor connected between the first reference voltage and a sixth node;
    A seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, and a gate of the fifth PMOS transistor is connected to the first node; Are connected to the first bias voltage, gates of the fifth NMOS transistor and the sixth NMOS transistor are respectively connected to diodes, a gate of the seventh PMOS transistor is connected to the sixth node, and a gate of the seventh NMOS transistor is connected. A gate connected to the second node; a gate of the eighth NMOS transistor connected to the fifth node;
    The adding unit is
    An eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node;
    A tenth PMOS transistor connected between the first reference voltage and the seventh node;
    A ninth NMOS transistor connected between the seventh node and the second reference voltage;
    A tenth NMOS transistor connected between a bias node for generating the bias current and the second reference voltage; a gate of the eighth PMOS transistor connected to the first node; The gate is connected to the first bias voltage, the gate of the tenth PMOS transistor is connected to the sixth node, the gate of the ninth NMOS transistor is connected to the seventh node, and the gate of the tenth NMOS transistor is the first node. A bias current generator connected to 7 nodes .
  2. It said first reference voltage is a power supply voltage, the bias current generator of claim 1, wherein said second reference voltage is a ground potential.
  3. The first diode is a PNP-type BJT having an emitter connected to the third node and a base and a collector connected to the second reference voltage , and the second diode has an emitter connected to the fourth node, bias current generator according to claim 1, which is a PNP type BJT base and collector are connected to the second reference voltage.
  4. The first bias voltage has a voltage level that can saturate the second PMOS transistor and the fourth PMOS transistor, and the second bias voltage can saturate the first NMOS transistor and the third NMOS transistor. bias current generator according to claim 1, characterized in that it comprises a voltage level.
  5. The bias current generator is
    A first voltage generator for generating a first bias voltage; a fifteenth to a sixteenth PMOS transistor; a fourteenth to a sixteenth NMOS transistor; and a third diode, the eleventh to fourteenth PMOS transistors and the eleventh to thirteenth NMOS transistors. A bias voltage generator having a second voltage generator for generating a second bias voltage, wherein the eleventh PMOS transistor and the eleventh NMOS transistor are connected in series between the first reference voltage and the second reference voltage. A gate of the eleventh PMOS transistor is coupled to a first node; a gate of the eleventh NMOS transistor is coupled to a junction node between the eleventh PMOS transistor and the eleventh NMOS transistor;
    The twelfth PMOS transistor and the twelfth NMOS transistor are connected in series between the first reference voltage and the second reference voltage, and a gate of the twelfth PMOS transistor is between the twelfth PMOS transistor and the twelfth NMOS transistor. A gate of the twelfth NMOS transistor is coupled to a gate of the eleventh NMOS transistor;
    The thirteenth to fourteenth PMOS transistors and the thirteenth NMOS transistor are connected in series between the first reference voltage and the second reference voltage, and a gate of the thirteenth PMOS transistor is connected to a gate of the twelfth PMOS transistor. A gate of the fourteenth PMOS transistor is connected to a junction node between the fourteenth PMOS transistor and the thirteenth NMOS transistor; a gate of the thirteenth NMOS transistor is connected to a gate of the twelfth NMOS transistor;
    The fifteenth PMOS transistor and the fifteenth NMOS transistor are connected in series between the first reference voltage and an eighth node, and a gate of the fifteenth PMOS transistor is connected to the first node. A gate connected to a junction node between the fifteenth PMOS transistor and the fifteen NMOS transistor;
    The sixteenth PMOS transistor, the fourteenth NMOS transistor, and the sixteenth NMOS transistor are connected in series between the first reference voltage and the eighth node, and a gate of the sixteenth PMOS transistor is connected to the first node. A gate of the fourteenth NMOS transistor is connected to a junction node between the sixteenth PMOS transistor and the fourteenth NMOS transistor; a gate of the sixteenth NMOS transistor is connected to a gate of the fifteenth NMOS transistor;
    The third diode is connected in series between the eighth node and the second reference voltage, and the junction node between the fourteenth PMOS transistor and the thirteenth NMOS transistor generates the first bias voltage. a bias current generator according to claim 1, wherein said joining node, characterized in that to generate the second bias voltage between said first 14NMOS transistor and the second 16PMOS transistor.
  6. The third diode is
    6. The bias current generator of claim 5, wherein the emitter is a PNP-type BJT having an emitter connected to the eighth node and a base and a collector connected to the second reference voltage.
  7. The bias current generator is
    Bias current generator according to claim 1, further comprising a starting unit in which the transistors of the temperature-proportional current generating unit and the temperature is inversely proportional current generating unit to disengage from the degenerate bias point.
  8. The starter is
    A seventeenth PMOS transistor;
    An eighteenth PMOS transistor;
    A nineteenth NMOS transistor;
    A twentieth NMOS transistor;
    A seventeenth NMOS transistor connected in series between the first node and the two reference voltages;
    An eighteenth NMOS transistor connected between the first bias voltage and the second reference voltage, and the seventeenth to eighteenth PMOS transistors and the nineteenth to twentieth NMOS transistors are connected to the first reference voltage and the second reference voltage, respectively. A gate of each of the seventeenth to eighteenth PMOS transistors is connected to the second reference voltage, and a gate of the nineteenth NMOS transistor is connected to the second bias voltage. 8. The bias current generator of claim 7, wherein a gate of the twentieth NMOS transistor is connected to the second node.
  9. The adding unit is
    A first mirror that generates a first mirror current corresponding to the first current generated by the temperature proportional current generator;
    A second mirror unit that generates a second mirror current corresponding to the second current generated by the temperature inversely proportional current generation unit;
    The bias current generator according to claim 1, further comprising: a third mirror unit that generates the bias current by adding the first mirror current and the second mirror current.
  10. The first current is
    The first current path and the second current path are generated based on a first transistor size of at least one transistor in the first current path and a second trans size of at least one transistor in the second current path. 2. The bias according to claim 1, wherein the bias is configured in a current mirror form, and the first transistor size and the second transistor size corresponding to the transistors of the first current path and the second current path are different from each other. Current generator.
  11. The second current is
    It is generated based on the voltage generated by the temperature-proportional current generating unit, according to claim 10, wherein the voltage is divided by the active circuit elements of the temperature inversely proportional current generating unit, wherein the second current is generated The bias current generator described.
  12. The temperature proportional current generator is
    A first current path comprising only a plurality of transistors;
    A second current path including only a plurality of transistors, and at least one of the plurality of transistors of the second current path corresponds to one of the plurality of transistors of the first current path, and At least a pair of transistors corresponding to one current path and the second current path have different transistor sizes, and the first current is generated corresponding to the different transistor sizes. The bias current generator according to claim 1.
  13. The temperature inversely proportional current generator is
    A third current path including only a plurality of transistors, the second current is generated based on a voltage generated by the temperature proportional current generation unit, and the voltage is divided by the transistors of the third current path; bias current generator of claim 12 wherein the second current is generated, wherein the Turkey.
  14. A temperature-proportional current generation unit composed of only active circuit elements that generate a first current proportional to the operating temperature;
    A temperature inversely proportional current generation unit composed of only active circuit elements that generate a second current inversely proportional to the operating temperature;
    A bias current generator including an adding unit composed only of active circuit elements that generate a bias current by adding the first current and the second current,
    The bias current is generated substantially independent of the operating temperature;
    The temperature proportional current generator is
    A first diode coupled in series between the first reference voltage and the third node;
    A second diode connected in series between the first reference voltage and a fourth node;
    Consists first to 4PMOS transistor, said first 1PMOS transistor and the second 2PMOS transistor is connected in series between the third node and the first node, said first 3PMOS transistor and the second 4PMOS transistor fourth A gate connected to the second node, and gates of the second PMOS transistor and the fourth PMOS transistor are connected to a first bias voltage. A PMOS cascode current mirror coupled to
    Consists first to 4NMOS transistor, said first 1NMOS transistor and the second 2NMOS transistor are connected in series between said first node and a second reference voltage, said first 3NMOS transistor and the second 4NMOS transistor the first Two nodes and the second reference voltage are connected in series, the gates of the first NMOS transistor and the third NMOS transistor are connected to a second bias voltage, and the gates of the second NMOS transistor and the fourth NMOS transistor are and an NMOS cascode current mirror coupled to the first node, only including,
    The temperature inversely proportional current generator is
    A fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node;
    A fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage;
    A seventh PMOS transistor and an eighth PMOS transistor connected in series between the first reference voltage and a sixth node;
    A seventh NMOS transistor connected between the sixth node and the second reference voltage, wherein the fifth PMOS transistor and the sixth PMOS transistor are diode-connected, and the gate of the fifth NMOS transistor is the second NMOS transistor. A gate of the sixth NMOS transistor is connected to the first node, a gate of the seventh PMOS transistor is connected to the fifth node, and a gate of the eighth PMOS transistor is connected to the second node; A gate of the seventh NMOS transistor is connected to the sixth node;
    The adding unit is
    An eighth NMOS transistor and a ninth NMOS transistor connected in series between a seventh node and the second reference voltage;
    A tenth NMOS transistor connected between the seventh node and the second reference voltage;
    A ninth PMOS transistor connected between the first reference voltage and the seventh node;
    A tenth PMOS transistor connected between the first reference voltage and a bias node where the bias current is generated, and the gate of the eighth NMOS transistor is connected to the second bias voltage, and the ninth NMOS transistor. The gate of the tenth NMOS transistor is connected to the sixth node, the gate of the ninth PMOS transistor is connected to the seventh node, and the gate of the tenth PMOS transistor is connected to the first node. features and to Luba bias current generator that is connected to the seventh node.
  15. It said first reference voltage is a power supply voltage, the bias current generator according to claim 14, wherein said second reference voltage is a ground potential.
  16. The first diode is an NPN BJT having an emitter connected to the third node and a base and a collector connected to the first reference voltage , and the second diode has an emitter connected to the fourth node; bias current generator according to claim 14, characterized in that an NPN BJT base and collector are connected to the first reference voltage.
  17. The first bias voltage has a voltage level that can saturate the second PMOS transistor and the fourth PMOS transistor, and the second bias voltage can saturate the first NMOS transistor and the third NMOS transistor. The bias current generator of claim 14 having a voltage level.
  18. Includes a first current path and a second current path consisting only of a plurality of transistors consists of only a plurality of transistors, and a temperature proportional current generator for generating a first current proportional to the operating temperature,
    A temperature inversely proportional current generating unit including a third current path including only a plurality of transistors and generating a second current inversely proportional to the operating temperature;
    An adder that adds the first current and the second current to generate a bias current;
    The bias current is generated without substantially independent with respect to the operating temperature, among the plurality of transistors of the second current path, at least one and one of the plurality of transistors of said first current path Correspondingly, at least a pair of the transistors corresponding to the first current path and the second current path has different transistor sizes, and the first current is generated corresponding to the different transistor sizes, The second current is generated based on a voltage generated by the temperature proportional current generation unit, the voltage is divided by the transistors in the third current path, and the second current is generated. Current generator.
  19. The temperature proportional current generator is
    Is composed of a first to 4PMOS transistor, said first 1PMOS transistor and the second 2PMOS transistor are connected in series between the first reference voltage and a first node, said first 3PMOS transistor and the second 4PMOS transistor, the The first and third PMOS transistors are connected in series between a first reference voltage and a second node, the gates of the first and third PMOS transistors are connected to the first node, and the gates of the second and fourth PMOS transistors are connected to the first node. A PMOS cascode current mirror coupled to one bias voltage;
    The first NMOS transistor and the second NMOS transistor are connected in series between the first node and the third node, and the third NMOS transistor and the fourth NMOS transistor are: The gates of the first NMOS transistor and the third NMOS transistor are connected to a second bias voltage, and the gates of the second NMOS transistor and the fourth NMOS transistor are connected to the second node and the fourth node, respectively. An NMOS cascode current mirror coupled to the second node;
    A first diode coupled in series between the third node and a second reference voltage;
    19. The bias current generator of claim 18 , further comprising a second diode connected in series between the fourth node and the second reference voltage.
  20. It said first reference voltage is a power supply voltage, the bias current generator according to claim 19, wherein said second reference voltage is a ground potential.
  21. It said first diode emitter is connected to the third node, a PNP type BJT base and collector are connected to a second reference voltage, said second diode is connected emitter to said fourth node, base and bias current generator according to claim 19, wherein the collector is a PNP type BJT that is coupled to the second reference voltage.
  22. The first bias voltage has a voltage level capable of saturating the second PMOS transistor and the fourth PMOS transistor, and the second bias voltage is a voltage capable of saturating the first NMOS transistor and the third NMOS transistor. 20. The bias current generator of claim 19 , wherein the bias current generator has a level.
  23. The temperature inversely proportional current generator is
    A fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node;
    A fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage;
    A seventh PMOS transistor connected between the first reference voltage and a sixth node;
    A seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the second reference voltage, and a gate of the fifth PMOS transistor is connected to the first node; The fifth NMOS transistor and the sixth NMOS transistor are each connected to a diode, the gate of the seventh PMOS transistor is connected to the sixth node, and the gate of the seventh NMOS transistor is connected to the first bias voltage. The bias current generator of claim 19 , wherein the bias current generator is connected to the second node, and a gate of the eighth NMOS transistor is connected to the fifth node.
  24. The adding unit is
    An eighth PMOS transistor and a ninth PMOS transistor connected in series between the first reference voltage and a seventh node;
    A tenth PMOS transistor connected between the first reference voltage and the seventh node;
    A ninth NMOS transistor connected between the seventh node and the second reference voltage;
    A tenth NMOS transistor connected between a bias node for generating the bias current and the second reference voltage; a gate of the eighth PMOS transistor connected to the first node; the gate is coupled to the first bias voltage, the gate of the second 10PMOS transistor is connected to the sixth node, a gate of said first 9NMOS transistor is consolidated to the seventh node, a gate of said first 10NMOS transistor the first The bias current generator of claim 23 , wherein the bias current generator is connected to 7 nodes.
  25. The bias current generator is
    Including 11th to 14th PMOS transistors and 11th to 13th NMOS transistors, including a first voltage generator for generating a first bias voltage, 15th to 16th PMOS transistors, 14th to 16th NMOS transistors and a third diode; A bias voltage generator having a second voltage generator for generating two bias voltages, wherein the eleventh PMOS transistor and the eleventh NMOS transistor are connected in series between the first reference voltage and the second reference voltage; A gate of the eleventh PMOS transistor is connected to a first node; a gate of the eleventh NMOS transistor is connected to a junction node between the eleventh PMOS transistor and the eleventh NMOS transistor;
    The twelfth PMOS transistor and the twelfth NMOS transistor are connected in series between the first reference voltage and the second reference voltage, and a gate of the twelfth PMOS transistor is a junction of the twelfth PMOS transistor and the twelfth NMOS transistor. A gate of the twelfth NMOS transistor is coupled to a gate of the eleventh NMOS transistor;
    The thirteenth to fourteenth PMOS transistors and the thirteenth NMOS transistor are connected in series between the first reference voltage and the second reference voltage, and the gate of the thirteenth PMOS transistor is connected to the gate of the twelfth PMOS transistor. A gate of the fourteenth PMOS transistor is connected to a junction node between the fourteenth PMOS transistor and the thirteenth NMOS transistor; a gate of the thirteenth NMOS transistor is connected to a gate of the twelfth NMOS transistor;
    The fifteenth PMOS transistor and the fifteenth NMOS transistor are connected in series between the first reference voltage and an eighth node, the fifteenth PMOS transistor gate is connected to the first node, and the gate of the fifteenth NMOS transistor. Is connected to a junction node between the fifteenth PMOS transistor and the fifteenth NMOS transistor,
    The sixteenth PMOS transistor, the fourteenth transistor, and the sixteenth NMOS transistor are connected in series between the first reference voltage and the eighth node, and a gate of the sixteenth PMOS transistor is connected to the first node. A gate of the fourteenth NMOS transistor is connected to a junction node between the sixteenth PMOS transistor and the fourteenth NMOS transistor; a gate of the sixteenth NMOS transistor is connected to a gate of the fifteenth NMOS transistor;
    The third diode is connected in series between the eighth node and the second reference voltage, and the junction node between the fourteenth PMOS transistor and the thirteenth NMOS transistor generates the first bias voltage. The bias current generator as claimed in claim 19 , wherein the junction node between the sixteenth PMOS transistor and the fourteenth NMOS transistor generates the second bias voltage.
  26. The third diode is
    26. The bias current generator of claim 25 , wherein the bias current generator is a PNP type BJT having an emitter connected to the eighth node and a base and a collector connected to the second reference voltage.
  27. The bias current generator is
    The bias current generator according to claim 19 , further comprising a starter configured to cause the transistors of the temperature proportional current generator and the temperature inversely proportional current generator to deviate from a degenerate bias point.
  28. The starter is
    A seventeenth PMOS transistor;
    An eighteenth PMOS transistor;
    A nineteenth NMOS transistor;
    A twentieth NMOS transistor;
    A seventeenth NMOS transistor connected in series between the first node and the two reference voltages;
    An eighteenth NMOS transistor connected between the first bias voltage and the second reference voltage, and the seventeenth to eighteenth PMOS transistors and the nineteenth to twentieth NMOS transistors are connected to the first reference voltage and the second reference voltage, respectively. A gate of each of the seventeenth to eighteenth PMOS transistors is connected to the second reference voltage, and a gate of the nineteenth NMOS transistor is connected to the second bias voltage. 28. The bias current generator of claim 27, wherein a gate of the twentieth NMOS transistor is connected to the second node.
  29. The adding unit is
    A first mirror that generates a first mirror current corresponding to the first current generated by the temperature proportional current generator;
    A second mirror unit that generates a second mirror current corresponding to the second current generated by the temperature inversely proportional current generation unit;
    The bias current generator according to claim 18 , further comprising: a third mirror unit that generates the bias current by adding the first mirror current and the second mirror current.
  30. The temperature proportional current generator is
    A first current path comprising only a plurality of transistors;
    A second current path including only a plurality of transistors, and at least one of the plurality of transistors of the second current path corresponds to one of the plurality of transistors of the first current path, and At least a pair of transistors corresponding to one current path and the second current path have different transistor sizes, and the first current is generated corresponding to the different transistor sizes. The bias current generator according to claim 18 .
  31. The temperature inversely proportional current generator is
    And a third current path consisting only of a plurality of transistors, a second current is generated based on the voltage generated by the temperature-proportional current generating unit, wherein the voltage is the temperature inversely proportional current generating portion of the active circuit elements The bias current generator according to claim 30 , wherein the second current is generated by dividing the current by the first current.
  32. The temperature proportional current generator is
    A first diode coupled in series between the first reference voltage and the third node;
    A second diode connected in series between the first reference voltage and a fourth node;
    First to fourth PMOS transistors, wherein the first PMOS transistor and the second PMOS transistor are connected in series between a third node and a first node, and the third PMOS transistor and the fourth PMOS transistor are the fourth node. And the second node, the gates of the first PMOS transistor and the third PMOS transistor are connected to the second node, and the gates of the second PMOS transistor and the fourth PMOS transistor are set to the first bias voltage. A coupled PMOS cascode current mirror;
    The first NMOS transistor and the second NMOS transistor are connected in series between the first node and a second reference voltage, and the third NMOS transistor and the fourth NMOS transistor are the second NMOS transistor. A node connected in series with the second reference voltage; gates of the first NMOS transistor and the third NMOS transistor are connected to a second bias voltage; and gates of the second NMOS transistor and the fourth NMOS transistor are connected to the second NMOS transistor. The bias current generator according to claim 18 , further comprising an NMOS cascode current mirror coupled to one node.
  33. It said first reference voltage is a power supply voltage, the bias current generator according to claim 32, wherein said second reference voltage is a ground potential.
  34. The first diode is an NPN BJT having an emitter connected to the third node and a base and a collector connected to the first reference voltage , and the second diode has an emitter connected to the fourth node; bias current generator according to claim 32, wherein the base and the collector is an NPN BJT that is coupled to said first reference voltage.
  35. The first bias voltage has a voltage level that can saturate the second PMOS transistor and the fourth PMOS transistor, and the second bias voltage can saturate the first NMOS transistor and the third NMOS transistor. The bias current generator of claim 32 , having a voltage level.
  36. The temperature inversely proportional current generator is
    A fifth PMOS transistor and a sixth PMOS transistor connected in series between the first reference voltage and a fifth node;
    A fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the second reference voltage;
    A seventh PMOS transistor and an eighth PMOS transistor connected in series between the first reference voltage and the sixth node;
    A seventh NMOS transistor connected between the sixth node and the second reference voltage, wherein the fifth PMOS transistor and the sixth PMOS transistor are diode-connected, and the gate of the fifth NMOS transistor is the second NMOS transistor. A gate of the sixth NMOS transistor is connected to the first node, a gate of the seventh PMOS transistor is connected to the fifth node, and a gate of the eighth PMOS transistor is connected to the second node; The bias current generator of claim 32, wherein a gate of the seventh NMOS transistor is connected to the sixth node.
  37. The adding unit is
    An eighth NMOS transistor and a ninth NMOS transistor connected in series between a seventh node and the second reference voltage;
    A tenth NMOS transistor coupled between the seventh node and the second reference voltage;
    A ninth PMOS transistor connected between the first reference voltage and the seventh node;
    A tenth PMOS transistor connected between the first reference voltage and a bias node where the bias current is generated, and a gate of the eighth NMOS transistor is connected to the second bias voltage, and the ninth NMOS transistor. The gate of the tenth NMOS transistor is connected to the sixth node, the gate of the ninth PMOS transistor is connected to the seventh node, and the gate of the tenth PMOS transistor is connected to the seventh node. The bias current generator of claim 36 , wherein the bias current generator is coupled to a node.
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US11/225,587 US7227401B2 (en) 2004-11-15 2005-08-31 Resistorless bias current generation circuit

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