TW201901971A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

A semiconductor device having favorable electrical characteristics is provided. One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes an oxide, a first insulator over the oxide, a conductor over the first insulator, and a second insulator on the side surface of the first insulator and the side surface of the conductor. The oxide includes a first region, a second region, and a third region between the first region and the second region. The first insulator is over the first region. The third region includes a region overlapping with the second insulator. Oxygen concentration of the second region is lower than oxygen concentration of the first region and oxygen concentration of the third region. The third region includes a region having oxygen concentration between the oxygen concentration of the first region and the oxygen concentration of the second region.

Description

Semiconductor device and manufacturing method of semiconductor device

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. An embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

Note that in this specification and the like, a semiconductor device refers to all devices capable of operating by utilizing semiconductor characteristics. In addition to a semiconductor element such as a transistor, a semiconductor circuit, a computing device, or a memory device is also an embodiment of a semiconductor device. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting equipment, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may include semiconductor devices.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, an embodiment of the present invention relates to a process, a machine, a product, or a composition of matter.

In recent years, semiconductor devices have been developed, mainly using LSIs, CPUs, and memories. The CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit (including at least a transistor and a memory) separated from a semiconductor wafer and formed with electrodes as connection terminals.

Semiconductor circuits (IC chips) such as LSI, CPU, memory, etc. are mounted on a circuit substrate such as a printed wiring board, and are used as one of components of various electronic devices.

In addition, a technique of forming a transistor by using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits (ICs) and video display devices (also simply referred to as display devices). As a semiconductor thin film that can be applied to a transistor, a silicon-based semiconductor material is widely known. In addition, oxide semiconductors have attracted attention as other materials.

It is known that the leakage current in the non-conductive state of a transistor using an oxide semiconductor is extremely small. For example, a low-power-consumption CPU or the like to which a small leakage current characteristic using a transistor using an oxide semiconductor is applied has been disclosed (see Patent Document 1).

In addition, as a transistor using an oxide semiconductor, a transistor having a self-aligned structure has been proposed. As a method for manufacturing a self-aligned transistor, a method is disclosed in which a metal film is formed on a source region and a drain region, and the metal film is heat-treated to increase the resistance of the metal film while reducing the source region. And the resistance of the drain region (see Patent Document 2).

In addition, as a method for manufacturing a transistor using an oxide semiconductor, a method is disclosed in which a metal film is formed on a source region and a drain region, and then a heat treatment is performed to introduce a dopant through the metal film to reduce a source electrode. Method of the resistance in the region and the drain region (see Patent Document 3).

In addition, in recent years, with the miniaturization and weight reduction of electronic devices, the demand for integrated circuits in which transistors and the like are integrated at high density has increased. In addition, there is a need to improve the productivity of semiconductor devices including integrated circuits.

[Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-228622 [Patent Document 3] Japanese Patent Application Publication No. 2013-016782

In Patent Document 2, when the resistance of the source region and the drain region is reduced, a metal film is formed on the source region and the drain region, and the metal film is heat-treated in an oxygen atmosphere. By performing the heat treatment, the constituent elements of the metal film are introduced as dopants into the source region and the drain region of the oxide semiconductor film to reduce the resistance. In addition, by conducting heat treatment in an oxygen atmosphere, the conductive film is oxidized to increase the resistance of the conductive film. In addition, since the heat treatment is performed in an oxygen atmosphere, it is difficult for the metal film to extract oxygen from the oxide semiconductor film.

In addition, although Patent Document 2 describes the oxygen concentration in the channel formation region, it does not involve the concentration of impurities such as water or hydrogen. In other words, since high purification of the channel formation region (reduction of impurities such as water or hydrogen, typically dehydration and dehydrogenation) is not performed, there is a problem that the transistor characteristics are easily turned on. The normally-on transistor characteristic refers to a state in which a channel exists even when no voltage is applied to the gate, and a current flows through the transistor. In contrast, a transistor characteristic that is normally turned off refers to a state in which a current does not flow through the transistor when a voltage is not applied to the gate.

In view of the above problems, an object of one embodiment of the present invention is to provide a semiconductor device in which a channel formation region is highly purified while stably reducing the resistance of a source region and a drain region of a transistor, thereby achieving good results. Electrical characteristics.

Another object of one embodiment of the present invention is to provide a semiconductor device capable of miniaturization or high integration. An object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long period of time. An object of one embodiment of the present invention is to provide a semiconductor device having a fast data writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of the above purpose does not prevent the existence of other purposes. In addition, one embodiment of the present invention is not required to achieve all the above-mentioned objects. In addition, the purposes other than these are natural and clear from the description of the description, drawings, and scope of patent application, and other purposes can be derived from the description of the description, drawings, and scope of patent application.

An embodiment of the present invention is a semiconductor device including a transistor, wherein the transistor includes an oxide, a first insulator on the oxide, a conductor on the first insulator, a side surface of the first insulator, and a side surface of the conductor. The second insulator, the oxide includes a first region, a second region, and a third region between the first region and the second region, the first insulator is located on the first region, and the third region includes an overlap with the second insulator The second region has a lower oxygen concentration than the first region and the third region. The third region includes a region having an oxygen concentration between the first region and the second region.

An embodiment of the present invention is a semiconductor device including a transistor, wherein the transistor includes an oxide, a first insulator and a first film on the oxide, a conductor on the first insulator, a side surface of the first insulator, and a conductivity A second insulator on the side of the body, the oxide includes a first region, a second region, and a third region between the first region and the second region; the first film is in contact with the second region; the first insulator is located at the first In the region, the third region includes a region overlapping the second insulator. The second region has a lower oxygen concentration than the first region and the third region. The third region includes the oxygen concentration between the first region and the second region. The area of oxygen concentration.

In the above aspect, it is preferable that the oxide contains In, the element M (M is Al, Ga, Y, or Sn) and Zn.

In the above aspect, the atomic ratio of In in the oxide is preferably larger than that of the element M.

In the above aspect, the second region preferably includes at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above aspect, it is preferable that the second region further contains nitrogen.

In the above aspect, the hydrogen concentration in the first region is preferably lower than that in the second region.

In the above aspect, the hydrogen concentration in the first region is preferably lower than that in the second region and the third region.

In the above mode, it is preferable that the transistor is a normally-off transistor.

In the above aspect, it is preferable that the first film is partially mixed with the second region.

In the above aspect, the first film preferably includes at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

In the above aspect, it is preferable that the first film further contains nitrogen.

In the above aspect, the thickness of the first film is preferably 0.5 nm or more and less than 5 nm.

One embodiment of the present invention is a method for manufacturing a semiconductor device including a transistor, wherein the transistor includes an oxide and an oxide including a first region, a second region, and a third region between the first region and the second region. The first insulator on the first insulator, the conductor on the first insulator, the second insulator on the side of the first insulator, and the second insulator on the side of the conductor. The manufacturing method of the semiconductor device includes: covering the oxide, the first insulator, the conductor, and the first insulator. Forming a first film containing a metal with two insulators in contact with the second region; and performing at least a first heat treatment on the oxide and the first film under an atmosphere containing nitrogen to extract the oxygen contained in the second region to the first region; A film.

In the above aspect, the first film is preferably formed by a sputtering method using one or two gases of argon and nitrogen.

In the above aspect, the first film may be removed after the first heat treatment.

In the above aspect, the second heat treatment may be further performed after the first heat treatment.

In the above aspect, a second film covering at least the oxide, the first insulator, the conductor, and the second insulator may be formed after the first heat treatment.

According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to an embodiment of the present invention, it is possible to provide a semiconductor device capable of achieving miniaturization or high integration. According to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

In addition, a semiconductor device capable of holding data for a long period of time can be provided. In addition, a semiconductor device having a fast data writing speed can be provided. In addition, a semiconductor device having a high design flexibility can be provided. In addition, a semiconductor device capable of suppressing power consumption can be provided. In addition, a novel semiconductor device can be provided.

Note that the description of these effects does not prevent the existence of other effects. In addition, one embodiment of the present invention does not need to have all of the above effects. In addition, effects other than these effects are naturally clear from the description of the description, drawings, and scope of patent application, and other effects can be obtained from the description of the description, drawings, and scope of patent application.

Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art can easily understand the fact that the implementation can be implemented in many different forms, and the manner and details can be changed without departing from the spirit and scope of the present invention. For various forms. Therefore, the present invention should not be interpreted as being limited to the content described in the following embodiments.

In the drawings, the size, thickness, or area of an layer is sometimes exaggerated for clarity. Therefore, the present invention is not necessarily limited to the above dimensions. In addition, since ideal examples are schematically shown in the drawings, the present invention is not limited to the shapes, numerical values, and the like shown in the drawings. For example, in an actual manufacturing process, a layer or a photoresist mask may be thinned unintentionally due to a process such as etching, but the illustration may be omitted for ease of understanding. In addition, in the drawings, the same element symbols may be commonly used between different drawings to represent the same parts or parts having the same functions, and repeated descriptions thereof are omitted. In addition, the same hatching is sometimes used when representing parts having the same function, and element symbols are not particularly attached.

In addition, particularly in a plan view (also referred to as a plan view) or a perspective view, in order to facilitate understanding of the invention, the description of some components may be omitted. In addition, descriptions such as partially hidden lines may be omitted.

In addition, in this specification and the like, ordinal numbers such as first and second are added for convenience, and they do not indicate a process order or a stacking order. Therefore, for example, "first" may be appropriately replaced with "second" or "third" and the like. In addition, the ordinal numbers described in this specification and the like do not always match the ordinal numbers used to designate one embodiment of the present invention.

In this specification and the like, for convenience, terms such as “up”, “down” and the like are used to describe the positional relationship of components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to a direction in which each component is described. Therefore, it is not limited to the words and phrases described in this specification, and can be replaced as appropriate according to circumstances.

For example, in this specification and the like, when "X and Y are connected", it means that X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship (for example, a connection relationship shown in a drawing or a text), and a connection relationship other than the connection relationship shown in a drawing or the text is also included in the content described in the drawing or the text.

Here, X and Y are objects (for example, devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

As an example of a case where X and Y are directly connected, there is an element (such as a switch, transistor, capacitor, inductor, resistor, diode, Display element, light emitting element, load, etc.), and X and Y are not electrically connected to X and Y by elements (such as switches, transistors, capacitors, inductors, resistors, diodes, display elements, light emitting elements, and Load, etc.).

As an example of the case where X and Y are electrically connected, for example, one or more elements (such as a switch, a transistor, a capacitor, an inductor, a resistor, and a diode) capable of electrically connecting X and Y may be connected between X and Y. , Display elements, light-emitting elements, and loads). In addition, the switch has a function of controlling opening and closing. In other words, whether the current is allowed to flow is controlled by putting the switch in a conducting state (on state) or a non-conducting state (off state). Alternatively, the switch has a function of selecting and switching a current path. The case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (inverter, NAND circuit, NOR, etc.) may be connected between X and Y. Circuit, etc.), signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level of changing the potential level of the signal Quasi-transfer circuits, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase the signal width or current, etc., operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), Signal generation circuit, memory circuit, control circuit, etc.). Note that, for example, even if another circuit is sandwiched between X and Y, when a signal output from X is transmitted to Y, it can be said that X and Y are functionally connected. In addition, the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In this specification and the like, a transistor refers to an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel forming region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and the current through the channel forming region Can flow between source and drain. Note that, in this specification and the like, a region where a channel is formed refers to a region through which a current mainly flows.

In addition, in a case where transistors having different polarities are used or a current direction changes during circuit operation, the functions of the source and the drain may be exchanged with each other. Therefore, in this specification and the like, the source and the drain may be interchanged with each other.

Note that the channel length refers to, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor flows when the transistor is on) and a gate electrode overlap each other or a source in a region where a channel is formed in a plan view of the transistor (Source area or source electrode) and the drain (drain area or source electrode). In addition, in a transistor, the channel length does not necessarily have to be the same value in all regions. That is, the channel length of a transistor is sometimes not limited to a value. Therefore, in this specification, the channel length is any value, maximum value, minimum value, or average value in the area where the channel is formed.

The channel width refers to, for example, a region in which a semiconductor (or a portion in which a current flows when the transistor is in an on state) and a gate electrode overlap each other, or a portion where a source and a drain are opposite to each other in a region where a channel is formed. length. In addition, in one transistor, the channel width does not necessarily have to be the same value in all regions. That is, the channel width of a transistor is sometimes not limited to a value. Therefore, in this specification, the channel width is any value, maximum value, minimum value, or average value in the area where the channel is formed.

In addition, depending on the structure of the transistor, the actual channel width (hereinafter also referred to as "effective channel width") in the region where the channel is formed and the channel width (hereinafter also referred to as " Apparent channel width "). For example, when the gate electrode covers the side of the semiconductor, sometimes the effective channel width is larger than the apparent channel width, so its influence cannot be ignored. For example, in a miniature transistor in which a gate electrode covers a side surface of a semiconductor, a proportion of a channel formation region formed on a side surface of the semiconductor may increase. In this case, the effective channel width is greater than the apparent channel width.

In this case, it is sometimes difficult to estimate the effective channel width by actual measurement. For example, to estimate the effective channel width from design values, you need to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is unclear, it is difficult to accurately measure the effective channel width.

Therefore, in this specification, the apparent channel width is sometimes referred to as "Surrounded Channel Width (SCW)." In addition, in this specification, when simply expressed as "channel width", it sometimes means the width of the surrounding channel or the width of the apparent channel. Alternatively, in this specification, when the “channel width” is simply expressed, the effective channel width may be expressed in some cases. Note that by analyzing the cross-section TEM image, etc., values such as channel length, channel width, effective channel width, apparent channel width, and surrounding channel width can be determined.

Note that the impurity of the semiconductor refers to an element other than the main component of the semiconductor, for example. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. Containing impurities may increase the semiconductor's DOS (Density of States: Density of State) and decrease crystallinity. When the semiconductor is an oxide semiconductor, as impurities that change the characteristics of the semiconductor, there are, for example, a group 1 element, a group 2 element, a group 13 element, a group 14 element, a group 15 element, and a main component of the oxide semiconductor. Outside transition metals. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. When the semiconductor is an oxide semiconductor, water may also function as an impurity. When the semiconductor is an oxide semiconductor, oxygen vacancies may be generated due to, for example, entry of impurities. In addition, when the semiconductor is silicon, impurities that change the semiconductor characteristics include, for example, oxygen, a Group 1 element other than hydrogen, a Group 2 element, a Group 13 element, and a Group 15 element.

Note that in this specification and the like, a silicon oxynitride film refers to a film having an oxygen content greater than a nitrogen content. For example, the concentration of oxygen is preferably 55 atomic% or more and 65 atomic% or less, the nitrogen concentration is 1 atomic% or more and 20 atomic% or less, and the silicon concentration is 25 atomic% or more and 35 atomic% or less, and The concentration of hydrogen is within a range of 0.1 atomic% to 10 atomic%. The silicon oxynitride film refers to a film having a nitrogen content greater than an oxygen content. For example, the concentration of nitrogen is preferably 55 atomic% or more and 65 atomic% or less, the oxygen concentration is 1 atomic% or more and 20 atomic% or less, and the silicon concentration is 25 atomic% or more and 35 atomic% or less, and The concentration of hydrogen is within a range of 0.1 atomic% to 10 atomic%.

In addition, in this specification and the like, "film" and "layer" may be interchanged with each other. For example, the "conductive layer" may sometimes be converted into a "conductive film". In addition, for example, the "insulating film" may be converted into an "insulating layer".

In addition, in this specification and the like, the “insulator” may be referred to as an “insulating film” or an “insulating layer”. In addition, the “conductor” may be referred to as a “conductive film” or a “conductive layer”. In addition, "semiconductor" may be referred to as "semiconductor film" or "semiconductor layer".

In addition, unless otherwise stated, the transistor shown in this specification and the like is a field effect transistor. In addition, unless otherwise stated, the transistor shown in this specification and the like is an n-channel transistor. Therefore, unless specifically stated, the threshold voltage (also referred to as "Vth") is greater than 0V.

In this specification and the like, "parallel" refers to a state where the angle formed by two straight lines is -10 ° or more and 10 ° or less. Therefore, a state where the angle is -5 ° or more and 5 ° or less is also included. "Substantially parallel" refers to a state where the angle formed by the two straight lines is -30 ° or more and 30 ° or less. In addition, "vertical" refers to a state where the angle of two straight lines is 80 ° or more and 100 ° or less. Therefore, a state in which the angle is 85 ° or more and 95 ° or less is also included. "Substantially perpendicular" refers to a state where the angle formed by the two straight lines is 60 ° or more and 120 ° or less.

In addition, in this specification, a hexagonal system includes a trigonal system and a rhombohedral system.

Note that in this specification, the barrier film refers to a film having a function of suppressing the transmission of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, it is sometimes referred to as a conductive barrier film.

In this specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as OS), and the like. For example, when a metal oxide is used as the active layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, the OS FET can be referred to as a transistor including an oxide or an oxide semiconductor.

Note that in this specification and the like, normally closed means that a current of 1 mm per channel width flowing through the transistor when no voltage is applied to the gate or a ground potential is applied to the gate is 1 × 10 ^-20 A or less at room temperature, 1 × 10 ^-18 A or lower at 85 ° C, or 1 × 10 ^-16 A or lower at 125 ° C.

Embodiment 1 An example of a semiconductor device including a transistor 200 according to an embodiment of the present invention will be described below.

<Structural Example of Semiconductor Device> FIG. 1A to FIG. 1D are a plan view and a cross-sectional view of a transistor 200 and the periphery of the transistor 200 according to an embodiment of the present invention.

FIG. 1A is a plan view of a semiconductor device including a transistor 200. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion taken along a chain line A1-A2 in FIG. 1A, and the cross-sectional view corresponds to a cross-sectional view in the channel length direction of the transistor 200. FIG. 1C is a cross-sectional view of a portion taken along a chain line A3-A4 in FIG. 1A, and the cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. FIG. 1D is a cross-sectional view of a portion along a chain line A5-A6 in FIG. 1A, and the cross-sectional view is equivalent to a cross-sectional view of a source region or a drain region of the transistor 200. For clarity, some components are omitted in the top view of FIG. 1A.

A semiconductor device according to an embodiment of the present invention includes a transistor 200, an insulator 210 used as an interlayer film, an insulator 212, and an insulator 280. The semiconductor device further includes a conductor 203 electrically connected to the transistor 200 and used as a wiring, and a conductor 240 used as a plug.

In the electric conductor 203, a first electric conductor of the electric conductor 203 is formed so as to be in contact with an inner wall of the opening of the insulator 212, and a second electric conductor of the electric conductor 203 is formed on the inner side of the electric conductor 203. Here, the height of the top surface of the conductor 203 and the height of the top surface of the insulator 212 may be substantially the same. In addition, in the transistor 200, the first conductive body of the conductive body 203 and the second conductive body of the conductive body 203 are laminated, but the present invention is not limited thereto. For example, the conductor 203 may have a single-layer structure or a stacked structure of three or more layers. Moreover, when a structure has a laminated structure, an ordinal number may be given in order of formation to distinguish it.

The conductor 240 is formed so as to be in contact with the inner wall of the opening of the insulator 280. Here, the height of the top surface of the conductor 240 and the height of the top surface of the insulator 280 may be substantially the same. In addition, in the transistor 200, the conductor 240 has a two-layer structure, but the present invention is not limited thereto. For example, the conductor 240 may have a single layer or a stacked structure of three or more layers.

[Transistor 200] As shown in FIGS. 1A to 1D, the transistor 200 includes: an insulator 214 and an insulator 216 on a substrate (not shown); a conductor 205 buried in the insulator 214 and the insulator 216; the insulator 216 and Insulator 220 on conductor 205; insulator 222 on insulator 220; insulator 224 on insulator 222; oxide 230 (oxide 230a, oxide 230b, and oxide 230c) on insulator 224; insulator 250 on oxide 230 ; Metal oxide 252 on insulator 250; conductor 260 (conductor 260a and conductor 260b) on metal oxide 252; insulator 270 on conductor 260; insulator 271 on insulator 270; at least with insulator 250 and conductive An insulator 272 that is in contact with the side surface of the body 260 and that is in contact with a portion of the top surface of the oxide 230c; an insulator that is provided on the side of the conductor 260 through the insulator 272 and on the side of the insulator 224, oxide 230a, and oxide 230b 275; side of insulator 275 and insulator 273 on oxide 230.

In the transistor 200, three layers of an oxide 230a, an oxide 230b, and an oxide 230c are stacked, but the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers may be provided. In addition, in the transistor 200, the conductive body 260a and the conductive body 260b are laminated, but the present invention is not limited to this.

In addition, a metal oxide (hereinafter, sometimes referred to as an oxide semiconductor) used as an oxide semiconductor in the transistor 200 is preferably used to include a region where a channel is formed (hereinafter, sometimes referred to as a channel formation region). Oxide 230 (oxide 230a, oxide 230b, and oxide 230c).

Since the transistor 200 using an oxide semiconductor for the channel formation region has a very small leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. In addition, since the oxide semiconductor can be formed by a sputtering method or the like, it can be used for the transistor 200 constituting a highly integrated semiconductor device.

The oxide 230 is preferably an In-M-Zn oxide (the element M is selected from the group consisting of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, and cerium , Neodymium, praseodymium, tantalum, tungsten, and magnesium). In addition, as the oxide 230, an In-Ga oxide or an In-Zn oxide may be used.

Here, when an oxide semiconductor is added with a metal element such as aluminum, ruthenium, titanium, tantalum, chromium, or tungsten in addition to the elements constituting the oxide semiconductor, the oxide semiconductor becomes a metal compound and its resistance decreases. In addition, aluminum, titanium, tantalum, tungsten, or the like is preferably used. When a metal element is added to the oxide semiconductor, for example, it is preferable to form a metal film containing the metal element, a nitride film or an oxide film containing the metal element on the oxide semiconductor. In addition, when the film is formed, some of the oxygen in the interface between the film and the oxide semiconductor or in the oxide semiconductor near the interface is absorbed into the film, etc., forming oxygen vacancies, and reducing the oxide semiconductor near the interface. The resistance.

In addition, it is preferable to perform a heat treatment in an atmosphere containing nitrogen after forming a metal film or a nitride film or an oxide film containing a metal element on the oxide semiconductor. By performing the heat treatment in an atmosphere containing nitrogen, a metal element is diffused from the metal film or the nitride film or the oxide film containing the metal element to the oxide semiconductor, and the metal element can be added to the oxide semiconductor. At this time, the oxide semiconductor and the metal element may form an alloy. When an oxide semiconductor forms an alloy with a metal element, the metal element added to the oxide semiconductor becomes a relatively stable state, so a highly reliable semiconductor device can be provided.

In addition, when hydrogen in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor and enters oxygen vacancies in the low-resistance region, it becomes a relatively stable state. In addition, it is known that hydrogen in the oxygen vacancies of the oxide semiconductor is separated from the oxygen vacancies by a heat treatment at 250 ° C. or higher and diffuses into the low-resistance region of the oxide semiconductor, enters the oxygen vacancies in the low-resistance region, and becomes a stable state. Therefore, by performing the heat treatment, the resistance of the area where the oxide semiconductor has been reduced in resistance or the area where the metal compound is formed is further reduced, and the area where the resistance of the oxide semiconductor is not reduced is highly purified (reduction of impurities such as water or hydrogen). ), Its resistance further increases.

When an impurity element such as hydrogen or nitrogen is present in the oxide semiconductor, the carrier density increases. In some cases, hydrogen in an oxide semiconductor reacts with oxygen bonded to a metal atom to generate water to form an oxygen vacancy. When hydrogen enters this oxygen vacancy, the carrier density increases. In addition, a part of hydrogen may be bonded to oxygen bonded to a metal atom to generate an electron as a carrier. In other words, the resistance of an oxide semiconductor containing nitrogen or hydrogen decreases.

Therefore, by selectively adding a metal element and impurity elements such as hydrogen and nitrogen to the oxide semiconductor, a high-resistance region and a low-resistance region can be formed in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, a region used as a semiconductor with a low carrier density and a low region used as a source region or a drain region can be formed in the oxide 230 processed into an island shape. Resistance area.

2A and 2B show enlarged views of a region 239 surrounded by a dotted line in FIG. 1B.

As shown in FIG. 2A, the oxide 230 includes a region 234 used as a channel formation region of a transistor, a region 231 (a region 231a and a region 231b) used as a source region or a drain region, and a region 234 and a region 231. Area 232 (area 232a and area 232b).

A region 231 used as a source region or a drain region is a low-resistance region having a low oxygen concentration. In addition, the region 234 used as the channel formation region is a high-resistance region having a higher oxygen concentration and a lower carrier density than the region 231 used as the source region or the drain region. In addition, the region 232 has a higher oxygen concentration and a lower carrier density than the region 231 used as a source region or a drain region, and has a lower oxygen concentration and a carrier than the region 234 used as a channel formation region. High-density areas.

The concentration of at least one of a metal element and an impurity element such as hydrogen and nitrogen in the region 231 is preferably higher than that in the regions 232 and 234.

For example, the region 231 preferably contains one or more metal elements selected from aluminum, ruthenium, titanium, tantalum, tungsten, and chromium in addition to the metal elements included in the oxide 230. By adding a metal element to the oxide 230, the resistance of the region 231 can be reduced. In addition, the region 231 may include a region where the metal element in the oxide 230 and the added metal element form an alloy.

The region 232 has a region overlapping the insulator 272. The concentration of at least one of metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium and impurity elements such as hydrogen and nitrogen in the region 232 is preferably higher than that in the region 234. In order to form the region 232, for example, a metal film or an oxide film or a nitride film containing a metal element may be formed so as to be in contact with the region 231 of the oxide 230. As a result, a metal element in the film may be added to the oxide semiconductor to form a metal compound in the oxide semiconductor. This metal compound may attract hydrogen contained in the oxide 230. As a result, the hydrogen concentration in the region 232 near the region 231 may increase.

In addition, one or both of the region 232a and the region 232b may have a region overlapping the conductor 260.

In FIGS. 1A to 1D and FIGS. 2A and 2B, the region 234, the region 231, and the region 232 are formed in the oxide 230b, but are not limited thereto. For example, these regions may be formed in the oxide 230a or the oxide 230c. In addition, although the boundaries of the regions in FIGS. 1A to 1D and FIGS. 2A and 2B are shown as being substantially perpendicular to the top surface of the oxide 230, this embodiment is not limited thereto. For example, the region 232 may have a shape that protrudes toward the conductor 260 side near the surface of the oxide 230b and retracts toward the conductor 240a side or the conductor 240b side near the bottom surface of the oxide 230b.

In the oxide 230, it is sometimes difficult to clearly observe the boundary of each region. The concentration of the metal element and impurity elements such as hydrogen and nitrogen detected in each region does not necessarily have to be changed in stages for each region, and may be gradually changed in each region (also called gradation). That is, the closer to the channel formation region, the smaller the concentration of metal elements and impurity elements such as hydrogen and nitrogen may be.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of metal elements and impurities that improve conductivity such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium is added to a desired region. As the impurity, an element that forms an oxygen vacancy, an element that is trapped by an oxygen vacancy, or the like can be used. Examples of the element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, and rare gas elements. Typical examples of the rare gas element include helium, neon, argon, krypton, and xenon.

Therefore, by increasing the content of the above-mentioned conductive metal element, the element forming an oxygen vacancy, or the element captured by the oxygen vacancy in the region 231, the carrier density can be increased, and thus the resistance can be reduced.

In order to reduce the resistance of the region 231, for example, it is preferable to form a metal film or an oxide film or a nitride film containing a metal element so as to be in contact with the region 231 of the oxide 230. The metal film or the oxide film or nitride film containing a metal element is preferably provided on the oxide 230 via at least the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, the insulator 271, the insulator 272, and the insulator 275.

When a metal film or an oxide film or a nitride film containing a metal element is formed in contact with the region 231 of the oxide 230, the metal element diffuses from the film to the region 231 of the oxide 230, and a metal compound is formed in the region 231. Its resistance is reduced. In addition, part of the oxygen in the interface between the region 231 and the metal film or the oxide film or nitride film containing a metal element or the oxide 230 near the interface is absorbed into the film, and oxygen vacancies are formed in the region 231, and the resistance reduce.

In addition, in FIG. 2A, a low-resistance region of the oxide 230 is shown by oblique lines as an example. In addition, in this specification and the like, the range shown by the diagonal lines is not limited to the range of FIG. 2A. For example, as shown in FIG. 2B, the low-resistance region (or range) may be formed in a region near the interface between the oxide 230 and the conductor 240 or in the region 231 from the top surface of the oxide 230 to the bottom surface of the oxide 230. Area. In addition, the same applies to other drawings.

The heat treatment is preferably performed in an atmosphere containing nitrogen in a state where the region 231 is in contact with a metal film or a nitride film or an oxide film containing a metal element. By performing this heat treatment, a metal element is diffused from the metal film or the nitride film or the oxide film containing the metal element into the region 231 of the oxide 230, and the metal element can be added to the region 231. At this time, the region 231 of the oxide 230 and the metal element may form an alloy. When the region 231 of the oxide 230 forms an alloy with a metal element, the metal element added to the oxide semiconductor becomes a relatively stable state, and thus a highly reliable semiconductor device can be provided.

In addition, when the hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancy in the region 231, it becomes a relatively stable state. In addition, the hydrogen in the oxygen vacancies in the region 234 is separated from the oxygen vacancies and diffused into the region 231 through a heat treatment at 250 ° C. or higher, and enters into the oxygen vacancies in the region 231 and becomes a relatively stable state. Therefore, by performing the heat treatment, the resistance of the region 231 is further reduced, the region 234 is highly purified (reduction of impurities such as water or hydrogen), and its resistance is further increased.

In addition, since a part of the region of the oxide 230 (the region 234 and the region 232) overlaps the conductor 260 and the insulator 272, the addition of a metal element can be suppressed. In addition, in the regions 234 and 232 of the oxide 230, the absorption of oxygen in the oxide 230 into the above-mentioned metal film or a nitride film or an oxide film containing a metal element can be suppressed.

In addition, when oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed into a metal film or an oxide film or a nitride film containing a metal element, it may be generated in the regions 231 and 232. Oxygen vacancy. When the hydrogen in the oxide 230 enters this oxygen vacancy, the carrier density of the regions 231 and 232 increases. Therefore, the resistance of the regions 231 and 232 of the oxide 230 decreases.

Here, in a case where a metal film or an oxide film or a nitride film containing a metal element has a characteristic of absorbing hydrogen, hydrogen in the oxide 230 is absorbed into the film. Therefore, hydrogen as an impurity in the oxide 230 can be reduced. In addition, a metal film or an oxide film or a nitride film containing a metal element may be removed together with hydrogen absorbed from the oxide 230 in a later process.

In addition, it is not necessary to remove a metal film or an oxide film or a nitride film containing a metal element. For example, when a metal film, an oxide film or a nitride film containing a metal element is oxidized by oxygen absorbed from the oxide 230 and becomes an insulator, and the resistance increases, the film may remain. In this case, the film is sometimes used as an interlayer film.

In addition, for example, in a case where a conductive region remains in a metal film or an oxide film or a nitride film containing a metal element, the region is oxidized by heat treatment in an oxidizing atmosphere to become an insulator, and its resistance increases. . When a metal film or an oxide film or a nitride film containing a metal element is left as an insulator, it can be used as an interlayer film.

Therefore, the thickness of the metal film or the oxide film or nitride film containing a metal element is preferably 0.5 nm or more and 5 nm or less, and more preferably 1 nm or more and 2 nm or less. For example, when aluminum is heat-treated and oxidized to a thickness of 0.5 nm to 5 nm, it may become alumina of 0.7 nm to 8 nm.

Here, in a transistor using an oxide semiconductor, if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to change and reliability may be reduced. In addition, in the case where the channel forming region in the oxide semiconductor contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Therefore, the oxygen vacancies in the region 234 where the channel is formed are reduced as much as possible.

Therefore, as shown in FIGS. 1A to 1D and FIG. 2A, it is preferable to provide an insulator 275 containing oxygen in excess of stoichiometric composition (also referred to as excess oxygen) in contact with the insulator 224, the insulator 272, and the oxide 230 c. In other words, when the excessive oxygen contained in the insulator 275 diffuses into the region 234 of the oxide 230, the oxygen vacancy of the region 234 of the oxide 230 can be reduced.

In addition, as the insulator 275, silicon oxide, silicon oxynitride, silicon oxynitride, or silicon oxide having pores is preferably used. Excessive oxygen regions are easily formed in materials such as silicon oxynitride. On the other hand, compared with the above-mentioned materials such as silicon oxynitride, it is difficult to form an excessive oxygen region in the oxide 230. Therefore, by arranging the insulator 275 containing the region of excess oxygen around the region 234 of the oxide 230, the excess oxygen of the insulator 275 can be efficiently supplied to the region 234 of the oxide 230.

In addition, in order to form an excessive oxygen region in the insulator 275, it is preferable to form an oxide by a sputtering method as the insulator 273 in contact with the insulator 275. By forming an oxide by a sputtering method, an insulator with few impurities such as water or hydrogen can be formed. When a sputtering method is used, for example, it is preferable to form a film using a counter-target sputtering device. The opposite target type sputtering device can form a film without the exposed surface being exposed to a high electric field region between the facing targets. Therefore, the formed surface is less susceptible to plasma damage and can be reduced. The film formation damage to the oxide 230 when an insulator to be the insulator 273 is formed is preferable. A film formation method using an opposing target type sputtering apparatus may be referred to as VDSP (Vapor Deposition SP) (registered trademark).

When a film is formed by a sputtering method, ions and sputtered particles are present between the target and the substrate. For example, the target is connected to a power source and is supplied with a potential E0. In addition, the substrate is supplied with a potential E1 such as a ground potential. Note that the substrate may also be in an electrically floating state. In addition, a region that becomes the potential E2 exists between the target and the substrate. The magnitude relationship of each potential is E2> E1> E0.

By accelerating the ions in the plasma due to the potential difference E2-E0, the ions collide with the target, and the sputtered particles are ejected from the target. The sputtered particles are deposited on a film-forming surface to form a film. In addition, a part of the ions may be recoiled by the target, and may be absorbed into the insulator 275 in contact with the surface to be formed as a recoil ion through the formed film. In addition, the ions in the plasma may be accelerated due to the potential difference E2-E1, and may impact the film-forming surface. At this time, a part of the ions reach the inside of the insulator 275. As the ions are absorbed into the insulator 275, a region in which the ions are absorbed is formed in the insulator 275. In other words, in the case where the ions are ions containing oxygen, an excessive oxygen region is formed in the insulator 275.

By introducing excess oxygen into the insulator 275, a region of excess oxygen can be formed in the insulator 275. Excess oxygen in the insulator 275 is supplied into the region 234 of the oxide 230, which can fill up oxygen vacancies in the oxide 230.

As the insulator 273, alumina is preferably used. When the heat treatment is performed while alumina is in contact with the oxide 230, the alumina may extract hydrogen from the oxide 230 in some cases. Therefore, the hydrogen concentration in the oxide 230 can be reduced.

By combining the above structure or the above process, the resistance of the oxide 230 can be selectively reduced.

In other words, when a low-resistance region is formed in the oxide 230, by using the conductor 260 or the insulator 272 having a function of a gate electrode as a mask, the resistance of the oxide 230 can be self-aligned. Therefore, in the case where a plurality of transistors 200 are formed at the same time, it is possible to reduce unevenness in electrical characteristics among the transistors. In addition, the channel length of the transistor 200 depends on the width of the conductor 260 and the film thickness of the insulator 272. Therefore, by setting the width of the conductor 260 to the minimum feature size, the transistor 200 can be miniaturized.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having the required electrical characteristics according to the circuit design.

In addition, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device. In addition, since an oxide semiconductor is used for the non-conducting state of the transistor in the channel formation region, the leakage current (off-state current) is extremely small, so that a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor having a large on-state current can be provided. Alternatively, a semiconductor device including a transistor having a small off-state current may be provided. Alternatively, a semiconductor device having stable electrical characteristics and high reliability can be realized while suppressing variations in electrical characteristics.

Hereinafter, a detailed configuration of a semiconductor device including the transistor 200 according to an embodiment of the present invention will be described.

As shown in FIGS. 1A and 1C, the conductor 203 extends in the channel width direction and is used as a wiring for applying a potential to the conductor 205. The conductive body 203 is preferably buried in the insulator 212.

The conductor 205 is arranged so as to overlap the oxide 230 and the conductor 260. The conductive body 205 is preferably provided so as to be in contact with the top surface of the conductive body 203. The conductive body 205 is preferably buried in the insulator 214 and the insulator 216.

Here, the conductor 260 is sometimes used as a first gate (also referred to as a top gate) electrode. The conductor 205 is sometimes used as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 200 can be controlled by independently changing the potential supplied to the conductive body 205 without interlocking with the potential supplied to the conductive body 260. In particular, by supplying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be made greater than 0V and the off-state current can be reduced. Therefore, compared with a case where a negative potential is not applied to the conductor 205, the drain current when the potential supplied to the conductor 260 is 0 V can be reduced when a negative potential is applied to the conductor 205.

In addition, by providing the conductive body 205 on the conductive body 203, the distance between the conductive body 260 and the conductive body 203 used as the first gate electrode and the wiring can be appropriately set. That is, when the insulator 214 and the insulator 216 are provided between the conductor 203 and the conductor 260, the parasitic capacitance between the conductor 203 and the conductor 260 can be reduced, and the distance between the conductor 203 and the conductor 260 can be increased. Insulation withstand voltage.

By reducing the parasitic capacitance between the conductive body 203 and the conductive body 260, the switching speed of the transistor 200 can be increased, and a transistor with high frequency characteristics can be realized. In addition, the reliability of the transistor 200 can be improved by increasing the withstand voltage between the conductor 203 and the conductor 260. Therefore, the thicknesses of the insulators 214 and 216 are preferably large. The extending direction of the conductive body 203 is not limited to this, and may extend in the channel length direction of the transistor 200, for example.

As shown in FIG. 1A, the conductor 205 overlaps the oxide 230 and the conductor 260. The conductor 205 is preferably larger than the region 234 in the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 is preferably a region extending outside the end of the region 234 in the oxide 230 that intersects the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap each other with an insulator on a side surface in the channel width direction of the oxide 230.

When the above structure is provided, when the electric potential is supplied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to cover the channel formation region formed in the oxide 230. .

That is, the channel forming region of the region 234 may be electrically surrounded by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In this specification, a structure of a transistor in which a channel formation region is electrically surrounded by the electric field of the first gate electrode and the electric field of the second gate electrode is referred to as a surrounding channel (S-channel) structure.

In the electric conductor 205, a first electric conductor is formed so as to be in contact with the inner walls of the openings of the insulator 214 and the insulator 216, and a second electric conductor is formed on the inner side thereof. Here, the heights of the top surfaces of the first and second conductors and the height of the top surface of the insulator 216 may be substantially the same. Note that the first conductor and the second conductor are laminated in the transistor 200, but the present invention is not limited thereto. For example, the conductor 205 may have a single-layer structure or a stacked structure of three or more layers.

Here, as the first electrical conductor of the electrical conductor 205 or the electrical conductor 203, it is preferable to use a material having a suppressed hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, and nitrogen oxide molecule (N ₂ O, NO, NO ₂ and the like). ), A conductive material with a function of diffusing impurities such as copper atoms (it is not easy to allow the impurities to pass through). In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) (it is difficult to allow the oxygen to pass through). In the present specification, the "function of suppressing the diffusion of impurities or oxygen" means a function of suppressing the diffusion of at least one or all of the impurities and the oxygen.

By making the conductive body 205 or the first conductive body of the conductive body 203 have a function of suppressing the diffusion of oxygen, it is possible to prevent a decrease in conductivity due to the oxidation of the conductive body 205 or the second conductive body of the conductive body 203. As the conductive material having a function of suppressing the diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used. Therefore, the conductive body 205 or the first conductive body of the conductive body 203 may be a single layer or a stack of the aforementioned conductive materials. This can prevent impurities such as hydrogen and water from being diffused to the transistor 200 side through the conductor 203 and the conductor 205.

As the second conductive body of the conductive body 205, a conductive material mainly containing tungsten, copper, or aluminum is preferably used. In the drawings, the second conductor of the conductor 205 has a single-layer structure, but may have a laminated structure. For example, a laminated structure of titanium, titanium nitride, and the above-mentioned conductive material may be used.

Since the second conductor of the conductor 203 is used as a wiring, it is preferable to use a conductor having higher conductivity than the second conductor of the conductor 205. For example, a conductive material containing copper or aluminum as a main component can be used. The second conductor of the conductor 203 may have a laminated structure. For example, a laminated structure of titanium, titanium nitride, and the above-mentioned conductive material may be used.

In particular, copper is preferably used as the conductor 203. Since copper has low resistance, it is preferably used for wiring and the like. On the other hand, copper diffuses easily, and therefore copper diffuses into the oxide 230 and the electrical characteristics of the transistor 200 may decrease. Therefore, for example, by using a material such as alumina or hafnium oxide with low copper permeability as the insulator 214, copper diffusion can be suppressed.

It is not necessary to provide the conductor 205, the insulator 214, and the insulator 216. In this case, a part of the conductor 203 may be used as the second gate electrode.

The insulator 210 and the insulator 214 are preferably used as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, as the insulator 210 and the insulator 214, it is preferable to use a substance that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ and the like), and copper atoms. Function (not easy to let the impurities mentioned above) through the insulating material. In addition, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, and the like) (the oxygen is not easily transmitted through).

For example, it is preferable to use aluminum oxide or the like as the insulator 210 and silicon nitride or the like as the insulator 214. This can prevent impurities such as hydrogen and water from diffusing from the side closer to the substrate than the insulator 210 and the insulator 214 to the transistor 200 side. In addition, it is possible to suppress diffusion of oxygen in the insulator 224 and the like closer to the substrate side than the insulator 210 and the insulator 214.

In addition, by stacking the conductive body 205 on the conductive body 203, an insulator 214 can be provided between the conductive body 203 and the conductive body 205. Here, even if a metal that easily diffuses, such as copper, is used as the second conductor of the conductive body 203, the silicon dipped in silicon or the like as the insulator 214 can prevent the metal from diffusing to a layer above the insulator 214.

The dielectric constant of the insulator 212, the insulator 216, and the insulator 280 used as the interlayer film is preferably lower than that of the insulator 210 or the insulator 214. By using a material with a lower dielectric constant for the interlayer film, it is possible to reduce parasitic capacitance generated between wirings.

Examples of the insulator 212, insulator 216, and insulator 280 include silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconia, lead zirconate titanate (PZT), and strontium titanate (SrTiO). ₃ ) A single layer or a stack of insulators such as (Ba, Sr) TiO ₃ (BST). Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconia may be added to these insulators. These insulators may be subjected to a nitriding treatment. It is also possible to laminate silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

The insulator 220, the insulator 222, and the insulator 224 are used as a gate insulator.

In addition, as the insulator 224 in contact with the oxide 230, an insulator containing more than a stoichiometric composition of oxygen is preferably used. In other words, it is preferable that an excessive oxygen region is formed in the insulator 224. By providing the insulator containing excessive oxygen as described above in contact with the oxide 230, the oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

Specifically, as the insulator having an excessive oxygen region, it is preferable to use an oxide material which is capable of removing a part of oxygen by heating. The oxide that desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen molecules in a TDS (Thermal Desorption Spectroscopy) analysis is 1.0 × 10 ¹⁸ molecules / cm ³ or more, preferably 1.0 × An oxide film of 10 ¹⁹ molecules / cm ³ or more, more preferably 2.0 × 10 ¹⁹ molecules / cm ³ or more, or 3.0 × 10 ²⁰ molecules / cm ³ or more. The surface temperature of the film when the TDS analysis is performed is preferably within a range of 100 ° C to 700 ° C, or a range of 100 ° C to 400 ° C.

When the insulator 224 has an excessive oxygen region, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.) (it is not easy to allow the above-mentioned oxygen to pass through).

By providing the insulator 222 with a function of suppressing the diffusion of oxygen, oxygen in an excess oxygen region included in the insulator 224 can be efficiently supplied to the oxide 230 without being diffused to the insulator 220 side. In addition, it is possible to suppress the reaction between the conductor 205 and the oxygen in the excess oxygen region included in the insulator 224.

As the insulator 222, it is preferable to use, for example, so-called alumina, hafnium oxide, tantalum oxide, zirconia, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). Single-layer or laminate of high-k insulators. When miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material as an insulator used as a gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material having a function of suppressing the diffusion of impurities, oxygen, and the like (the oxygen is not easily transmitted through). As the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use alumina, hafnium oxide, an oxide (hafnium aluminate) containing aluminum and hafnium, and the like. When the insulator 222 is formed using such a material, the insulator 222 is used as a layer that suppresses the release of oxygen from the oxide 230 or impurities such as hydrogen from entering the oxide 230 from the surrounding portion of the transistor 200.

Alternatively, for example, alumina, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, and zirconia may be added to the insulator. The insulator may be subjected to a nitriding treatment. It is also possible to laminate silicon oxide, silicon oxynitride, or silicon nitride on the insulator.

The insulator 220 is preferably thermally stable. For example, because silicon oxide and silicon oxynitride have thermal stability, by combining with a high-k material insulator, the gate insulator can be made into a laminated structure having thermal stability and a high relative dielectric constant.

The insulator 220, the insulator 222, and the insulator 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure formed using the same material, and a laminated structure formed using different materials may be used.

The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230c on the oxide 230b. When the oxide 230a is provided under the oxide 230b, it is possible to prevent impurities from diffusing from the structure formed under the oxide 230a to the oxide 230b. When the oxide 230c is provided on the oxide 230b, impurities can be prevented from diffusing from the structure formed above the oxide 230c to the oxide 230b.

In addition, the oxide 230 preferably has a stacked structure of oxides having atomic ratios of metal atoms different from each other. Specifically, the atomic number of the element M in the constituent elements of the metal oxide used for the oxide 230a is preferably larger than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 230b. The number of atoms of M in the metal oxide used for the oxide 230a with respect to the In element is preferably larger than the ratio of the number of atoms in the metal oxide used for the oxide 230b with respect to M of the In element. In addition, the number of atoms of In with respect to the element M in the metal oxide used for the oxide 230b is preferably larger than the ratio of the number of atoms of In with respect to the element M in the metal oxide used for the oxide 230a. In addition, as the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

Preferably, the energy at the bottom of the conduction band of the oxides 230a and 230c is higher than the energy at the bottom of the conduction band of the oxides 230b. In other words, the electron affinities of the oxides 230a and 230c are preferably smaller than the electron affinities of the oxides 230b.

Here, in the joint portion of the oxide 230a, the oxide 230b, and the oxide 230c, the conduction band bottom changes gently. In other words, the above-mentioned case may be expressed as that the conduction band bottoms of the junctions of the oxides 230a, 230b, and 230c are continuously changed or continuously joined. For this reason, it is preferable to reduce the density of defects in the mixed layer formed on the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c.

Specifically, the oxide 230a and the oxide 230b and the oxide 230b and the oxide 230c contain a common element (as a main component) other than oxygen to form a mixed layer having a low density of defects. For example, when the oxide 230b is an In-Ga-Zn oxide, it is preferable to use an In-Ga-Zn oxide, a Ga-Zn oxide, gallium oxide, or the like as the oxides 230a and 230c.

At this time, the main path of the carrier is the oxide 230b. By providing the oxides 230a and 230c with the above-mentioned structures, the density of defects in the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of the interface scattering on the carrier conduction is reduced, and the on-state current of the transistor 200 can be increased.

The oxide 230 includes a region 231, a region 232, and a region 234. Preferably, at least a part of the region 231 includes a region in contact with the insulator 273. The region 232 includes at least a region overlapping the insulator 272.

When the transistor 200 is turned on, the region 231a or the region 231b is used as a source region or a drain region. On the other hand, at least a part of the region 234 is used as a channel formation region. When the region 232 is provided between the region 231 and the region 234, the on-state current of the transistor 200 can be increased and the leakage current (off-state current) when the transistor 200 is non-conductive can be reduced.

By providing the region 232 in the transistor 200, a high-resistance region can be prevented from being formed between the region 231 used as the source region and the drain region and the region 234 forming the channel, and the on-state current of the transistor can be increased and improved Carrier mobility of the transistor. When the region 232 is included, the source region and the drain region do not overlap with the first gate electrode (conductor 260) in the channel length direction, so that it is possible to suppress the formation of an unnecessary capacitance between the two. In addition, when the region 232 is included, the leakage current at the time of non-conduction can be reduced.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having the required electrical characteristics according to the circuit design.

As the oxide 230, a metal oxide (hereinafter also referred to as an oxide semiconductor) used as an oxide semiconductor is preferably used. For example, it is preferable to use a metal oxide having a band gap of 2 eV or more, and more preferably 2.5 eV or more as the metal oxide that becomes the region 234. In this way, by using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

Since a transistor using an oxide semiconductor has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. In addition, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor constituting a highly integrated semiconductor device.

The insulator 250 is used as a gate insulator. The insulator 250 is preferably arranged in contact with the top surface of the oxide 230c. The insulator 250 is preferably formed using an insulator that releases oxygen by heating. For example, in a thermal desorption spectrum analysis (TDS analysis), the amount of oxygen released by the insulator, which is converted into oxygen molecules, is 1.0 × 10 ¹⁸ molecules / cm ³ or more, and preferably 1.0 × 10 ¹⁹ molecules / cm ³ or more. It is more preferably 2.0 × 10 ¹⁹ molecules / cm ³ or more, or 3.0 × 10 ²⁰ molecules / cm ³ or more. The surface temperature of the film when the TDS analysis is performed is preferably in a range of 100 ° C to 700 ° C.

Specifically, silicon oxide containing excessive oxygen, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, Hollow silicon oxide. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability.

By providing the insulator 250 that is in contact with the top surface of the oxide 230c with an insulator that releases oxygen by heating, it is possible to efficiently supply oxygen from the insulator 250 to the region 234 of the oxide 230b. As with the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

In addition, in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230, a metal oxide 252 may be provided. Therefore, the metal oxide 252 preferably suppresses oxygen diffusion from the insulator 250. By providing the metal oxide 252 that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a reduction in excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excessive oxygen can be suppressed.

In addition, the metal oxide 252 is sometimes used as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide 252 is preferably a metal oxide that is a high-k material having a high relative dielectric constant. By using this laminated structure, a laminated structure having thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied during the transistor operation can be reduced while maintaining the physical thickness. In addition, the equivalent oxide thickness (EOT) of an insulator used as a gate insulator can be reduced.

In addition, the metal oxide 252 may be used as a part of the first gate. For example, an oxide semiconductor that can be used as the oxide 230 can be used for the metal oxide 252. In this case, by forming the conductive body 260 by a sputtering method, the resistivity of the metal oxide 252 can be reduced to make it a conductive body. This conductor is called an OC (Oxide Conductor) electrode.

By providing the metal oxide 252, the on-state current of the transistor 200 can be increased without reducing the influence of the electric field from the conductor 260. In addition, by keeping the distance between the conductive body 260 and the oxide 230 by the physical thickness of the insulator 250 and the metal oxide 252, a leakage current between the conductive body 260 and the oxide 230 can be suppressed. In addition, by providing a laminated structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the oxide 230 and the strength of the electric field applied from the conductor 260 to the oxide 230 can be easily adjusted.

Specifically, as the metal oxide 252, one or two or more metal oxides selected from the group consisting of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In addition, by reducing the resistance of the oxide semiconductor that can be used for the oxide 230, it can be used as the metal oxide 252.

In particular, alumina, hafnium oxide, and an oxide (hafnium aluminate) containing aluminum and hafnium are preferably used as an insulator including an oxide of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is not easy to crystallize in the thermal history of the subsequent processes, so it is preferable.

The conductor 260 used as the first gate electrode includes a conductor 260a and a conductor 260b on the conductor 260a. Similarly, the conductive member 260a is preferably used in the first conductor 205 having conductive suppressing hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a molecule of nitric oxide _{(N 2 O, NO, NO} 2 , etc.), A conductive material that functions as a diffusion of impurities such as copper atoms. In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule).

When the conductive body 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the excess of oxygen contained in the insulator 250 and the metal oxide 252 from oxidizing the conductive body 260b and causing a decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

In addition, since the conductor 260 is used as a wiring, it is preferable to use a highly conductive conductor. For example, as the conductor 260b, a conductive material containing tungsten, copper, or aluminum as a main component can be used. In addition, the conductor 260b may have a laminated structure, and may include, for example, a laminate of titanium, titanium nitride, and the above-mentioned conductive material.

When the conductor 205 extends to a region outside the end portion of the oxide 230 that intersects the channel width as shown in FIG. 1C, the conductor 260 preferably overlaps the conductor 205 with the insulator 250 interposed therebetween. That is, on the outside of the side surface of the oxide 230, it is preferable that a laminated structure is formed by the conductor 205, the insulator 250, and the conductor 260.

When the above structure is provided, when the electric potential is supplied to the conductor 260 and the conductor 205, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to cover the channel formation region formed in the oxide 230. .

That is, the channel forming region of the region 234 may be electrically surrounded by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode.

In addition, an insulator 270 used as a barrier film may be provided on the conductor 260b. As the insulator 270, an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, alumina or hafnium oxide is preferably used. This prevents the conductor 260 from being oxidized by oxygen from above the insulator 270. In addition, impurities such as water or hydrogen from above the insulator 270 can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250.

An insulator 271 used as a hard mask is preferably disposed on the insulator 270. By providing the insulator 271, the conductor 260 can be processed such that its side surface is substantially perpendicular to the substrate surface. Specifically, the angle formed by the side surface of the conductor 260 and the substrate surface can be 75 degrees or more and 100 degrees or less. It is preferably 80 degrees or more and 95 degrees or less. By processing the electrical conductor 260 into the shape described above, the insulator 272 to be formed later can be formed into a desired shape.

In addition, the insulator 271 can also function as a barrier film by using an insulating material having a function of suppressing the transmission of impurities such as water or hydrogen and oxygen as the insulator 271. In this case, the insulator 270 may not be provided.

The insulator 272 used as the barrier film and the buffer layer is provided in contact with the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270.

The insulator 272 used as the buffer layer is provided in contact with the side surface of the oxide 230c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270. As the insulator 272, an insulating material having a function of suppressing the permeation of impurities such as water or hydrogen and oxygen can also be used. In this case, the insulator 272 is also used as a barrier layer.

For example, the insulator 272 is preferably formed by an ALD method. A dense film can be formed by using the ALD method. As the insulator 272, for example, alumina or hafnium oxide is preferably used. When alumina is formed as the insulator 272 by the ALD method, the thickness of the insulator 272 is preferably 0.5 nm or more and 3.0 nm or less.

By providing the insulator 272, the sides of the insulator 250, the metal oxide 252, and the conductor 260 can be covered with an insulator having a function of suppressing the transmission of impurities such as water or hydrogen and oxygen. Therefore, it is possible to prevent impurities such as hydrogen or water from being mixed into the oxide 230 from the ends of the insulator 250 and the metal oxide 252. Therefore, the formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 can be suppressed, and the reliability of the transistor 200 can be improved. In other words, the insulator 272 can be used as a side barrier that protects the gate electrode and the sides of the gate insulator.

By adopting this structure, it is possible to supply an excessive amount of oxygen contained in the insulator 275 to the insulator 250 while suppressing the oxidation of the conductor 260.

An insulator 275 is provided on the side of the metal oxide 252, the insulator 250, and the conductor 260 via an insulator 272. The insulator 275 preferably contains a region of excess oxygen. Here, when the insulator 224 is processed into an island shape, the insulator 224 and the insulator 275 may be in contact with each other outside the insulator 224. By adopting this structure, the excess oxygen of the insulator 275 can be supplied to the oxide 230 through the insulator 224.

The insulator 273 is provided on at least the region 231 of the oxide 230 and the insulator 275. By forming the insulator 273 by a sputtering method, an excessive oxygen region can be formed in the insulator 275. It is thereby possible to supply oxygen to the oxide 230 from this excess oxygen region. In addition, by forming the insulator 273 on the region 231 of the oxide 230, the hydrogen in the oxide 230 can be extracted to the insulator 273.

For example, as the insulator 273, one or two or more metal oxides selected from the group consisting of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

In particular, alumina has high barrier properties, and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm.

An insulator 280 used as an interlayer film is preferably formed on the insulator 273. As with the insulator 224 and the like, the concentration of impurities such as water or hydrogen in the insulator 280 is preferably reduced. In addition, an insulator similar to the insulator 210 may be formed on the insulator 280.

In addition, a conductor 240 a and a conductor 240 b are formed in the openings of the insulator 280 and the insulator 273. The conductor 240 a and the conductor 240 b are provided so as to face each other with the conductor 260 interposed therebetween. In addition, the top surfaces of the conductors 240a and 240b and the top surface of the insulator 280 may be located on the same plane.

Here, the conductor 240 a is in contact with a region 231 a used as one of the source region and the drain region of the transistor 200, and the conductor 240 b is in contact with the other of the source region and the drain region used as the transistor 200. One area 231b is in contact. Therefore, the conductive body 240a may be used as one of the source electrode and the drain electrode, and the conductive body 240b may be used as the other of the source electrode and the drain electrode.

A conductor 240 is formed so as to be in contact with the inner wall of the opening of the insulator 280 and the insulator 273. The region 231a of the oxide 230 is located in at least a part of the bottom of the opening, and the conductor 240a is in contact with the region 231a. Similarly, a conductor 240 b is formed so as to be in contact with the inner wall of the opening of the insulator 280 and the insulator 273. The region 231b of the oxide 230 is located in at least a part of the bottom of the opening, and the conductor 240b is in contact with the region 231b.

Here, as shown in FIG. 1D, the conductive body 240 a and the conductive body 240 b are in contact with at least the top surface of the oxide 230, and preferably they are also in contact with the side surface of the oxide 230. It is particularly preferable that the conductor 240 a and the conductor 240 b contact one or both of the side surfaces (the side surface on the A5 side and the side surface on the A6 side) of the oxide 230 that intersect with the channel width direction. In addition, a structure in which the conductor 240a and the conductor 240b are in contact with the side surface (the A1 side or the A2 side) of the oxide 230 that intersects with the channel length direction may be employed. In this way, by contacting the conductive body 240a and the conductive body 240b with the top surface of the oxide 230 and the side surface of the oxide 230, it is possible to increase the area of the top surface of the contact portion of the conductive body 240a and the conductive body 240b with the oxide 230. In this case, the contact area of the contact portion is increased, and the contact resistance between the conductor 240 a and the conductor 240 b and the oxide 230 is reduced. This makes it possible to increase the on-state current while miniaturizing the source electrode and the drain electrode of the transistor.

The conductive body 240a and the conductive body 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a laminated structure.

Here, as shown in FIG. 2B, for example, when openings are formed in the insulator 280 and the insulator 273, the low-resistance region of the region 231 in the oxide 230 may be removed. In this case, it is preferable to use a metal film or a nitride film or an oxide film containing a metal element as the conductor for the first conductor of the conductor 240. In other words, when the oxide 230 is in contact with the first conductor of the conductor 240, a metal compound or an oxygen vacancy is formed, and the resistance of the region 231 of the oxide 230 is reduced. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductive body of the conductive body 240, the contact resistance of the oxide 230 and the conductive body 240 can be reduced. The first conductive body of the conductive body 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, and tungsten.

When a laminated structure is adopted as the conductive body 240, it is preferable to use a material having a function of suppressing the transmission of impurities such as water or hydrogen as the first conductive body of the conductive body 205 as the conductive body in contact with the insulator 273 and the insulator 280. Conductive material. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. The conductive material having a function of suppressing the permeation of impurities such as water or hydrogen may be a single layer or a laminate. By using this conductive material, impurities such as water or hydrogen can be prevented from entering the oxide 230 through the conductor 240a and the conductor 240b from the layer above the insulator 280.

Although not shown, the conductive body used as the wiring may be arranged so as to be in contact with the top surfaces of the conductive body 240a and the conductive body 240b. The conductive material used for the wiring is preferably a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, and for example, may have a laminated structure of titanium, titanium nitride, and the conductive material. In addition, like the conductor 203 and the like, the conductor may be buried in the opening of the insulator.

<Constituent Materials of Semiconductor Device> Hereinafter, the constituent materials that can be used for a semiconductor device will be described.

<< Substrate >> As the substrate forming the transistor 200, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttrium-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. In addition, a semiconductor substrate having an insulator region inside the semiconductor substrate may be mentioned, such as a SOI (Silicon On Insulator) substrate and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, and the like can be given. Furthermore, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, and the like can also be mentioned. Alternatively, a substrate provided with elements on these substrates may be used. Examples of the element provided on the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

A flexible substrate may be used as the substrate. As a method of providing a transistor on a flexible substrate, a method may also be mentioned. After the transistor is formed on a non-flexible substrate, the transistor is peeled off and the transistor is transferred onto the flexible substrate. In this case, it is preferable to provide a release layer between the non-flexible substrate and the transistor. The substrate may be stretchable. In addition, the substrate may have a property of returning to the original shape when the bending or stretching is stopped. Alternatively, it may have a property that it does not return to the original shape. The substrate includes, for example, an area having a thickness of 5 mm to 700 mm, preferably 10 mm to 500 mm, and more preferably 15 mm to 300 mm. By forming the substrate thin, it is possible to reduce the weight of a semiconductor device including a transistor. In addition, by forming the substrate thin, even when glass or the like is used, it may have the property of being stretchable or returning to its original shape when bending or stretching is stopped. Therefore, it is possible to alleviate the impact and the like on the semiconductor device on the substrate due to dropping and the like. That is, a semiconductor device with high durability can be provided.

As the flexible substrate, for example, a metal, an alloy, a resin, a glass, or a fiber thereof can be used. In addition, as the substrate, a sheet, film, foil, or the like containing fibers may be used. The lower the linear expansion coefficient of the flexible substrate, the more the deformation due to the environment is suppressed, which is preferable. As the flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less may be used. Examples of the resin include polyester, polyolefin, polyimide (nylon, aromatic polyamine, etc.), polyimide, polycarbonate, acrylic, and the like. In particular, aromatic polyamidamine has a low linear expansion coefficient, and is therefore suitable for flexible substrates.

<< Insulator >> As the insulator, there are insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.

For example, when miniaturization and high integration of transistors are performed, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical thickness. On the other hand, by using a material having a relatively low dielectric constant for an insulator used as an interlayer film, it is possible to reduce parasitic capacitance generated between wirings. Therefore, it is preferable to select a material according to the function of the insulator.

Examples of insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconia, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and Samarium oxynitride or nitrides containing silicon and samarium.

Examples of insulators having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, and oxidation with carbon and nitrogen added. Silicon, silicon oxide with voids, or resin.

In addition, in particular, silicon oxide and silicon oxynitride have thermal stability. Therefore, for example, by combining with a resin, a laminated structure having thermal stability and a low relative dielectric constant can be realized. Examples of the resin include polyester, polyolefin, polyimide (nylon, aromatic polyamine, etc.), polyimide, polycarbonate, or acrylic. For example, by combining silicon oxide and silicon oxynitride with an insulator having a high relative permittivity, a laminated structure having thermal stability and a high relative permittivity can be realized.

By surrounding the transistor using an oxide semiconductor with an insulator having a function of suppressing the transmission of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized.

As the insulator having a function of suppressing the transmission of impurities such as hydrogen and oxygen, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum can be used. Single layer or stack of insulators of neodymium, neodymium, praseodymium or tantalum. Specifically, as the insulator having a function of suppressing the transmission of impurities such as hydrogen and oxygen, alumina, magnesia, gallium oxide, germanium oxide, yttrium oxide, zirconia, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide can be used. And other metal oxides, silicon oxynitride or silicon nitride.

For example, as the insulator 273, one or two or more metal oxides selected from the group consisting of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

In particular, alumina has high barrier properties, and can suppress the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. In addition, hafnium oxide has lower barrier properties than alumina, but by increasing its thickness, barrier properties can be improved. Therefore, by adjusting the thickness of hafnium oxide, the amount of hydrogen and nitrogen added can be adjusted appropriately.

For example, the insulator 224 and the insulator 250 used as a part of the gate insulator are preferably insulators including an excessive oxygen region. For example, by contacting silicon oxide or silicon oxynitride containing an excessive oxygen region with the oxide 230, the oxygen vacancies contained in the oxide 230 can be filled.

In addition, for example, as the insulator 222 and the metal oxide 252 used as a part of the gate insulator, an insulator containing one or more oxides of aluminum, hafnium, and gallium can be used. In particular, as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use alumina, hafnium oxide, an oxide (hafnium aluminate) containing aluminum and hafnium, and the like.

For example, as the insulator 220, it is preferable to use silicon oxide or silicon oxynitride having thermal stability. By making the gate insulator a laminated structure of a film having thermal stability and a film having a high relative dielectric constant, the equivalent oxide thickness (EOT) of the gate insulator can be reduced while maintaining the physical thickness.

By using the above-mentioned stacked structure, the on-state current can be increased without reducing the influence of the electric field from the gate electrode. In addition, by using the physical thickness of the gate insulator to maintain the distance between the gate electrode and the region where the channel is formed, it is possible to suppress the leakage current between the gate electrode and the channel formation region.

The insulator 212, the insulator 216, the insulator 271, the insulator 275, and the insulator 280 preferably include an insulator having a low relative dielectric constant. For example, the insulator 212, insulator 216, insulator 271, insulator 275, and insulator 280 preferably include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, Carbon oxide and nitrogen-added silicon oxide, silicon oxide with voids, or resin. Alternatively, the insulator 212, the insulator 216, the insulator 271, the insulator 275, and the insulator 280 preferably have silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, Carbon and nitrogen-added silicon oxide or a layered structure of silicon oxide with voids and resin. Since silicon oxide and silicon oxynitride have thermal stability, by combining them with a resin, a laminated structure having thermal stability and a low relative dielectric constant can be realized. Examples of the resin include polyester, polyolefin, polyimide (nylon, aromatic polyamine, etc.), polyimide, polycarbonate, or acrylic.

As the insulator 210, the insulator 214, the insulator 270, and the insulator 273, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used. As the insulator 210, the insulator 214, the insulator 270, and the insulator 273, for example, metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconia, lanthanum oxide, neodymium oxide, or tantalum oxide, Silicon oxynitride or silicon nitride.

<< Conductor> As the conductor, it is preferable to use 包含 as a conductor. One or more materials of metal elements such as beryllium, indium, and ruthenium. In addition, a semiconductor having a high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus and a silicide such as nickel silicide may also be used.

In addition, a plurality of conductive layers formed of the above materials may be laminated. For example, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined may be employed. In addition, a laminated structure in which a material containing the above-mentioned metal element and a conductive material containing nitrogen are combined may be employed. In addition, a laminated structure in which a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used in combination.

In addition, in the case where an oxide is used for a channel formation region of a transistor, it is preferable that a laminated structure having a combination of a material containing the above-mentioned metal element and a conductive material containing oxygen is used as a conductor used as a gate electrode. In this case, it is preferable to arrange a conductive material containing oxygen on the side of the channel formation region. By disposing a conductive material containing oxygen on one side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, as a conductor to be used as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in a metal oxide forming a channel. Alternatively, a conductive material containing the metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, Indium tin oxide of silicon. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using the above-mentioned materials, it is sometimes possible to trap hydrogen contained in the metal oxide forming the channel. Alternatively, hydrogen that has entered from an external insulator or the like may be trapped.

As the conductor 260, the conductor 203, the conductor 205, and the conductor 240, it is preferable to use a material selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, rhenium, vanadium, and niobium. Materials of one or more of the metallic elements such as, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. In addition, a semiconductor having a high conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus and a silicide such as nickel silicide may also be used.

<Metal oxide> As the oxide 230, a metal oxide (hereinafter, also referred to as an oxide semiconductor) used as an oxide semiconductor is preferably used. Hereinafter, a metal oxide that can be used for the oxide 230 of the present invention will be described.

The metal oxide preferably contains at least indium or zinc. It is particularly preferable to include indium and zinc. In addition, it is preferable to further include aluminum, gallium, yttrium, or tin. Alternatively, one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, praseodymium, tantalum, tungsten, or magnesium may be contained.

Here, a case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc is considered. Note that the element M is aluminum, gallium, yttrium, tin, or the like. As other elements that can be used as the element M, there are boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, praseodymium, tantalum, tungsten, magnesium, and the like. Note that as the element M, a plurality of the above-mentioned elements may be combined in some cases.

In this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[Configuration of Metal Oxide] Hereinafter, a configuration of a CAC (Cloud-Aligned Composite) -OS that can be used for a transistor disclosed in one embodiment of the present invention will be described.

In this specification and the like, it may be described as CAAC (c-axis aligned crystal) or CAC (Cloud-Aligned Composite). Note that CAAC is an example of a crystalline structure, and CAC is an example of a function or a material composition.

CAC-OS or CAC-metal oxide has the function of conductivity in one part of the material, and the function of insulation in the other part of the material, and has the function of a semiconductor as a whole. In addition, when CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the function of conductivity is a function of passing electrons (or holes) used as carriers, and a function of insulation. It is a function to prevent electrons used as carriers from flowing. The complementary function of the conductive function and the insulating function enables the CAC-OS or CAC-metal oxide to have a switching function (a function to control on / off). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

In addition, CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the aforementioned function of conductivity, and the insulating region has the aforementioned function of insulation. Further, in the material, the conductive region and the insulating region are sometimes separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material. In addition, conductive regions whose edges are blurred and connected in a cloud shape are sometimes observed.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less.

In addition, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In this configuration, when a carrier is caused to flow, the carrier mainly flows in a component having a narrow gap. In addition, a component having a narrow gap causes carriers to flow through the component having a wide gap by interacting with the component having a wide gap by a complementary action with the component having a wide gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, a high current driving force can be obtained in the conducting state of the transistor, that is, a large on-state current and a high field-effect mobility.

That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite or a metal matrix composite.

[Structure of Metal Oxide] A hafnium oxide semiconductor (metal oxide) is divided into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. Examples of non-single-crystal oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and non- Crystalline oxide semiconductors, etc.

CAAC-OS has c-axis alignment, and a plurality of nanocrystals are connected in the a-b plane direction, and the crystal structure has distortion. Note that the distortion refers to a portion in which the direction of the lattice arrangement is changed between a region where the lattice arrangement is the same as that of other regions where the lattice arrangement is the same among the regions where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and may not be regular hexagons. In addition, the distortion sometimes has a lattice arrangement such as a pentagon or a heptagon. In CAAC-OS, no clear grain boundary was observed even near the distortion. That is, it was found that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the low density of the oxygen atom arrangement in the a-b plane direction or the change in the bonding distance between atoms due to the substitution of metal elements.

CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure). In this layered crystal structure, a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element containing M, zinc, and oxygen are laminated. Layer (hereinafter referred to as (M, Zn) layer). In addition, indium and element M may be substituted for each other. When the element M in the (M, Zn) layer is replaced with indium, this layer may be expressed as an (In, M, Zn) layer. In addition, when the indium in the In layer is replaced with the element M, the layer may be expressed as an (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, it is not easy to observe a clear grain boundary, and therefore it is not easy to cause a decrease in electron mobility due to the grain boundary. In addition, the crystallinity of a metal oxide may be reduced due to entry of impurities or generation of defects. Therefore, it can be said that CAAC-OS is a metal oxide with few impurities or defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

In nc-OS, the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less) has periodicity. In addition, nc-OS does not observe regularity of crystal orientation between different nanocrystals. Therefore, no alignment was observed in the entire film. Therefore, sometimes nc-OS is not different from a-like OS or amorphous oxide semiconductor in some analytical methods.

a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS contains holes or low-density areas. That is, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

An oxide semiconductor (metal oxide) has various structures and various characteristics. The oxide semiconductor that can be used in one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[Transistor with Metal Oxide] Next, a case where the above-mentioned metal oxide is used in a channel formation region of a transistor will be described.

By using the above metal oxide for the channel formation region of the transistor, a transistor having a high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

In addition, a metal oxide having a low carrier density is preferably used for the transistor. When the carrier density of the metal oxide film is to be reduced, the impurity concentration in the metal oxide film can be reduced to reduce the density of defect states. In this specification and the like, a state in which the impurity concentration is low and the density of defect states is low is referred to as a "high-purity essence" or a "substantially high-purity essence". For example, the carrier density in the metal oxide may be less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and is 1 × 10 ^-9 / cm ³ or more.

In addition, a metal oxide film having a high-purity nature or a substantially high-purity nature has a lower density of defect states, and thus sometimes has a lower density of trap states.

In addition, it takes a long time for the charges captured by the trap level of the metal oxide to disappear, and it sometimes behaves like a fixed charge. Therefore, the electrical characteristics of a transistor having a channel formation region in a metal oxide having a high trap state density are sometimes unstable.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the concentration of impurities in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[Impurities] Here, the influence of each impurity in the metal oxide will be described.

When the metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect energy level is formed in the metal oxide. Therefore, the concentration of silicon or carbon in the metal oxide or near the interface of the metal oxide (concentration measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry)) is set to 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed to form a carrier. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as the channel formation region easily has a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide measured by SIMS is 1 × 10 ¹⁸ atoms / cm ³ or less, and preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

When the metal oxide contains nitrogen, electrons as carriers are easily generated, the carrier density is increased, and the n-type is formed. As a result, a transistor in which a metal oxide containing nitrogen is used in the channel formation region tends to have a normally-on characteristic. Therefore, in this metal oxide, it is preferable to reduce nitrogen in the channel formation region as much as possible. For example, the nitrogen concentration in the metal oxide measured by SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, and more preferably 1 × 10 ¹⁸ atoms / cm ³ or less It is more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to generate water, and thus oxygen vacancies may be formed. When hydrogen enters this oxygen vacancy, an electron as a carrier is sometimes generated. In addition, a part of hydrogen may be bonded to oxygen bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using a metal oxide containing hydrogen as a channel formation region easily has a normally-on characteristic. Therefore, it is preferable to reduce hydrogen in the metal oxide as much as possible. Specifically, in metal oxides, the hydrogen concentration measured by SIMS is set to less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , and more preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

By using a metal oxide whose impurities are sufficiently reduced for the channel formation region of the transistor, the transistor can have stable electrical characteristics.

<Method for Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device including the transistor 200 of the present invention will be described with reference to FIGS. 3A to 14D. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 14A are plan views. 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B, 13B, and 14B are taken along FIG. 3A, FIG. 4A, FIG. 5A, and FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, FIG. 12A, FIG. 13A, and FIG. 14A are cross-sectional views of a part of the dashed line A1-A2, which is equivalent to the channel length of the transistor 200 Sectional view in the direction. 3C, 4C, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13C, and 14C are taken along FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, FIG. 12A, FIG. 13A, and FIG. 14A are cross-sectional views of a portion of a dashed line A3-A4, which is equivalent to the channel width direction of the transistor 200. Section view. 3D, 4D, 5D, 6D, 7D, 8D, 9D, 10D, 11D, 12D, 13D, and 14D are taken along FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11A, FIG. 12A, FIG. 13A, and FIG. 14A are cross-sectional views of a part of a dashed line A5-A6, which is equivalent to the source region of the transistor 200 or A cross-sectional view of the drain region. For clarity, some components are omitted in the top views of FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 14A.

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The insulator 210 can be formed by a sputtering method, a chemical vapor deposition (CVD: Chemical Vapor Deposition) method, a molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, a pulsed laser deposition (PLD: Pulsed Laser Deposition) method, or an atomic layer deposition. (ALD: Atomic Layer Deposition).

Note that the CVD method can be divided into a plasma enhanced CVD (PECVD: Plasma Enhanced CVD) method using a plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. Furthermore, the CVD method can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to a source gas used.

By using the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. In addition, since plasma is not used, the thermal CVD method is a film-forming method capable of reducing plasma damage to an object to be processed. For example, a wiring, an electrode, an element (a transistor, a capacitor, and the like) included in a semiconductor device may generate charge up due to receiving a charge from a plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be damaged due to the accumulated electric charges. On the other hand, since the above-mentioned plasma damage does not occur in the thermal CVD method without using a plasma, the yield of a semiconductor device can be improved. In addition, in the thermal CVD method, since plasma damage during film formation does not occur, a film with fewer defects can be obtained.

In addition, the ALD method is also a film-forming method capable of reducing plasma damage to an object to be processed. In addition, since no plasma damage occurs during film formation by the ALD method, a film with fewer defects can be obtained. The precursor used in the ALD method may contain impurities such as carbon. Therefore, a film formed by the ALD method may contain more impurities such as carbon than a film formed by another film formation method. The quantification of impurities can be performed by X-ray Photoelectron Spectroscopy (XPS).

Unlike a film formation method in which particles released from a target or the like are deposited, the CVD method and the ALD method are methods of forming a film due to a reaction on the surface of the object to be processed. Therefore, the film formed by the CVD method and the ALD method is not easily affected by the shape of the object to be processed, and has good step coverage. In particular, the film formed by the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for a case where the surface to be opened with a high aspect ratio is to be covered. However, since the deposition rate of the ALD method is relatively slow, it is sometimes preferable to use it in combination with another film-forming method such as a CVD method that has a high deposition rate.

The CVD method and the ALD method can control the composition of the obtained film by adjusting the flow rate ratio of the source gas. For example, when a CVD method or an ALD method is used, a film having an arbitrary composition can be formed by adjusting the flow rate ratio of the source gas. In addition, for example, when a CVD method and an ALD method are used, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming a film. When the film is formed while changing the flow rate ratio of the source gas, the time required for transferring and adjusting the pressure is not required, so that the film forming time can be shortened compared to the case where a plurality of film forming chambers are used for film formation. Therefore, the productivity of a semiconductor device may be improved in some cases.

In this embodiment, as the insulator 210, alumina is formed by a sputtering method. The insulator 210 may have a multilayer structure. For example, a structure in which alumina is formed by a sputtering method, and then another alumina is formed on the alumina by an ALD method may be adopted. Alternatively, a structure in which alumina is formed by an ALD method, and then another alumina is formed on the alumina by a sputtering method may also be adopted.

Next, an insulator 212 is formed on the insulator 210. The insulator 212 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulator 212, silicon oxide is formed by a CVD method.

Next, an opening reaching the insulator 210 is formed in the insulator 212. The opening includes, for example, a groove or a slit. The area where the opening is formed is sometimes called an opening. When the opening is formed, a wet etching method can be used, but a dry etching method is preferable for micromachining. As the insulator 210, an insulator used as an etching barrier film when the insulator 212 is etched to form an opening is preferably selected. For example, when a silicon oxide film is used as the opening-forming insulator 212, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film can be used as the insulator 210. By using a film having an etching rate different from that of the silicon oxide film, the insulator 210 can be used as an etching barrier film.

After the opening is formed, a conductive film that is a first conductor to be the conductor 203 is formed. The conductive film preferably contains a conductor having a function of suppressing transmission of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film to be the first conductive body of the conductive body 203 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as the conductive film to be the first conductor of the conductor 203, a tantalum nitride film is formed by a sputtering method or a film in which titanium nitride is laminated on tantalum nitride. By using such a metal nitride as the first conductor of the conductor 203, even if a metal that easily diffuses, such as copper, is used as the second conductor of the conductor 203 described later, the metal can be suppressed from the first conductor of the conductor 203. A conductive body diffuses to the outside.

Next, a conductive film to be a second conductor of the conductor 203 is formed on a conductive film of the first conductor to be the conductor 203. This conductive film can be formed using a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film of the second conductor to be the conductor 203.

Next, by performing a CMP process, a part of the conductive film of the first conductive body to be the conductive body 203 and a portion of the conductive film of the second conductive body to be the conductive body 203 are removed to expose the insulator 212. As a result, only the conductive film of the first conductive body to be the conductive body 203 and the conductive film of the second conductive body to be the conductive body 203 remain in the openings. Thereby, it is possible to form the conductive body 203 including the first conductive body 203 and the second conductive body of the conductive body 203 whose top surfaces are flat (see FIGS. 3A to 3D). Note that a part of the insulator 212 may be removed due to the CMP process.

Next, an insulator 214 is formed on the insulator 212 and the conductor 203. The insulator 214 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulator 214, silicon nitride is formed by a CVD method. As described above, by using an insulator such as silicon nitride that does not easily penetrate copper as the insulator 214, even if a metal that easily diffuses, such as copper, is used as the second conductor of the conductor 203, the diffusion of the metal to the layer above the insulator 214 can be suppressed. .

Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide is formed as the insulator 216 by a CVD method.

Next, openings reaching the conductor 203 are formed in the insulator 214 and the insulator 216. In forming the opening, a wet etching method may be used, but a dry etching method is preferable for micromachining.

After the opening is formed, a conductive film that is to be the first conductor of the conductor 205 is formed. The conductive film to be the first conductive body of the conductive body 205 preferably contains a conductive material having a function of suppressing the transmission of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film to be the first conductive body of the conductive body 205 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

In this embodiment, tantalum nitride is formed by a sputtering method as a conductive film of the first conductive body to be the conductive body 205.

Next, a conductive film to be a second conductor of the conductor 205 is formed on a conductive film of a first conductor to be the conductor 205. This conductive film can be formed using a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

In this embodiment, as a conductive film to be a second conductor of the conductor 205, titanium nitride is formed by a CVD method, and tungsten is formed on the titanium nitride by a CVD method.

Next, by performing a CMP process, a part of the conductive film of the first conductor to be the conductor 205 and a part of the conductive film of the second conductor to be the conductor 205 are removed, and the insulator 216 is exposed. As a result, only the conductive film that becomes the first conductor of the conductor 205 and the second conductor of the conductor 205 remains in the opening. As a result, a conductive body 205 including a first conductive body of the conductive body 205 and a second conductive body of the conductive body 205 with a flat top surface can be formed (see FIGS. 3A to 3D). Note that a part of the insulator 216 may be removed due to the CMP process.

Next, an insulator 220 is formed on the insulator 216 and the conductor 205. The insulator 220 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulator 220, silicon oxide is formed by a CVD method.

Next, an insulator 222 is formed on the insulator 220. The insulator 222 is preferably an insulator formed of an oxide of one or both of aluminum and hafnium. In addition, as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use alumina, hafnium oxide, an oxide (hafnium aluminate) containing aluminum and hafnium, and the like. An insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 is resistant to hydrogen and water, the hydrogen and water contained in the structure around the transistor 200 can be suppressed from being diffused to the inside of the transistor 200 by the insulator 222, so that the oxygen vacancy in the oxide 230 can be suppressed Build.

The insulator 222 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

Next, an insulating film 224A is formed on the insulator 222. The insulating film 224A can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like (see FIGS. 3A to 3D). In this embodiment, as the insulating film 224A, silicon oxide is formed by a CVD method.

Next, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250 ° C or higher and 650 ° C or lower, preferably 300 ° C or higher and 500 ° C or lower, and more preferably 320 ° C or higher and 450 ° C or lower. The heat treatment is performed in an atmosphere of nitrogen or an inert gas or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen or an inert gas, and then heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to replace the desorbed oxygen.

In this embodiment, as the heat treatment, after the insulating film 224A is formed, a treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere. By performing this heat treatment, impurities such as hydrogen and water contained in the insulating film 224A can be removed.

The heat treatment may be performed after the insulator 220 is formed and after the insulator 222 is formed. As the conditions for the heat treatment, the conditions for the heat treatment described above may be adopted, but the heat treatment after the insulator 220 is formed is preferably performed in an atmosphere containing nitrogen.

Here, in order to form an excessive oxygen region in the insulating film 224A, a plasma treatment including oxygen may be performed under a reduced pressure. An oxygen-containing plasma treatment is preferably a device including a power source for generating a high-density plasma using microwaves, for example. Alternatively, it may include a power source that applies RF (Radio Frequency) to one side of the substrate. By using a high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulating film 224A. Alternatively, after performing a plasma treatment including an inert gas using such a device, a plasma treatment including oxygen may be performed in order to fill the desorbed oxygen. In addition, by appropriately selecting the conditions of the plasma treatment, impurities such as hydrogen and water contained in the insulating film 224A can be removed. In this case, heat treatment may not be performed.

Next, an oxide film 230A to be an oxide 230a and an oxide film 230B to be an oxide 230b are sequentially formed on the insulating film 224A (see FIGS. 3A to 3D). The oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the oxide film without being exposed to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230A and the oxide film 230B, so the vicinity of the interface between the oxide film 230A and the oxide film 230B can be kept clean.

The oxide film 230A and the oxide film 230B can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of the oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. When the oxide film is formed by a sputtering method, the In-M-Zn oxide target can be used.

In particular, when forming the oxide film 230A, a part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the ratio of the oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

In addition, when the oxide film 230B is formed by a sputtering method, it is performed in a state where the ratio of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. During film formation, an oxygen-deficient oxide semiconductor is formed. The transistor using an oxygen-deficient oxide semiconductor for the channel formation region can have a high field-effect mobility.

In this embodiment, an oxide film 230A is formed by using a sputtering method using a target material of In: Ga: Zn = 1: 3: 4 [atomic number ratio]. In addition, an oxide film 230B was formed by a sputtering method using a target material of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]. The oxide film can be formed by appropriately selecting film formation conditions and atomic ratios in accordance with the characteristics required for the oxide 230.

Subsequently, heat treatment may be performed. As the conditions for the heat treatment, the above-mentioned heat treatment conditions can be used. By performing the heat treatment, impurities such as water or hydrogen in the oxide film 230A and the oxide film 230B can be removed. In the present embodiment, the treatment is performed at a temperature of 400 ° C. for 1 hour under a nitrogen atmosphere, and then the treatment is performed continuously at a temperature of 400 ° C. for 1 hour under an oxygen atmosphere.

Next, the oxide film 230A and the oxide film 230B are processed into an island shape to form an oxide 230a and an oxide 230b (see FIGS. 4A to 4D).

Here, the oxide 230a and the oxide 230b are formed so that at least a part of the oxide 230a overlaps the conductor 205. The side surfaces of the oxides 230a and 230b are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the oxides 230a and 230b are substantially perpendicular to the top surface of the insulator 222, when a plurality of transistors 200 are provided, it is possible to reduce the area and increase the density. A structure in which the angle formed by the side surfaces of the oxide 230a and the oxide 230b and the top surface of the insulator 222 is an acute angle may be adopted. At this time, the larger the angle formed by the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222, the better.

A curved surface is provided between the side surfaces of the oxides 230a and 230b and the top surface of the oxides 230b. That is, the end portion of the side surface and the end portion of the top surface are preferably curved (hereinafter, also referred to as a circle). For example, at the end of the oxide 230b, the curvature radius of the curved surface is 3 nm or more and 10 nm or less, and more preferably 5 nm or more and 6 nm or less. When the end portion does not have a corner portion, the coverage of the film in the subsequent film-forming process can be improved.

The processing of this oxide film can be performed by a photolithography method. This process can be performed by a dry etching method or a wet etching method. The processing by the dry etching method is suitable for fine processing.

In the photolithography method, a photoresist is first exposed through a mask. Next, a developing solution is used to remove or leave the exposed areas to form a photoresist mask. Next, an etching process is performed through this photoresist mask to process a conductor, a semiconductor, an insulator, or the like into a desired shape. For example, KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light or the like may be used to form a photoresist mask by exposing the photoresist. Alternatively, a liquid immersion technique may be used in which exposure is performed while a liquid (for example, water) is filled between the substrate and the projection lens. Alternatively, an electron beam or an ion beam may be used instead of the light. Note that when an electron beam or an ion beam is used, writing is performed directly on the photoresist, so the above-mentioned photoresist exposure mask is not required. In addition, as a method for removing the photoresist mask, a dry etching process such as an ashing process or a wet etching process may be performed, a wet etching process may be performed after the dry etching process, or a dry etching process may be performed after the wet etching process. .

Instead of a photoresist mask, a hard mask composed of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that becomes a hard mask material can be formed on the oxide film 230B and a photoresist mask can be formed thereon, and then the hard mask material is etched to form a desired shape. Hard matte. The etching of the oxide film 230A and the oxide film 230B may be performed after removing the photoresist mask, or may be performed without removing the photoresist mask. In the latter case, the photoresist mask may disappear during etching. After the oxide film is etched, the hard mask can be removed by etching. On the other hand, if the hard mask material does not affect the subsequent processes or can be used in the later processes, it is not necessary to remove the hard mask.

As the dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including a parallel plate-type electrode can be used. The capacitance-coupled plasma etching device including the parallel plate-type electrode may have a structure in which a high-frequency power source is applied to one of the parallel plate-type electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one of the parallel plate-type electrodes may be adopted. Alternatively, a configuration in which a high-frequency power source having the same frequency is applied to each of the parallel plate-shaped electrodes may be adopted. Alternatively, a configuration in which a high-frequency power source having a different frequency is applied to each of the parallel plate-shaped electrodes may be adopted. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, as a dry etching device having a high-density plasma source, an inductively coupled plasma (ICP) etching device or the like can be used.

By performing the above-mentioned processes such as dry etching, impurities due to an etching gas or the like may be attached to or diffused on the surface or inside of the oxide 230a, the oxide 230b, or the like. Examples of impurities include fluorine and chlorine.

In order to remove the impurities and the like, washing is performed. As a washing method, there are wet cleaning using a washing solution or the like, plasma treatment using a plasma, washing using a heat treatment, and the like, and the above-mentioned washing can be appropriately combined.

For wet cleaning, an aqueous solution such as oxalic acid, phosphoric acid, or hydrofluoric acid diluted with carbonated water or pure water can be used for washing treatment. Alternatively, ultrasonic washing may be performed using pure water or carbonated water. In this embodiment, ultrasonic washing is performed using pure water or carbonated water.

Subsequently, heat treatment may be performed. As the conditions for the heat treatment, the above-mentioned heat treatment conditions can be used.

Next, an oxide film 230C is formed on the insulating film 224A, the oxide 230a, and the oxide 230b (see FIGS. 5A to 5D).

The oxide film 230C can be formed using a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. The oxide film 230C can be formed using the same formation method as the oxide film 230A or the oxide film 230B according to the characteristics required for the oxide 230c. In this embodiment, an oxide film 230C is formed by using a sputtering method using a target material of In: Ga: Zn = 1: 3: 4 [atom number ratio].

Next, an insulating film 250A, a metal oxide film 252A, a conductive film 260A, a conductive film 260B, an insulating film 270A, and an insulating film 271A are sequentially formed on the oxide film 230C (see FIGS. 5A to 5D).

First, an insulating film 250A is formed. The insulating film 250A can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, it is preferable to form silicon oxynitride by a CVD method. The film formation temperature of the insulating film 250A is preferably 350 ° C. or higher and lower than 450 ° C., and particularly preferably about 400 ° C. By forming the insulating film 250A at a temperature of 400 ° C., an insulator with few impurities can be formed.

In addition, by using a microwave to excite oxygen to generate a high-density oxygen plasma, and exposing the insulating film 250A to the oxygen plasma, oxygen can be introduced into the insulating film 250A.

In addition, heat treatment may be performed. As the conditions for the heat treatment, the above-mentioned heat treatment conditions can be used. By this heat treatment, the water concentration and the hydrogen concentration of the insulating film 250A can be reduced.

Next, a metal oxide film 252A, a conductive film 260A, and a conductive film 260B are formed. As the metal oxide film 252A, an In-Ga-Zn oxide is formed by a sputtering method. The metal oxide film 252A is preferably formed in an atmosphere containing an oxygen gas by a sputtering method. By forming the metal oxide film 252A in an atmosphere containing an oxygen gas, an excessive oxygen region can be formed in the insulating film 250A. By supplying an excessive amount of oxygen added to the insulating film 250A to the oxide 230, an oxygen vacancy in the oxide 230 can be filled.

Here, when the metal oxide film 252A is formed in an oxygen gas atmosphere using a sputtering device, oxygen can be introduced into the insulating film 250A and the insulating film 224A while forming the metal oxide film 252A. In addition, by using an oxide of one or both of aluminum and hafnium having a barrier property as the metal oxide film 252A, it is possible to effectively block an excessive amount of oxygen introduced into the insulating film 250A.

The conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. For example, as the conductive film 260A, titanium nitride is preferably formed, and as the conductive film 260B, tungsten is preferably formed.

For example, as the conductive film 260A, it is preferable to form a metal nitride by a sputtering method. For example, when an oxide semiconductor typified by In-Ga-Zn oxide is used as the metal oxide film 252A, the carrier density can be increased by supplying nitrogen or hydrogen to the metal oxide film 252A. In other words, it functions as an oxide conductor (OC: Oxide Conductor). Therefore, when a metal nitride is formed as a conductive film 260A by a sputtering method, constituent elements (particularly nitrogen) in the metal nitride diffuse into the metal oxide film 252A, thereby reducing the resistance of the metal oxide film 252A. In addition, the electrical resistance of the metal oxide film 252A decreases due to damage (for example, sputtering damage) during the formation of the conductive film 260A. Therefore, the carrier density of the metal oxide film 252A is increased, and the conductivity of the metal oxide film 252A is improved.

In addition, by stacking a low-resistance metal film as the conductive film 260B, a transistor having a small driving voltage can be provided.

Then, heat treatment may be performed. As the conditions for the heat treatment, the above-mentioned heat treatment conditions can be used. Note that the heat treatment may not be performed in some cases. By performing this heat treatment, excess oxygen is added from the metal oxide film 252A to the insulating film 250A, and an excessive oxygen region can be easily formed in the insulating film 250A.

The insulating film 270A can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A is used as a barrier film, it is preferable to use an insulating material having a function of suppressing the transmission of impurities such as water or hydrogen and oxygen as the insulating film 270A. For example, alumina or hafnium oxide is preferably used. This can suppress the oxidation of the conductor 260. In addition, impurities such as water or hydrogen can be suppressed from entering the oxide 230 through the conductor 260 and the insulator 250. In this embodiment, as the insulating film 270A, alumina is formed by an ALD method.

The insulating film 271A can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. Here, the thickness of the insulating film 271A is preferably larger than the thickness of the insulating film 272A formed in a later process. Therefore, when the insulator 272 is formed in a later process, the insulator 271 can be easily left on the conductor 260. In this embodiment, as the insulating film 271A, silicon oxide is formed by a CVD method.

Next, the insulating film 271A is etched to form an insulator 271. Here, the insulator 271 is used as a hard mask. By providing the insulator 271, the side surface of the insulator 250, the side of the conductor 260a, the side of the conductor 260b, and the side of the insulator 270 can be made substantially perpendicular to the top surface of the substrate.

Next, using the insulator 271 as a mask, the insulating film 250A, the metal oxide film 252A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched to form the insulator 250, the metal oxide 252, and the conductor 260 (the conductor 260a). And conductor 260b) and insulator 270 (see FIGS. 6A to 6D).

In the region where the oxide film 230C and the insulator 250 do not overlap, a part of the oxide film 230C may be removed by the etching. In this case, a thickness of a film in a region of the oxide film 230C that overlaps the insulator 250 may be larger than a thickness of a region in the oxide film 230C that does not overlap the insulator 250.

The insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 271 are formed so that at least a part of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 271 overlap the conductor 205 and the oxide 230.

The sides of the insulator 250, the sides of the metal oxide 252, the sides of the conductor 260, and the sides of the insulator 270 are preferably in the same plane.

The surface shared by the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270 is preferably substantially perpendicular to the top surface of the substrate. That is, in the cross-sectional shape, the angle between the sides of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230 is preferably an acute angle, and the larger the better. In the cross-sectional shape, the angle formed by the side surfaces of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230 may be an acute angle. At this time, the larger the angle formed by the side surfaces of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230, the better.

In addition, after the above processing, the subsequent processes may be performed without removing the hard mask (insulator 271).

Next, an insulating film 272A is formed so as to cover the oxide 230, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 271 (see FIGS. 7A to 7D). The insulating film 272A can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

The insulating film 272A is preferably formed by an ALD method with good coverage. By using the ALD method, an insulating film 272A having a uniform thickness is also formed on the side surfaces of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 on the step portions formed by the conductor 260 and the like. In addition, by using the ALD method, a dense thin film can be formed.

The insulating film 272A preferably contains silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, Silicon oxide or resin. In particular, silicon oxide and silicon oxynitride are preferable because they have thermal stability. In particular, silicon oxide and silicon oxide with pores are more likely to form regions of excess oxygen in subsequent processes, so they are preferred.

In addition, as the insulating film 272A, alumina or the like having barrier properties may be formed. For example, when the conductor 260 is a metal film that is easily oxidized, by providing a barrier insulator, it is possible to suppress the conductor 260 from being oxidized by oxygen from above the insulating film 272A. This can suppress an increase in the resistance value of the conductor 260.

When alumina is formed by the ALD method as the insulating film 272A, the thickness of the insulating film 272A is preferably 0.5 nm or more and 3.0 nm or less. By adopting this structure, it is possible to supply an excessive amount of oxygen contained in the insulator 275 to the insulator 250 while suppressing oxidation of the conductor 260 in a later process.

Next, anisotropic etching is performed on the insulating film 272A to form an insulator 272 on the side surfaces of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270. In addition, the oxide 230c is formed by removing the exposed portion of the oxide film 230C to form the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) (see FIGS. 8A to 8D).

As the anisotropic etching treatment, a dry etching treatment is preferably performed. Thereby, the insulating film formed on the surface substantially parallel to the substrate is removed, and the insulator 272 can be formed in a self-aligned manner.

In addition, in this process, the insulating film 224A may be processed into an island shape (insulator 224). In this case, the insulator 222 can be used as an etching stopper film.

Next, a film 242A is formed on the insulator 222, the insulator 224, and the oxide 230 via the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 272 (see FIGS. 9A to 9D). The thickness of the film 242A is 0.5 nm or more and 5 nm or less, and preferably 1 nm or more and 3 nm or less. As the film 242A, a metal film or a nitride film or an oxide film containing a metal element is used. The film 242A contains, for example, metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium. The film 242A can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

Next, heat treatment is performed (see FIGS. 10A to 10D). The heat treatment may be performed at a temperature of 250 ° C or higher and 650 ° C or lower, preferably 300 ° C or higher and 500 ° C or lower, and more preferably 320 ° C or higher and 450 ° C or lower. The heat treatment is performed under a nitrogen or inert gas atmosphere. The heat treatment may be performed under a reduced pressure. For example, as the heat treatment, after the film 242A is formed, a treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.

By performing the heat treatment in an atmosphere containing nitrogen, the above-mentioned metal element is diffused from the film 242A to the oxide 230, whereby a metal element can be added to the oxide 230. In addition, oxygen in the vicinity of the interface between the oxide 230 and the film 242A may be absorbed into the film 242A. As a result, the vicinity of the interface between the oxide 230 and the film 242A becomes a metal compound, and its resistance is reduced (see FIGS. 10A to 10D). At this time, a part of the oxide 230 may form an alloy with the above-mentioned metal element. When a part of the oxide 230 forms an alloy with a metal element, the metal element added to the oxide 230 becomes a relatively stable state, so that a highly reliable semiconductor device can be provided.

In addition, when the hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancy in the region 231, it becomes a relatively stable state. In addition, the hydrogen in the oxygen vacancies in the region 234 is separated from the oxygen vacancies and diffused into the region 231 through a heat treatment at 250 ° C. or higher, and enters into the oxygen vacancies in the region 231 and becomes a relatively stable state. Therefore, by performing the heat treatment, the resistance of the region 231 is further reduced, and the region 234 is highly purified (reduction of impurities such as water or hydrogen), and its resistance is further increased.

Alternatively, the heat treatment may be performed in an atmosphere of nitrogen or an inert gas, and then may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at a temperature of 250 ° C or higher and 650 ° C or lower, preferably 300 ° C or higher and 500 ° C or lower, and more preferably 320 ° C or higher and 450 ° C or lower.

In addition, when a region having conductivity is left in the film 242A, the region is oxidized by heat treatment in an oxidizing atmosphere to become an insulator, and its resistance increases. Since the film 242A remains in an insulator state, it can be used as an interlayer film.

In addition, in the process of forming the film 242A or the heating process, when oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed into the film 242A, it may occur in the region 231 and the region 232. Oxygen vacancy. When the hydrogen in the oxide 230 enters this oxygen vacancy, the carrier density of the regions 231 and 232 increases. Therefore, the region 231 and the region 232 of the oxide 230 become n-type, and their resistance is reduced.

Next, the film 242A is removed. In addition, it is not necessary to remove the film 242A. For example, when a metal film, an oxide film or a nitride film containing a metal element is oxidized by oxygen absorbed from the oxide 230 and becomes an insulator, and the resistance increases, the film may remain. In this case, the film is sometimes used as an interlayer film. In this process, a dry etching method or a wet etching method can be used. When the film 242A is removed, the hydrogen absorbed from the oxide 230 to the film 242A can be simultaneously removed. Therefore, hydrogen of impurities in the transistor 200 can be reduced.

Next, an insulating film 275A is formed (see FIGS. 11A to 11D). The insulating film 275A preferably includes an insulator having a low relative dielectric constant. For example, it is preferable to include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and oxidation with holes. Silicon or resin. In particular, when silicon oxide, silicon oxynitride, silicon oxynitride, or silicon oxide having pores is used for the insulating film 275A, an excessive oxygen region can be easily formed in the insulator 275 in a later process, so it is preferable of. In addition, silicon oxide and silicon oxynitride are preferable because they have thermal stability.

Next, anisotropic etching is performed on the insulating film 275A to form an insulator 275 on the side surface of the insulator 272 and the side surface of the oxide 230 (see FIGS. 12A to 12D). Next, an insulating film to be the insulator 273 is formed on the insulator 275 and the oxide 230 (see FIGS. 13A to 13D).

The insulating film to be the insulator 273 is preferably formed by a sputtering method. By using the sputtering method, an insulator with few impurities such as water and hydrogen can be formed.

In addition, an insulating film to be the insulator 273 is formed in an oxygen gas atmosphere using a sputtering device, and oxygen can be introduced into the insulator 275 while the film is formed. In particular, when silicon oxide, silicon oxynitride, silicon oxynitride, or silicon oxide having pores is used as the insulator 275, an excessive oxygen region is easily formed in the insulator 275. On the other hand, compared with the above-mentioned silicon oxide, even if an oxide film is formed on the oxide 230 by a sputtering method, it is not easy to form an excessive oxygen region in the oxide 230. Therefore, for example, in the case where an oxide film is formed by a sputtering method as an insulating film to be the insulator 273, an excessive oxygen region can be selectively formed in the insulator 275. In this case, it is not easy to form an excessive oxygen region in the oxide 230, so it is possible to suppress an increase in the resistance of the low-resistance region in the oxide 230.

By forming the excess oxygen region in the insulator 275 in the above steps, oxygen can be efficiently supplied from the excess oxygen region to the region 234 of the oxide 230.

By adopting the above structure, each region of the oxide 230 can be formed in a self-aligned manner. Therefore, a miniaturized or highly integrated semiconductor device can be manufactured with a high yield.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having the required electrical characteristics according to the circuit design.

Then, heat treatment may be performed. As the conditions for the heat treatment, the above-mentioned heat treatment conditions can be used. By performing the heat treatment, the hydrogen trapped in the oxygen vacancies in the region 231 of the oxide 230 is absorbed into the insulator 273, whereby the hydrogen in the oxide 230 can be reduced.

Next, an insulator 280 is formed on the insulator 273 (see FIGS. 13A to 13D). The insulator 280 can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dipping method, a droplet ejection method (inkjet method, etc.), a printing method (screen printing, lithography, etc.), a doctor knife method, a roll coater method, or a curtain can be used. It is formed by a curtain coater method or the like. In this embodiment, silicon oxynitride is used as the insulator 280.

Next, a part of the insulator 280 is removed. The insulator 280 is preferably formed so that the top surface thereof is flat. For example, the top surface of the insulator 280 can be made flat after film formation. Alternatively, for example, after the film is formed, the insulator or the like may be removed from the top surface so that the top surface of the insulator 280 is parallel to a reference surface such as the back surface of the substrate, so that the top surface of the insulator 280 is flat. This process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. In this embodiment, a CMP process is used as the planarization process. However, the top surface of the insulator 280 does not necessarily have to be flat.

Next, an opening reaching the oxide 230 is formed in the insulator 280 and the insulator 273 (see FIGS. 14A to 14D). The opening can be formed by a photolithography method. The opening is formed so that the side surface of the oxide 230 is exposed in the opening that reaches the oxide 230 so that the conductor 240 a and the conductor 240 b are in contact with the side surface of the oxide 230.

Next, a conductive film to be a first conductive body of the conductive body 240 and a second conductive body of the conductive body 240 is formed. The conductive film can be formed by a sputtering method, a CVD method, a MBE method, a PLD method, an ALD method, or the like.

Here, for example, when openings are formed in the insulator 280 and the insulator 273, the low-resistance region of the region 231 in the oxide 230 can be removed. In addition, as the first conductor of the conductor 240, a metal film or a nitride film or an oxide film containing a metal element may be used. Thereby, a region where the oxide 230 is in contact with the first conductor of the conductor 240 is formed, so a metal compound or an oxygen vacancy is formed in this region, and the resistance of the contact region between the oxide 230 and the conductor 240 can be reduced. By reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, it is possible to ensure sufficient ohmic contact of the oxide 230 with the conductor 240. Therefore, the first conductive body of the conductive body 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium.

Next, a part of the conductive film to be the conductor 240a and the conductor 240b is removed by a CMP process, and the insulator 280 is exposed. As a result, the conductive film is left only in the opening, and thus the conductive body 240a and the conductive body 240b having flat top surfaces can be formed (see FIGS. 1A to 1D).

Through the above process, a semiconductor device including the transistor 200 can be manufactured. As shown in FIGS. 3A to 14D, the transistor 200 can be formed by using the manufacturing method of the semiconductor device described in this embodiment mode.

According to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to an embodiment of the present invention, a semiconductor device having a small off-state current can be provided. In addition, according to an embodiment of the present invention, a semiconductor device having a large on-state current can be provided. In addition, according to an embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to an embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to an embodiment of the present invention, a semiconductor device having high productivity can be provided.

The structures, methods, and the like described in this embodiment can be implemented in appropriate combination with the structures, methods, and the like shown in other embodiments.

<Modified Example of Semiconductor Device> Next, an example of a semiconductor device including a transistor 200 according to an embodiment of the present invention will be described with reference to FIGS. 15A to 15D.

FIG. 15A is a plan view of a semiconductor device including a transistor 200. FIG. 15B and 15C are cross-sectional views of the semiconductor device. Here, FIG. 15B is a cross-sectional view of a portion taken along a chain line A1-A2 in FIG. 15A, and the cross-sectional view corresponds to a cross-sectional view in the channel length direction of the transistor 200. FIG. 15C is a cross-sectional view of a portion along a chain line A3-A4 in FIG. 15A, and the cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. FIG. 15D shows an enlarged view of a region 277 surrounded by a dotted line shown in FIG. 15B. For clarity, some components are omitted in the top view of FIG. 15A.

In the semiconductor device shown in FIGS. 15A to 15D, components having the same functions as those of the semiconductor device shown in the <Structural Example of the Semiconductor Device> are assigned the same element symbols.

Hereinafter, each component of the transistor 200 will be described with reference to FIGS. 15A to 15D. In this section, as the constituent material of the transistor 200, a material described in detail in <Structural Example of Semiconductor Device> can be used.

The transistor 200 shown in FIGS. 15A to 15D is different from the semiconductor device shown in <Structural Example of Semiconductor Device> at least in that the insulator 274 is included. In addition, the other difference is that the insulator 272 remains on the side of the insulator 224.

Specifically, as shown in FIG. 15D, the insulator 272 may remain on the side of the insulator 224. For example, when the insulator 272 is processed, the insulator 272 may remain due to the influence of the thickness of the insulator 271 used as a hard mask (see FIGS. 7A to 8D). At this time, at least the insulator 272 on the side of the oxide 230 may be removed. In other words, as shown in FIGS. 9A to 9D, it is preferable that the side surface of the oxide 230 is in contact with the film 242A when the film 242A is formed.

When the insulator 272 remains on the side of the insulator 224, the coverage of the insulator 275 can be improved.

An insulator 274 may be provided on the transistor 200. As the insulator 274, silicon nitride or the like in which hydrogen is reduced can be used.

By covering the transistor 200 with the insulator 274, it is possible to prevent impurities such as hydrogen from entering the transistor 200 from components outside the transistor 200.

The structures, structures, and methods described in this embodiment can be implemented in appropriate combination with the structures, structures, and methods described in other embodiments.

Embodiment 2 First, hydrogen in IGZO which can be used as an oxide semiconductor in the transistor 200 according to an embodiment of the present invention will be described.

<1. Movement of hydrogen atom> Here, the ease of movement of the hydrogen atom in the IGZO crystal was evaluated from the viewpoint of the activation energy barrier on the movement path of the hydrogen atom. In addition, as a movement mode of the hydrogen atom, a beating from one oxygen to another oxygen and a movement on one oxygen are assumed.

FIG. 16 is a schematic diagram showing the division of regions in an InGaZnO ₄ crystal in which a moving path of a hydrogen atom is investigated. Here, the respective paths (in-ab direction) and the spans of the InO ₂ region, the (Ga, Zn) O region, and the region between the InO ₂ plane and the (Ga, Zn) O plane shown in FIG. 16 will be discussed. Path (c-axis direction).

In the evaluation of the activation energy barrier, the first-principles electronic state / molecular dynamics calculation program VASP (Vienna ab initio simulation package) was used, and the NEB (Nudged Elastic Band) method as a method for finding a chemical reaction path was used. The NEB method refers to a method of finding the state with the lowest energy required among the states connecting the two states from the initial state and the final state. The activation energy barrier is the difference between the maximum energy in the path and the energy of the most stable structure on the path.

<<< Region between InO ₂ plane and (Ga, Zn) O plane >> FIGS. 17A to 17D show a hydrogen atom movement path in a region between the InO ₂ plane and (Ga, Zn) O plane and the Active energy barrier on the path. Note that the energy of this structure is taken as the origin of the energy based on the most stable structure on the path. 17A and 17C show a moving path of a hydrogen atom, and these paths are referred to as a path A and a path B, respectively. In addition, in Figs. 17A to 17D, the sequence of movement of hydrogen atoms is shown by numerals. In the path A, a path in which a hydrogen atom moves from 3 to 4 is a linear path. On the other hand, in the path B, the hydrogen atom moves from 3 to 5 via 4.

In addition, FIG. 17B shows the calculation result of the activation energy barrier on the path A (the path where the hydrogen atom moves from 1 to 4), and FIG. 17D shows the activation on the path B (the path where the hydrogen atom moves from 1 to 5 through 4). Calculation of energy barriers.

The activation energy barrier on the path A shown in FIG. 17B is 1.12 eV, and the activation energy barrier on the path B shown in FIG. 17D is 0.23 eV. Since the activation energy barrier on the path B is smaller than the path A, it can be considered that when the hydrogen atom moves from 3 to 4, the path B having a low energy barrier on the path easily passes. In other words, it can be presumed that when the hydrogen atom moves in the region between the InO ₂ plane and the (Ga, Zn) O plane, it is easy to pass through the path B having a low energy barrier on the path.

<<< (Ga, Zn) O region >> Next, FIGS. 18A and 18B show a moving path of a hydrogen atom in the (Ga, Zn) O region and an activation energy barrier on the path. Note that the energy of this structure is taken as the origin of the energy based on the most stable structure on the path. FIG. 18A illustrates a moving path of a hydrogen atom in a (Ga, Zn) O region. In FIG. 18A, the sequence of movement of hydrogen atoms is shown by numbers. FIG. 18B shows the calculation result of the activation energy barrier on the path where the hydrogen atom moves from 1 to 4 in FIG. 18A.

It can be seen from FIG. 18B that the activation energy barrier on the movement path of the hydrogen atom in the (Ga, Zn) O region is 0.16 eV, which is smaller than the activation energy barrier shown in FIG. 17D. From the height of the energy barrier alone, it can be expected that when hydrogen atoms are present in the (Ga, Zn) O region, they will be compared with the case where hydrogen atoms are present in the region between the InO ₂ plane and the (Ga, Zn) O plane. In comparison, the movement of hydrogen atoms easily occurs.

<< InO ₂ Region >> Next, FIG. 19A and FIG. 19B show a moving path of a hydrogen atom in the InO ₂ region and an activation energy barrier on the path. Note that the energy of this structure is taken as the origin of the energy based on the most stable structure on the path. FIG. 19A illustrates a moving path of a hydrogen atom in the InO ₂ region. In FIG. 19A, the sequence of movement of hydrogen atoms is shown by numerals. FIG. 19B shows the calculation result of the activation energy barrier on the path where the hydrogen atom moves from 1 to 4 in FIG. 19A.

19B, the region in InO ₂ activation barrier for hydrogen to move from one to another oxygen oxygen 1.2eV or more. In other words, the activation energy of the moving path of hydrogen as compared to the activation barrier shown in FIG. 17D and FIG. 18B, InO ₂ region much impaired. Therefore, compared with other regions, the movement of hydrogen atoms is less likely to occur in the InO ₂ region.

Next, FIGS. 20A and 20B show a moving path of the hydrogen atom along the c-axis direction and an activation energy barrier on the path. Note that the energy of this structure is taken as the origin of the energy based on the most stable structure on the path. FIG. 20A illustrates a movement path of a hydrogen atom along the c-axis direction. In FIG. 20A, the sequence of movement of hydrogen atoms is numerically shown. FIG. 20B shows the calculation result of the activation energy barrier on the path where the hydrogen atom moves from 1 to 8 in FIG. 20A.

As shown in FIG. 20B, the activation energy barrier on the path where the hydrogen atom moves from 2 to 5 is 0.9 eV. In other words, there is a large activation energy barrier when a hydrogen atom enters the (Ga, Zn) O region or departs from the (Ga, Zn) O region. This is considered to be because the movement path of the hydrogen atom is blocked by the bonding of the metal atom and the oxygen atom. In addition, as shown in FIG. 20B, the activation energy barrier on the path where the hydrogen atom moves from 7 to 8 is approximately 1.5 eV. In other words, there is also a large activation energy barrier in the movement of hydrogen atoms in the InO ₂ region. Therefore, it is not easy for the hydrogen atom to move continuously in the c-axis direction. In addition, one of the reasons for the large activation energy barrier is the large ionic radius of In.

Here, the moving frequency (G) is calculated from the activation energy barrier obtained by calculation and the following formula 1.

[Formula 1]

Here, E _a represents an activation energy barrier, k _B represents a Bozeman constant, T represents an absolute temperature, and n represents a frequency factor.

Finally, Table 1 shows the moving frequency estimated from the maximum value (maximum energy barrier) of the active energy barrier on each path.

It can be seen that at 27 ° C and 450 ° C, the frequency of movement in the direction of the ab plane in the region between the InO ₂ plane and the (Ga, Zn) O plane and the (Ga, Zn) O region is highest. In addition, InO _The frequency of movement in the c-axis direction in the ₂ region is low. This means that hydrogen diffuses preferentially on the ab plane in a completely crystalline system. Note that hydrogen was sufficiently diffused in the IGZO film during the heat treatment at 450 ° C.

<2. Prone oxygen vacancies V _O sites> bonding strength of the metal and oxygen atoms depending on the kind or the valency of the metal is different, and therefore is presumed that oxygen vacancies V _O of IGZO is occurring readily depends The oxygen atom The type, number, or distance of the metal to be bonded to each other. Therefore, the easiness of the occurrence of oxygen vacancies in the InGaZnO ₄ crystal model was calculated.

In the calculation, an InGaZnO ₄ crystal model (112 atoms) was used. Figure 21 shows this model. In the (Ga, Zn) O region, Ga and Zn are arranged in an energy-stable manner. There are four kinds of oxygen sites (1 to 4 shown in Fig. 21) according to the type and number of bonding partners. Table 2 shows each oxygen site.

By extracting an oxygen atom from the oxygen site of the above model, an oxygen vacancy model is formed, and the total energy after the structure optimization is compared. Table 3 shows the calculation conditions.

Compare the full energy of the optimized structure. FIG. 22 shows the relative value of the total energy based on the total energy of the oxygen vacancy model of the oxygen site 4 (0.0 eV). It can be inferred from FIG. 22 that the oxygen site that easily forms an oxygen vacancy is oxygen site 4, and the oxygen site 2 is also relatively easy to form an oxygen vacancy. On the other hand, oxygen vacancies are less likely to be formed in oxygen sites 1 and 3 than in oxygen sites 2 and 4.

<3. Ease of formation and stability of _HO > In <1. Movement of hydrogen atom>, the calculation results of hydrogen diffusion in IGZO, especially during heat treatment, will be described. Thus, the presence of oxygen vacancies in the calculation of V _O V _O the case where the oxygen vacancies in whether hydrogen is disengaged from the oxygen vacancies V _O. Here, a state where a hydrogen atom is present in the oxygen vacancy V _O is referred to as H _O (may also be referred to as V _O H).

In the calculation, an InGaZnO ₄ crystal model shown in FIG. 21 was used. Here, the activation energy barrier (E _a ) on the movement path of the hydrogen atom in which the hydrogen atom in the oxygen vacancy V _O is detached from V _O and bonded to the oxygen atom is calculated by the NEB method. Table 4 shows the calculation conditions.

In "2. Sites where oxygen vacancies V _O are prone to occur", the calculation result of the oxygen site 4 where the oxygen vacancies V _O are most easily formed is shown as the oxygen site 4 shown in FIG. 21. Thus, an oxygen vacancy is calculated in V _O if present in the hydrogen atom of an oxygen vacancy V _O V _O departing from oxygen vacancies a case where Ga and Zn oxygen bonded to two sites (21 in FIG. 3) of the.

FIG. 23A shows a model of an initial state, and FIG. 23B shows a model of a final state. Here, the initial state is the state (H _O) in the presence of a hydrogen atom of oxygen vacancies V _O, the final state is a state comprising oxygen vacancies V _O and bonded to a state of Zn, Ga, and two oxygen atoms bonded to a hydrogen atom ( HO) structure. In addition, FIG. 24 shows an activation energy barrier on a path where a hydrogen atom moves from an initial state to a final state. Here, the total energy in the initial state is used as a reference (0.0 eV).

By calculation, it can be known that the activation energy barrier (E _a ) when the hydrogen atom in the oxygen vacancy V _O is detached from V _O is about 1.70 eV.

Next, the activation barrier is obtained by calculating (E _a) of the above formula 1, calculate the average number of hydrogen atoms per hour of oxygen vacancies V _O is disengaged from the oxygen vacancies V _O.

Suppose frequency factor n = 10 ¹³ [1 / sec], the average number of hydrogen atoms calculated from the oxygen vacancies V _O at room temperature and at 250 deg.] C in oxygen vacancies disengaged from V _O. The average number of times a hydrogen atom moves from the model shown in FIG. 23A to the model shown in FIG. 23B is about 1 × 10 ^-12 [times] at room temperature. This represents the probability of a hydrogen atom at room temperature in an oxygen vacancy V _O disengaged from low oxygen vacancies V _O, H _O in a stable state. On the other hand, the average number of times a hydrogen atom moves from the model shown in FIG. 23A to the model shown in FIG. 23B is about 2 [times] at 250 ° C. This means that in the case where heat treatment is performed for 1 hour at a temperature above 250 deg.] C, the hydrogen atom of oxygen vacancies V _O may be disengaged from the oxygen vacancies V _O.

From the above results, it can be seen that the hydrogen existing in the oxygen vacancy V _O in the channel formation region is desorbed from the oxygen vacancy V _O by heat treatment. In addition, it can be seen that the hydrogen detached from the oxygen vacancy diffuses into the low-resistance region, and enters the oxygen vacancy V _O in the low-resistance region, so that H _{O is} easily formed. Therefore, by performing the heat treatment, the channel formation region is highly purified (reduction of impurities such as water or hydrogen), and a transistor characteristic that is always turned off can be obtained.

The structures, structures, and methods described in this embodiment can be implemented in appropriate combination with the structures, structures, and methods described in other embodiments.

Embodiment 3 First, an example of a semiconductor device including a transistor 200 according to an embodiment of the present invention will be described.

<Structural Example of Semiconductor Device> Figs. 25A, 25B, and 25C are a plan view and a cross-sectional view of the periphery of the transistor 200, the capacitor 100, and the transistor 200 according to an embodiment of the present invention. In this specification, a memory device having one capacitor and at least one transistor is referred to as a cell.

FIG. 25A is a plan view of a cell 600 including a transistor 200 and a capacitor 100. 25B and 25C are cross-sectional views of the cell 600. Here, FIG. 25B is a cross-sectional view of a portion taken along a chain line A1-A2 in FIG. 25A, and the cross-sectional view corresponds to a cross-sectional view in the channel length direction of the transistor 200. 25C is a cross-sectional view of a portion taken along a chain line A3-A4 in FIG. 25A, and the cross-sectional view corresponds to a cross-sectional view in the channel width direction of the transistor 200. For clarity, some components are omitted in the top view of FIG. 25A.

[Cell 600] A semiconductor device according to an embodiment of the present invention includes a transistor 200, a capacitor 100, and an insulator 280 used as an interlayer film. In addition, a conductive body 240 (a conductive body 240a, a conductive body 240b, and a conductive body 240c) used as a plug that is electrically connected to the transistor 200 is also included.

In the unit 600 shown in FIGS. 25A to 25C, by disposing the transistor 200 and the capacitor 100 in the same layer, some components of the transistor 200 can also be used as some components of the capacitor 100. That is, some components of the transistor 200 are sometimes used as some components of the capacitor 100.

In addition, by overlapping part or all of the transistor 200 and the capacitor 100, the total area of the projection area of the transistor 200 and the projection area of the capacitor 100 can be reduced.

By providing a plug electrically connected to the transistor 200 or a conductor 240 b and a conductor 207 used as wiring under the area where the capacitor 100 and the transistor 200 overlap, miniaturization or high integration of the unit 600 becomes easy. . In addition, the conductive body 207 can be formed in the same process as the conductive body 205 which is one of the components of the transistor 200, so the manufacturing process can be shortened. In addition, in the capacitor 100, as in the transistor 200, a conductor used as a wiring may be provided so as to be in contact with the bottom surface of the conductor 207.

The layout of the transistor 200 and the capacitor 100 can be appropriately designed according to the required capacitance value of the capacitor 100.

For example, the area of the capacitor 100 depends on the area of a region 231 b of the oxide 230 and a region where the conductor 120 overlaps each other with the insulator 130 interposed therebetween. Therefore, in the case where the capacitance value required for the cell 600 cannot be obtained in the capacitor 100 shown in FIGS. 25A and 25B, the width in the A3-A4 direction of the oxide 230a and the region 231b of the oxide 230b is larger than that of the oxide. The width in the A3-A4 direction of the region 234 of the object 230a and the oxide 230b can increase the capacitance value.

In addition, for example, the length in the A1-A2 direction of the region 231b of the oxide 230 may be longer than the length in the A1-A2 direction of the conductor 120. In this case, the conductor 240 b may be buried in the insulator 280. In other words, the region 231b of the oxide 230 and the conductor 240b may be in contact with each other in a region where the region 231b of the oxide 230 does not overlap the conductor 120. Thereby, the conductive body 240a, the conductive body 240b, and the conductive body 240c can be formed in the same process, and the manufacturing process can be shortened.

By having the above structure, miniaturization or high integration can be achieved. In addition, design flexibility can be improved. In addition, the transistor 200 and the capacitor 100 can be formed by the same process. Thereby, a manufacturing process can be shortened, and productivity can be improved.

[Transistor 200] As the structure of the transistor 200, the structure of the transistor included in the semiconductor device described in the above embodiment can be adopted. Note that the structure of the transistor 200 shown in FIGS. 25A to 25C is only an example, and is not limited to the above structure, and an appropriate transistor may be used according to a circuit structure or a driving method.

[Capacitor 100] As shown in FIGS. 25A to 25C, the capacitor 100 and the transistor 200 commonly use some components. In the present embodiment, the capacitor 100 is exemplified in which a region 231 b provided in the oxide 230 of the transistor 200 is used as one of the electrodes of the capacitor 100.

The capacitor 100 includes a region 231b of the oxide 230, an insulator 273 on the region 231b, an insulator 130 on the insulator 273, and a conductor 120 on the insulator 130. In addition, it is preferable that the conductor 120 is disposed on the insulator 130 so that at least a part of the insulator 120 overlaps the region 231 b of the oxide 230. In addition, it is preferable that the conductive body 240 c is provided on the conductive body 120 so as to be in contact therewith.

The region 231 b of the oxide 230 is used as one of the electrodes of the capacitor 100, and the conductor 120 is used as the other of the electrodes of the capacitor 100. The insulator 130 and the insulator 273 are used as a dielectric of the capacitor 100. The region 231b of the oxide 230 is a conductive oxide whose resistance is reduced. Therefore, the region 231 b of the oxide 230 may be used as one of the electrodes of the capacitor 100.

As the insulator 130, an insulator having a large relative permittivity is preferably used, and an insulator that can be used for the insulator 222 and the like can be used. For example, an insulator including an oxide of one or both of aluminum and hafnium may be used. As the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use alumina, hafnium oxide, an oxide (hafnium aluminate) containing aluminum and hafnium, and the like. In addition, the insulator 130 may have a laminated structure, for example, may include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, hafnium oxide, and an oxide (hafnium aluminate) containing aluminum and hafnium. Choose more than two laminated structures. For example, it is preferable to form hafnium oxide, alumina, and hafnium oxide in order to form a stacked structure by the ALD method. The thickness of hafnium oxide and alumina is set to 0.5 nm or more and 5 nm or less, respectively. By using such a laminated structure, a capacitor 100 having a large capacitance value and a small leakage current can be formed.

As shown in FIG. 25A, the side surface of the insulator 130 is aligned with the side surface of the conductor 120 in a plan view, but is not limited thereto. For example, the transistor 200 may not be patterned and the transistor 200 may be covered with the insulator 130.

In addition, FIGS. 25A to 25C show a structure in which the insulator 130 and the insulator 273 are provided as the dielectric of the capacitor 100, but the invention is not limited thereto. For example, an area of the insulator 273 overlapping the capacitor 100 may be removed and the insulator 130 may be used as the dielectric of the capacitor 100. In addition, for example, the insulator 273 may be used as the dielectric of the capacitor 100 without providing the insulator 130.

In addition, when the insulator 274 is provided in the transistor 200, a region of the insulator 274 overlapping the capacitor 100 can be removed, and the insulator 274 can also be used as a dielectric of the capacitor 100.

As the conductor 120, a conductive material mainly containing tungsten, copper, or aluminum is preferably used. In addition, although not shown, the conductor 120 may have a laminated structure, and for example, it may have a laminate of titanium, titanium nitride, and the above-mentioned conductive material.

<Configuration of Cell Array> FIG. 26A and FIG. 26B and FIGS. 27A and 27B show an example of a cell array according to this embodiment. For example, a cell array can be configured by arranging the cells 600 including the transistor 200 and the capacitor 100 shown in FIGS. 25A to 25C in a matrix.

FIG. 26A is a circuit diagram of an embodiment in which the cells 600 shown in FIGS. 25A to 25C are arranged in a matrix. In FIG. 26A, one of the source and the drain of the transistors in the cells 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, and BL03). The BL is also electrically connected to one of a source and a drain of a transistor in the cell 600 arranged in the column direction. In addition, the first gates of the transistors in the cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). In addition, a second gate BG may be provided in a transistor in each cell 600. The threshold value of the transistor can be controlled according to the potential applied to the BG. In addition, the first electrode of the capacitor in the unit 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be composed of a part of a transistor. In addition, the second electrode of the capacitor in the unit 600 is electrically connected to the PL.

26B is a cross-sectional view of a circuit 610 including a cell 600a electrically connected to WL04 and BL02 and a cell 600b electrically connected to WL03 and BL02 as part of a row in FIG. 26A. FIG. 26B is a cross-sectional view of the cell 600a and the cell 600b.

The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600b includes a transistor 200b and a capacitor 100b.

One of the source and the drain of the transistor 200a and one of the source and the drain of the transistor 200b are electrically connected to the BL02.

By adopting the above-mentioned structure, the wirings electrically connected to one of the source and the drain are made common, whereby the occupied area of the cell array can be further reduced.

FIG. 27A is a circuit diagram of a circuit in which the cells 600 shown in FIGS. 25A to 25C are arranged in a matrix, which is different from that of FIG. 26A. In FIG. 27A, the first gates of the transistors in the cells 600 arranged in the row direction are electrically connected to a common WL (WL01, WL02, and WL03). In addition, one of the source and the drain of the transistor in the cell 600 arranged in the column direction is electrically connected to a common BL (BL01 to BL06). In addition, a second gate BG may be provided in a transistor in each cell 600. The threshold value of the transistor can be controlled according to the potential applied to the BG. In addition, the first electrode of the capacitor in the unit 600 is electrically connected to the other of the source and the drain of the transistor. At this time, the first electrode of the capacitor may be composed of a part of a transistor. In addition, the second electrode of the capacitor in the unit 600 is electrically connected to the PL. Here, as shown in FIG. 27A, the second electrode of the capacitor of the unit 600 and the second electrode of the capacitor of the unit 600 adjacent to the unit 600 may be electrically connected to a common PL.

FIG. 27B is a cross-sectional view of a circuit 620 including a cell 600a electrically connected to WL02 and BL03 and a cell 600b electrically connected to WL02 and BL04 as part of a row in FIG. 27A. FIG. 27B is a cross-sectional view of the unit 600a and the unit 600b.

The cell 600a includes a transistor 200a and a capacitor 100a. The cell 600b includes a transistor 200b and a capacitor 100b.

The second electrode of the capacitor 100a and the second electrode of the capacitor 100b use a common conductor, which is electrically connected to the PL.

In addition, not only the unit 600 is arranged on a plane, but the unit 600 may be stacked. FIG. 28 is a cross-sectional view showing a structure of a cell array including a circuit 610 in which n + 1 layers are stacked. As shown in FIG. 28, by stacking a plurality of cell arrays, cells can be integrated without increasing the occupied area of the cell array. In other words, a 3D cell array can be constructed.

The structures, structures, and methods described in this embodiment can be implemented in appropriate combination with the structures, structures, and methods described in other embodiments.

Embodiment Mode 4 In this embodiment mode, an embodiment of a semiconductor device will be described with reference to FIGS. 29 to 34.

<Memory Device 1> 的 The memory device shown in FIGS. 29, 30, and 31 includes a transistor 300, a transistor 200, and a capacitor 100. 29 and 31 are cross-sectional views in the channel length direction of the transistor 200 and the transistor 300. FIG. 30 is a cross-sectional view in the channel width direction of the transistor 300 near the transistor 300.

The transistor 200 is a transistor whose channels are formed in a semiconductor layer containing an oxide semiconductor. Since the off-state current of the transistor 200 is small, by using the transistor in a memory device, the memory content can be maintained for a long time. In other words, since no refresh work is required or the frequency of the refresh work is extremely low, the power consumption of the memory device can be sufficiently reduced.

In the memory device shown in FIGS. 29 and 31, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. In addition, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. In addition, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100.

By making the memory device shown in FIGS. 29 and 31 capable of holding the potential of the gate of the transistor 300, data can be written, held, and read as described below.

The writing and holding of data will be described. First, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, and the transistor 200 is turned on. Thereby, the potential of the wiring 1003 is applied to the node SN electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. In other words, a predetermined charge (write) is applied to the gate of the transistor 300. Here, any one of charges (hereinafter, referred to as a low-level charge and a high-level charge) imparted to two different potential levels is applied. Then, the potential of the wiring 1004 is set to a potential at which the transistor 200 becomes a non-conducting state, so that the transistor 200 is in a non-conducting state, and the charge is held at the node SN (hold).

When the off-state current of the transistor 200 is small, the charge of the node SN is maintained for a long period of time.

Next, the reading of data will be described. When an appropriate potential (read potential) is applied to the wiring 1005 in a state where a predetermined potential (constant potential) is applied to the wiring 1001, the wiring 1002 has a potential corresponding to the amount of charge held in the node SN. This is because when the transistor 300 is an n-channel transistor, the threshold voltage V _{th_H} in appearance when a high-level charge is applied to the gate of the transistor 300 is lower than when a low-level charge is applied to the gate of the transistor 300. The critical voltage V _{th_L} at the time of appearance. Here, the external critical voltage refers to the potential of the wiring 1005 required for the transistor 300 to be brought into a “on state”. Accordingly, by setting the potential of the wiring 1005 to the potential V ₀ between V _{th_H} and V _{th_L} , the electric charge applied to the node SN can be discriminated. For example, when the node SN is supplied with a high level of charge at the time of writing, if the potential of the wiring 1005 is V ₀ (> V _{th_H} ), the transistor 300 becomes a “on state”. On the other hand, when the node SN is supplied with a low level charge, even if the potential of the wiring 1005 is V ₀ (<V _{th_L} ), the transistor 300 remains in a “non-conducting state”. Therefore, by discriminating the potential of the wiring 1002, the data held by the node SN can be read.

<Configuration of Memory Device 1> As shown in FIG. 29, a memory device according to an embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100. The transistor 200 is disposed above the transistor 300, and the capacitor 100 is disposed above the transistor 300 and the transistor 200.

The transistor 300 is disposed on the substrate 311 and includes: a conductor 316, an insulator 315, a semiconductor region 313 composed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region used as a source region or a drain region. 314b.

As shown in FIG. 30, in the transistor 300, the conductor 316 covers the top surface of the semiconductor region 313 and the side surface in the channel width direction via the insulator 315. In this way, by providing the transistor 300 with a Fin-type structure, the effective channel width is increased, so the on-state characteristics of the transistor 300 can be improved. In addition, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 300 can be improved.

The transistor 300 may be a p-channel transistor or an n-channel transistor.

The channel formation region of the semiconductor region 313 or a region in the vicinity thereof, the low-resistance region 314 a and the low-resistance region 314 b used as a source region or a drain region preferably include a semiconductor such as a silicon-based semiconductor, and more preferably a single crystal Silicon. Alternatively, it may be formed using a material including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. It is possible to control the effective quality of silicon by applying stress to the crystal lattice and changing the interplanar spacing. In addition, the transistor 300 may be a HEMT (High Electron Mobility Transistor) using GaAs, GaAlAs, or the like.

The low-resistance region 314a and the low-resistance region 314b include, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity such as arsenic and phosphorus or an element that imparts p-type conductivity such as boron.

As the conductor 316 used as the gate electrode, a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide containing silicon containing an element that imparts n-type conductivity such as arsenic and phosphorus or an element that imparts p-type conductivity such as boron can be used. Materials such as conductive materials.

In addition, since the material of the conductor determines the work function, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. In order to have both conductivity and embedding property, it is preferable to use a laminate of a metal material such as tungsten or aluminum as the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

Note that the structure of the transistor 300 shown in FIG. 29 is only an example, and is not limited to the above-mentioned structure. An appropriate transistor may be used according to a circuit structure or a driving method.

An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order so as to cover the transistor 300.

Examples of the insulator 320, insulator 322, insulator 324, and insulator 326 include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

The insulator 322 can also be used as a flattening film that flattens the steps generated by the transistor 300 or the like provided below it. For example, in order to improve the flatness of the top surface of the insulator 322, the top surface may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

As the insulator 324, it is preferable to use a barrier film capable of preventing hydrogen or impurities from diffusing from the substrate 311, the transistor 300, or the like into a region where the transistor 200 is provided.

As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as the transistor 200 and the characteristics of the semiconductor element may be deteriorated. Therefore, it is preferable to provide a film that suppresses the diffusion of hydrogen between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen refers to a film with a small amount of hydrogen detachment.

The amount of hydrogen detached can be measured by, for example, thermal desorption spectrometry (TDS). For example, when the film surface temperature in the TDS analysis is in the range of 50 ° C. to 500 ° C., when the amount of hydrogen atom conversion is converted to the amount per unit area of the insulator 324, the amount of hydrogen separation in the insulator 324 is 10 × 10 ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less, may be sufficient.

Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less the relative dielectric constant of the insulator 324. By using a low dielectric constant material for the interlayer film, it is possible to reduce parasitic capacitance generated between wirings.

Further, a conductor 328, a conductor 330, and the like electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductive body 328 and the conductive body 330 are used as a plug or a wiring. Note that the same component symbol is sometimes used to indicate multiple electrical conductors used as plugs or wiring. In this specification and the like, the wiring and the plug electrically connected to the wiring may be a single component. That is, a part of the conductor is sometimes used as a wiring, and a part of the conductor is sometimes used as a plug.

As the material of each plug and wiring (conductor 328, conductor 330, etc.), a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. It is preferable to use a high melting point material such as tungsten or molybdenum having both heat resistance and electrical conductivity, and it is particularly preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The wiring resistance can be reduced by using a low-resistance conductive material.

A wiring layer may be formed on the insulator 326 and the conductor 330. For example, in FIG. 29, the insulator 350, the insulator 352, and the insulator 354 are laminated in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The electrical conductor 356 is used as a plug or wiring. The conductive body 356 can be formed using the same material as the conductive body 328 and the conductive body 330.

In addition, like the insulator 324, the insulator 350 is preferably an insulator having a barrier property against hydrogen, for example. In addition, the conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. By adopting this structure, the transistor 300 can be separated from the transistor 200 using the barrier layer, and the diffusion of hydrogen from the transistor 300 into the transistor 200 can be suppressed.

Note that as the conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is preferably used. In addition, by stacking tantalum nitride and highly conductive tungsten, not only the conductivity as a wiring can be maintained, but also the diffusion of hydrogen from the transistor 300 can be suppressed. At this time, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be formed on the insulator 354 and the conductor 356. For example, in FIG. 29, the insulator 360, the insulator 362, and the insulator 364 are laminated in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The electrical conductor 366 is used as a plug or wiring. The conductive body 366 can be formed using the same material as the conductive body 328 and the conductive body 330.

In addition, like the insulator 324, the insulator 360 is preferably, for example, an insulator having a barrier property against hydrogen. In addition, the conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. By adopting this structure, the transistor 300 can be separated from the transistor 200 using the barrier layer, and the diffusion of hydrogen from the transistor 300 into the transistor 200 can be suppressed.

A wiring layer may be formed on the insulator 364 and the conductor 366. For example, in FIG. 29, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 is used as a plug or wiring. The conductive body 376 can be formed using the same material as the conductive body 328 and the conductive body 330.

In addition, like the insulator 324, the insulator 370 is preferably an insulator having a barrier property against hydrogen, for example. In addition, the conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. By adopting this structure, the transistor 300 can be separated from the transistor 200 using the barrier layer, and the diffusion of hydrogen from the transistor 300 into the transistor 200 can be suppressed.

A wiring layer may be formed on the insulator 374 and the conductor 376. For example, in FIG. 29, an insulator 380, an insulator 382, and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, and the insulator 384. The electrical conductor 386 is used as a plug or wiring. The conductive body 386 can be formed using the same material as the conductive body 328 and the conductive body 330.

In addition, like the insulator 324, the insulator 380 is preferably an insulator having a barrier property against hydrogen, for example. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. By adopting this structure, the transistor 300 can be separated from the transistor 200 using the barrier layer, and the diffusion of hydrogen from the transistor 300 into the transistor 200 can be suppressed.

Although the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described above, the memory device of the present embodiment is not limited to this. The same wiring layer as the wiring layer including the conductor 356 may be three or less, and the same wiring layer as the wiring layer including the conductor 356 may be five or more.

On the insulator 384, an insulator 210, an insulator 212, an insulator 214, and an insulator 216 are sequentially stacked. As any one of the insulator 210, the insulator 212, the insulator 214, and the insulator 216, it is preferable to use a substance having a barrier property against oxygen or hydrogen.

For example, as the insulator 210 and the insulator 214, for example, it is preferable to use a barrier film capable of preventing hydrogen or impurities from diffusing from the substrate 311 or the region where the transistor 300 is provided into the region where the transistor 200 is provided. Therefore, the insulator 210 and the insulator 214 can be made of the same material as the insulator 324.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen may diffuse into a semiconductor element having an oxide semiconductor such as the transistor 200 and the characteristics of the semiconductor element may be deteriorated. Therefore, it is preferable to provide a film that suppresses the diffusion of hydrogen between the transistor 300 and the transistor 200. Specifically, the film that suppresses the diffusion of hydrogen refers to a film with a small amount of hydrogen detachment.

For example, as the film having a barrier property against hydrogen, the insulator 210 and the insulator 214 are preferably metal oxides such as alumina, hafnium oxide, and tantalum oxide.

In particular, alumina has a high barrier effect that does not allow oxygen and impurities such as hydrogen and moisture that cause the electrical characteristics of the transistor to change. Therefore, during and after the transistor process, alumina can prevent impurities such as hydrogen and moisture from entering the transistor 200. In addition, alumina can suppress the release of oxygen from the oxide constituting the transistor 200. Therefore, alumina is suitable as a protective film for the transistor 200.

For example, as the insulator 212 and the insulator 216, the same material as the insulator 320 can be used. In addition, by forming the interlayer film from a material having a lower dielectric constant, it is possible to reduce parasitic capacitance generated between wirings. For example, as the insulator 212 and the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

A conductor 218, a conductor (conductor 205) constituting the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. In addition, the conductor 218 is used as a plug or wiring that is electrically connected to the capacitor 100 or the transistor 300. The conductive body 218 can be formed using the same material as the conductive body 328 and the conductive body 330.

In particular, the conductor 218 in a region in contact with the insulator 210 and the insulator 214 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. By adopting this structure, the transistor 300 and the transistor 200 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and the diffusion of hydrogen from the transistor 300 into the transistor 200 can be suppressed.

A transistor 200 is provided above the insulator 216. In addition, as the transistor 200, a transistor included in the semiconductor device described in the above embodiment can be used. Note that the structure of the transistor 200 shown in FIG. 29 is only an example and is not limited to the above-mentioned structure. An appropriate transistor may be used according to a circuit structure or a driving method.

An insulator 280 is provided above the transistor 200.

An insulator 282 is provided on the insulator 280. The insulator 282 is preferably a substance having a barrier property against oxygen or hydrogen. Therefore, the same material as the insulator 214 can be used as the insulator 282. For example, as the insulator 282, a metal oxide such as alumina, hafnium oxide, or tantalum oxide is preferably used.

In particular, alumina has a high barrier effect that does not allow oxygen and impurities such as hydrogen and moisture that cause the electrical characteristics of the transistor to change. Therefore, during and after the transistor process, alumina can prevent impurities such as hydrogen and moisture from entering the transistor 200. In addition, alumina can suppress the release of oxygen from the oxide constituting the transistor 200. Therefore, alumina is suitable as a protective film for the transistor 200.

An insulator 286 is provided on the insulator 282. The insulator 286 can be made of the same material as the insulator 320. In addition, by forming the interlayer film from a material having a lower dielectric constant, it is possible to reduce parasitic capacitance generated between wirings. For example, as the insulator 286, a silicon oxide film, a silicon oxynitride film, or the like can be used.

Further, a conductor 246, a conductor 248, and the like are embedded in the insulator 220, the insulator 222, the insulator 280, the insulator 282, and the insulator 286.

The conductor 246 and the conductor 248 are used as plugs or wirings electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductive body 246 and the conductive body 248 can be formed using the same materials as the conductive body 328 and the conductive body 330.

Next, a capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110, a conductor 120, and an insulator 130.

In addition, the conductor 112 may be provided on the conductor 246 and the conductor 248. The electrical conductor 112 is used as a plug or wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 110 is used as an electrode of the capacitor 100. In addition, the conductive body 112 and the conductive body 110 may be formed at the same time.

As the conductor 112 and the conductor 110, a metal film containing an element selected from the group consisting of molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and praseodymium, or a metal nitride film (nitriding containing the above elements) Tantalum film, titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.). Alternatively, indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, indium zinc oxide, There are conductive materials such as indium tin oxide of silicon oxide.

In FIG. 29, the conductor 112 and the conductor 110 have a single-layer structure, but the invention is not limited to this, and may have a laminated structure of two or more layers. For example, a conductive body having a high tightness with the conductive body having a barrier property and the conductive body having a high conductivity may be formed between the conductive body having a barrier property and the conductive body having a high conductivity.

In addition, an insulator 130 is provided on the conductor 112 and the conductor 110 as a dielectric of the capacitor 100. As the insulator 130, for example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, nitrogen Laminated or single layers of chemical compounds.

For example, as the insulator 130, a material having high insulation strength such as silicon oxynitride can be used. By adopting this structure, since the capacitor 100 includes the insulator 130, it is possible to improve the insulation strength and suppress the electrostatic destruction of the capacitor 100.

A conductive body 120 is provided on the insulator 130 so as to overlap the conductive body 110. As the conductor 120, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high melting point material such as tungsten or molybdenum having both heat resistance and electrical conductivity, and it is particularly preferable to use tungsten. When the conductor 120 is formed simultaneously with other components such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low-resistance metal material, may be used.

An insulator 150 is provided on the conductor 120 and the insulator 130. The insulator 150 can be formed using the same material as the insulator 320. In addition, the insulator 150 may be used as a flattening film having a concave-convex shape covering it.

By adopting this structure, it is possible to improve reliability while suppressing variations in electrical characteristics of a semiconductor device using a transistor including an oxide semiconductor. In addition, an transistor including an oxide semiconductor having a large on-state current can be provided. In addition, an transistor including an oxide semiconductor having a small off-state current can be provided. In addition, a semiconductor device with reduced power consumption can be provided.

<Modified Example of Memory Device 1> Next, an example of a memory device according to an embodiment of the present invention will be described with reference to FIG. 31.

31 is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, and a transistor 300. In addition, in the memory device shown in FIG. 31, components having the same functions as those of the semiconductor device and the memory device shown in the above-described embodiment and <Configuration of the memory device 1> are assigned the same element symbols.

The memory device shown in FIG. 31 is different from the memory device shown in <Configuration of Memory Device 1> in that the unit 600 described in the above embodiment is included.

Specifically, the memory device shown in FIG. 31 includes a unit 600 whose components are shared by the capacitor 100 and the transistor 200.

In the above structure, since the unit 600 and a part or all of the transistor 300 overlap, the total area of the projected area of the memory device can be reduced. Therefore, miniaturization or high integration of the unit 600 is easy. In addition, the process can be shortened.

<Memory Device 2> 的 The semiconductor device shown in FIGS. 32A and 32B is a memory device including a transistor 400, a transistor 200, and a capacitor 100. An embodiment of the memory device will be described below with reference to FIGS. 32A and 32B.

FIG. 32A is a circuit diagram illustrating an example of a connection relationship between the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device shown in this embodiment. In addition, FIG. 32B shows a cross-sectional view of the semiconductor device in which the wirings 1004 to 1010 and the like correspond to the wirings shown in FIG. 32A.

The transistor 200 and the transistor 400 formed on a substrate (not shown) have different structures from each other. For example, the drain current when the bottom gate voltage and top gate voltage of the transistor 400 are 0V may be smaller than that of the transistor 200. The potential of the bottom gate of the transistor 200 is controlled by using the transistor 400 as a switching element. Accordingly, by setting the transistor 400 to the off state after the node connected to the bottom gate of the transistor 200 is set to a desired potential, it is possible to suppress the charge of the node connected to the bottom gate of the transistor 200 from disappearing.

As shown in FIGS. 32A and 32B, in the transistor 200, the gate is electrically connected to the wiring 1004, one of the source and the drain is electrically connected to the wiring 1003, and the other of the source and the drain is electrically connected to the capacitor 100. One of the electrodes is electrically connected. In addition, the other of the electrodes of the capacitor 100 is electrically connected to the wiring 1005. The drain of the transistor 400 is electrically connected to the wiring 1010. In addition, as shown in FIG. 32B, the bottom gate of the transistor 200, the source, the top gate, and the bottom gate of the transistor 400 are electrically connected by a wiring 1006, a wiring 1007, a wiring 1008, and a wiring 1009.

Here, by supplying a potential to the wiring 1004, the on state and the off state of the transistor 200 can be controlled. By making the transistor 200 in an on state and supplying a potential to the wiring 1003, electric charges can be supplied to the capacitor 100 through the transistor 200. At this time, by turning off the transistor 200, the electric charge supplied to the capacitor 100 can be maintained. In addition, by supplying an arbitrary potential to the wiring 1005, the potential of the connection portion between the transistor 200 and the capacitor 100 can be controlled by capacitive coupling. For example, when the ground potential is supplied to the wiring 1005, it is easy to maintain the above-mentioned charges. In addition, when a negative potential is supplied to the wiring 1010, a negative potential can be supplied to the bottom gate of the transistor 200 through the transistor 400, so that the threshold voltage of the transistor 200 is greater than 0V, the off-state current is reduced, and Icut is extremely small. Here, Icut refers to the drain current when the voltage applied to the top gate is 0V.

By adopting a structure in which the top gate and the bottom gate of the transistor 400 are connected to the source and the source of the transistor 400 is connected to the bottom gate of the transistor 200, the transistor can be controlled by the wiring 1010. Bottom gate voltage of 200. When the negative potential of the bottom gate of the transistor 200 is maintained, the voltage between the top gate and the source of the transistor 400 and the voltage between the back gate and the source become 0V. Because the Icut of the transistor 400 is extremely small and the threshold voltage of the transistor 400 is greater than that of the transistor 200, by adopting this structure, the negative potential of the bottom gate of the transistor 200 can be maintained for a long time even if no power is supplied to the transistor 400.

Furthermore, by maintaining the negative potential of the bottom gate of the transistor 200, even if no power is supplied to the transistor 200, the Icut of the transistor 200 can be made extremely small. That is, even if the transistor 200 and the transistor 400 are not supplied with power, the charge can be held in the capacitor 100 for a long time. For example, by using such a semiconductor device as a memory element, it is possible to hold the stored content for a long time without power supply. Therefore, it is possible to provide a memory device with a low frequency of updating work or requiring no updating work.

Note that the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 is not limited to the connection relationship shown in FIGS. 32A and 32B. The connection relationship can be appropriately changed according to the required circuit structure.

<Configuration of Memory Device 2> FIG. 32B is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, and a transistor 400. In addition, in the memory device shown in FIGS. 32A and 32B, components having the same functions as those of the semiconductor device and the memory device shown in the above-described embodiment and the <Configuration of the Memory Device 1> are added with the same components. Component symbol.

As shown in FIGS. 32A and 32B, a memory device according to an embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100. The transistor 200 and the transistor 400 are formed in the same layer, and the capacitor 100 is disposed above the transistor 200 and the transistor 400.

As the capacitor 100 and the transistor 200, the capacitor and the transistor included in the semiconductor device and the memory device described in the above embodiment and FIGS. 29 and 31 can be used. In addition, the structures of the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 shown in FIGS. 32A and 32B are only examples, and are not limited to the above-mentioned structures. An appropriate transistor may be used depending on the circuit structure or driving method.

The transistor 400 is formed in the same layer as the transistor 200, whereby they can be manufactured at the same time. The transistor 400 includes: a conductor 460 (conductors 460a and 460b) used as a top gate electrode; a conductor 405 used as a bottom gate electrode; an insulator 470 and an insulator 472 in contact with the conductor 460; Insulator 475 provided on the side of conductor 460 via insulator 472; insulator 220, insulator 222, insulator 224, and insulator 450 used as a gate insulating layer; oxide 430c including a region forming a channel; used as a source An oxide 431a and an oxide 431b of one of the electrode and the drain; and an oxide 432a and an oxide 432b used as the other of the source and the drain. In addition, a conductor 405 used as a bottom gate electrode is electrically connected to a conductor 403 used as a wiring.

In the transistor 400, the conductor 405 and the conductor 205 are formed in the same layer. The oxides 431a and 432a are formed in the same layer as the oxide 230a, and the oxides 431b and 432b are formed in the same layer as the oxide 230b. The oxide 430c and the oxide 230c are formed in the same layer. The insulator 450 and the insulator 250 are formed in the same layer. The metal oxide 452 and the metal oxide 252 are formed in the same layer. The conductor 460 and the conductor 260 are formed in the same layer. In addition, the insulator 470 and the insulator 270 are formed in the same layer. In addition, the insulator 472 and the insulator 272 are formed in the same layer. The insulator 475 and the insulator 275 are formed in the same layer.

Like the oxide 230 and the like, in the oxide 430c used as the active layer of the transistor 400, oxygen vacancies and impurities such as hydrogen or water are reduced. Therefore, the threshold voltage of the transistor 400 can be greater than 0V, the off-state current can be reduced, and the drain current when the bottom gate voltage and the top gate voltage are 0V is very small.

As described above, the oxides 431a and 432a are formed in the same layer as the oxide 230a, and the oxides 431b and 432b are formed in the same layer as the oxide 230b. Therefore, low-resistance regions corresponding to the regions 231a and 231b are formed in the oxides 431a, 432a, 431b, and 432b.

By adopting this structure, it is possible to improve reliability while suppressing variations in electrical characteristics of a semiconductor device using a transistor including an oxide semiconductor. In addition, power consumption of a semiconductor device using a transistor including an oxide semiconductor can be reduced. In addition, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved. In addition, miniaturized or highly integrated semiconductor devices can be provided with high productivity.

<Memory Device 3> 的 The semiconductor device shown in FIG. 33 is a memory device including a transistor 300, a transistor 200, and a capacitor 100. Hereinafter, an embodiment of the memory device will be described using FIG. 33.

The transistor 200 is a transistor whose channels are formed in a semiconductor layer containing an oxide semiconductor, and the transistor described in the above embodiment can be used. The transistor described in the above embodiment can be formed at a high yield even if it is miniaturized, so that the transistor 200 can be miniaturized. By using the transistor as a memory device, the memory device can be miniaturized or high-volume. Since the off-state current of the transistor shown in the above-mentioned embodiment is small, by using the transistor in a memory device, the stored content can be maintained for a long time. In other words, since no refresh work is required or the frequency of the refresh work is extremely low, the power consumption of the memory device can be sufficiently reduced.

In FIG. 33, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. In addition, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the top gate of the transistor 200, and the wiring 1006 is electrically connected to the bottom gate of the transistor 200. Furthermore, the other of the gate of the transistor 300 and the source and the drain of the transistor 200 is electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100.

The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is electrically connected to the drain stage of the transistor 400. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

By providing the semiconductor device shown in FIG. 33 with a feature capable of holding the potential of the gate of the transistor 300, data can be written, held, and read as described below.

The writing and holding of data will be described. First, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, and the transistor 200 is turned on. Thereby, the potential of the wiring 1003 is applied to the node SN electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. In other words, a predetermined charge (write) is applied to the gate of the transistor 300. Here, any one of charges (hereinafter, referred to as a low-level charge and a high-level charge) imparted to two different potential levels is applied. Then, the potential of the wiring 1004 is set to a potential at which the transistor 200 becomes a non-conducting state, so that the transistor 200 is in a non-conducting state, and the charge is held at the node SN (hold).

When the off-state current of the transistor 200 is small, the charge of the node SN is maintained for a long period of time.

Next, the reading of data will be described. When an appropriate potential (read potential) is applied to the wiring 1005 in a state where a predetermined potential (constant potential) is applied to the wiring 1001, the wiring 1002 has a potential corresponding to the amount of charge held in the node SN. This is because when the transistor 300 is an n-channel transistor, the threshold voltage V _{th_H} in appearance when a high-level charge is applied to the gate of the transistor 300 is lower than when a low-level charge is applied to the gate of the transistor 300. The critical voltage V _{th_L} at the time of appearance. Here, the external critical voltage refers to the potential of the wiring 1005 required for the transistor 300 to be brought into a “on state”. Accordingly, by setting the potential of the wiring 1005 to the potential V ₀ between V _{th_H} and V _{th_L} , the electric charge applied to the node SN can be discriminated. For example, when the node SN is supplied with a high level of charge at the time of writing, if the potential of the wiring 1005 is V ₀ (> V _{th_H} ), the transistor 300 becomes a “on state”. On the other hand, when the node SN is supplied with a low level charge, even if the potential of the wiring 1005 is V ₀ (<V _{th_L} ), the transistor 300 remains in a “non-conducting state”. Therefore, by discriminating the potential of the wiring 1002, the data held by the node SN can be read.

<Configuration of Memory Device 3> FIG. 33 is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, a transistor 300, and a transistor 400. In addition, in the memory device shown in FIG. 33, the same components as those of the semiconductor device and the memory device shown in the above-mentioned embodiment, <Configuration of Memory Device 1>, and <Configuration of Memory Device 2> are used. Functional components are assigned the same symbol.

As shown in FIG. 33, a memory device according to an embodiment of the present invention includes a transistor 200, a transistor 300, a transistor 400, and a capacitor 100. The transistor 200 and the transistor 400 are formed above the transistor 300, and the capacitor 100 is disposed above the transistor 200, the transistor 300, and the transistor 400.

As the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, the capacitor and the transistor included in the semiconductor device and the memory device described in the above embodiment and FIGS. 29 to 32B can be used. In addition, the structures of the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 shown in FIG. 33 are merely examples, and are not limited to the above-mentioned structures. An appropriate transistor may be used depending on the circuit structure or driving method.

By adopting this structure, it is possible to improve reliability while suppressing variations in electrical characteristics of a semiconductor device using a transistor including an oxide semiconductor. In addition, power consumption of a semiconductor device using a transistor including an oxide semiconductor can be reduced. In addition, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved. In addition, miniaturized or highly integrated semiconductor devices can be provided with high productivity.

<Configuration of Memory Cell Array> FIG. 34 shows an example of a memory cell array according to the present embodiment. By using the transistor 200 as a memory cell and the memory cells are arranged in a matrix, a memory cell array can be configured.

The memory device shown in FIG. 34 is a semiconductor device in which the memory devices shown in FIGS. 29 and 33 are arranged in a matrix to form a memory unit. One transistor 400 can control the back gate voltage in the plurality of transistors 200. Therefore, it is preferable to make the number of the transistors 400 less than the number of the transistors 200.

Note that the transistor 400 shown in FIG. 33 is omitted in FIG. 34. 34 is a cross-sectional view showing a part of a row when the memory devices shown in FIGS. 29 and 33 are arranged in a matrix.

34 is different from FIG. 33 in the structure of the transistor 300. In the transistor 300 shown in FIG. 34, the semiconductor region 313 (a part of the substrate 311) forming a channel has a convex shape. A conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween. A material for adjusting the work function can be used for the conductor 316. Because the convex portion of the semiconductor substrate is used, this transistor 300 is also called a Fin-type transistor. Moreover, you may have the insulator used as a mask for forming a convex part so that it may contact the upper part of a convex part. In addition, although a case where a part of a semiconductor substrate is processed to form a convex portion is shown here, a SOI substrate may be processed to form a semiconductor film having a convex shape.

In the memory device shown in FIG. 34, the memory unit 650a is provided adjacent to the memory unit 650b. Memory unit 650a and memory unit 650b include transistor 300, transistor 200, and capacitor 100, and are electrically connected to wiring 1001, wiring 1002, wiring 1003, wiring 1004, wiring 1005, and wiring 1006. In addition, in the memory unit 650a and the memory unit 650b, a node where the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is similarly referred to as a node SN. Note that the wiring 1002 is a wiring common to adjacent memory cells 650a and 650b.

When the memory cells are arranged in a matrix, the data of a desired memory cell must be read out during reading. For example, when the memory cell array has a NOR structure, the transistor 300 of the memory cell that does not read data can be turned off, so that only the data in the desired memory cell can be read. In this case, the wiring 1005 connected to the memory cell that does not read data may be used to supply a potential that causes the transistor 300 to be in a “non-conducting state” regardless of the charge applied to the node SN, that is, a voltage lower than V _{th_H} Potential to read only the data in the desired memory cell. Alternatively, for example, when the memory cell array has a NAND type structure, the transistor 300 of the memory cell that does not read data can be turned on, so that only the data in the desired memory cell can be read. In this case, the wiring 1005 connected to the memory cell that does not read data may be used to supply a potential that causes the transistor 300 to be in a “on state” regardless of the charge applied to the node SN, that is, a potential higher than V _{th_L} , To read only the structure of the data of the desired memory unit.

By adopting this structure, it is possible to improve reliability while suppressing variations in electrical characteristics of a semiconductor device using a transistor including an oxide semiconductor. In addition, power consumption of a semiconductor device using a transistor including an oxide semiconductor can be reduced. In addition, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved. In addition, miniaturized or highly integrated semiconductor devices can be provided with high productivity.

The structures, structures, and methods described in this embodiment can be implemented in appropriate combination with the structures, structures, and methods described in other embodiments.

Embodiment 5 参照 In this embodiment, referring to FIGS. 35 to 37, one embodiment of the present invention is one of a memory device using a transistor (hereinafter referred to as an OS transistor) using an oxide for a semiconductor and a capacitor. An example is to explain NOSRAM. NOSRAM (registered trademark) is an abbreviation of "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM with a gain cell type (2T type, 3T type) memory cell. Hereinafter, a memory device using an OS transistor such as NOSRAM is sometimes referred to as an OS memory.

In NOSRAM, a memory device (hereinafter referred to as “OS memory”) using an OS transistor in a memory unit can be used. The OS memory is a memory including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory has good holding characteristics and can be used as a non-volatile memory.

<< NOSRAM> FIG. 35 shows a configuration example of NOSRAM. The NOSRAM 1600 shown in FIG. 35 includes a memory cell array 1610, a controller 1640, a row driver 1650, a column driver 1660, and an output driver 1670. In addition, NOSRAM1600 is a multi-valued NOSRAM that stores multi-valued data in one memory unit.

The memory cell array 1610 includes a plurality of memory cells 1611, a plurality of word lines WWL, RWL, a bit line BL, and a source line SL. The word line WWL is a write word line, and the word line RWL is a read word line. In NOSRAM1600, three bits (eight values) of data are stored in one memory unit 1611.

The controller 1640 controls the entire NOSRAM 1600, and performs writing of data WDA [31: 0] and reading of data RDA [31: 0]. The controller 1640 processes external command signals (for example, wafer enable signals, write enable signals, etc.) to generate control signals for the row driver 1650, the column driver 1660, and the output driver 1670.

The row driver 1650 has a function of selecting a row to be accessed. The row driver 1650 includes a row decoder 1651 and a word line driver 1652.

The column driver 1660 drives the source line SL and the bit line BL. The column driver 1660 includes a column decoder 1661, a write driver 1662, and a DAC (Digital-Analog Conversion Circuit) 1663.

The DAC1663 converts 3-bit digital data into an analog voltage. DAC1663 converts 32-bit data WDA [31: 0] into analog voltage every 3 bits.

The write driver 1662 has the following functions: pre-charging the source line SL; changing the source line SL to an electrically floating state; selecting the source line SL; and inputting the write voltage generated by the DAC1663 to the selected source line SL Pre-charge the bit line BL; make the bit line BL electrically floating; and so on.

The output driver 1670 includes a selector 1671, an ADC (analog-to-digital conversion circuit) 1672, and an output buffer 1673. The selector 1671 selects the source line SL to be accessed and sends the voltage of the selected source line SL to the ADC 1672. ADC1672 has the function of converting analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC 1672, and the output buffer 1673 holds the data output from the ADC 1672.

Note that the structures of the row driver 1650, the column driver 1660, and the output driver 1670 shown in this embodiment are not limited to the above-mentioned structures. Depending on the structure or driving method of the memory cell array 1610, the configuration of the drivers and the wirings connected to the drivers may be changed, and the functions of the drivers and the wirings connected to the drivers may be changed or added. For example, the bit line BL may be provided with a part of the function of the source line SL described above.

In addition, in the above-mentioned configuration, the amount of data held by each memory unit 1611 is 3 bits, but the configuration of the memory device shown in this embodiment is not limited to this. The amount of data held by each memory unit 1611 may be 2 bits or less, or may be 4 bits or more. For example, when the amount of data held by each memory unit 1611 is one bit, the DAC1663 and the ADC1672 may not be provided.

<Memory Unit> FIG. 36A is a circuit diagram showing a configuration example of the memory unit 1611. The memory unit 1611 is a 2T-type gain unit. The memory unit 1611 is electrically connected to the word lines WWL, RWL, bit lines BL, source lines SL, and wiring BGL. The memory unit 1611 includes a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. The transistor MP61 is a readout transistor, and is composed of, for example, a p-channel Si transistor. The capacitor C61 is a storage capacitor for holding the voltage of the node SN. The node SN is a node for holding data, which is equivalent to the gate of the transistor MP61.

Since the write transistor of the memory unit 1611 is composed of the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

Although the write bit line and the read bit line are common in the example of FIG. 36A, the bit line WBL used as the write bit line and the read bit line may be separately provided as shown in FIG. 36B. The bit line RBL out of the bit line.

36C to 36E show other structural examples of the memory unit. Although an example in which the write bit line WBL and the read bit line RBL are provided is shown in FIGS. 36C to 36E, as shown in FIG. 36A, the write bit line and the read bit line may be common. .

The memory unit 1612 shown in FIG. 36C is a modified example of the memory unit 1611 in which an n-channel transistor (MN61) is used instead of the readout transistor. The transistor MN61 may be an OS transistor or a Si transistor.

In the memory unit 1611 and the memory unit 1612, the OS transistor MO61 may be an OS transistor without a back gate.

The memory cell 1613 shown in FIG. 36D is a 3T-type gain unit and is electrically connected to the word lines WWL, RWL, bit lines WBL, RBL, source lines SL, wiring BGL, and wiring PCL. The memory unit 1613 includes a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. The transistor MP62 is a readout transistor, and the transistor MP63 is a selection transistor.

The memory unit 1614 shown in FIG. 36E is a modified example of the memory unit 1613, in which n-channel transistors (MN62, MN63) are used instead of the readout transistor and the selection transistor. The transistors MN62 and MN63 may be OS transistors or Si transistors.

The OS transistors provided in the memory unit 1611 to the memory unit 1614 may be transistors without a back gate or transistors with a back gate.

Although the so-called NOR-type memory device connected in parallel such as the memory unit 1611 has been described above, the memory device shown in this embodiment is not limited to this. For example, a so-called NAND-type memory device in which the memory cells 1615 shown below are connected in series may be used.

FIG. 37 is a circuit diagram showing a configuration example of a NAND-type memory cell array 1610. The memory cell array 1610 shown in FIG. 37 includes a source line SL, a bit line RBL, a bit line WBL, a word line WWL, a word line RWL, a wiring BGL, and a memory cell 1615. The memory unit 1615 includes a node SN, an OS transistor MO63, a transistor MN64, and a capacitor C63. Here, the transistor MN64 is, for example, an n-channel Si transistor. However, without limitation, the transistor MN64 may be a p-channel Si transistor or an OS transistor.

The following description uses the memory unit 1615a and the memory unit 1615b shown in FIG. 37 as an example. Here, the symbols a and b are attached to the wiring or circuit elements connected to the memory unit 1615a and the memory unit 1615b, respectively.

In the memory unit 1615a, one of the gate of the transistor MN64a, one of the source and the drain of the OS transistor MO63a, and one of the electrodes of the capacitor C63a are electrically connected. In addition, the bit line WBL is electrically connected to the other of the source and the drain of the OS transistor MO63a. The word line WWLa is electrically connected to the gate of the OS transistor MO63a. The wiring BGLa is electrically connected to the back gate of the OS transistor MO63a. In addition, the word line RWLa is electrically connected to the other of the electrodes of the capacitor C63a.

The memory unit 1615b may be disposed symmetrically to the memory unit 1615a with a contact portion with the bit line WBL as an axis. Therefore, the circuit elements included in the memory unit 1615b are also connected to the wiring in the same manner as the above-mentioned memory unit 1615a.

In addition, the source of the transistor MN64a included in the memory unit 1615a is electrically connected to the drain of the transistor MN64b of the memory unit 1615b. The drain of the transistor MN64a included in the memory unit 1615a is electrically connected to the bit line RBL. The source of the transistor MN64b included in the memory unit 1615b is electrically connected to the source line SL through the transistor MN64 included in the plurality of memory units 1615. As described above, in the NAND-type memory cell array 1610, a plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.

In a memory device including the memory cell array 1610 shown in FIG. 37, writing and reading are performed by a plurality of memory cells (hereinafter, referred to as a memory cell row) connected to the same word line WWL (or word line RWL). Out of work. For example, writing can be performed as follows. A potential for turning on the OS transistor MO63 is applied to the word line WWL connected to the writing target memory cell column to turn on the OS transistor MO63 of the writing target memory cell column. As a result, the potential of the bit line WBL is applied to one of the gate of the transistor MN64 of the specified memory cell row and the electrode of the capacitor C63, and a predetermined charge is supplied to the gate. Then, the OS transistor MO63 of the memory cell row is turned off to maintain the specified charge supplied to the gate. Thereby, data can be written in the memory cell 1615 of the designated memory cell row.

In addition, for example, the reading operation can be performed as follows. First, a potential is applied to the word line RWL that is not connected to the memory cell column to be read to turn on the transistor MN64 regardless of the charge supplied to the gate of the transistor MN64, so that electricity other than the memory cell column to be read is applied. The crystal MN64 is turned on. Then, the word line RWL connected to the memory cell column to be read out is applied with a potential (reading potential) that selects the on-state or off-state of the transistor MN64 based on the charge of the gate of the transistor MN64. Then, a constant potential is applied to the source line SL, and the readout circuit connected to the bit line RBL is put into an operating state. Here, since the transistors MN64 other than the memory cell column to be read out of the plurality of transistors MN64 between the source line SL and the bit line RBL are in a conducting state, the distance between the source line SL and the bit line RBL is on. The conductivity depends on the state (on state or off state) of the transistor MN64 in the memory cell row to be read. Since the conductivity of the transistor changes according to the electric charge of the gate of the transistor MN64 of the memory cell row to be read, the bit line RBL takes a different potential according to the conductivity. By reading the potential of the bit line RBL using a readout circuit, information can be read out from the memory cell 1615 of the designated memory cell row.

Since data is rewritten by charging and discharging of capacitor C61, capacitor C62, or capacitor C63, there is theoretically no limit to the number of times that NOSRAM1600 can be rewritten, and data can be written and read with low energy. In addition, since the data can be held for a long time, the update frequency can be reduced.

When the semiconductor device described in the above embodiment is used for the memory cells 1611, 1612, 1613, 1614, and 1615, the transistor 200 can be used as the OS transistor MO61, MO62, and MO63, and the capacitor can be used as the capacitor C61, C62, and C63. 100. As the transistors MP61, MP62, MP63, MN61, MN62, MN63, and MN64, a transistor 300 can be used. As a result, the occupation area in the plan view of each group consisting of one transistor and one capacitor can be reduced, and the memory device of the present embodiment can be further integrated. Thereby, the memory capacity per unit area of the memory device of this embodiment can be increased.

The structure described in this embodiment can be used in appropriate combination with the structures described in other embodiments.

Embodiment 6 In this embodiment, DOSRAM will be described using FIG. 38 and FIGS. 39A and 39B as an example of a memory device according to an embodiment of the present invention using an OS transistor and a capacitor. DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor RAM" and refers to a RAM including a 1T (transistor) 1C (capacitor) type memory cell. Like NOSRAM, DOSRAM also uses OS memory.

<< DOSRAM1400 >> Fig. 38 shows an example of the structure of DOSRAM. As shown in FIG. 38, the DOSRAM 1400 includes a controller 1405, a row circuit 1410, a column circuit 1415, a memory unit, and a sense amplifier array 1420 (hereinafter referred to as "MC-SA array 1420").

The row circuit 1410 includes a decoder 1411, a word line driver circuit 1412, a column selector 1413, and a sense amplifier drive circuit 1414. The column circuit 1415 includes a global sense amplifier array 1416 and an input-output circuit 1417. The global sense amplifier array 1416 includes a plurality of global sense amplifiers 1447. The MC-SA array 1420 includes a memory cell array 1422, a sense amplifier array 1423, global bit lines GBLL, and GBLR.

(MC-SA array 1420) The MC-SA array 1420 has a stacked structure in which a memory cell array 1422 is stacked on a sense amplifier array 1423. The global bit lines GBLL and GBLR are stacked on the memory cell array 1422. In DOSRAM 1400, a layered bit line structure in which a local bit line and a global bit line are layered is adopted as a bit line structure.

The memory cell array 1422 includes N (N is an integer of 2 or more) local memory cell arrays 1425 <0> to 1425 <N-1>. FIG. 39A illustrates a configuration example of the local memory cell array 1425. The local memory cell array 1425 includes a plurality of memory cells 1445, a plurality of word lines WL, and a plurality of bit lines BLL and BLR. In the example of FIG. 39A, the structure of the local memory cell array 1425 is an open bit line type, but it may be a folded bit line type.

FIG. 39B shows an example of a circuit configuration of a pair of memory cells 1445a and 1445b connected to a common bit line BLL (BLR). The memory unit 1445a includes a transistor MW1a, a capacitor CS1a, and terminals B1a and B2a, and is connected to the word line WLa and the bit line BLL (BLR). In addition, the memory unit 1445b includes a transistor MW1b, a capacitor CS1b, terminals B1b, and B2b, and is connected to the word line WLb and the bit line BLL (BLR). In the following, when describing the contents of both the memory unit 1445a and the memory unit 1445b, the memory unit 1445 and the accompanying components may not be assigned a or b symbols.

The transistor MW1a has a function of controlling the charge and discharge of the capacitor CS1a, and the transistor MW1b has a function of controlling the charge and discharge of the capacitor CS1b. The gate of the transistor MW1a is electrically connected to the word line WLa, the first terminal is electrically connected to the bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1a. In addition, the gate of the transistor MW1b is electrically connected to the word line WLb, the first terminal is electrically connected to the bit line BLL (BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1b. In this way, both the first terminal of the transistor MW1a and the first terminal of the transistor MW1b are connected to the bit line BLL (BLR).

The transistor MW1 has a function of controlling the charge and discharge of the capacitor CS1. The second terminal of the capacitor CS1 is electrically connected to the terminal B2. The terminal B2 is input with a constant voltage (for example, a low power supply voltage).

When the semiconductor device described in the above embodiment is used for the memory cells 1445a and 1445b, the transistor MW1a may be the transistor 200a, the transistor MW1b may be the transistor 200b, the capacitor CS1a may be the capacitor 100a, and the capacitor CS1b A capacitor 100b may be used. As a result, the area occupied by each of the groups including one transistor and one capacitor in a plan view can be reduced, and therefore, the memory device of the present embodiment can be made more compact. Therefore, the memory capacity per unit area of the memory device of the present embodiment can be increased.

Transistor MW1 includes a back gate, which is electrically connected to terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed according to the voltage of the terminal B1. For example, the voltage of the terminal B1 may be a fixed voltage (for example, a negative constant voltage), or the voltage of the terminal B1 may be changed according to the operation of the DOSRAM 1400.

In addition, the back gate of transistor MW1 may be electrically connected to the gate, source, or drain of transistor MW1. Alternatively, the back gate may not be provided in the transistor MW1.

The sense amplifier array 1423 includes N local sense amplifier arrays 1426 <0> to 1426 <N-1>. The local sense amplifier array 1426 includes a switch array 1444 and a plurality of sense amplifiers 1446. The bit line pair is electrically connected to a sense amplifier 1446. The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying a voltage difference of the bit line pair, and a function of maintaining the voltage difference. The switch array 1444 has a function of selecting a bit line pair, and turning a selected bit line pair into a conducting state with a global bit line pair.

Here, the bit line pair refers to two bit lines that are compared by the sense amplifier at the same time. A global bit line pair refers to two global bit lines that are simultaneously compared by a global sense amplifier. The bit line pairs can be referred to as a pair of bit lines, and the global bit line pairs can be referred to as a pair of global bit lines. Here, the bit line BLL and the bit line BLR constitute a group of bit line pairs. The global bit line GBLL and the global bit line GBLR form a group of global bit line pairs. The following are also referred to as bit line pairs (BLL, BLR) and global bit line pairs (GBLL, GBLR).

(Controller 1405) The controller 1405 has a function of controlling the entire operation of the DOSRAM 1400. The controller 1405 has a function of performing a logical operation on an instruction signal input from the outside and determining an operation mode; a function of generating control signals of the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed; and maintaining a bit input from the outside Address signal function; and the function of generating an internal address signal.

(Line circuit 1410) The line circuit 1410 has a function of driving the MC-SA array 1420. The decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal that selects the word line WL of the access target row.

The column selector 1413 and the sense amplifier driving circuit 1414 are circuits for driving the sense amplifier array 1423. The column selector 1413 has a function of generating a selection signal for selecting a bit line of an access target column. The switch array 1444 of each local sense amplifier array 1426 is controlled by the selection signal of the column selector 1413. By the control signal of the sense amplifier driving circuit 1414, the plurality of local sense amplifier arrays 1426 are independently driven.

(Column circuit 1415) The queue circuit 1415 has a function of controlling the input of the data signal WDA [31: 0] and a function of controlling the output of the data signal RDA [31: 0]. The data signal WDA [31: 0] is a write data signal, and the data signal RDA [31: 0] is a read data signal.

The global sense amplifier 1447 is electrically connected to the global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying a voltage difference between global bit line pairs (GBLL, GBLR) and a function of maintaining the voltage difference. Writing and reading of data to and from the global bit line pairs (GBLL, GBLR) are performed by the input-output circuit 1417.

The outline of the write operation of DOSRAM1400 will be described. Through the input-output circuit 1417, data is written to the global bit line pair. The data of the global bit line pair is held by the global sense amplifier array 1416. With the switch array 1444 of the local sense amplifier array 1426 designated by the address signal, the data of the global bit line pair is written to the bit line pair of the target column. The local sense amplifier array 1426 amplifies and holds the written data. In the designated local memory cell array 1425, the word circuit WL of the target row is selected by the row circuit 1410, and the holding data of the local sense amplifier array 1426 is written into the memory cell 1445 of the selected row.

The outline of the read operation of the DOSRAM 1400 will be described. One line of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL of the target row is selected, and the data of the memory cell 1445 is written to the bit line. The voltage difference between the bit line pairs of each column is detected and held by the local sense amplifier array 1426 as data. The data of the column specified by the address signal in the holding data of the local sense amplifier array 1426 is written to the global bit line pair by the switch array 1444. The global sense amplifier array 1416 detects and maintains data of global bit line pairs. The holding data of the global sense amplifier array 1416 is output to the input-output circuit 1417. Through the above steps, the reading operation is completed.

Since the data is rewritten by charging and discharging of the capacitor CS1, there is theoretically no limit to the number of rewrites of the DOSRAM 1400, and data can be written and read with low energy. In addition, the circuit structure of the memory unit 1445 is simple, and it is easy to increase the capacity.

Transistor MW1 is an OS transistor. Since the off-state current of the OS transistor is extremely small, the charge leakage of the capacitor CS1 can be suppressed. Therefore, the holding time of DOSRAM1400 is much longer than that of DRAM. As a result, the update frequency can be reduced, and the power consumption required for update work can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device that rewrites large-capacity data at a high frequency, such as a frame memory for image processing.

Since the MC-SA array 1420 is a stacked structure, the bit line length can be shortened to the same extent as the length of the local sense amplifier array 1426. By shortening the bit line, the bit line capacitance is reduced, thereby reducing the storage capacitance of the memory unit 1445. In addition, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load driven by DOSRAM 1400 can be reduced, and the power consumption can be reduced.

The structure described in this embodiment can be implemented in appropriate combination with the structures described in other embodiments.

Embodiment 7 In this embodiment, an FPGA (field programmable logic gate array) will be described using FIG. 40A to FIG. 43B as an example of a semiconductor device according to an embodiment of the present invention using an OS transistor and a capacitor. In the FPGA of this embodiment, the OS memory is used as a configuration memory and a register. Here, the above-mentioned FPGA is called "OS-FPGA".

<< OS-FPGA> FIG. 40A shows a configuration example of the OS-FPGA. The OS-FPGA3110 shown in FIG. 40A can implement a context switch using a multi-context structure and a NOFF (normally off) operation that is gated by the fine-grained power source of each PLE. The OS-FPGA 3110 includes a controller 3111, a word line driver 3112, a data driver 3113, and a programmable area 3115.

The programmable area 3115 includes two input-output blocks (IOBs) 3117 and a core 3119. IOB3117 includes multiple programmable input and output circuits. The core 3119 includes a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130. LAB3120 includes multiple PLE3121. FIG. 40B shows an example in which the LAB3120 is configured using five PLE3121s. As shown in FIG. 40C, the SAB 3130 includes a plurality of switch blocks (SB) 3131 arranged in an array. The LAB3120 is connected to the LAB3120 in four directions (up, down, left and right) through its input terminals and SAB3130.

The SB3131 will be described with reference to FIGS. 41A to 41C. The SB3131 shown in FIG. 41A is input with data, datab, signal context [1: 0], and signal word [1: 0]. data and datab are configuration data, and the logic of data and datab is in a complementary relationship. The context number of OS-FPGA3110 is 2, and the signal context [1: 0] is the context selection signal. The signal word [1: 0] is a word line selection signal, and the wiring of the input signal word [1: 0] is a word line.

The SB3131 includes PRS (programmable routing switches) 3133 [0] and 3133 [1]. PRS3133 [0] and 3133 [1] include configuration memory (CM) capable of storing complementary data. Note that in the case where PRS3133 [0] and PRS3133 [1] are not distinguished, it is denoted as PRS3133. The same applies to other components.

FIG. 41B shows a circuit configuration example of PRS3133 [0]. PRS3133 [0] and PRS3133 [1] have the same circuit structure. Between PRS3133 [0] and PRS3133 [1], the context selection signal and the word line selection signal that are input are different. The signals context [0] and word [0] are input to PRS3133 [0], and the signals context [1] and word [1] are input to PRS3133 [1]. For example, in SB3131, when the signal context [0] becomes "H", PRS3133 [0] becomes active.

PRS3133 [0] includes CM3135 and Si transistor M31. The Si transistor M31 is a pass transistor controlled by CM3135. The CM3135 includes memory circuits 3137 and 3137B. The memory circuits 3137 and 3137B have the same circuit structure. The memory circuit 3137 includes a capacitor C31, an OS transistor MO31, and MO32. The memory circuit 3137B includes a capacitor CB31, an OS transistor MOB31, and a MOB32.

When the semiconductor device described in the above embodiment is used for the SAB3130, the transistor 200 may be used as the OS transistor M031 and the OS transistor MOB31, and the capacitor 100 may be used as the capacitor C31 and the capacitor CB31. As a result, the occupation area in the plan view of each group consisting of one transistor and one capacitor can be reduced, so that the semiconductor device of this embodiment can be made more compact.

The OS transistors MO31, MO32, MOB31, and MOB32 include back gates, which are electrically connected to power lines respectively supplying a fixed voltage.

The gate of the Si transistor M31 is equivalent to the node N31, the gate of the OS transistor MO32 is equivalent to the node N32, and the gate of the OS transistor MOB32 is equivalent to the node NB32. Nodes N32 and NB32 are charge retention nodes of CM3135. The OS transistor MO32 controls the conduction state between the node N31 and the signal context [0] signal line. The OS transistor MOB32 controls the conduction state between the node N31 and the low-potential power supply line VSS.

The data held by the memory circuits 3137 and 3137B are in a complementary relationship. Therefore, any one of the OS transistors MO32 and MOB32 is turned on.

A working example of PRS3133 [0] will be described with reference to FIG. 41C. PRS3133 [0] has been written with configuration data. Node N32 of PRS3133 [0] is "H" and node NB32 is "L".

While the signal context [0] is "L", PRS3133 [0] is inactive. During this period, even if the input terminal of PRS3133 [0] transitions to "H", the gate of the Si transistor M31 maintains "L" and the output terminal of PRS3133 [0] also maintains "L".

While the signal context [0] is "H", PRS3133 [0] is active. When the signal context [0] is transferred to "H", the gate of the Si transistor M31 is transferred to "H" according to the configuration data stored in the CM3135.

While PRS3133 [0] is in the active state, when the potential of the input terminal shifts to "H", since the OS transistor MO32 of the memory circuit 3137 is a source follower, the The gate voltage rises. As a result, the OS transistor MO32 of the memory circuit 3137 loses the driving ability, and the gate of the Si transistor M31 becomes a floating state.

In the PRS3133 with a multi context function, the CM3135 is also used as a multiplexer.

FIG. 42 shows a configuration example of the PLE3121. PLE3121 includes a LUT (lookup table) block 3123, a register block 3124, a selector 3125, and a CM3126. The LUT block 3123 selects its internal data according to the inputs inA to inD and outputs it. The selector 3125 selects the output of the LUT block 3123 or the output of the register block 3124 according to the configuration data stored in the CM3126.

The PLE3121 is electrically connected to a power line for voltage VDD through a power switch 3127. The opening and closing of the power switch 3127 is determined according to the configuration data stored in the CM3128. By setting the power switch 3127 according to each PLE3121, fine-grain power supply gating can be performed. Due to the fine-grained power gating function, the PLE3121 that is not used after context switching can be power-gated, so it can effectively reduce standby power.

In order to realize the NOFF operation, the register block 3124 is constituted by a non-volatile register. The non-volatile register in PLE3121 is a flip-flop including an OS memory (hereinafter referred to as "OS-FF").

The register block 3124 includes OS-FF3140 [1] and 3140 [2]. The signals user_res, load, and store are input to OS-FF3140 [1] and 3140 [2]. The clock signal CLK1 is input to the OS-FF3140 [1], and the clock signal CLK2 is input to the OS-FF3140 [2]. FIG. 43A shows a configuration example of the OS-FF3140.

OS-FF3140 includes FF3141 and shadow register 3142. FF3141 includes nodes CK, R, D, Q, and QB. The node CK is input with a clock signal. The node R is input with a signal user_res. The signal user_res is a reset signal. Node D is a data input node, and node Q is a data output node. The logic of node Q and node QB are in a complementary relationship.

The shadow register 3142 is used as a backup circuit of the FF3141. The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and returns the backed up data to the nodes Q and QB according to the signal load.

The shadow register 3142 includes inverter circuits 3188 and 3189, Si transistors M37 and MB37, and memory circuits 3143 and 3143B. The memory circuits 3143 and 3143B have the same circuit structure as the memory circuit 3137 of the PRS 3133. The memory circuit 3143 includes a capacitor C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B includes a capacitor CB36, an OS transistor MOB35, and an OS transistor MOB36. The nodes N36 and NB36 correspond to the gates of the OS transistor MO36 and the OS transistor MOB36, respectively, and they are both charge holding nodes. The nodes N37 and NB37 correspond to the gates of the Si transistor M37 and the Si transistor MB37.

When the semiconductor device described in the above embodiment is used for the LAB 3120, the transistor 200 can be used as the OS transistor M035 and the OS transistor MOB35, and the capacitor 100 can be used as the capacitor C36 and the capacitor CB36. As a result, the occupation area in the plan view of each group consisting of one transistor and one capacitor can be reduced, so that the semiconductor device of this embodiment can be made more compact.

The OS transistors MO35, MO36, MOB35, and MOB36 include back gates, which are electrically connected to power lines respectively supplying a fixed voltage.

An example of the operating method of the OS-FF3140 will be described with reference to FIG. 43B.

(Backup) When the “H” signal store is input to OS-FF3140, the shadow register 3142 backs up the data of FF3141. The node N36 becomes "L" by the data input to the node Q, and the node NB36 becomes "H" by the data written in the node QB. Then, the power is gated, and the power switch 3127 is turned off. Although the data of the nodes Q and QB of the FF3141 are lost, the shadow register 3142 retains the backed up data even when the power supply is stopped.

(Restoration) Turn on the power switch 3127 to supply power to the PLE3121. Then, when the signal load of "H" is input to the OS-FF3140, the shadow register 3142 returns the backed-up data to the FF3141. Because node N36 is "L", node N37 remains "L", and because node NB36 is "H", node NB37 is "H". Therefore, the node Q becomes "H" and the node QB becomes "L". In other words, OS-FF3140 is restored to the state at the time of backup work.

By combining fine-grained power gating and OS-FF3140's backup / recovery, the power consumption of OS-FPGA3110 can be effectively reduced.

Examples of errors that may occur in a memory circuit include soft errors caused by radiation incident. Soft errors are phenomena such as irradiation of a-rays released from materials constituting memory or packaging, or secondary cosmic ray neutrons generated by a nuclear reaction between the primary cosmic ray incident into the atmosphere from the universe and the nucleus of an atom existing in the atmosphere. To the transistor to generate an electron hole pair, thereby causing a failure such as data reversal held in the memory. The OS memory using OS transistors has high soft error tolerance. Therefore, by installing the OS memory, it is possible to provide a highly reliable OS-FPGA3110.

The structure described in this embodiment can be implemented in appropriate combination with the structures described in other embodiments.

Embodiment 8 In this embodiment, an AI system using the semiconductor device described in the above embodiment will be described with reference to FIG. 44.

FIG. 44 is a block diagram showing a configuration example of the AI system 4041. The AI system 4041 includes a computing unit 4010, a control unit 4020, and an input / output unit 4030.

The arithmetic unit 4010 includes an analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014. As the DOSRAM 4012, NOSRAM 4013, and FPGA 4014, DOSRAM 1400, NOSRAM 1600, and OS-FPGA 3110 described in the above embodiment can be used.

The control unit 4020 includes a CPU (Central Processing Unit) 4021, a GPU (Graphics Processing Unit) 4022, a PLL (Phase Locked Loop) 4023, and a Static Random Access Memory (SRAM) (Access memory) 4024, PROM (Programmable Read Only Memory) 4025, memory controller 4026, power circuit 4027, and PMU (Power Management Unit) 4028.

The input / output section 4030 includes an external memory control circuit 4031, an audio codec 4032, a video codec 4033, a universal input / output module 4034, and a communication module 4035.

The computing unit 4010 can perform neural network learning or neural network inference.

The analog operation circuit 4011 includes an A / D (analog / digital) conversion circuit, a D / A (digital / analog) conversion circuit, and a product-sum operation circuit.

The analog operation circuit 4011 is preferably formed using an OS transistor. The analog operation circuit 4011 using an OS transistor has an analog memory and can perform products and calculations required for learning or inference with low power consumption.

DOSRAM 4012 is a DRAM formed using an OS transistor, and DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021. DOSRAM4012 includes a memory cell with an OS transistor and a readout circuit section with a Si transistor. Since the above-mentioned memory unit and readout circuit section can be provided on different layers to be stacked, the overall circuit area of the DOSRAM 4012 can be reduced.

In calculations using neural networks, the input data sometimes exceeds 1,000. When the input data is stored in the SRAM, the input area has to be stored little by little due to the limited circuit area of the SRAM and the small memory capacity. DOSRAM4012 allows highly integrated memory cells to be configured even in a limited circuit area, and has a larger memory capacity than SRAM. Therefore, DOSRAM4012 can efficiently store the above input data.

NOSRAM4013 is a non-volatile memory using OS transistors. Compared with other non-volatile memories such as flash memory, Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), and other non-volatile memories, NOSRAM4013 writes The power consumption during data is small. In addition, NOSRAM4013 does not suffer from component degradation when writing data like flash memory or ReRAM, and there is no limit on the number of data writes.

In addition, NOSRAM4013 can store not only binary data of 1 bit, but also multi-value data of 2 bits or more. NOSRAM4013 can reduce the memory cell area per bit by storing multi-valued data.

In addition, NOSRAM4013 can store analog data in addition to digital data. Therefore, the analog operation circuit 4011 can use the NOSRAM 4013 as an analog memory. Since NOSRAM4013 can be stored by analogy, no D / A conversion circuit or A / D conversion circuit is needed. Therefore, the area of the peripheral circuit for NOSRAM 4013 can be reduced. The analog data in this specification refers to data having a resolution of 3 bits (8 values) or more. The above multi-valued data can also be included in the analog data.

The data and parameters used in the calculation of the neural network can be temporarily stored in NOSRAM4013. Although the above-mentioned data and parameters can also be stored in the memory set outside the AI system 4041 by the CPU 4021, the NOSRAM 4013 stored in the inside can store the above-mentioned data and parameters at higher speed and lower power consumption. In addition, NOSRAM 4013 can make the bit line longer than the bit line of DOSRAM 4012, which can increase the memory capacity.

FPGA4014 is an FPGA using an OS transistor. The AI system 4041 can use hardware FPGA 4014 to form a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, and a deep Boltzmann machine ( DBM), Deep Belief Network (DBN) and other neural networks. The above-mentioned neural network connection can be executed at a higher speed by hardware.

FPGA4014 is an FPGA including an OS transistor. The memory area of OS-FPGA can be smaller than FPGA made of SRAM. Therefore, even if a context switching function is added thereto, the increase in area is small. In addition, OS-FPGA can boost data and parameters at high speed by boosting.

The AI system 4041 can set the analog operation circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014 on a bare chip (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and low power consumption. In addition, the analog operation circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014 can be manufactured by the same process. Therefore, the AI system 4041 can be manufactured at a low cost.

Note that it is not necessary for the arithmetic unit 4010 to have all of DOSRAM 4012, NOSRAM 4013, and FPGA 4014. Select one or more of DOSRAM 4012, NOSRAM 4013, and FPGA 4014 according to the problem that AI system 4041 wants to solve.

The AI system 4041 can execute deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Bozman machines (DBM), Deep Belief Network (DBN) and other methods. The PROM4025 can store programs for performing at least one of the above methods. In addition, some or all of the above programs can be stored in NOSRAM4013.

Most of the existing programs that are stored in the program library are designed on the premise of processing by the GPU. For this reason, it is preferable that the AI system 4041 has a GPU 4022. The AI system 4041 can use the arithmetic unit 4010 to perform the time-consuming product and operation of the product and operation used for learning and inference, and use the GPU 4022 to perform the remaining product and operation. This enables high-speed learning and inference.

The power supply circuit 4027 generates not only a low power supply potential for a logic circuit but also an analog calculation potential. The power supply circuit 4027 may use an OS memory. The power consumption of the power circuit 4027 can be reduced by storing the reference potential in the OS memory.

The PMU4028 has a function of temporarily stopping the power supply of the AI system 4041.

The CPU 4021 and the GPU 4022 preferably include an OS memory as a register. When the CPU 4021 and the GPU 4022 include the OS memory, the data (logic value) can be maintained in the OS memory even if the power supply is stopped. As a result, the AI system 4041 can save power.

PLL4023 has a function of generating a clock. The AI system 4041 works based on the clock generated by the PLL 4023. The PLL 4023 preferably has an OS memory. By including the PLL 4023 with the OS memory, it is possible to use it to maintain an analog potential that controls the oscillation frequency of the clock.

The AI system 4041 can use external memory such as DRAM to store data. For this reason, the AI system 4041 is preferably a memory controller 4026 having an interface to be used with an external DRAM. In addition, the memory controller 4026 is preferably disposed near the CPU 4021 or the GPU 4022. As a result, data communication can be performed at high speed.

A part or all of the circuit shown in the control unit 4020 may be formed on the same die as the operation unit 4010. As a result, the AI system 4041 can perform calculations of the neural network at high speed and low power consumption.

The data used for the calculation of the neural network are mostly stored in external memory devices (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). For this reason, the AI system 4041 preferably has an external memory control circuit 4031 having an interface used as an interface with an external memory device.

Learning and inference using neural networks mostly use sound or video. The AI system 4041 includes an audio codec 4032 and a video codec 4033. The audio codec 4032 performs encoding processing (symbolization) and decoding (multiple number) of sound data, and the video codec 4033 performs encoding processing and decoding of video data.

The AI system 4041 can use data obtained from external sensors for learning or inference. To this end, the AI system 4041 includes a universal input-output module 4034. The universal input / output module 4034 includes, for example, a USB (Universal Serial Bus) or an I2C (Inter-Integrated Circuit).

The AI system 4041 can use data obtained through the Internet for learning or inference. For this reason, the AI system 4041 preferably includes a communication module 4035.

The analog operation circuit 4011 can use a multi-valued flash memory as the analog memory. However, flash memory may be rewritten a limited number of times. In addition, it is difficult to form a multi-value flash memory in an embedded manner (that is, it is difficult to form an arithmetic circuit and a memory on the same die).

In addition, the analog operation circuit 4011 can use ReRAM as an analog memory. However, ReRAM may be rewritten a limited number of times, and there are also problems in storage accuracy. In addition, since it is a two-terminal device, the circuit design for writing and reading data is complicated.

In addition, the analog operation circuit 4011 can use MRAM as an analog memory. However, MRAM has a low rate of change in resistance and has problems in storage accuracy.

For the reasons described above, the analog operation circuit 4011 preferably uses the OS memory as the analog memory.

The structure described in this embodiment can be used in appropriate combination with the structures described in other embodiments.

Embodiment 9 <Application example of AI system> In this embodiment, an application example of the AI system shown in the above embodiment will be described with reference to FIGS. 45A and 45B.

FIG. 45A is an AI system 4041A in which the AI system 4041 described in FIG. 44 is arranged in parallel to transmit and receive signals between the systems through a bus.

The AI system 4041A shown in FIG. 45A includes a plurality of AI systems 4041_1 to AI systems 4041_n (n is a natural number). The AI systems 4041_1 to 4041_n are connected to each other through a bus bar 4098.

FIG. 45B is an AI system 4041B in which the AI system 4041 described in FIG. 44 is arranged in parallel with FIG. 45A in order to transmit and receive signals between systems via a network.

The AI system 4041B shown in FIG. 45B includes a plurality of AI systems 4041_1 to 4041_n. The AI systems 4041_1 to 4041_n are connected to each other via a network 4099.

The network 4099 may adopt a structure in which a communication module is set in the AI system 4041_1 to the AI system 4041_n to perform wireless or wired communication. The communication module can communicate through an antenna. For example, each electronic device and the World Wide Web (WWW: World Wide Web) based Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network: campus network), MAN (Metropolitan Area Network: Metropolitan Area Network), WAN (Wide Area Network: Wide Area Network), GAN (Global Area Network: Global Network) and other computer network connections for communication. When performing wireless communication, it can be used as a communication protocol or communication technology: communication standards such as LTE (Long Term Evolution: Long Term Evolution), GSM (Global System for Mobile Communication) (registered trademark), EDGE (Enhanced Data Rates for GSM Evolution: CDMA2000 (Code Division Multiple Access 2000), W-CDMA (registered trademark); or specifications standardized by IEEE (Institute of Electrical and Electronics Engineers) communications such as Wi -Fi (registered trademark), Bluetooth (registered trademark), ZigBee (registered trademark), etc.

By adopting the structures of FIGS. 45A and 45B, analog signals obtained from external sensors and the like can be processed by different AI systems. For example, various sensors such as brain wave sensors, pulse wave sensors, blood pressure sensors, and temperature sensors can be used to obtain biological information such as brain waves, pulse, blood pressure, and body temperature and use different AI systems to process analogies. signal. By using different AI systems to perform signal processing or learning separately, the amount of information processing of each AI system can be reduced. Therefore, it is possible to perform signal processing or learning with a small amount of calculation. Thereby, recognition accuracy can be improved. With the information obtained by different AI systems, it can be expected that changes in biological information that are irregularly changed can be grasped immediately.

The structure described in this embodiment can be used in appropriate combination with the structures described in other embodiments.

Embodiment 10 This embodiment shows an example of an IC on which the AI system described in the above embodiment is mounted.

The AI system described in the above embodiment can integrate a digital processing circuit composed of a Si transistor such as a CPU, an analog operation circuit using an OS transistor, OS-FPGA, and OS memory such as DOSRAM, NOSRAM, etc. on a single bare chip.

FIG. 46 shows an example of an IC on which an AI system is mounted. The AI system IC7000 shown in FIG. 46 includes a lead 7001 and a circuit portion 7003. The AI system IC7000 is mounted on a printed circuit board 7002, for example. By combining a plurality of such IC chips and electrically connecting them to each other on the printed circuit board 7002, a substrate on which electronic components are mounted (mounting substrate 7004) is completed. In the circuit portion 7003, the various circuits described in the above embodiments are provided on a single die. As shown in the above embodiment, the circuit portion 7003 has a laminated structure, and is roughly divided into a Si transistor layer 7031, a wiring layer 7032, and an OS transistor layer 7033. Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the miniaturization of the AI system IC7000 can be easily achieved.

Although the QFP (Quad Flat Package) is used as the package of the AI system IC7000 in FIG. 46, the packaging method is not limited to this.

Digital processing circuits such as a CPU, analog operation circuits using OS transistors, OS memories such as OS-FPGA, DOSRAM, and NOSRAM can be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. In other words, the components constituting the above-mentioned AI system can be formed using the same process. Therefore, the IC described in this embodiment does not need to increase the number of processes even if the number of constituent elements is increased, so that the above-mentioned AI system can be installed at a low cost.

The structure described in this embodiment can be used in appropriate combination with the structures described in other embodiments.

Embodiment 11 <Electronic device> The semiconductor device according to an embodiment of the present invention can be used for various electronic devices. 47A to 49 show specific examples of electronic devices using the semiconductor device according to an embodiment of the present invention.

The robot 2100 shown in FIG. 47A includes a computing device 2110, an illuminance sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, a lower camera 2106, an obstacle sensor 2107, and a moving mechanism 2108.

The microphone 2102 has a function of detecting a user's voice, a surrounding voice, and the like. The speaker 2104 has a function of emitting sound. The robot 2100 can communicate with the user using the microphone 2102 and the speaker 2104.

The display 2105 has a function of displaying various information. The robot 2100 can display information desired by the user on the display 2105. The display 2105 may be mounted with a touch panel.

The upper camera 2103 and the lower camera 2106 have a function of imaging the surroundings of the robot 2100. In addition, the obstacle sensor 2107 can detect the presence or absence of an obstacle ahead when the robot 2100 moves using the moving mechanism 2108. The robot 2100 can use the upper camera 2103, the lower camera 2106, and the obstacle sensor 2107 to recognize the surrounding environment and move safely.

The flying object 2120 shown in FIG. 47B includes a computing device 2121, a propeller 2123, and a camera 2122, and has an autonomous flying function.

In the flying object 2120, the above-mentioned electronic components can be used for the computing device 2121 and the camera 2122.

FIG. 47C is an external view showing an example of a car. The car 2980 includes a camera 2981 and the like. In addition, the automobile 2980 includes various sensors such as an infrared radar, a millimeter wave radar, and a laser radar. The car 2980 analyzes the image captured by the camera 2981 to determine the presence or absence of pedestrians and other traffic conditions, thereby enabling automatic driving.

FIG. 47D illustrates a case where the portable electronic device 2130 is used for simultaneous interpretation when communicating between a plurality of people speaking in languages different from each other.

The portable electronic device 2130 includes a microphone, a speaker, and the like, and has a function of recognizing a user's voice and translating it into the language of the other party.

In addition, in FIG. 47D, the user wears a portable microphone 2131. The portable microphone 2131 has a wireless communication function, and can send the detected sound to the portable electronic device 2130.

FIG. 48A is a schematic cross-sectional view showing an example of a pacemaker.

The pacemaker body 5300 includes at least batteries 5301a, 5301b, a regulator, a control circuit, an antenna 5304, a lead 5302 reaching the right atrium, and a lead 5303 reaching the right ventricle.

The pacemaker body 5300 is surgically implanted into the body. Two leads pass through the subclavian vein 5305 and superior vena cava 5306 of the human body. The top of one lead reaches the right ventricle and the top of the other lead reaches the right atrium.

In addition, the antenna 5304 can be used to receive power, and the power is charged to the batteries 5301a and 5301b, which can reduce the frequency of pacemaker replacement. Since the pacemaker body 5300 includes a plurality of batteries, safety is improved. Even if one battery fails, the other battery will work. As such, these batteries can be used as auxiliary power sources.

In addition to an antenna 5304 capable of receiving power, an antenna capable of transmitting physiological signals may be included. For example, a system for monitoring cardiac activity that can confirm physiological signals such as pulse, breathing rate, heart rate, and body temperature can be configured on an external monitor device. .

The sensor 5900 shown in FIG. 48B is attached to the human body using an adhesive pad or the like. The sensor 5900 supplies signals to electrodes 5931 and the like mounted on the human body by wiring 5932 to obtain biological information such as heart rate and electrocardiogram. The obtained information is transmitted to a terminal such as a reader as a wireless signal.

FIG. 49 is a schematic diagram showing an example of a cleaning robot.

The cleaning robot 5100 includes a display 5101 on the top surface and a plurality of cameras 5102, brushes 5103, and operation buttons 5104 on the side. Although not shown, the bottom surface of the cleaning robot 5100 is provided with a tire, a suction port, and the like. In addition, the cleaning robot 5100 also includes various sensors such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezoelectric sensor, a light sensor, and a gyroscope sensor. In addition, the cleaning robot 5100 includes a wireless communication unit.

The sweeping robot 5100 can automatically walk and detect garbage 5120, and can attract garbage from the suction port on the bottom surface.

In addition, the cleaning robot 5100 analyzes the images captured by the camera 5102, and can determine the presence of obstacles such as walls, furniture, or steps. In addition, when an object that may be wound around the brush 5103 is detected by image analysis, the rotation of the brush 5103 can be stopped.

The remaining power of the battery, the amount of garbage attracted, and the like can be displayed on the display 5101. In addition, the walking path of the cleaning robot 5100 may be displayed on the display 5101. In addition, the display 5101 may be a touch panel, and the operation buttons 5104 may be displayed on the display 5101.

The cleaning robot 5100 can communicate with a portable electronic device 5140 such as a smart phone. The image captured by the camera 5102 can be displayed on the portable electronic device 5140. Therefore, the owner of the cleaning robot 5100 can know the condition of the room when going out. In addition, the portable electronic device 5140 such as a smartphone can be used to check the display content of the display 5101.

For example, a memory device using a semiconductor device according to an embodiment of the present invention can hold the control data or control program of the electronic device for a long period of time. By using the semiconductor device according to an embodiment of the present invention, a highly reliable electronic device can be realized.

In addition, for example, an IC on which the AI system is mounted may be used for a computing device of the electronic device and the like. As a result, the electronic device described in this embodiment can use the AI system to perform appropriate work suitable for the situation with low power consumption.

This embodiment can be implemented in appropriate combination with the structures shown in other embodiments or examples. Examples

In this embodiment, the interface between the oxide and the metal or metal compound provided thereon is evaluated. In the evaluation, two samples were used: Sample 1 in which a metal or a metal compound was formed on an oxide; and Sample 2 in which a metal or a metal compound was formed on an oxide and heat-treated in a nitrogen atmosphere was the same as Sample 1.

The manufacturing method of the sample 1 is demonstrated. As an oxide, an oxide was formed on a substrate by a sputtering method using a target material of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]. Next, the formed oxide was subjected to a heat treatment at a temperature of 400 ° C. under a nitrogen atmosphere for 1 hour, and a heat treatment was performed continuously at a temperature of 400 ° C. under an oxygen atmosphere for 1 hour. After the heat treatment, a target material of Ti: Al = 1: 1 [atomic number ratio] was formed on the oxide using a sputtering method as a metal compound to form a 20 nm-thick metal compound in an atmosphere containing nitrogen. The obtained metal compound contains titanium, aluminum, and nitrogen, and can be expressed as TiAlN or TiAlNx.

Next, the manufacturing method of the sample 2 is demonstrated. As an oxide, an oxide was formed on a substrate by a sputtering method using a target material of In: Ga: Zn = 4: 2: 4.1 [atomic number ratio]. Next, the formed oxide was subjected to a heat treatment at a temperature of 400 ° C. under a nitrogen atmosphere for 1 hour, and a heat treatment was performed continuously at a temperature of 400 ° C. under an oxygen atmosphere for 1 hour. After the heat treatment, a target material of Ti: Al = 1: 1 [atomic number ratio] was formed on the oxide using a sputtering method as a metal compound to form a 20 nm-thick metal compound in an atmosphere containing nitrogen. The obtained metal compound contains titanium, aluminum, and nitrogen, and can be expressed as TiAlN or TiAlNx. After the metal compound is formed, a heat treatment is performed at a temperature of 400 ° C. for 1 hour under a nitrogen atmosphere.

The cross sections of the interfaces between the oxide and the metal compound in Samples 1 and 2 were observed. The cross-sectional observation was performed with a scanning transmission electron microscope (STEM). As the observation device, HD-2700 manufactured by Hitachi High-Technologies Corporation was used. FIG. 50A shows a cross-sectional STEM observation result of the sample 1. FIG. FIG. 50B shows a cross-sectional STEM observation result of the sample 2.

As can be seen from a comparison between FIG. 50A and FIG. 50B, a layer is formed between the oxide and the metal compound in FIG. 50B. This layer is considered to be a layer formed by a heat treatment after the metal compound is formed.

Next, the sheet resistance of the oxide is measured. As the sheet resistance measuring device, a measuring device having an upper measurement limit of 6 × 10 ⁶ W / square was used. For the measurement of the sheet resistance, Sample 3 (that is, a sample in which oxides are formed and heat-treated in the same manner as Samples 1 and 2) and Sample 4 (that is, formed in the same manner as in Sample 2) Metal compound and heat-treated, and then the metal compound was removed to expose the layer).

The measurement result of the sheet resistance of the sample 3 exceeded the upper limit of measurement, and the sheet resistance of the oxide was 6 × 10 ⁶ W / square or more. On the other hand, the sheet resistance of Sample 4 was 402 W / square. From this, it can be seen that by forming a metal compound on the oxide and performing heat treatment, a low-resistance region is formed at least on the surface of the oxide (see FIG. 51).

[Comparative Example] Also, as a technique for reducing the resistance of an oxide, a method of forming silicon nitride containing hydrogen in contact with the oxide is known. An oxide was formed in the same manner as in samples 1 and 2, and silicon nitride was formed on the oxide by a plasma CVD method, and then silicon nitride was removed. Sample 5 was then prepared, and the sheet resistance of the oxide was measured. The chip resistance value of Sample 5 is 833 W / square. From this, it can be seen that by forming silicon nitride in contact with the oxide, the sheet resistance value of the oxide can also be reduced. On the other hand, the resistance of the sample 4 shown in this embodiment is lower than that of the sample 5 (see FIG. 51).

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments or examples.

100‧‧‧Capacitor

100a‧‧‧capacitor

100b‧‧‧capacitor

110‧‧‧Conductor

112‧‧‧Conductor

120‧‧‧Conductor

130‧‧‧ insulator

150‧‧‧ insulator

200‧‧‧ Transistor

200a‧‧‧ Transistor

200b‧‧‧Transistor

203‧‧‧Conductor

205‧‧‧Conductor

207‧‧‧Conductor

210‧‧‧ insulator

212‧‧‧ insulator

214‧‧‧ insulator

216‧‧‧ insulator

218‧‧‧Conductor

220‧‧‧ insulator

222‧‧‧ insulator

224‧‧‧ insulator

224A‧‧‧Insulation film

230‧‧‧oxide

230a‧‧‧oxide

230A‧‧‧oxide film

230b‧‧‧oxide

230B‧‧‧ oxide film

230c‧‧‧oxide

230C‧‧‧oxide film

231‧‧‧area

231a‧‧‧area

231b‧‧‧area

232‧‧‧area

232a‧‧‧area

232b‧‧‧area

234‧‧‧area

239‧‧‧area

240‧‧‧conductor

240a‧‧‧Conductor

240b‧‧‧conductor

240c‧‧‧Conductor

242A‧‧‧ film

246‧‧‧Conductor

248‧‧‧Conductor

250‧‧‧ insulator

250A‧‧‧Insulation film

252‧‧‧ metal oxide

252A‧‧‧metal oxide film

260‧‧‧Conductor

260a‧‧‧Conductor

260A‧‧‧Conductive film

260b‧‧‧conductor

260B‧‧‧Conductive film

270‧‧‧ insulator

270A‧‧‧Insulation film

271‧‧‧ insulator

271A‧‧‧Insulation film

272‧‧‧ insulator

272A‧‧‧Insulation film

273‧‧‧ insulator

274‧‧‧ insulator

275‧‧‧ insulator

275A‧‧‧Insulation film

277‧‧‧area

280‧‧‧ insulator

282‧‧‧ insulator

286‧‧‧ insulator

300‧‧‧ Transistor

311‧‧‧ substrate

313‧‧‧Semiconductor area

314a‧‧‧Low resistance area

314b‧‧‧Low resistance area

315‧‧‧ insulator

316‧‧‧conductor

320‧‧‧ insulator

322‧‧‧ insulator

324‧‧‧ insulator

326‧‧‧ insulator

328‧‧‧conductor

330‧‧‧Conductor

350‧‧‧ insulator

352‧‧‧ insulator

354‧‧‧ insulator

356‧‧‧Conductor

360‧‧‧ insulator

362‧‧‧ insulator

364‧‧‧ insulator

366‧‧‧Conductor

370‧‧‧ insulator

372‧‧‧ insulator

374‧‧‧ insulator

376‧‧‧conductor

380‧‧‧ insulator

382‧‧‧ insulator

384‧‧‧ insulator

386‧‧‧conductor

400‧‧‧ Transistor

403‧‧‧conductor

405‧‧‧Conductor

430c‧‧‧oxide

431a‧‧‧oxide

431b‧‧‧oxide

432a‧‧‧oxide

432b‧‧‧oxide

450‧‧‧ insulator

452‧‧‧ metal oxide

460‧‧‧Conductor

460a‧‧‧Conductor

460b‧‧‧conductor

470‧‧‧ insulator

472‧‧‧ insulator

475‧‧‧ insulator

600‧‧‧Unit

600a‧‧‧Unit

600b‧‧‧unit

610‧‧‧circuit

620‧‧‧circuit

650a‧‧‧memory unit

650b‧‧‧memory unit

1001‧‧‧Wiring

1002‧‧‧Wiring

1003‧‧‧Wiring

1004‧‧‧Wiring

1005‧‧‧Wiring

1006‧‧‧Wiring

1007‧‧‧Wiring

1008‧‧‧Wiring

1009‧‧‧Wiring

1010‧‧‧Wiring

In the drawings: FIGS. 1A to 1D are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention; FIGS. 2A and 2B are cross-sectional views of a semiconductor device according to an embodiment of the present invention; FIGS. 3A to 3D 4A to 4D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; and FIGS. 5A to 5D 5D is a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention; FIGS. 6A to 6D are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention; 7A to 7D are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention; and FIGS. 8A to 8D are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention; 9A to 9D are a plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention; 10A to 10D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; FIGS. 11A to 11D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; 12A to 12D are a plan view and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention; FIGS. 13A to 13D are plan views and a plan view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention; 14A to 14D are a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; and FIGS. 15A to 15D are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention; Fig. 16 is a schematic diagram illustrating the division of regions in the InGaZnO ₄ crystal; Figs. 17A to 17D are diagrams illustrating the movement path of hydrogen atoms in the region between the InO ₂ plane and the (Ga, Zn) O plane and the activation energy barrier on the path FIG. 18A and FIG. 18B are diagrams illustrating a moving path of a hydrogen atom in the (Ga, Zn) O region and an activation energy barrier on the path; FIGS. 19A and 19B DESCRIPTION OF FIG activation barrier on the path of movement of the hydrogen atoms InO ₂ and the path region; FIG. 20A and FIG. 20B is the activation energy barrier on the path along the c-axis direction is a hydrogen atom and the path specification; 21 is a diagram illustrating a calculation model; FIG. 22 is a diagram illustrating a relative value of total energy of an oxygen vacancy model; FIGS. 23A and 23B are diagrams illustrating a model of an initial state and a model of a final state; FIG. 24 is a diagram illustrating activation energy 25A to 25C are a plan view and a cross-sectional view of a semiconductor device according to an embodiment of the present invention; FIGS. 26A and 26B are a circuit diagram and a cross-sectional view of a semiconductor device according to an embodiment of the present invention; FIG. 27A and FIG. 27B is a circuit diagram and a cross-sectional view of a semiconductor device according to an embodiment of the present invention; FIG. 28 is a cross-sectional view showing the structure of a memory device according to an embodiment of the present invention; A cross-sectional view of the structure of a memory device; FIG. 30 is a cross-sectional view showing the structure of a memory device according to an embodiment of the present invention; 32A and 32B are circuit diagrams and cross-sectional views of a memory device according to an embodiment of the present invention; and FIG. 33 is a memory device showing an embodiment of the present invention. 34 is a cross-sectional view showing a structure of a memory device according to an embodiment of the present invention; FIG. 35 is a block diagram showing a structure example of a memory device according to an embodiment of the present invention; 36A to 36E are circuit diagrams showing a configuration example of a memory device according to an embodiment of the present invention; FIG. 37 is a circuit diagram showing a configuration example of a memory device according to an embodiment of the present invention; FIG. 39A and FIG. 39B are block diagrams and circuit diagrams showing a configuration example of a memory device according to an embodiment of the present invention; FIGS. 40A to 40C are views showing A block diagram showing a structural example of a semiconductor device according to an embodiment of the present invention; FIGS. 41A and 41B are diagrams showing an embodiment of the present invention A block diagram and a circuit diagram of a structural example of a semiconductor device. FIG. 41C is a timing chart showing a working example of the semiconductor device. FIG. 42 is a block diagram showing a structural example of a semiconductor device according to an embodiment of the present invention. FIG. 43A FIG. 43B is a circuit diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention, and FIG. 43B is a timing chart illustrating an operation example of the semiconductor device; FIG. 44 is a configuration example illustrating an AI system according to an embodiment of the present invention. Block diagrams; FIGS. 45A and 45B are block diagrams illustrating an application example of an AI system according to an embodiment of the present invention; FIG. 46 is a schematic perspective view showing a configuration example of an IC in which an AI system according to an embodiment of the present invention is installed 47A to 47D are diagrams illustrating an electronic device according to an embodiment of the present invention, and FIGS. 48A and 48B are diagrams illustrating an electronic device according to an embodiment of the present invention; FIG. 49 is a diagram illustrating an electronic device according to an embodiment of the present invention; FIG. 50A and FIG. 50B are STEM images of a cross section of a sample of an example; FIG. 51 is a diagram illustrating a sample of an example Graph of sheet resistance.

Claims (13)

A semiconductor device includes: a transistor including: an oxide having a first region, a second region, and a third region therebetween; a first insulator on the first region; a conductor on the first insulator; and The second insulator in contact with the side of the first insulator and the side of the conductor, wherein: the first region is used as a channel forming region of the transistor, the third region partially overlaps the second insulator, the The two regions have a lower oxygen concentration than the first region and the third region, and the third region includes a region having an oxygen concentration between the first region and the second region. The semiconductor device according to claim 1, wherein the transistor further includes a first film in contact with the second region and on the oxide. The semiconductor device according to claim 1 or 2, wherein the oxide contains In, elements M, and Zn (M is Al, Ga, Y, or Sn). According to the semiconductor device of claim 3, the atomic ratio of In is higher than the atomic ratio of M. The semiconductor device according to claim 1 or 2, wherein the second region includes at least one of Al, Ru, Ti, Ta, Cr, and W and nitrogen. According to the semiconductor device of claim 1 or 2, the hydrogen concentration in the first region is lower than that in the second region and the third region. The semiconductor device according to claim 1 or claim 2, wherein the transistor is a normally-off transistor. The semiconductor device according to claim 2, wherein the first film is partially mixed with the second region. The semiconductor device according to item 2 of the application, wherein the first film includes at least one of Al, Ru, Ti, Ta, Cr, and W and nitrogen. According to the semiconductor device of claim 2, the thickness of the first film is 0.5 nm or more and less than 5 nm. A method for manufacturing a semiconductor device includes: forming a transistor including: 包括 an oxide having a first region, a second region, and a third region therebetween; a first insulator on the oxide; 氧化物 on the first insulator And a second insulator in contact with the side surface of the first insulator and the side of the conductor; covering the oxide, the first insulator, the conductor, and the second insulator and contacting the second region Forming a first film containing metal; and performing a first heat treatment on the oxide and the first film under an atmosphere containing nitrogen to extract oxygen in the second region to the first film, wherein, the first A region is used as a channel forming region of the transistor. The method according to claim 11, wherein the first film is formed by using a sputtering method using at least one of an argon gas and a nitrogen gas. The method according to item 11 of the patent application scope, further comprising: removing the first film after the first heat treatment; performing a second heat treatment; and forming at least the oxide, the first insulator, the conductor, and the second The second film of the insulator.