JP7237822B2 - semiconductor equipment - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one aspect of the present invention relates to semiconductor wafers, modules, and electronic devices.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices. A display device (such as a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like can be said to include a semiconductor device in some cases.

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter.

In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. A CPU is an aggregate of semiconductor elements having semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and having electrodes as connection terminals formed thereon.

2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.

Also, a technique for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

Further, it is known that a transistor including an oxide semiconductor has extremely low leakage current in a non-conducting state. For example, a low-power-consumption CPU and the like that utilize the low leakage current characteristic of a transistor including an oxide semiconductor have been disclosed (see Patent Document 1).

As a transistor including an oxide semiconductor, a self-aligned transistor has been proposed. As the self-aligned transistor, a metal film is formed over the source region and the drain region, and heat treatment is performed on the metal film to increase the resistance of the metal film and reduce the resistance of the source region and the drain region. A method for making it possible is disclosed (see Patent Document 2).

Further, as a method for manufacturing a transistor using an oxide semiconductor, a metal film is formed over a source region and a drain region, heat treatment is performed, and then a dopant is introduced through the metal film. A method for reducing the resistance of the drain region is disclosed (see Patent Document 3).

In recent years, as electronic devices have become smaller and lighter, there has been an increasing demand for integrated circuits in which transistors and the like are densely integrated. In addition, there is a demand for improvement in productivity of semiconductor devices including integrated circuits.

JP 2012-257187 A JP 2011-228622 A JP 2013-016782 A

In Patent Document 2, when the resistance of the source region and the drain region is reduced, a metal film is formed on the source region and the drain region, and the metal film is heat-treated in an oxygen atmosphere. By performing the heat treatment, a constituent element of the metal film enters as a dopant into the source region and the drain region of the oxide semiconductor film, thereby reducing the resistance. Further, the heat treatment is performed in an oxygen atmosphere to oxidize the conductive film and increase the resistance of the conductive film. However, since the heat treatment is performed in an oxygen atmosphere, the effect of extracting oxygen from the oxide semiconductor film by the metal film is low.

Moreover, although Patent Document 2 describes the oxygen concentration in the channel forming region, it does not mention the concentration of impurities such as water and hydrogen. That is, since the channel formation region is not highly purified (reduction of impurities such as water and hydrogen, typically dehydration and dehydrogenation), there is a problem that normally-on transistor characteristics tend to occur. . Note that a normally-on transistor characteristic is a state in which a channel exists and a current flows through the transistor even if a potential is not applied to the gate. On the other hand, the normally-off transistor characteristic is a state in which current does not flow in the transistor when no potential is applied to the gate.

In view of the above problem, one embodiment of the present invention provides a semiconductor device having favorable electrical characteristics by stably reducing the resistance of a source region and a drain region of a transistor and highly purifying a channel formation region. One of the tasks is to

Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time. An object of one embodiment of the present invention is to provide a semiconductor device in which data can be written at high speed. An object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in design. An object of one embodiment of the present invention is to provide a semiconductor device that can consume less power. An object of one embodiment of the present invention is to provide a novel semiconductor device.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the descriptions of the specification, drawings, claims, etc. is.

One embodiment of the present invention is a semiconductor device including a transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, and the first insulator. and a second insulator disposed on the side surface of the conductor, and a layer having an oxide, the second insulator, and metal atoms disposed on the conductor, wherein the oxide is the second insulator. a first region, a second region, and a third region located between the first region and the second region, the first region overlapping the first insulator; The second region overlaps with the layer having metal atoms and has a metal compound, the third region has a region that overlaps with the second insulator, and the second region overlaps the first and the third region, and the third region has a portion with an oxygen concentration between the oxygen concentration of the first region and the oxygen concentration of the second region. be.

One embodiment of the present invention is a semiconductor device including a transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, and a first insulator. and a second insulator disposed on the side of the conductor, wherein the oxide comprises a first region, a second region, and the first region and the second region; a third region located therebetween, the first region overlapping the first insulator, the second region comprising a metal compound, the third region overlapping the second insulator; The second region has a lower oxygen concentration than the first region and the third region, and the third region has the oxygen concentration of the first region and the second region. The semiconductor device has a portion having an oxygen concentration between that of the region.

One embodiment of the present invention is a semiconductor device including a transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, and a first insulator. a second insulator arranged on a side surface of the insulator and a side surface of the conductor; a layer containing metal atoms arranged over the oxide, the second insulator, and the conductor; a third insulator disposed on the third insulator; and a fourth insulator disposed on the third insulator, the fourth insulator having less carbon than the second insulator; The insulator has an excess oxygen region, and the oxide has a first region, a second region, and a third region located between the first and second regions. the first region overlaps the first insulator, the second region overlaps the layer having metal atoms and has a metal compound, and the third region overlaps the second insulator The second region has a lower resistance than the first region and the third region, and the first region has a higher resistance than the third region.

One embodiment of the present invention is a semiconductor device including a transistor including an oxide, a first insulator over the oxide, a conductor over the first insulator, and a first insulator. a second insulator disposed on a side surface of the insulator and a side surface of the conductor; a third insulator disposed on the oxide, the second insulator, and the conductor; and a disposed fourth insulator, the fourth insulator having less carbon than the second insulator, the third insulator having excess oxygen regions, and the oxide comprising: a first region, a second region, and a third region located between the first region and the second region, the first region overlapping the first insulator; , the second region has a metal compound, the third region has a region overlapping the second insulator, the second region lower than the first region and the third region resistance, and the first region has a higher resistance than the third region.

In the above, the oxide includes In, element M (M is Al, Ga, Y, or Sn), and Zn.

In the above, the oxide has a larger In value than the element M in atomic number ratio.

In the above, the metal compound contains at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

Also, in the above, the second region contains nitrogen.

Further, in the above, the first region has a lower hydrogen concentration than the second region.

Further, in the above, the first region has a lower hydrogen concentration than the second region and the third region.

Further, in the above, the transistor is a normally-off type.

Moreover, in the above, the metal compound has a portion that mixes with the second region.

In the above, the metal compound contains at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

Also, in the above, the metal compound includes aluminum and titanium.

In addition, in the above, the metal compound contains nitrogen.

Moreover, in the above, the metal compound contains either one or both of nitrogen and oxygen.

In the above, the metal compound has a thickness of 0.5 nm or more and less than 5 nm.

Further, in the above, the carbon contained in the second insulator and the carbon contained in the fourth insulator are measured by X-ray photoelectron spectroscopy.

Another embodiment of the present invention is a semiconductor device including a transistor, wherein the transistor includes a first insulator, an oxide over the first insulator, a second insulator over the oxide, and a second insulator. 3 insulators, a conductor on the second insulator, a fourth insulator on the third insulator, the second insulator, the conductor, the third insulator, and the fourth insulator a fifth insulator provided over the oxide with an insulator interposed therebetween, and a sixth insulator provided over the fifth insulator, the oxide being in contact with the first region; , a second region and a third region located between the first region and the second region, the first region having a region overlapping the second insulator; The third region has a region overlapping with the third insulator and the fourth insulator, the second region has a lower oxygen concentration than the first region and the third region, and the third region has a lower oxygen concentration than the first region and the third region. The region has a portion with an oxygen concentration between the oxygen concentration of the first region and the oxygen concentration of the second region, and the third insulator flanks the second insulator and the conductor. , and the fourth insulator has a region facing the side surfaces of the second insulator and the conductor with the third insulator interposed therebetween.

Another embodiment of the present invention is a semiconductor device including a transistor including a first insulator, an oxide over the first insulator, and a second insulator over the oxide. , a first film, a third insulator, a conductor over the second insulator, a fourth insulator over the third insulator, the second insulator, the conductor, the third and a fourth insulator, a fifth insulator provided over the oxide, and a sixth insulator provided over the fifth insulator; The article has a first region, a second region, and a third region located between the first region and the second region, the first region being a second insulator. and the third region has a region that overlaps with a third insulator and a fourth insulator, and the second region has a region that overlaps with the first region and the third region. The oxygen concentration is low, the third region has a portion with an oxygen concentration between the oxygen concentration of the first region and the oxygen concentration of the second region, and the first film has the oxygen concentration of the second region The third insulator has a region in contact with the side surfaces of the second insulator and the conductor, and the fourth insulator is provided in contact with the second insulator via the third insulator. a semiconductor device having a region facing side surfaces of an insulator and a conductor.

In the above, the third insulator may have a region in contact with the upper surface of the first insulator.

In the above, the oxide may contain In, an element M (M is Al, Ga, Y, or Sn), and Zn.

In the above, the oxide may have a larger In value than the element M in terms of atomic number ratio.

In the above, the second region may contain at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

Moreover, in the above, the second region may further contain nitrogen.

Further, in the above, the first region may have a lower hydrogen concentration than the second region.

Further, in the above, the first region may have a lower hydrogen concentration than the second region and the third region.

Further, in the above, the transistor may be of a normally-off type.

Moreover, in the above, the first film may have a portion that is mixed with the second region.

In the above, the first film may contain at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

Further, in the above, the first film may contain aluminum and titanium.

Moreover, in the above, the first film may further contain either one or both of nitrogen and oxygen.

In the above, the first film may have a thickness of 0.5 nm or more and less than 5 nm.

Another embodiment of the present invention is a method for manufacturing a semiconductor device having a transistor, wherein the transistor includes a first region, a second region, and a region between the first region and the second region. a first insulator and a second insulator over the oxide; a conductor over the first insulator; a conductor over the first insulator; a third insulator provided over the insulator and in contact with side surfaces of the first insulator and the conductor; a fourth insulator-on-insulator and a fifth insulator-on-fourth insulator, comprising an oxide, a first insulator, a conductor, a second insulator, and a third insulator; forming a first film containing a metal so as to cover the insulator and in contact with the second region; and subjecting at least the oxide and the first film to a first heat treatment in an atmosphere containing nitrogen. This is a method for manufacturing a semiconductor device, in which oxygen contained in the second region is extracted into the first film by performing the process.

In the above, the first film may be formed by a sputtering method using one or more gases selected from argon, nitrogen, and nitrogen.

Further, in the above, the first film may be removed after the first heat treatment.

Further, in the above, the second heat treatment may be performed after the first heat treatment.

Further, in the above, the fourth insulator and the fifth insulator may be formed after removing the first film.

Another embodiment of the present invention is a semiconductor device including an oxide in a channel formation region, the semiconductor device including a transistor and a wiring, the transistor including an oxide over a first insulator and an oxide over a first insulator. a second insulator on the top, a first conductor on the second insulator, a third insulator on the first conductor, the second insulator, the first conductor, and a fourth insulator in contact with the third insulator; and a fifth insulator in contact with the fourth insulator, wherein the oxide and the first region overlap with the second insulator; , a second region overlapping the fourth insulator and a third region contacting the second region, the third region having a higher oxygen concentration than the first region and the second region The second region has a lower oxygen concentration than the first region, and the wiring is in contact with the fifth insulator and electrically connected to the third region.

Another embodiment of the present invention is a semiconductor device including an oxide in a channel formation region, the semiconductor device including a transistor and a wiring, the transistor including an oxide over a first insulator; a second insulator and a first film on oxide; a first conductor on the second insulator; a third insulator on the first conductor; a second insulator; a fourth insulator in contact with the first conductor and the third insulator; and a fifth insulator in contact with the fourth insulator, wherein the oxide is the second insulator a first region overlapping with the fourth insulator; a second region overlapping with the fourth insulator; and a third region in contact with the second region, wherein the first film is in contact with the third region wherein the third region has a lower oxygen concentration than the first region and the second region, the second region has a lower oxygen concentration than the first region, and the wiring is a fifth insulator and electrically connected to the third region.

In the above, the oxide is a semiconductor device containing In, an element M (M is Al, Ga, Y, or Sn), and Zn.

In the above, the oxide is a semiconductor device in which the value of In is greater than the value of the element M in terms of atomic number ratio.

In the semiconductor device described above, the third region has a higher carrier density than the second region, and the second region has a higher carrier density than the first region.

Further, in the above, the third region is the semiconductor device containing at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

Further, in the above, the third region is a semiconductor device further containing nitrogen.

Further, in the above, the first region is a semiconductor device having a lower hydrogen concentration than the second region.

Further, in the above, the first region is a semiconductor device having a lower hydrogen concentration than the second region and the third region.

Further, in the above, the fifth insulator is a semiconductor device containing a metal oxide.

Further, in the above, the transistor is preferably of a normally-off type.

Moreover, in the above, it is preferable that the first film has a portion that is mixed with the third region.

In the above, the first film preferably contains at least one of aluminum, ruthenium, titanium, tantalum, chromium, and tungsten.

Further, in the above, the first film may contain aluminum and titanium.

Moreover, in the above, the first film preferably further contains either one or both of nitrogen and oxygen.

Moreover, in the above, the first film preferably has a thickness of 0.5 nm or more and less than 5 nm.

In another embodiment of the present invention, a first insulator is formed over a substrate, an oxide layer is formed over the first insulator, and a first insulator is formed over the oxide layer. A film, a first conductive film, and a second insulating film are formed in this order, and the first insulating film, the first conductive film, and the second insulating film are processed to form a second insulator and a first insulating film. forming a conductor and a third insulator; covering the first insulator, the oxide layer, the second insulator, the first conductor, and the third insulator; 4 insulating films are formed in order, and the third insulating film and the fourth insulating film are processed to form a fourth insulating film in contact with the second insulator, the first conductor, and the third insulator. forming an insulator and a fifth insulator in contact with the fourth insulator, and forming a first film containing a metal in contact with the first insulator, the oxide layer, and the fifth insulator; , heat treatment is performed in an atmosphere containing nitrogen, the first film is removed, a sixth insulator is formed over the first insulator, the oxide layer, and the fifth insulator; and forming a second conductor to fill the opening.

Further, in the above, the first film is preferably formed by a sputtering method using one or more gases selected from argon, nitrogen, and oxygen.

Further, in the above, it is preferable that oxygen contained in a region where the oxide layer of the oxide layer is in contact with the first film is extracted into the first film by performing the heat treatment.

In the above, after the heat treatment, a second film covering at least the oxide, the first insulator, the third insulator, the fourth insulator, and the fifth insulator may be formed.

Further, in the above, the opening is preferably formed so that part of the fifth insulator, the top surface of the oxide layer, and at least part of the side surface of the oxide layer are exposed.

Further, in the above, the third insulating film and the fourth insulating film are preferably processed by anisotropic etching using a dry etching method.

According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

Alternatively, a semiconductor device capable of holding data for a long time can be provided. Alternatively, a semiconductor device in which information can be written at high speed can be provided. Alternatively, a semiconductor device with a high degree of freedom in design can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Effects other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract effects other than these from the descriptions of the specification, drawings, claims, etc. is.

1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 4A and 4B illustrate an energy band structure of an oxide semiconductor; Schematic diagram for explaining the division of regions in an InGaZnO ₄ crystal. FIG. 4 is a diagram for explaining the migration paths of hydrogen atoms in the region between the InO ₂ plane and the (Ga, Zn)O plane, and the activation barriers on the paths. FIG. 10 is a diagram for explaining a movement path of hydrogen atoms in a (Ga, Zn)O region and an activation barrier on the path; FIG. 4 is a diagram for explaining migration paths of hydrogen atoms in the InO ₂ region and activation barriers along the paths. FIG. 4 is a diagram for explaining a movement path of hydrogen atoms along the c-axis direction and an activation barrier on the path; The figure explaining a calculation model. The figure explaining the relative value of the total energy of an oxygen deficiency model. The figure explaining the model of an initial state, and the model of a final state. The figure explaining an activation barrier. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views of a semiconductor device according to one embodiment of the present invention; 1A and 1B are circuit diagrams of a semiconductor device according to one embodiment of the present invention; FIG. 2 is a cross-sectional view showing a configuration example of a semiconductor device; 1A and 1B are a circuit diagram and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are a circuit diagram and a cross-sectional view of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 4A and 4B are a circuit diagram showing a configuration example of an inverter circuit and a timing chart showing an operation example thereof; 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention; FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention; FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention; FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention; FIG. 1A and 1B are block diagrams and circuit diagrams each illustrating a configuration example of a memory device according to one embodiment of the present invention; 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention; FIG. 4A and 4B are a block diagram and a circuit diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and a timing chart illustrating an operation example of the semiconductor device; 1 is a block diagram illustrating a configuration example of a semiconductor device according to one embodiment of the present invention; FIG. 4A and 4B are circuit diagrams each illustrating a configuration example of a semiconductor device according to one embodiment of the present invention, and timing charts each illustrating an operation example of the semiconductor device; 1 is a block diagram showing a configuration example of an AI system according to one aspect of the present invention; FIG. 1 is a block diagram illustrating an application example of an AI system according to one aspect of the present invention; FIG. 1 is a schematic perspective view showing a configuration example of an IC incorporating an AI system according to one embodiment of the present invention; FIG. 1A and 1B illustrate electronic devices according to one embodiment of the present invention; 1A and 1B illustrate electronic devices according to one embodiment of the present invention; 1A and 1B illustrate electronic devices according to one embodiment of the present invention; 1A and 1B illustrate electronic devices according to one embodiment of the present invention; 1A and 1B illustrate electronic devices according to one embodiment of the present invention; FIG. 5 is a diagram for explaining the sheet resistance of the sample of the present embodiment; FIG. 4 is a diagram for explaining SIMS analysis results of the sample of the present example; FIG. 4 is a diagram showing the Id-Vg characteristics of samples according to the present example; FIG. 4 is a diagram showing the Id-Vg characteristics of samples according to the present example;

Hereinafter, embodiments will be described with reference to the drawings. Those skilled in the art will readily appreciate, however, that the embodiments can be embodied in many different forms and that various changes in form and detail can be made therein without departing from the spirit and scope thereof. . Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

Also, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but are sometimes omitted for ease of understanding. In addition, in the drawings, the same reference numerals may be used in common for the same parts or parts having similar functions, and repeated description thereof may be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

In particular, in top views (also referred to as “plan views”) and perspective views, description of some components may be omitted in order to facilitate understanding of the invention. Also, description of some hidden lines may be omitted.

In this specification and the like, ordinal numbers such as first and second are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third". Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

In this specification and the like, terms such as “above” and “below” are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. In addition, the positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately rephrased according to the situation.

For example, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y function This specification and the like disclose the case where X and Y are directly connected and the case where X and Y are directly connected. Therefore, it is assumed that the connection relationships other than the connection relationships shown in the drawings or the text are not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or the text.

Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

An example of the case where X and Y are directly connected is an element (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display element) that enables electrical connection between X and Y. element, light-emitting element, load, etc.) is not connected between X and Y, and an element that enables electrical connection between X and Y (e.g., switch, transistor, capacitive element, inductor , resistance element, diode, display element, light emitting element, load, etc.).

An example of the case where X and Y are electrically connected is an element that enables electrical connection between X and Y (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display elements, light emitting elements, loads, etc.) can be connected between X and Y. Note that the switch has a function of being controlled to be turned on and off. In other words, the switch has a function of controlling whether it is in a conducting state (on state) or a non-conducting state (off state) to allow current to flow. Alternatively, the switch has a function of selecting and switching a path through which current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (eg, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (booster circuit, step-down circuit, etc.), level shifter circuit that changes the potential level of a signal, etc.), voltage source, current source, switching Circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) One or more connections can be made between them. As an example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected. do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a region in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and through the region in which the channel is formed, A current can flow between the source and the drain. Note that in this specification and the like, a region where a channel is formed means a region where current mainly flows.

Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" can be used interchangeably in some cases.

Note that the channel length is, for example, a region in which a semiconductor (or a portion of the semiconductor in which current flows when the transistor is on) overlaps with a gate electrode in a top view of a transistor, or a region where a channel is formed. The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in Note that the channel length does not always have the same value in all regions of one transistor. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one value, maximum value, minimum value, or average value in the region where the channel is formed.

The channel width is, for example, in a top view of a transistor, a region in which a semiconductor (or a portion of the semiconductor in which current flows when the transistor is on) and a gate electrode overlap each other, or a region in which a channel is formed. Refers to the length of the region in which the channel is formed in the vertical direction with respect to the channel length direction. Note that the channel width does not always have the same value in all regions of one transistor. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one value, maximum value, minimum value, or average value in the region where the channel is formed.

Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as the “effective channel width”) and the channel width shown in the top view of the transistor (hereinafter referred to as the “apparent channel width”). (also referred to as "channel width") and may differ. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and its influence cannot be ignored. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from design values, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width if the shape of the semiconductor is not accurately known.

Therefore, in this specification, the apparent channel width is sometimes referred to as "surrounded channel width (SCW)". In addition, in this specification, simply referring to the channel width may refer to the enclosing channel width or the apparent channel width. Alternatively, in this specification, simply referring to the channel width may refer to the effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, enclosing channel width, etc. can be determined by analyzing cross-sectional TEM images or the like.

Note that impurities in a semiconductor refer to, for example, substances other than the main components that constitute the semiconductor. For example, an element whose concentration is less than 0.1 atomic percent can be said to be an impurity. When impurities are contained, for example, the DOS (Density of States) of the semiconductor may increase, the crystallinity may decrease, and the like. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors. There are transition metals other than the main component of , such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, for example, oxygen vacancies may be formed due to contamination by impurities. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Note that in this specification and the like, a silicon oxynitride film contains more oxygen than nitrogen as its composition. For example, oxygen is preferably 55 atomic % or more and 65 atomic % or less, nitrogen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0.1 atomic % or more and 10 atomic % or less. It refers to what is included in the concentration range. A silicon nitride oxide film contains more nitrogen than oxygen in its composition. For example, preferably nitrogen is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, and hydrogen is 0.1 atomic % or more and 10 atomic % or less. It refers to what is included in the concentration range.

In this specification and the like, the terms “film” and “layer” can be used interchangeably. For example, it may be possible to change the term "conductive layer" to the term "conductive film." Or, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

In this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Also, the term “conductor” can be replaced with a conductive film or a conductive layer. Also, the term "semiconductor" can be interchanged with a semiconductor film or a semiconductor layer.

In addition, transistors described in this specification and the like are field-effect transistors unless otherwise specified. In addition, transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, its threshold voltage (also referred to as "Vth") is assumed to be higher than 0 V unless otherwise specified.

In this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of −5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. In addition, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Also, in this specification, when a crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

In this specification, a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen and oxygen, and when the barrier film has conductivity, it is called a conductive barrier film. There is

In this specification and the like, a metal oxide is a metal oxide in broad terms. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In other words, an OS FET or an OS transistor can also be referred to as a transistor including an oxide or an oxide semiconductor.

In this specification and the like, the term “normally off” means that a current per 1 μm of channel width flowing through a transistor when no voltage is applied to the gate or a ground potential is applied to the gate is 1×10 ⁻²⁰ at room temperature. A or less, 1×10 ⁻¹⁸ A or less at 85° C., or 1×10 ⁻¹⁶ A or less at 125° C.

(Embodiment 1)
An example of a semiconductor device including the transistor 200A according to one embodiment of the present invention is described below.

<Structure example of semiconductor device>
1A, 1B, 1C, and 1D are a top view and a cross-sectional view of a transistor 200A and its periphery according to one embodiment of the present invention.

FIG. 1A is a top view of a semiconductor device including a transistor 200A. 1B, 1C, and 1D are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view in the channel length direction of the transistor 200A. FIG. 1C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200A in the channel width direction. FIG. 1D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 1A, and is also a cross-sectional view of the source region or the drain region of the transistor 200A. Note that in the top view of FIG. 1A, some elements are omitted for clarity.

A semiconductor device of one embodiment of the present invention includes a transistor 200A and insulators 210, 212, 280, 282, and 284 functioning as interlayer films. It also includes a conductor 203 that is electrically connected to the transistor 200A and functions as a wiring, and a conductor 240 (a conductor 240a and a conductor 240b) that functions as a plug.

Note that a first conductor of the conductor 203 is formed in contact with the inner wall of the opening of the insulator 212, and a second conductor of the conductor 203 is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be made approximately the same. Note that although a structure in which the first conductor of the conductor 203 and the second conductor of the conductor 203 are stacked in this embodiment mode, the present invention is not limited to this. For example, the conductor 203 may be provided as a single layer or a laminated structure of three or more layers. In addition, when the structure has a laminated structure, an ordinal number may be given in order of formation for distinction.

The conductor 240 is formed in contact with the inner walls of the openings of the insulators 273 , 274 , 280 , 282 , and 284 . Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 284 can be made approximately the same. Note that although the structure in which the conductor 240 has a two-layer laminated structure is shown in this embodiment mode, the present invention is not limited to this. For example, the conductor 240 may be a single layer or a laminated structure of three or more layers.

[Transistor 200A]
As shown in FIG. 1, transistor 200A includes insulators 214 and 216 disposed over a substrate (not shown) and conductors disposed to be embedded in insulators 214 and 216. 205, an insulator 220 overlying the insulator 216 and the conductor 205, an insulator 222 overlying the insulator 220, an insulator 224 overlying the insulator 222, an insulator Oxide 230 (oxide 230 a , oxide 230 b , and oxide 230 c ) overlying body 224 , insulator 250 overlying oxide 230 , and metal overlying insulator 250 . Oxide 252 , conductor 260 (conductor 260 a and conductor 260 b ) overlying metal oxide 252 , insulator 270 overlying conductor 260 , over insulator 270 . an insulator 271 in contact with at least sides of the oxide 230c, the insulator 250, the metal oxide 252, and the conductor 260; an insulator 273 disposed on the layer 242 and an insulator 274 disposed on the insulator 273;

Note that although the transistor 200A has a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked, the present invention is not limited to this. For example, a single layer of the oxide 230b, a two-layer structure of the oxides 230b and 230a, a two-layer structure of the oxides 230b and 230c, or a stacked structure of four or more layers may be employed. Further, although the structure in which the conductors 260a and 260b are stacked is shown in the transistor 200A, the present invention is not limited to this.

In the transistor 200A, a metal functioning as an oxide semiconductor is added to the oxide 230 (the oxide 230a, the oxide 230b, and the oxide 230c) including a region where a channel is formed (hereinafter also referred to as a channel formation region). An oxide (hereinafter also referred to as an oxide semiconductor) is preferably used.

Since the transistor 200A including an oxide semiconductor for a channel formation region has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. Further, since an oxide semiconductor can be deposited by a sputtering method or the like, it can be used for the transistor 200A included in a highly integrated semiconductor device.

For example, as the oxide 230, In-M-Zn oxide (element M is aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or the like) may be used. Alternatively, as the oxide 230, an In--Ga oxide or an In--Zn oxide may be used.

Here, the oxide semiconductor forms a metal compound with low resistance by adding metal elements such as aluminum, ruthenium, titanium, tantalum, chromium, and tungsten in addition to the elements constituting the oxide semiconductor. become Note that it is preferable to use aluminum, titanium, tantalum, tungsten, or the like.

In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. Further, when the film is provided, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film or the like to form oxygen vacancies. The vicinity of the interface may have a low resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment is preferably performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is converted into an oxide semiconductor by the metal element as a component of the film, or as a component of the oxide semiconductor. A certain metal element diffuses into the film, the oxide semiconductor and the film form a metal compound, and the resistance can be reduced. The metal element added to the oxide semiconductor forms a metal compound with the oxide semiconductor and the metal element, so that the metal element is in a relatively stable state; therefore, a highly reliable semiconductor device can be provided.

A compound layer (hereinafter also referred to as a different layer) may be formed at the interface between the metal film, the nitride film containing the metal element, or the oxide film containing the metal element, and the oxide semiconductor. Note that the compound layer (different layer) is a layer having a metal compound containing a component of a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, and a component of an oxide semiconductor. For example, as the compound layer, a layer in which the metal element of the oxide semiconductor and the added metal element are alloyed may be formed. The alloyed layer is in a relatively stable state and can provide a highly reliable semiconductor device.

In addition, when hydrogen existing in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor and enters oxygen vacancies in the low-resistance region, the hydrogen is in a relatively stable state. Further, hydrogen in the oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and oxygen vacancies existing in the low-resistance region. It is known that it enters into the inside and becomes a relatively stable state. Therefore, by heat treatment, the resistance of the region where the resistance of the oxide semiconductor is reduced or the region where the metal compound is formed is further reduced, and the oxide semiconductor which is not reduced in resistance is purified (impurities such as water and hydrogen). reduction) and tends to increase the resistance.

In addition, the oxide semiconductor has an increased carrier density when an impurity element such as hydrogen or nitrogen is present. Hydrogen in the oxide semiconductor reacts with oxygen that bonds to a metal atom to become water, which may cause oxygen vacancies. When hydrogen enters the oxygen vacancies, the carrier density increases. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen or nitrogen to an oxide semiconductor, a high-resistance region and a low-resistance region can be provided in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the island-shaped oxide 230 has a region functioning as a semiconductor with low carrier density and a region functioning as a source region or a drain region. A region can be provided.

Here, FIG. 2 shows an enlarged view of a region 239 surrounded by a broken line in FIG. 1B and including the selectively low-resistance oxide 230b.

As shown in FIG. 2, the oxide 230 includes a region 234 functioning as a channel forming region of a transistor, a region 231 (regions 231a and 231b) functioning as a source region or a drain region, and regions 234 and 231. and a region 232 (region 232a and region 232b) provided between.

A region 231 functioning as a source region or a drain region has a low oxygen concentration and a low resistance. A region 234 functioning as a channel formation region is a high-resistance region having a higher oxygen concentration and a lower carrier density than the region 231 functioning as a source region or a drain region. Further, the region 232 has a higher oxygen concentration and a lower carrier density than the region 231 functioning as a source region or a drain region, and has a lower oxygen concentration and a lower carrier density than the region 234 functioning as a channel formation region. High area.

Note that the concentration of at least one of the metal element and the impurity element such as hydrogen and nitrogen is preferably higher in the region 231 than in the regions 232 and 234 .

For example, in addition to the oxide 230, the region 231 preferably contains one or more metal elements selected from metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium.

In order to form the region 231 , for example, a layer 242 may be provided as a film containing a metal element in contact with the region 231 of the oxide 230 . Note that a metal film, a nitride film containing a metal element, or an oxide film containing a metal element can be used as the layer 242 . At that time, a compound layer may be formed at the interface between the layer 242 and the oxide 230 . Note that the compound layer is a layer having a metal compound containing a component of the layer 242 and a component of the oxide 230 . For example, as the compound layer, a layer in which the metal element in the oxide 230 and the added metal element are alloyed may be formed.

By adding a metal element to the oxide 230, a metal compound is formed in the oxide 230, and the resistance of the region 231 can be reduced. Note that the metal compound does not necessarily have to be formed in the oxide 230 . For example, layer 242 may be formed with a metal compound. Alternatively, for example, it may be provided on the surface of the oxide 230 , the surface of the layer 242 , or a compound layer formed on the interface between the layer 242 and the oxide 230 .

Thus, region 231 may also include a low resistance region of layer 242 or a low resistance region of a compound layer formed between layer 242 and oxide 230 . That is, in this specification, the region 231 is a region that functions as a source region or a drain region.

Region 232 has a region that overlaps insulator 275 . Region 232 preferably has a higher concentration than region 234 in at least one of metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and impurity elements such as hydrogen and nitrogen. For example, by providing the layer 242, which is a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, in contact with the region 231 of the oxide 230, the components in the layer 242 and the components of the oxide semiconductor may form metal compounds. The metal compound may attract hydrogen contained in oxide 230 . Therefore, the concentration of hydrogen in the region 232 near the region 231 may become high.

Note that one or both of the regions 232 a and 232 b may have a region overlapping with the conductor 260 . With this structure, the conductor 260 can overlap with the regions 232a and 232b.

Also, in FIG. 2, the regions 234, 231, and 232 are formed in the oxide 230b, but the invention is not limited to this. For example, these regions may also be formed in layer 242, a compound layer formed between layer 242 and oxide 230, oxide 230a, and oxide 230c. In addition, in FIG. 2, the boundaries of the regions are shown substantially perpendicular to the top surface of the oxide 230, but the present embodiment is not limited to this. For example, the region 232 may protrude toward the conductor 260 near the surface of the oxide 230b and recede toward the conductor 240a or 240b near the bottom surface of the oxide 230a.

Also, in the oxide 230, it may be difficult to clearly detect the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes between regions, but also change continuously (also called gradation) within each region. good too. In other words, the closer the region is to the channel formation region, the lower the concentrations of the metal elements and the impurity elements such as hydrogen and nitrogen.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity, such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and impurities are added to desired regions. Just do it. Note that an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used as the impurity. Examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, and rare gases. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon.

In the region 231, by increasing the content of the metal element that increases conductivity, the element that forms oxygen vacancies, or the element that is captured by oxygen vacancies, carrier density can be increased and resistance can be reduced. can.

To reduce the resistance of region 231 , for example, layer 242 may be deposited in contact with region 231 of oxide 230 . As the layer 242, a metal film, a nitride film containing a metal element, an oxide film containing a metal element, or the like can be used. Layer 242 is preferably provided over oxide 230 with at least insulator 250 , metal oxide 252 , conductor 260 , insulator 270 , insulator 271 , and insulator 275 interposed therebetween.

By contacting the oxide 230 and the layer 242, the components of the layer 242 and the oxide 230 form a metal compound, which becomes the region 231 and has a low resistance. In addition, part of the oxygen in the oxide 230 located at or near the interface between the oxide 230 and the layer 242 is absorbed by the layer 242 to form oxygen vacancies in the oxide 230, thereby reducing the resistance of the region. 231 may be formed.

Further, heat treatment is preferably performed in an atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. By the heat treatment, the metal element that is a component of the layer 242 diffuses from the layer 242 into the oxide 230 or the metal element that is a component of the oxide 230 diffuses into the layer 242, so that the oxide 230 and the layer 242 are separated. Forms a metal compound to lower the resistance. At that time, the metal element of the oxide 230 and the metal element of the layer 242 may be alloyed. By alloying the metal element of the oxide 230 and the metal element of the layer 242, the metal element is in a relatively stable state, so that a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

On the other hand, addition of the metal element is suppressed by the conductor 260 and the insulator 275 in the regions (the regions 234 and 232 ) of the oxide 230 that overlap with the conductor 260 and the insulator 275 . Also, in the regions 234 and 232 of the oxide 230, absorption of oxygen atoms in the oxide 230 into the layer 242 described above is suppressed.

In addition, oxygen in the region 231 of the oxide 230 and in the region 232 adjacent to the region 231 is absorbed by the layer 242 , so that oxygen vacancies may occur in the region 231 and the region 232 . Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are made low resistance.

Here, if the layer 242 has the property of absorbing hydrogen, the hydrogen in the oxide 230 will be absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Layer 242 may also be removed along with hydrogen absorbed from oxide 230 in a later step.

Note that the layer 242 does not necessarily have to be removed. For example, if the layer 242 is insulating and has a high resistance, it may remain. For example, layer 242 may be oxidized by oxygen absorbed from oxide 230, become an insulator, and become highly resistive. In that case, layer 242 may function as an interlayer.

Further, for example, when a conductive region remains in the layer 242, it becomes an insulator and has a high resistance by being oxidized by heat treatment. The heat treatment is preferably performed, for example, in an oxidizing atmosphere. Further, when there is a structure containing oxygen in the vicinity of the layer 242, the layer 242 may react with oxygen contained in the structure and be oxidized by heat treatment.

By leaving the layer 242 as an insulator, it can function as an interlayer film. In the case of this structure, the layer 242 is provided with a thickness that can be insulated in a later step. For example, the layer 242 is preferably provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. Note that when the heat treatment is performed in the above oxidizing atmosphere, it is preferable to perform the heat treatment once in an atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. Once heat treatment is performed in an atmosphere containing nitrogen, oxygen in the oxide 230 can easily diffuse into the layer 242 .

Here, in a transistor including an oxide semiconductor, if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded. In addition, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor tends to have normally-on characteristics. Therefore, oxygen vacancies in the region 234 where the channel is formed are preferably reduced as much as possible.

Therefore, as shown in FIG. 2, oxygen in contact with the insulator 250, the region 232 of the oxide 230b, and the oxide 230c contains more oxygen than the stoichiometric composition (also referred to as excess oxygen). An insulator 275 is preferably provided. That is, excess oxygen in the insulator 275 diffuses into the region 234 of the oxide 230, so that oxygen vacancies in the region 234 of the oxide 230 can be reduced.

In order to provide the excess oxygen region in the insulator 275, an oxide film is preferably formed as the insulator 273 close to the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide film, an insulator containing few impurities such as water or hydrogen can be formed. When the sputtering method is used, it is preferable to form the film using, for example, a facing target type sputtering apparatus. The facing target type sputtering apparatus can form a film without exposing the film formation surface to the high electric field region between the opposing targets. This is preferable because film damage to the oxide 230 can be reduced when the insulator 273 is formed. A film formation method using a facing target type sputtering apparatus can be called VDSP (Vapor Deposition SP) (registered trademark).

During film formation by the sputtering method, ions and sputtered particles are present between the target and the substrate. For example, the target is connected to a power supply and given a potential E0. A potential E1 such as a ground potential is applied to the substrate. However, the substrate may be electrically floating. A region having potential E2 exists between the target and the substrate. The magnitude relationship between the potentials is E2>E1>E0.

Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, thereby ejecting sputtered particles from the target. The sputtered particles adhere to the film formation surface and accumulate to form a film. In addition, some ions recoil by the target, pass through the film formed as recoil ions, and may be taken into the insulator 275 in contact with the deposition surface. Also, the ions in the plasma are accelerated by the potential difference E2-E1 and bombard the surface of the film. At this time, some of the ions reach the inside of the insulator 275 . By capturing ions into the insulator 275 , a region in which ions are captured is formed in the insulator 275 . That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 275 .

By introducing excess oxygen into the insulator 275 , an excess oxygen region can be formed in the insulator 275 . Excess oxygen in insulator 275 can be supplied to region 234 of oxide 230 to compensate for oxygen vacancies in oxide 230 .

Note that silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes is preferably used for the insulator 275 . Materials such as silicon oxynitride are prone to the formation of excess oxygen regions. On the other hand, compared with the above materials such as silicon oxynitride, the oxide 230 tends to be less likely to form an excess oxygen region even if an oxide film is formed on the oxide 230 using a sputtering method. Therefore, by providing the insulator 275 having the excess oxygen region around the region 234 of the oxide 230 , excess oxygen of the insulator 275 can be effectively supplied to the region 234 of the oxide 230 .

Aluminum oxide is preferably used for the insulator 273 . When aluminum oxide is heat-treated in proximity to the oxide 230, hydrogen in the oxide 230 may be extracted. Note that in the case where the layer 242 is provided between the oxide 230 and aluminum oxide, the aluminum oxide absorbs hydrogen in the layer 242, and the layer 242 in which hydrogen is reduced absorbs hydrogen in the oxide 230. May be absorbed. Therefore, the hydrogen concentration in the oxide 230 can be reduced. Further, when heat treatment is performed with the insulator 273 and the oxide 230 in close proximity, oxygen can be supplied from the insulator 273 to the oxide 230, the insulator 224, or the insulator 222 in some cases.

By combining the above structure or the above steps, the resistance of the oxide 230 can be selectively reduced.

That is, when the low-resistance region is formed in the oxide 230, the resistance of the oxide 230 is lowered in a self-aligned manner by using the conductor 260 functioning as a gate electrode and the insulator 275 as a mask. Therefore, when a plurality of transistors 200A are formed at the same time, variations in electrical characteristics among the transistors can be reduced. In addition, the channel length of the transistor 200A is determined by the width of the conductor 260 and the film thickness of the insulator 275; Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor including an oxide semiconductor for a channel formation region has extremely low leakage current (off-state current) in a non-conducting state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

A detailed structure of a semiconductor device including the transistor 200A according to one embodiment of the present invention is described below.

As shown in FIGS. 1A and 1C, the conductor 203 extends in the channel width direction and functions as a wiring that applies a potential to the conductor 205 . Note that the conductor 203 is preferably embedded in the insulator 212 .

Conductor 205 is arranged to overlap with oxide 230 and conductor 260 . Further, the conductor 205 is preferably provided on and in contact with the conductor 203 . Further, the conductor 205 is preferably embedded in the insulators 214 and 216 .

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. In some cases, the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode. In that case, the potential applied to the conductor 205 is changed independently of the potential applied to the conductor 260, so that the threshold voltage of the transistor 200A can be controlled. In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200A can be made higher than 0 V and the off current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.

By providing the conductor 205 over the conductor 203, the distance between the conductor 203 and the conductor 260 functioning as the first gate electrode and the wiring can be designed as appropriate. In other words, by providing the insulator 214 and the insulator 216 between the conductor 203 and the conductor 260, the parasitic capacitance between the conductor 203 and the conductor 260 is reduced, can increase the dielectric strength between

In addition, by reducing the parasitic capacitance between the conductor 203 and the conductor 260, the switching speed of the transistor 200A can be improved and the transistor can have high frequency characteristics. Further, by increasing the withstand voltage between the conductor 203 and the conductor 260, the reliability of the transistor 200A can be improved. Therefore, it is preferable to increase the thickness of the insulators 214 and 216 . Note that the extending direction of the conductor 203 is not limited to this, and may be extended in the channel length direction of the transistor 200A, for example.

Note that the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260 as shown in FIG. Also, the conductor 205 is preferably provided larger than the region 234 in the oxide 230 . In particular, as shown in FIG. 1C, it is preferable that the conductor 205 extends also in a region outside the edge of the region 234 of the oxide 230 crossing the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween on side surfaces of the oxide 230 in the channel width direction.

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, an electric field generated from the conductor 260 and an electric field generated from the conductor 205 are connected to form a channel in the oxide 230. area can be covered.

In other words, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region of the region 234 . . In this specification, a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

The conductor 205 has a first conductor formed in contact with the inner walls of the openings of the insulators 214 and 216, and a second conductor formed further inside. Here, the height of the top surface of the first conductor of the conductor 205 and the top surface of the second conductor of the conductor 205 can be made approximately the same as the height of the top surface of the insulator 216 . Note that although the structure in which the first conductor of the conductor 205 and the second conductor of the conductor 205 are stacked is shown in the transistor 200A, the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure of three or more layers.

Here, the conductor 205 or the first conductor of the conductor 203 includes hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N ₂ O, NO, NO ₂ ), copper It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as atoms (the impurities are less likely to permeate). Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the above-described oxygen hardly permeates). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of either one or all of the impurities or oxygen.

Since the conductor 205 or the first conductor of the conductor 203 has a function of suppressing the diffusion of oxygen, the conductor 205 or the second conductor of the conductor 203 is oxidized and the conductivity is lowered. can be suppressed. As the conductive material having a function of suppressing diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example. Therefore, as the conductor 205 or the first conductor of the conductor 203, a single layer or a laminate of the above conductive materials may be used. Accordingly, impurities such as hydrogen and water can be prevented from diffusing from the substrate side (below the insulator 210 ) to the transistor 200A side through the conductors 203 and 205 .

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the second conductor of the conductor 205 . Note that although the second conductor of the conductor 205 is illustrated as a single layer, it may have a stacked structure, for example, a stacked layer of titanium or titanium nitride and any of the above conductive materials.

In addition, since the second conductor of the conductor 203 functions as a wiring, a conductor having higher conductivity than the second conductor of the conductor 205 is preferably used. For example, a conductive material containing copper or aluminum as a main component can be used. Further, the second conductor of the conductor 203 may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.

In particular, it is preferable to use copper for the conductor 203 . Since copper has a low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, diffusion into the oxide 230 may degrade the electrical characteristics of the transistor 200A. Therefore, by using a material such as aluminum oxide or hafnium oxide, which has low copper permeability, for the insulator 214, the diffusion of copper can be suppressed.

Note that the conductor 205, the insulator 214, and the insulator 216 are not necessarily provided. In that case, part of the conductor 203 can function as the second gate electrode.

The insulator 210, the insulator 214, and the insulator 282 preferably function as barrier insulating films that prevent impurities such as water or hydrogen from entering the transistor 200A from the substrate side or the insulator 284 side. Therefore, the insulator 210, the insulator 214, and the insulator 282 can contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( _N2O , NO, _NO2, etc.), copper atoms, and the like. It is preferable to use an insulating material that has a function of suppressing diffusion of impurities (that is, the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the above-described oxygen hardly permeates).

For example, it is preferable to use aluminum oxide or the like for the insulators 210 and 282 and to use silicon nitride or the like for the insulator 214 . Accordingly, impurities such as hydrogen and water can be prevented from diffusing from the substrate side to the transistor 200A side with respect to the insulators 210 and 214 . Alternatively, oxygen contained in the insulator 224 or the like can be prevented from diffusing toward the substrate side of the insulators 210 and 214 . Alternatively, impurities such as hydrogen and water can be prevented from diffusing from the insulator 284 side to the transistor 200A side rather than the insulator 282 .

In addition, the insulator 214 can be provided between the conductors 203 and 205 by stacking the conductor 205 over the conductor 203 . Here, even if a metal that is easily diffused, such as copper, is used for the second conductor of the conductor 203 , the metal is prevented from diffusing into a layer above the insulator 214 by providing silicon nitride or the like as the insulator 214 . can be suppressed.

The insulators 212 , 216 , 280 , and 284 that function as interlayer films preferably have lower dielectric constants than the insulators 210 and 214 . By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

For example, insulator 212, insulator 216, insulator 280, and insulator 284 may be silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT). ), strontium titanate (SrTiO ₃ ) or (Ba,Sr)TiO ₃ (BST) can be used in single or multiple layers. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

Insulator 220, insulator 222, and insulator 224 function as gate insulators.

Here, the insulator 224 in contact with the oxide 230 preferably contains more oxygen than the stoichiometric composition. In other words, the insulator 224 preferably has an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200A can be improved.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having the excess oxygen region. The oxide that desorbs oxygen by heating means that the desorption amount of oxygen converted to oxygen atoms is 1.0×10 ¹⁸ atoms in thermal desorption spectroscopy (TDS) analysis. /cm ³ or more, preferably 1.0 × 10 ¹⁹ atoms/cm ³ or more, more preferably 2.0 × 10 ¹⁹ atoms/cm ³ or more, or 3.0 × 10 ²⁰ atoms/cm ³ or more is. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower, or 100° C. or higher and 400° C. or lower.

In addition, when the insulator 224 has an excess oxygen region, the insulator 222 has a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the oxygen is difficult to permeate). is preferred.

Since the insulator 222 has a function of suppressing diffusion of oxygen, oxygen in the excess oxygen region of the insulator 224 can be efficiently supplied to the oxide 230 without diffusing to the insulator 220 side. . In addition, the conductor 205 can be prevented from reacting with oxygen in the excess oxygen region of the insulator 224 .

As the insulator 222, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba,Sr)TiO ₃ (BST), so-called It is preferable to use insulators containing high-k materials in single layers or stacks. As transistors are miniaturized and highly integrated, thinning of gate insulators may cause problems such as leakage current. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material and has a function of suppressing the diffusion of impurities and oxygen (the oxygen is less permeable), is preferably used. As the insulator containing oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. When the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen into the oxide 230 from the peripheral portion of the transistor 200A. act as a layer.

Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

Also, insulator 220 or insulator 224 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are thermally stable, so by combining them with a high-k material insulator, the gate insulator should have a thermally stable laminated structure with a high dielectric constant. can be done.

Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may be used.

Oxide 230 has oxide 230a, oxide 230b over oxide 230a, and oxide 230c over oxide 230b. By providing the oxide 230a under the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, by having the oxide 230c over the oxide 230b, diffusion of impurities from a structure formed above the oxide 230c to the oxide 230b can be suppressed.

Note that the oxide 230 preferably has a layered structure with oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic number ratio of the element M among the constituent elements is greater than the atomic number ratio of the element M among the constituent elements in the metal oxide used for the oxide 230b. is preferred. Moreover, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In addition, the atomic ratio of In to the element M in the metal oxide used for the oxide 230b is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. In addition, the oxide 230c can be a metal oxide that can be used for the oxide 230a or the oxide 230b.

In addition, the energy levels of the conduction band bottoms of the oxides 230a and 230c are preferably higher than the energy levels of the conduction band bottoms of the oxide 230b. Also, in other words, the electron affinities of the oxides 230a and 230c are preferably smaller than the electron affinities of the oxide 230b.

Here, the energy level at the bottom of the conduction band changes smoothly at the junction of the oxide 230a, the oxide 230b, and the oxide 230c. In other words, it can be said that the energy level of the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c continuously changes or continuously joins. In order to achieve this, the defect level density of the mixed layers formed at the interface between the oxides 230a and 230b and at the interface between the oxides 230b and 230c should be reduced.

Specifically, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c have a common element (main component) other than oxygen, thereby forming a mixed layer with a low defect level density. can do. For example, when the oxide 230b is an In--Ga--Zn oxide, the oxides 230a and 230c may be In--Ga--Zn oxide, Ga--Zn oxide, gallium oxide, or the like.

At this time, the main path of carriers is the oxide 230b. When the oxides 230a and 230c have the above structures, defect level densities at the interfaces between the oxides 230a and 230b and between the oxides 230b and 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200A can obtain a high ON current.

Oxide 230 also has regions 231 , 232 , and 234 . Note that at least part of the region 231 has a region close to the insulator 273 . Also, the region 232 has at least a region overlapping with the insulator 275 .

Note that when the transistor 200A is turned on, the region 231a or the region 231b functions as a source region or a drain region. On the other hand, at least a portion of region 234 functions as a region in which a channel is formed. By providing the region 232 between the region 231 and the region 234, the on-state current can be increased and the leakage current (off-state current) can be reduced in the transistor 200A.

By providing the region 232 in the transistor 200A, a high-resistance region is not formed between the region 231 functioning as a source region and a drain region and the region 234 in which a channel is formed. can be increased. In addition, since the region 232 is provided, the source region and the drain region do not overlap with the first gate electrode (the conductor 260) in the channel length direction, so that unnecessary capacitance is formed between them. can be suppressed. In addition, since the region 232 is provided, leakage current can be reduced when the device is not conducting.

In other words, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

A metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used as the oxide 230 . For example, it is preferable to use a metal oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide that becomes the region 234 . By using a metal oxide with a large bandgap in this manner, off-state current of a transistor can be reduced.

A transistor including an oxide semiconductor has extremely low leakage current in a non-conducting state; therefore, a semiconductor device with low power consumption can be provided. Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device.

Insulator 250 functions as a gate insulator. Insulator 250 is preferably placed in contact with the top surface of oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in TDS analysis, the desorption amount of oxygen in terms of oxygen molecules is 1.0×10 ¹⁸ molecules/cm ³ or more, preferably 1.0×10 ¹⁹ molecules/cm ³ or more, more preferably 2. 0×10 ¹⁹ molecules/cm ³ or 3.0×10 ²⁰ molecules/cm ³ . The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower.

Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

By providing an insulator from which oxygen is released by heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied from the insulator 250 to the region 234 of the oxide 230b. . Further, similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

In addition, a metal oxide 252 may be provided in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230 . Therefore, metal oxide 252 preferably suppresses oxygen diffusion from insulator 250 . By providing the metal oxide 252 that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, reduction in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

Note that the metal oxide 252 may function as part of the first gate electrode. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide 252 . In that case, by forming the conductor 260 by a sputtering method, the electric resistance value of the metal oxide 252 can be lowered and the metal oxide 252 can be a conductor. This can be called an OC (Oxide Conductor) electrode.

Metal oxide 252 may also function as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide 252 is preferably a high-k material with a high dielectric constant. With the laminated structure, a laminated structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. Also, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced.

Although the metal oxide 252 is shown as a single layer in the transistor 200A, it may have a stacked structure of two or more layers. For example, a metal oxide that functions as part of the first gate electrode and a metal oxide that functions as part of the gate insulator may be stacked.

When the metal oxide 252 functions as the first gate electrode, the on-state current of the transistor 200A can be improved without weakening the influence of the electric field from the conductor 260. FIG. Alternatively, when functioning as a gate insulator, the physical thickness of insulator 250 and metal oxide 252 maintains a distance between conductor 260 and oxide 230, thereby reducing the distance between conductor 260 and oxide 230. Leakage current with the oxide 230 can be suppressed. Therefore, by providing the stacked structure of the insulator 250 and the metal oxide 252, the physical distance between the conductor 260 and the oxide 230 and the electric field intensity applied from the conductor 260 to the oxide 230 can be reduced to It can be easily adjusted accordingly.

Specifically, the metal oxide 252 can be used as the metal oxide 252 by reducing the resistance of an oxide semiconductor that can be used for the oxide 230 . Alternatively, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like can be used.

In particular, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing oxides of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in the subsequent steps. Note that the metal oxide 252 is not an essential component. It may be appropriately designed depending on the required transistor characteristics.

A conductor 260 functioning as a first gate electrode has a conductor 260a and a conductor 260b over the conductor 260a. The conductor 260a, like the first conductor of the conductor 205, contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _2, etc.), copper atoms. It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as . Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.

Since the conductor 260a has a function of suppressing the diffusion of oxygen, excess oxygen in the insulator 250 and the metal oxide 252 can suppress oxidation of the conductor 260b and reduction in conductivity. . As the conductive material having a function of suppressing diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.

Further, since the conductor 260 functions as a wiring, a conductor with high conductivity is preferably used. For example, the conductor 260b can use a conductive material whose main component is tungsten, copper, or aluminum. Also, the conductor 260b may have a layered structure, for example, a layered structure of titanium, titanium nitride, and any of the above conductive materials.

Further, as shown in FIG. 1C, when the conductor 205 extends in a region outside the end portion of the oxide 230 that intersects with the channel width direction, the conductor 260 extends in the region. It is preferable that they overlap each other with an insulator 250 interposed therebetween. That is, the conductor 205 , the insulator 250 , and the conductor 260 preferably form a stacked structure outside the side surfaces of the oxide 230 .

With the above structure, when a potential is applied to the conductor 260 and the conductor 205, an electric field generated from the conductor 260 and an electric field generated from the conductor 205 are connected to form a channel in the oxide 230. area can be covered.

In other words, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region of the region 234 . .

Further, an insulator 270 functioning as a barrier film may be placed over the conductor 260b. For the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, it is preferable to use aluminum oxide or hafnium oxide. Accordingly, oxidation of the conductor 260 by oxygen from above the insulator 270 can be suppressed. In addition, impurities such as water or hydrogen from above the insulator 270 can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250 .

An insulator 271 functioning as a hard mask is preferably provided over the insulator 270 . By providing the insulator 271, when the conductor 260 is processed, the side surface of the conductor 260 is substantially vertical. Preferably, it can be 80° or more and 95° or less. By processing the conductor 260 into such a shape, the insulator 275 to be formed next can be formed into a desired shape.

Note that the insulator 271 may also function as a barrier film by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the insulator 270 may not be provided.

The insulator 275 functioning as a buffer layer is provided in contact with side surfaces of the oxide 230 c , the insulator 250 , the metal oxide 252 , the conductor 260 , and the insulator 270 .

For example, the insulator 275 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. Alternatively, it is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.

Insulator 275 also preferably has excess oxygen regions. An insulator from which oxygen is released by heating is provided as the insulator 275 in contact with the oxide 230c and the insulator 250, whereby oxygen is effectively supplied from the insulator 250 to the region 234 of the oxide 230b. be able to. Further, the concentration of impurities such as water or hydrogen in the insulator 275 is preferably reduced.

An insulator 273 is provided over at least region 231 of oxide 230 and over insulator 275 . By forming the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 275 . Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region. Further, by providing the insulator 273 over the region 231 of the oxide 230 , hydrogen in the oxide 230 can be extracted to the insulator 273 .

For example, as the insulator 273, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. be able to.

In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film having a thickness of 0.5 nm or more and 3.0 nm or less.

An insulator 274 is provided over the insulator 273 . As the insulator 274, a film having a barrier property and having a reduced hydrogen concentration is preferably used. For example, the insulator 274 may be formed using silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, or the like. By providing the insulator 273 with a barrier property and the insulator 274 with a barrier property, diffusion of impurities from another structure such as an interlayer film into the transistor 200A can be suppressed.

An insulator 280 functioning as an interlayer film is preferably provided over the insulator 274 . Like the insulator 224 and the like, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that an insulator 282 similar to the insulator 210 may be provided over the insulator 280 . By forming the insulator 282 by a sputtering method, impurities in the insulator 280 can be reduced. Further, an insulator 284 similar to the insulator 280 may be provided over the insulator 282 .

In addition, the conductors 240 a and 240 b are arranged in the openings formed in the insulators 284 , 282 , 280 , 274 , and 273 . The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be flush with the top surface of the insulator 284 .

Conductor 240a is in contact with region 231a functioning as one of the source and drain regions of transistor 200A, and conductor 240b is in contact with region 231b functioning as the other of the source and drain regions of transistor 200A. Thus, the conductor 240a can function as one of the source and drain electrodes, and the conductor 240b can function as the other of the source and drain electrodes.

Note that the conductor 240 a is formed in contact with the inner walls of the openings of the insulators 284 , 282 , 280 , 274 , and 273 . A region 231a of oxide 230 is located in at least part of the bottom of the opening, and a conductor 240a is in contact with region 231a. Similarly, a conductor 240 b is formed in contact with the inner walls of the openings of the insulators 284 , 282 , 280 , 274 and 273 . A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductor 240b contacts region 231b.

Here, the conductor 240a and the conductor 240b preferably overlap with the side surface of the oxide 230 as shown in FIG. In particular, the conductors 240a and 240b preferably overlap with one or both of the A5-side side and the A6-side side of the oxide 230 which intersects with the channel width direction. Alternatively, the conductor 240a and the conductor 240b may overlap with the side surface of the oxide 230 on the A1 side (A2 side) on the side surface of the oxide 230 that intersects with the channel length direction. In this manner, the conductor 240a and the conductor 240b overlap with the side surface of the oxide 230 (in particular, the region 231 serving as a source region or a drain region), whereby the conductor 240a and the conductor 240b overlap with each other. The contact area of the contact portion can be increased without increasing the projected area of the contact portion of the transistor 200A, and the contact resistance between the conductors 240a and 240b and the transistor 200A can be reduced. As a result, the on current can be increased while miniaturizing the source electrode and the drain electrode of the transistor.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductors 240a and 240b. Further, the conductor 240a and the conductor 240b may have a laminated structure.

Here, for example, when forming openings in insulator 284, insulator 282, insulator 280, insulator 274, and insulator 273, in oxide 230, the low resistance region of region 231 is removed, The non-low-resistance oxide 230 may be exposed. In that case, a metal film, a nitride film containing a metal element, or a metal element is used as a conductor that is in contact with the oxide 230 of the conductor 240 (hereinafter also referred to as a first conductor of the conductor 240). It is preferable to use an oxide film having a That is, when the oxide 230 whose resistance is not lowered and the first conductor of the conductor 240 are in contact with each other, oxygen vacancies are formed in the metal compound or the oxide 230 and the first conductor of the conductor 240 is formed. The contacting oxide 230 becomes low resistance. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, the contact resistance between the oxide 230 and the conductor 240 can be reduced. Therefore, the first conductor of the conductor 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, and tungsten.

In the case where the conductor 240 has a layered structure, the conductors in contact with the insulators 284, 282, 280, 274, and 273 include the first conductor of the conductor 205 and the like. Similarly, it is preferable to use a conductive material that has a function of suppressing permeation of impurities such as water or hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. In addition, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from a layer above the insulator 280 can be prevented from entering the oxide 230 through the conductors 240a and 240b.

Further, although not illustrated, a conductor functioning as a wiring may be arranged in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. A conductive material containing tungsten, copper, or aluminum as a main component is preferably used for the conductor functioning as the wiring. Further, the conductor may have a layered structure, for example, a layered structure of titanium, titanium nitride, and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator, similarly to the conductor 203 and the like.

<Semiconductor Device Constituent Materials>
Constituent materials that can be used for the semiconductor device are described below.

<<Substrate>>
As a substrate for forming a transistor according to one embodiment of the present invention, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include a capacitor element, a resistance element, a switch element, a light emitting element, a memory element, and the like.

Alternatively, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is also a method in which a transistor is manufactured over a non-flexible substrate, separated, and transferred to a flexible substrate. In that case, a peeling layer is preferably provided between the non-flexible substrate and the transistor. Also, the substrate may have stretchability. The substrate may also have the property of returning to its original shape when bending or pulling is ceased. Alternatively, it may have the property of not returning to its original shape. The substrate has a region with a thickness of, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of a semiconductor device having a transistor can be reduced. In addition, by making the substrate thin, even when glass or the like is used, it may have stretchability, or may have the property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to mitigate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, a durable semiconductor device can be provided.

As the flexible substrate, for example, metal, alloy, resin, glass, or fiber thereof can be used. Also, as the substrate, a sheet, film, foil, or the like in which fibers are woven may be used. A flexible substrate preferably has a lower coefficient of linear expansion because deformation due to the environment is suppressed. As the flexible substrate, for example, a material having a coefficient of linear expansion of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. . Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. In particular, aramid has a low coefficient of linear expansion, so it is suitable as a flexible substrate.

<<insulator>>
As insulators, there are insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like.

For example, as transistors are miniaturized and highly integrated, thinning of gate insulators may cause problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material should be selected according to the function of the insulator.

Insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. oxynitride or nitride with silicon and hafnium.

Insulators with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and an empty silicon oxide. Examples include silicon oxide or resin with pores.

In particular, silicon oxide and silicon oxynitride are also thermally stable. Therefore, for example, by combining with a resin, it is possible to obtain a laminated structure that is thermally stable and has a low dielectric constant. Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like. Further, for example, silicon oxide and silicon oxynitride can be combined with an insulator having a high dielectric constant to form a thermally stable stacked structure having a high dielectric constant.

In addition, when a transistor including an oxide semiconductor is surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, electrical characteristics of the transistor can be stabilized.

Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

For example, the insulators 273 and 282 are metal containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like. Oxides can be used.

In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film having a thickness of 0.5 nm or more and 3.0 nm or less. Hafnium oxide has a lower barrier property than aluminum oxide, but the barrier property can be improved by increasing the film thickness. Therefore, by adjusting the film thickness of hafnium oxide, the appropriate amounts of hydrogen and nitrogen to be added can be adjusted.

For example, insulator 224 and insulator 250, which function as part of the gate insulator, are preferably insulators with excess oxygen regions. For example, by forming a structure in which silicon oxide or silicon oxynitride having an excess oxygen region is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

Alternatively, for example, an insulator 222 that functions as part of the gate insulator can be an insulator including oxides of one or more of aluminum, hafnium, and gallium. In particular, as the insulator containing oxides of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and the like are preferably used.

For example, the insulator 220 is preferably made of silicon oxide or silicon oxynitride, which is stable against heat. As a gate insulator, a thin film equivalent to the equivalent oxide thickness (EOT) of the gate insulator can be obtained while maintaining the physical thickness by forming a layered structure of a film that is stable against heat and a film with a high dielectric constant. becomes possible.

With the laminated structure described above, the on-current can be improved without weakening the influence of the electric field from the gate electrode. In addition, by maintaining the distance between the gate electrode and the region where the channel is formed by the physical thickness of the gate insulator, the leakage current between the gate electrode and the channel formation region can be suppressed. .

The insulators 212, 216, 271, 275, 280, and 284 preferably have low dielectric constants. For example, the insulator 212, the insulator 216, the insulator 271, the insulator 275, the insulator 280, and the insulator 284 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, and carbon. It is preferable to have doped silicon oxide, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, resin, or the like. Alternatively, the insulator 212, the insulator 216, the insulator 271, the insulator 275, the insulator 280, and the insulator 284 may contain silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, or carbon. It is preferable to have a layered structure of doped silicon oxide, silicon oxide doped with carbon and nitrogen, or silicon oxide having holes, and a resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

As the insulator 210, the insulator 214, the insulator 270, the insulator 273, the insulator 284, and the insulator 282, insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. Examples of the insulator 210, the insulator 214, the insulator 270, the insulator 273, the insulator 284, and the insulator 282 include aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, A metal oxide such as lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like may be used.

<<Conductor>>
The conductor is a metal selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more elements can be used. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Alternatively, a plurality of conductive layers formed using any of the above materials may be stacked and used. For example, a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used. Alternatively, a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined. Alternatively, a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.

Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked-layer structure in which the above-described material containing the metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode. is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed from an outer insulator or the like.

Conductors 260, 203, 205, and 240 include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, and magnesium. , zirconium, beryllium, indium, and ruthenium. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

<<metal oxide>>
A metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used as the oxide 230 . Metal oxides applicable to the oxide 230 according to the present invention are described below.

The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. In addition to these, aluminum, gallium, yttrium, tin, or the like is preferably contained. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

Consider here the case where the metal oxide is an In--M--Zn oxide with indium, the element M and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above elements may be combined.

In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[Structure of Metal Oxide]
A structure of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

In this specification and the like, it may be referred to as CAAC (c-axis aligned crystal) and CAC (cloud-aligned composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function in the whole material. Note that when CAC-OS or CAC-metal oxide is used for the active layer of a transistor, the conductive function is to flow electrons (or holes) that serve as carriers, and the insulating function is to serve as carriers. It is a function that does not flow electrons. A switching function (on/off function) can be imparted to the CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

CAC-OS or CAC-metal oxide also has a conductive region and an insulating region. The conductive regions have the above-described conductive function, and the insulating regions have the above-described insulating function. In some materials, the conductive region and the insulating region are separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected like a cloud with its periphery blurred.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. There is

Also, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from an insulating region and a component having a narrow gap resulting from a conductive region. In the case of this configuration, when the carriers flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having a narrow gap acts complementarily on the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, high current drivability, that is, large on-current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[Structure of Metal Oxide]
Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include, for example, CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductors), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductor, and the like.

CAAC-OS has a c-axis orientation and a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. Also, the distortion may have a lattice arrangement of pentagons, heptagons, and the like. In CAAC-OS, it is difficult to confirm clear crystal grain boundaries (also called grain boundaries) even in the vicinity of strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. It's for.

CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is substituted with indium, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, since it is difficult to confirm a clear crystal grain boundary, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. In addition, since the crystallinity of a metal oxide may be degraded by contamination with impurities, generation of defects, or the like, CAAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, a metal oxide containing CAAC-OS is heat resistant and highly reliable.

The nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Also, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

An a-like OS is a metal oxide having a structure between an nc-OS and an amorphous oxide semiconductor. An a-like OS has void or low density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors (metal oxides) have various structures, each of which has different characteristics. An oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[Transistor with Metal Oxide]
Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described.

Note that by using the above metal oxide for a channel formation region of a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

A metal oxide with low carrier density is preferably used for a transistor. In order to lower the carrier density of the metal oxide film, the impurity concentration in the metal oxide film should be lowered to lower the defect level density. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the metal oxide has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and a carrier density of 1×10 ⁻⁹ /cm 3 . cm ³ or more.

In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low.

In addition, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave like a fixed charge. Therefore, a transistor including a metal oxide with a high trap level density in a channel formation region may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. Moreover, in order to reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[impurities]
Here, the effect of each impurity in the metal oxide will be described.

If the metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2. ×10 ¹⁸ atoms/cm ³ or less, preferably 2 × 10 ¹⁷ atoms/cm ³ or less.

Further, if the metal oxide contains an alkali metal or an alkaline earth metal, it may form a defect level and generate carriers. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

In addition, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density increases, and the metal oxide tends to be n-type. As a result, a transistor using a metal oxide containing nitrogen for a channel formation region tends to have normally-on characteristics. Therefore, nitrogen in the channel formation region in the metal oxide is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5×10 ¹⁹ atoms/cm ³ in SIMS, preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and further preferably 1×10 18 atoms/cm 3 or less. It is preferably 5×10 ¹⁷ atoms/cm ³ or less.

In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons, which are carriers, are generated in some cases. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm Less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing a semiconductor device having the transistor 200A according to the present invention will be described with reference to FIGS. 3 to 13, (A) in each figure shows a top view. In addition, (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in (A). (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A). (D) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in (A).

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. The insulator 210 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic It can be carried out using a layer deposition (ALD: Atomic Layer Deposition) method or the like.

The CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, the method can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.

The plasma CVD method can obtain high quality films at relatively low temperatures. Moreover, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased. Moreover, since the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The ALD method is also a film forming method capable of reducing plasma damage to the object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained. Some precursors used in the ALD method contain impurities such as carbon. Therefore, a film formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of the object to be processed, unlike film forming methods in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.

In the CVD method and the ALD method, the composition of the film obtained can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method and the ALD method, it is possible to form a film of any composition depending on the flow rate ratio of source gases. Further, for example, in the CVD method and the ALD method, it is possible to form a film whose composition is continuously changed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation is reduced compared to film formation using multiple film formation chambers, as the time required for transportation and pressure adjustment is not required. can do. Therefore, productivity of semiconductor devices can be improved in some cases.

In this embodiment, the insulator 210 is formed using aluminum oxide by a sputtering method. Moreover, the insulator 210 may have a multilayer structure. For example, a structure in which an aluminum oxide film is formed by a sputtering method and an aluminum oxide film is formed on the aluminum oxide film by an ALD method may be employed. Alternatively, a structure may be employed in which aluminum oxide is deposited by an ALD method and aluminum oxide is deposited over the aluminum oxide by a sputtering method.

Next, an insulator 212 is formed over the insulator 210 . The insulator 212 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is deposited as the insulator 212 by a CVD method.

Next, an opening is formed in the insulator 212 to reach the insulator 210 . The opening includes, for example, grooves and slits. Also, an area in which an opening is formed may be referred to as an opening. A wet etching method may be used to form the opening, but it is preferable to use a dry etching method for fine processing. For the insulator 210, it is preferable to select an insulator that functions as an etching stopper film when the insulator 212 is etched to form an opening. For example, when a silicon oxide film is used for the insulator 212 forming the opening, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used for the insulator 210 as an insulating film functioning as an etching stopper film.

After forming the opening, a conductive film to be the first conductor of the conductor 203 is formed. The conductive film preferably contains a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductive film to be the first conductor of the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, as the conductive film serving as the first conductor of the conductor 203, a film of tantalum nitride or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using such a metal nitride as the first conductor of the conductor 203, even if a metal such as copper which is easily diffused is used as a second conductor of the conductor 203 to be described later, the metal can be used as the conductor 203. can be suppressed from diffusing to the outside from the first conductor.

Next, a conductive film to be the second conductor of the conductor 203 is formed over the conductive film to be the first conductor of the conductor 203 . The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a low-resistance conductive material such as copper is deposited as a conductive film to be the second conductor of the conductor 203 .

Next, by performing CMP (chemical mechanical polishing) treatment, part of the conductive film to be the first conductor of the conductor 203 and part of the conductive film to be the second conductor of the conductor 203 are removed. , exposing the insulator 212 . As a result, the conductive film to be the first conductor of the conductor 203 and the conductive film to be the second conductor of the conductor 203 remain only in the opening. Thus, the conductor 203 including the first conductor of the conductor 203 and the second conductor of the conductor 203 having a flat top surface can be formed (see FIG. 3). Note that part of the insulator 212 may be removed by the CMP treatment.

Next, an insulator 214 is formed over the insulator 212 and the conductor 203 . The insulator 214 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a silicon nitride film is formed as the insulator 214 by a CVD method. In this way, by using an insulator such as silicon nitride through which copper is difficult to permeate as the insulator 214 , even if a metal such as copper which is easily diffused is used as the second conductor of the conductor 203 , the metal is insulated. Diffusion into layers above body 214 can be suppressed.

Next, an insulator 216 is formed over the insulator 214 . The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the insulator 216 is formed using silicon oxide by a CVD method.

Next, an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216 . A wet etching method may be used to form the opening, but it is preferable to use a dry etching method for fine processing.

After the opening is formed, a conductive film to be the first conductor of the conductor 205 is formed. A conductive film that serves as the first conductor of the conductor 205 preferably contains a conductive material that has a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductive film to be the first conductor of the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, tantalum nitride is deposited by a sputtering method as the conductive film to be the first conductor of the conductor 205 .

Next, a conductive film to be the second conductor of the conductor 205 is formed over the conductive film to be the first conductor of the conductor 205 . The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, as the conductive film serving as the second conductor of the conductor 205, a titanium nitride film is formed by a CVD method, and tungsten is formed over the titanium nitride film by a CVD method.

Next, by performing CMP treatment, part of the conductive film serving as the first conductor of the conductor 205 and part of the conductive film serving as the second conductor of the conductor 205 are removed, and the insulator 216 is exposed. do. As a result, the conductive film to be the first conductor of the conductor 205 and the conductive film to be the second conductor of the conductor 205 remain only in the opening. Thus, the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 having a flat top surface can be formed (see FIG. 3). Note that part of the insulator 216 is removed by the CMP treatment in some cases.

Next, an insulator 220 is formed over the insulator 216 and the conductor 205 . The insulator 220 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 220 by a CVD method.

Next, an insulator 222 is formed over the insulator 220 . As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. Note that as the insulator containing oxides of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200A into the transistor 200A through the insulator 222 is suppressed. , the generation of oxygen vacancies in the oxide 230 can be suppressed.

The insulator 222 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an insulator 224 is formed over the insulator 222 . The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 3). In this embodiment mode, silicon oxide is deposited as the insulator 224 by a CVD method.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Moreover, you may perform heat processing in a pressure-reduced state. Alternatively, heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen. may

In this embodiment mode, heat treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere after the insulator 224 is formed. By the heat treatment, impurities such as hydrogen and water contained in the insulator 224 can be removed.

Alternatively, the heat treatment can be performed after the insulator 220 is deposited and after the insulator 222 is deposited. Although the above heat treatment conditions can be used for the heat treatment, the heat treatment after the insulator 220 is formed is preferably performed in an atmosphere containing nitrogen.

Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For plasma treatment containing oxygen, it is preferable to use an apparatus having a power supply that generates high-density plasma using microwaves, for example. Alternatively, the board may have a power supply for applying RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. can. Alternatively, plasma treatment containing an inert gas may be performed using this apparatus, and then plasma treatment containing oxygen may be performed to compensate for desorbed oxygen. Note that impurities such as hydrogen and water contained in the insulator 224 can be removed by appropriately selecting conditions for the plasma treatment. In that case, heat treatment may not be performed.

Next, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are formed in this order over the insulator 224 (see FIG. 4). Note that the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B. can be kept clean.

The oxide films 230A and 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, when the oxide films 230A and 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. Further, when the above oxide film is formed by a sputtering method, the above In--M--Zn oxide target can be used.

In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when forming the oxide film 230A. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230A should be 70% or more, preferably 80% or more, more preferably 100%.

In the case of forming the oxide film 230B by a sputtering method, if the oxygen content in the sputtering gas is 1% to 30%, preferably 5% to 20%, an oxygen-deficient oxide semiconductor is formed. It is formed. A transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region has relatively high field-effect mobility.

In this embodiment, the oxide film 230A is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio]. Also, the oxide film 230B is formed by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio]. It should be noted that each oxide film may be formed in accordance with the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and the atomic ratio.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. Impurities such as hydrogen and water in the oxide films 230A and 230B can be removed by heat treatment. In this embodiment mode, treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, and then treatment is continuously performed at a temperature of 400° C. in an oxygen atmosphere for 1 hour.

Next, the oxide films 230A and 230B are processed into an island shape to form oxides 230a and 230b (see FIG. 5).

Here, the oxides 230 a and 230 b are formed so that at least part of them overlaps with the conductor 205 . Side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the top surface of the insulator 222 . Since the side surfaces of the oxide 230a and the oxide 230b are substantially perpendicular to the top surface of the insulator 222, the area can be reduced and the density can be increased when a plurality of transistors 200A are provided. Note that the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may form an acute angle. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably as large as possible.

In addition, curved surfaces are provided between the side surfaces of the oxides 230a and 230b and the top surface of the oxide 230b. That is, it is preferable that the edge of the side surface and the edge of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the oxide 230b. Since the edges do not have corners, the coverage of the film in the subsequent film forming process is improved.

Note that processing of the oxide film may be performed using a lithography method. A dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.

In the lithographic method, first, a resist is exposed through a mask. The exposed regions are then removed or left behind using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching treatment through the resist mask. For example, a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Also, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, direct drawing is performed on the resist, so the mask for resist exposure is not necessary. Note that the resist mask can be removed by performing dry etching treatment such as ashing, performing wet etching treatment, performing wet etching treatment after dry etching treatment, performing dry etching treatment after wet etching treatment, or the like. .

A hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material is formed on the oxide film 230B, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do. The etching of the oxide film 230A and the oxide film 230B may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the oxide film, the hard mask may be removed by etching. On the other hand, if the hard mask material does not affect the post-process, or if it can be used in the post-process, it is not always necessary to remove the hard mask.

As a dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, a plurality of different high-frequency power sources may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency power source of the same frequency may be applied to each parallel plate type electrode. Alternatively, a configuration in which high-frequency power sources with different frequencies are applied to the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source.

Further, by performing the above-described dry etching or the like, impurities caused by an etching gas or the like may adhere to or diffuse onto or inside the oxides 230a and 230b. Impurities include, for example, fluorine or chlorine.

Cleaning is performed to remove the above impurities. As a cleaning method, there are wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, or the like, and the above cleaning may be performed in combination as appropriate.

Wet cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning is performed using pure water or carbonated water.

Subsequently, heat treatment may be performed. As the conditions for the heat treatment, the conditions for the heat treatment described above can be used.

Next, an oxide film 230C to be the oxide 230c is formed over the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 6).

The oxide film 230C can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide film 230C may be formed using a film formation method similar to that for the oxide film 230A or the oxide film 230B in accordance with the characteristics required for the oxide 230c. In this embodiment, the oxide film 230C is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio].

Subsequently, an insulating film 250A, a metal oxide film 252A, a conductive film 260A, a conductive film 260B, an insulating film 270A, and an insulating film 271A are sequentially formed on the oxide film 230C (see FIG. 6).

First, an insulating film 250A is formed. The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, silicon oxynitride is preferably deposited by a CVD method. The film formation temperature for forming the insulating film 250A is preferably 350.degree. C. or more and less than 450.degree. By forming the insulating film 250A at 400° C., an insulator with few impurities can be formed.

Note that oxygen can be introduced into the insulating film 250A by exciting oxygen with microwaves to generate high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma.

Alternatively, heat treatment may be performed. For the heat treatment, the heat treatment conditions described above can be used. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulating film 250A can be reduced.

Subsequently, a metal oxide film 252A, a conductive film 260A, and a conductive film 260B are formed. As the metal oxide film 252A, an In--Ga--Zn oxide is formed by a sputtering method. As a method for forming the metal oxide film 252A, it is preferable to use a sputtering method and form it in an atmosphere containing oxygen gas. By forming the metal oxide film 252A in an atmosphere containing oxygen gas, an excess oxygen region can be formed in the insulating film 250A. Excess oxygen added to the insulating film 250A supplies oxygen to the oxide 230, so that oxygen vacancies in the oxide 230 can be compensated.

Here, as a means for forming the metal oxide film 252A, a sputtering apparatus is used to form the film in an oxygen gas atmosphere. oxygen can be introduced into the Moreover, by using one or both oxides of aluminum and hafnium having barrier properties for the metal oxide film 252A, excess oxygen introduced into the insulating film 250A can be effectively confined.

The conductive films 260A and 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to deposit titanium nitride as the conductive film 260A and deposit tungsten as the conductive film 260B.

For example, as the conductive film 260A, a metal nitride may be formed by a sputtering method. For example, when an oxide semiconductor typified by an In--Ga--Zn oxide is used as the metal oxide film 252A, the metal oxide film 252A is supplied with nitrogen or hydrogen to increase the carrier density. That is, it functions as an oxide conductor (OC). Therefore, by forming a metal nitride by sputtering as the conductive film 260A, constituent elements (especially nitrogen) in the metal nitride are diffused into the metal oxide film 252A, and the resistance of the metal oxide film 252A is lowered. Also, the resistance of the metal oxide film 252A is reduced due to damage (for example, sputtering damage) during the formation of the conductive film 260A. Therefore, the carrier density of the metal oxide film 252A is increased, and the electrical conductivity of the metal oxide film 252A is increased.

Further, by stacking a low-resistance metal film as the conductive film 260B, a transistor with low driving voltage can be provided.

A heat treatment can then be performed. For the heat treatment, the heat treatment conditions described above can be used. Note that the heat treatment may not be performed in some cases. By this heat treatment, excess oxygen is added to the insulating film 250A from the metal oxide film 252A, and an excess oxygen region can be easily formed in the insulating film 250A.

The insulating film 270A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, it is preferable to use aluminum oxide or hafnium oxide. Thereby, oxidation of the conductor 260 can be suppressed. In addition, entry of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed. In this embodiment, an aluminum oxide film is formed as the insulating film 270A by the ALD method.

The insulating film 271A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the film thickness of the insulating film 271A is preferably thicker than the film thickness of the insulating film 275A to be formed in a later step. Accordingly, the insulator 271 can be easily left over the conductor 260 when the insulator 275 is formed in a later step. In this embodiment, silicon oxide is deposited by a CVD method as the insulating film 271A.

Next, the insulator 271 is formed by etching the insulating film 271A. Here, insulator 271 functions as a hard mask. By providing the insulator 271, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260a, the side surface of the conductor 260b, and the side surface of the insulator 270 are substantially perpendicular to the top surface of the substrate. can be formed.

Next, using the insulator 271 as a mask, the oxide film 230C, the insulating film 250A, the metal oxide film 252A, the conductive film 260A, the conductive film 260B, and the insulating film 270A are etched, and the oxide 230c, the insulator 250, and the metal oxide film are etched. An object 252, a conductor 260 (a conductor 260a and a conductor 260b), and an insulator 270 are formed (see FIG. 7).

At least part of the oxide 230 c , the insulator 250 , the metal oxide 252 , the conductor 260 , the insulator 270 , and the insulator 271 overlaps with the conductor 205 and the oxide 230 .

Moreover, the side surface of the oxide 230c, the side surface of the insulator 250, the side surface of the metal oxide 252, the side surface of the conductor 260, and the side surface of the insulator 270 are preferably in the same plane.

Also, the same plane shared by the side of oxide 230c, the side of insulator 250, the side of metal oxide 252, the side of conductor 260, and the side of insulator 270 is substantially perpendicular to the top surface of the substrate. is preferred. That is, in the cross-sectional shape, the angle formed by the side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230 is preferably acute and large. Note that in the cross-sectional shape, the side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230 may form an acute angle. In that case, the angle between the side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 and the top surface of the oxide 230 is preferably as large as possible.

Note that post-processes may be performed without removing the hard mask (insulator 271) after the above processing.

Next, an insulating film 275A is formed to cover the oxide 230, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 8).

The insulating film 275A preferably has an insulator with a low dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, resin, or the like is used. It is preferable to have In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies for the insulating film 275A because an excess oxygen region can be easily formed in the insulator 275 in a later step. In addition, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Next, an anisotropic etching treatment is performed on the insulating film 275A to form an insulator 275 on the side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 (see FIG. 9). reference.). Note that in this step, the insulator 224 may be processed into an island shape. In that case, the insulator 222 can be used as an etching stopper film.

Although not shown, the insulator 275 may remain on the side surface of the insulator 224 as well. In that case, it is possible to improve the coating property of an interlayer film or the like to be formed in a later step. In addition, since the structure in which the insulator 275 remains is formed in contact with the side surface of the insulator 224, the insulator 224 can also be provided with an excess oxygen region.

Subsequently, a film 242A is formed over the insulator 224 and the oxide 230 with the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 275 interposed therebetween (FIG. 10). Note that the film 242A may have a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less. A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used for the film 242A. The film 242A is, for example, a film containing metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium. Note that the film 242A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, heat treatment is performed (see FIG. 11). The heat treatment in the nitrogen-containing atmosphere causes the metal element that is a component of the film 242A to diffuse from the film 242A into the oxide 230 or the metal element that is a component of the oxide 230 into the film 242A, thereby forming the oxide 230. Then, the film 242A forms a metal compound, and the resistance can be lowered. By forming a metal compound between the oxide 230 and the film 242A, a relatively stable state can be obtained; therefore, a highly reliable semiconductor device can be provided.

Here, the layer 242 is formed by forming a metal compound with the metal element of the film 242A and the metal element of the oxide 230 . Also, a compound layer may be formed at the interface between the film 242A and the oxide 230 . Note that the compound layer is a layer having a metal compound containing a component of the film 242A and a component of the oxide 230. FIG. In addition, in this specification, the layer 242 may include a compound layer. For example, as the compound layer, a layer in which the metal element of the oxide 230 and the metal element of the film 242A are alloyed may be formed. By alloying, the metal elements are in a relatively stable state, and a highly reliable semiconductor device can be provided.

The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Moreover, you may perform heat processing in a pressure-reduced state.

Oxygen near the interface between oxide 230 and layer 242 may also be absorbed by layer 242 . As a result, the vicinity of the interface between oxide 230 and layer 242 becomes low in resistance (see FIG. 11). On the other hand, the layer 242 may be oxidized by oxygen absorbed from the oxide 230, become an insulator, and have a high resistance.

At that time, part of the oxide 230 and the metal element described above may be alloyed. By alloying part of the oxide 230 with the metal element, the metal element added to the oxide 230 is in a relatively stable state, so that a highly reliable semiconductor device can be provided. Also, the layer 242 with increased resistance may be used as an interlayer film.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

Alternatively, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.

Further, when a region having conductivity remains in the layer 242, heat treatment is performed in an oxidizing atmosphere to oxidize the layer 242, so that the layer 242 becomes an insulator and has a high resistance. By leaving the layer 242 as an insulator, it can function as an interlayer film.

In the formation step of the layer 242 or heat treatment, oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the layer 242, so that oxygen vacancies are generated in the regions 231 and 232. may occur. Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are n-type and have a low resistance.

Note that layer 242 may be removed. For example, a dry etching method or a wet etching method can be used as a removing method. By removing the layer 242, hydrogen in the oxide 230 absorbed in the layer 242 can be removed at the same time. Therefore, hydrogen which is an impurity in the transistor 200A can be reduced.

Subsequently, an insulator 273 is formed over the insulator 275 and the oxide 230 (see FIG. 12).

Further, the insulator 273 is preferably formed using a sputtering method. By using a sputtering method, an insulator containing few impurities such as water or hydrogen can be formed. For example, aluminum oxide is preferably used as the insulator 273 .

In addition, film formation is performed in an oxygen gas atmosphere using a sputtering apparatus, so that oxygen can be introduced into the insulator 275 while the insulator 273 is being formed. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies is used as the insulator 275, an excess oxygen region tends to be easily formed in the insulator 275. On the other hand, the oxide 230 tends to be less susceptible to the formation of excess oxygen regions than the silicon oxide discussed above. In addition, an oxide film formed by sputtering may extract hydrogen from a structure to be deposited. Therefore, for example, when an oxide film is formed as the insulator 273 by sputtering, an excess oxygen region can be selectively formed in the insulator 275 . Further, at this time, since an excess oxygen region is less likely to be formed in the oxide 230, it is possible to suppress the above-described low resistance region in the oxide 230 from increasing in resistance. Further, by absorbing hydrogen and water from the oxide 230 and the insulator 275, the hydrogen concentrations of the oxide 230 and the insulator 275 can be reduced.

The insulator 275 with the excess oxygen regions formed as described above can effectively supply oxygen from the excess oxygen regions to the regions 234 of the oxide 230 .

With the above structure, each region of the oxide 230 can be formed in a self-aligned manner. Therefore, miniaturized or highly integrated semiconductor devices can be manufactured with a high yield.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

A heat treatment can then be performed. For the heat treatment, the heat treatment conditions described above can be used. By the heat treatment, hydrogen trapped in oxygen vacancies formed in the region 231 of the oxide 230 is absorbed by the insulator 273, so that hydrogen in the oxide 230 can be reduced.

Next, an insulator 274 is formed over the insulator 273 (see FIG. 12). The insulator 274 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulator 274 preferably does not use a hydrogen gas as a deposition gas. By not using hydrogen gas, an insulating film with a reduced hydrogen concentration can be formed. For example, as the insulator 274, a silicon nitride film is preferably formed by a CVD method using silane (SiH ₄ ) and nitrogen (N ₂ ) gases.

Next, an insulator 280 is formed over the insulator 274 (see FIG. 12). The insulator 280 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (inkjet method, etc.), a printing method (screen printing, offset printing, etc.), a doctor knife method, a roll coater method, a curtain coater method, or the like can be used. . For example, silicon oxynitride may be used as the insulator 280 .

Next, a portion of insulator 280 is removed. The insulator 280 is preferably formed to have a flat upper surface. For example, the insulator 280 may have a flat upper surface immediately after being deposited. Alternatively, for example, the insulator 280 may have flatness by removing the insulator or the like from the top surface so as to be parallel to a reference plane such as the back surface of the substrate after deposition. Such processing is called planarization processing. Planarization processing includes CMP processing, dry etching processing, and the like. In this embodiment mode, CMP treatment is used as the planarization treatment. However, the top surface of the insulator 280 does not necessarily have to be flat.

Subsequently, an insulator 282 is formed over the insulator 280 . The insulator 282 is preferably deposited using a sputtering apparatus. With such a structure, hydrogen can be prevented from entering the structure below the insulator 282 . In addition, since hydrogen or water in the insulator 280 is absorbed by the insulator 282, the impurity concentration in the insulator 280 can be reduced.

Subsequently, an insulator 284 is formed over the insulator 282 (see FIG. 12). For example, as the insulator 284, an insulator containing oxygen such as a silicon oxide film or a silicon oxynitride film is formed by a CVD method. Insulator 284 preferably has a lower dielectric constant than insulator 282 . By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

Openings are then formed in insulator 284 , insulator 282 , insulator 280 , insulator 274 , and insulator 273 down to oxide 230 . The formation of the opening may be performed using a lithography method. Note that the openings reaching the oxide 230 are formed so that the side surfaces of the oxide 230 are exposed so that the conductors 240 a and 240 b are provided in contact with the side surfaces of the oxide 230 .

Next, a conductive film to be the first conductor of the conductor 240 and a conductive film to be the second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when forming openings in the insulators 284 , 282 , 280 , 274 , and 273 , the low-resistance region of the region 231 may be removed. In that case, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used as the first conductor of the conductor 240 . That is, since the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen vacancies are formed in the contact region, and the resistance of the contact region between the oxide 230 and the conductor 240 is reduced. be able to. Sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured by reducing the resistance of the oxide 230 that is in contact with the first conductor of the conductor 240 . Therefore, the first conductor of the conductor 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium.

Next, CMP treatment is performed to remove part of the conductive film to be the conductors 240 a and 240 b to expose the insulator 284 . As a result, the conductive film remains only in the openings, so that the conductors 240a and 240b with flat top surfaces can be formed (see FIG. 13).

Through the above steps, a semiconductor device including the transistor 200A can be manufactured. As illustrated in FIGS. 3 to 13, the transistor 200A can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

<Modified Example of Semiconductor Device>
Examples of a semiconductor device including a transistor 200A according to one embodiment of the present invention are described below with reference to FIGS.

Here, (A) in each figure shows a top view. In addition, (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in (A). (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A). (D) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in (A). In the top view of each figure (A), some elements are omitted for clarity of illustration.

Note that in the semiconductor devices shown in FIGS. 14 to 17, structures having the same functions as the structures constituting the semiconductor devices shown in <Structure Example of Semiconductor Device> are denoted by the same reference numerals.

Structures of semiconductor devices are described below with reference to FIGS. Note that in this item as well, the materials described in detail in <Structure Example of Semiconductor Device> can be used as constituent materials of the semiconductor device.

[Modification 1 of semiconductor device]
In the semiconductor device shown in FIG. 14, the side surface of oxide 230 and the surface parallel to the substrate have a taper angle. Specifically, as shown in FIG. 14B, the taper angle (θ) should be 45° or more and 80° or less, preferably 50° or more and 70° or less. Since the oxide 230 has a tapered structure, the side surface of the oxide 230 can be exposed when the insulator 275 is subjected to anisotropic etching treatment.

Accordingly, the side surfaces of the oxide 230 are also in contact with the film 242A, forming a metal compound and reducing the resistance. That is, regions 231 can also be formed on the sides of oxide 230 . In addition, since the oxide 230 has a tapered structure, the coating property of the structure formed above the oxide 230 can be improved.

[Modification 2 of semiconductor device]
The semiconductor device shown in FIG. 15 differs from the semiconductor device shown in <Structure Example of Semiconductor Device> in that the insulating region of the layer 242 is removed. Specifically, layer 242 may be left only on oxide 230, as shown in FIG. Alternatively, if metal compounds are formed in oxide 230, layer 242 may be removed. Therefore, region 231 may be formed in oxide 230 only.

Note that when the layer 242 has the property of absorbing hydrogen, the hydrogen in the oxide 230 is absorbed into the layer 242 . Therefore, by removing the layer 242, the hydrogen absorbed from the oxide 230 can also be removed. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced.

[Modification 3 of semiconductor device]
The semiconductor device shown in FIG. 16 differs from the semiconductor device shown in <Structure Example of Semiconductor Device> in the shape of the conductor 240 . That is, the semiconductor device shown in <Structure Example of Semiconductor Device> has a structure in which the conductor 240 is provided in contact with the insulators 280, 282, and 284 functioning as interlayer films. On the other hand, in the semiconductor device shown in FIG. 16, openings are provided in insulators 273 and 274 to form conductors 240 . That is, the conductor 240 has a structure not in contact with the interlayer film. Therefore, impurities in the insulator functioning as an interlayer film can be prevented from diffusing through the conductor 240 into the transistor 200A. Therefore, an insulator having a barrier property is preferably provided over the conductor 240 .

[Modification 4 of semiconductor device]
The semiconductor device shown in FIG. 17 differs from the semiconductor device shown in <Structure Example of Semiconductor Device> in that barriers are provided between the conductor 240 and insulators 280, 282, and 284 functioning as interlayer films. The difference is that insulators 276 (insulators 276a and 276b) functioning as layers are provided. Note that in this structure, the insulator 276 and the insulator 282 preferably have barrier properties against oxygen, hydrogen, and water.

Specifically, as shown in FIG. 17, an insulator 276 is preferably provided between the conductor 240, the insulator 280, and the insulator 282 having a barrier property. In particular, the insulator 276 is preferably provided in contact with the insulator 282 having a barrier property. Since the insulator 276 and the insulator 282 are provided in contact with each other, the insulator 276 extends to the insulator 284, so that diffusion of oxygen and impurities can be further suppressed.

In other words, provision of the insulator 276 can prevent impurities in the insulator 280 from diffusing into the transistor 200A through the conductor 240 and reducing the reliability of the semiconductor device. In addition, by providing the insulator 276, it is possible to widen the selection range of materials for conductors used for plugs and wirings.

A metal oxide can be used for the insulator 276, for example. In particular, it is preferable to use an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Alternatively, silicon nitride formed by a CVD method may be used.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 2)
An example of a semiconductor device including a transistor 200B according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 200A described in Embodiment 1, will be described below.

Note that in the semiconductor device described in this embodiment, structures having the same functions as the structures constituting the semiconductor devices described in the previous embodiments are denoted by the same reference numerals. Therefore, differences from the semiconductor device shown in the previous embodiment will be mainly described, and repeated descriptions will be omitted. Further, if there is no particular description of materials, functions, manufacturing methods, and the like of structures denoted by the same reference numerals, the materials, functions, manufacturing methods, and the like of the structures refer to the contents described in the above embodiments. be able to.

<Structure example of semiconductor device>
FIGS. 18A, 18B, 18C, and 18D are a top view and a cross-sectional view of a transistor 200B and its periphery according to one embodiment of the present invention.

FIG. 18A is a top view of a semiconductor device including a transistor 200B. 18B, 18C, and 18D are cross-sectional views of the semiconductor device. Here, FIG. 18B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 18A, and is also a cross-sectional view in the channel length direction of the transistor 200B. FIG. 18C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 18A, and is also a cross-sectional view in the channel width direction of the transistor 200B. FIG. 18D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 18A, and is also a cross-sectional view of the source region or drain region of the transistor 200B. Note that in the top view of FIG. 18A, some elements are omitted for clarity.

A semiconductor device of one embodiment of the present invention includes a transistor 200B and insulators 210, 212, 280, 282, and 284 functioning as interlayer films. It also includes a conductor 203 that is electrically connected to the transistor 200B and functions as a wiring, and a conductor 240 (a conductor 240a and a conductor 240b) that functions as a plug.

The conductor 240 is formed in contact with the inner walls of the openings of the insulators 275 , 273 , 274 , 280 , 282 , and 284 . Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 284 can be made approximately the same. Note that although the structure in which the conductor 240 has a two-layer laminated structure is shown in this embodiment mode, the present invention is not limited to this. For example, the conductor 240 may be a single layer or a laminated structure of three or more layers.

[Transistor 200B]
The transistor 200B illustrated in FIG. 18 includes at least the oxide 230c, the insulator 250, the metal oxide 252, and the insulator 272 which is in contact with the sides of the conductor 260, and the oxide 230 and the insulator 272. It has layer 242 disposed thereon, an insulator 275 disposed on layer 242, an insulator 273 disposed on insulator 275, and an insulator 274 disposed on insulator 273. It is different from the transistor 200A shown in the first embodiment in that point.

In the transistor 200B, an oxide semiconductor is preferably used for the oxides 230 (the oxides 230a, 230b, and 230c) including a channel formation region.

Since the transistor 200B including an oxide semiconductor for a channel formation region has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. Further, since an oxide semiconductor can be deposited by a sputtering method or the like, it can be used for the transistor 200B included in a highly integrated semiconductor device.

Here, the oxide semiconductor forms a metal compound with low resistance by adding metal elements such as aluminum, ruthenium, titanium, tantalum, chromium, and tungsten in addition to the elements constituting the oxide semiconductor. become Note that it is preferable to use aluminum, titanium, tantalum, tungsten, or the like.

In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. Further, when the film is provided, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film or the like to form oxygen vacancies. The vicinity of the interface may have a low resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment is preferably performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is converted into an oxide semiconductor by the metal element as a component of the film, or as a component of the oxide semiconductor. A certain metal element diffuses into the film, the oxide semiconductor and the film form a metal compound, and the resistance can be reduced. The metal element added to the oxide semiconductor forms a metal compound with the oxide semiconductor and the metal element, so that the metal element is in a relatively stable state; therefore, a highly reliable semiconductor device can be provided.

A compound layer (different layer) may be formed at the interface between the metal film, the nitride film containing the metal element, or the oxide film containing the metal element, and the oxide semiconductor. Note that the compound layer (different layer) is a layer having a metal compound containing a component of a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, and a component of an oxide semiconductor. For example, as the compound layer, a layer in which the metal element of the oxide semiconductor and the added metal element are alloyed may be formed. The alloyed layer is in a relatively stable state and can provide a highly reliable semiconductor device.

In addition, when hydrogen existing in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor and enters oxygen vacancies in the low-resistance region, the hydrogen is in a relatively stable state. Further, hydrogen in the oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and oxygen vacancies existing in the low-resistance region. It is known that it enters into the inside and becomes a relatively stable state. Therefore, by heat treatment, the resistance of the region where the resistance of the oxide semiconductor is reduced or the region where the metal compound is formed is further reduced, and the oxide semiconductor which is not reduced in resistance is purified (impurities such as water and hydrogen). reduction) and tends to increase the resistance.

In addition, the oxide semiconductor has an increased carrier density when an impurity element such as hydrogen or nitrogen is present. Hydrogen in the oxide semiconductor reacts with oxygen that bonds to a metal atom to become water, which may cause oxygen vacancies. When hydrogen enters the oxygen vacancies, the carrier density increases. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to an oxide semiconductor, a high-resistance region and a low-resistance region can be provided in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the island-shaped oxide 230 has a region functioning as a semiconductor with low carrier density and a region functioning as a source region or a drain region. A region can be provided.

Here, FIG. 19 shows an enlarged view of a region 239 surrounded by a broken line in FIG.

As shown in FIG. 19, the oxide 230 includes a region 234 functioning as a channel formation region of a transistor, regions 231 (regions 231a and 231b) functioning as a source region or a drain region, and regions 234 and 231. and a region 232 (region 232a and region 232b) provided between.

Region 232 has a region that overlaps insulator 272 .

To reduce the resistance of region 231 , for example, layer 242 may be deposited in contact with region 231 of oxide 230 . As the layer 242, a metal film, a nitride film containing a metal element, an oxide film containing a metal element, or the like can be used. Layer 242 is preferably provided over oxide 230 with at least insulator 250 , metal oxide 252 , conductor 260 , insulator 270 , insulator 271 , and insulator 272 interposed therebetween.

By contacting the oxide 230 and the layer 242, the components of the layer 242 and the oxide 230 form a metal compound, which becomes the region 231 and has a low resistance. In addition, part of the oxygen in the oxide 230 located at or near the interface between the oxide 230 and the layer 242 is absorbed by the layer 242 to form oxygen vacancies in the oxide 230, thereby reducing the resistance of the region. 231 may be formed.

Further, heat treatment is preferably performed in an atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. By the heat treatment, the metal element that is a component of the layer 242 diffuses from the layer 242 into the oxide 230 or the metal element that is a component of the oxide 230 diffuses into the layer 242, so that the oxide 230 and the layer 242 are separated. Forms a metal compound to lower the resistance. At that time, the metal element of the oxide 230 and the metal element of the layer 242 may be alloyed. By alloying the metal element of the oxide 230 and the metal element of the layer 242, the metal element is in a relatively stable state, so that a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

On the other hand, addition of a metal element to regions (regions 234 and 232 ) of the oxide 230 overlapping with the conductor 260 and the insulator 272 is suppressed by the conductor 260 and the insulator 272 . Also, in the regions 234 and 232 of the oxide 230, absorption of oxygen atoms in the oxide 230 into the layer 242 described above is suppressed.

In addition, oxygen in the region 231 of the oxide 230 and in the region 232 adjacent to the region 231 is absorbed by the layer 242 , so that oxygen vacancies may occur in the region 231 and the region 232 . Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are made low resistance.

Here, if the layer 242 has the property of absorbing hydrogen, the hydrogen in the oxide 230 will be absorbed into the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Layer 242 may also be removed along with hydrogen absorbed from oxide 230 in a later step.

Note that the layer 242 does not necessarily have to be removed. For example, if the layer 242 is insulating and has a high resistance, it may remain. For example, layer 242 may be oxidized by oxygen absorbed from oxide 230, become an insulator, and become highly resistive. In that case, layer 242 may function as an interlayer.

Further, for example, when a conductive region remains in the layer 242, it becomes an insulator and has a high resistance by being oxidized by heat treatment. The heat treatment is preferably performed, for example, in an oxidizing atmosphere. Further, when there is a structure containing oxygen in the vicinity of the layer 242, the layer 242 may react with oxygen contained in the structure and be oxidized by heat treatment.

By leaving the layer 242 as an insulator, it can function as an interlayer film. In the case of this structure, the layer 242 is provided with a thickness that can be insulated in a later step. For example, the layer 242 is preferably provided with a thickness of 0.5 nm to 5 nm, preferably 1 nm to 2 nm. Note that when the heat treatment is performed in the above oxidizing atmosphere, it is preferable to perform the heat treatment once in an atmosphere containing nitrogen while the oxide 230 and the layer 242 are in contact with each other. Once heat treatment is performed in an atmosphere containing nitrogen, oxygen in the oxide 230 can easily diffuse into the layer 242 .

Here, in a transistor including an oxide semiconductor, if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded. In addition, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor tends to have normally-on characteristics. Therefore, oxygen vacancies in the region 234 where the channel is formed are preferably reduced as much as possible.

Therefore, as shown in FIG. 19, an insulator 275 containing more oxygen than the stoichiometric composition (also referred to as excess oxygen) is preferably provided close to the oxide 230 . Excess oxygen in insulator 275 can pass through layer 242 and diffuse into oxide 230 to reduce oxygen vacancies in oxide 230 .

That is, excess oxygen in the insulator 275 diffuses into the region 234 of the oxide 230, so that oxygen vacancies in the region 234 of the oxide 230 can be reduced. On the other hand, oxygen vacancies formed in region 231 of oxide 230 are also compensated by oxygen supplied from insulator 275 . However, oxide 230 and the low resistance regions formed in layer 242 are stable due to the metal compound formed therein. Therefore, a lower resistance can be maintained than the region 234 where no metal compound is formed.

In order to provide the excess oxygen region in the insulator 275, an oxide film is preferably formed as the insulator 273 in contact with the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide film, an insulator containing few impurities such as water or hydrogen can be formed.

By introducing excess oxygen into the insulator 275 , an excess oxygen region can be formed in the insulator 275 . Excess oxygen in insulator 275 can be supplied to oxide 230 to compensate for oxygen vacancies in oxide 230 .

Aluminum oxide is preferably used for the insulator 273 . When aluminum oxide is heat-treated in proximity to the oxide 230, hydrogen in the oxide 230 may be extracted. Note that in the case where the layer 242 and the insulator 275 are provided between the oxide 230 and the aluminum oxide, the aluminum oxide absorbs hydrogen in the layer 242 and the insulator 275, and the hydrogen is reduced. 242 may absorb hydrogen in oxide 230 . Therefore, the hydrogen concentration in the oxide 230 can be reduced. Further, when heat treatment is performed with the insulator 273 and the oxide 230 in close proximity, oxygen can be supplied from the insulator 273 to the oxide 230, the insulator 224, or the insulator 222 in some cases.

By combining the above structure or the above steps, the resistance of the oxide 230 can be selectively reduced.

That is, when the low-resistance region is formed in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligned manner by using the conductor 260 functioning as a gate electrode and the insulator 272 as a mask. Therefore, when a plurality of transistors 200B are formed at the same time, variations in electrical characteristics among the transistors can be reduced. In addition, the channel length of the transistor 200B is determined by the width of the conductor 260 and the thickness of the insulator 272. By setting the width of the conductor 260 as the minimum processing dimension, the transistor 200B can be miniaturized.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor including an oxide semiconductor for a channel formation region has extremely low leakage current (off-state current) in a non-conducting state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

A structure of the semiconductor device including the transistor 200B according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 200A described in Embodiment 1, will be described below.

Region 232 has at least a region overlapping insulator 272 .

An insulator 271 functioning as a hard mask is preferably provided over the insulator 270 . By providing the insulator 271, when the conductor 260 is processed, the side surface of the conductor 260 is substantially vertical. Preferably, it can be 80° or more and 95° or less. By processing the conductor 260 into such a shape, the insulator 272 to be formed next can be formed into a desired shape.

The insulator 272 functioning as a buffer layer is provided in contact with side surfaces of the oxide 230 c , the insulator 250 , the metal oxide 252 , the conductor 260 , and the insulator 270 . For the insulator 272, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen may be used. In that case, the insulator 272 also functions as a barrier layer.

For example, the insulator 272 is preferably formed using an ALD method. A dense thin film can be formed by using the ALD method. For the insulator 272, for example, aluminum oxide, hafnium oxide, or the like is preferably used. In the case where aluminum oxide is provided as the insulator 272 by an ALD method, the thickness of the insulator 272 is preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm.

By providing the insulator 272, side surfaces of the insulator 250, the metal oxide 252, and the conductor 260 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Therefore, impurities such as hydrogen and water can be prevented from entering the oxide 230 from the insulator 250, the edge of the metal oxide 252, or the like. Therefore, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and reliability of the transistor 200B can be improved. That is, the insulator 272 functions as a side barrier that protects the side surfaces of the gate electrode and the gate insulator.

An insulator 275 is provided over oxide 230 , insulator 272 , and insulator 271 . An insulator 275 with excess oxygen regions is provided proximate oxide 230 .

For example, the insulator 275 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. Alternatively, it is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.

Insulator 275 also preferably has excess oxygen regions. An insulator from which oxygen is released by heating is provided as the insulator 275 in contact with the oxide 230c and the insulator 250, whereby oxygen is effectively supplied from the insulator 250 to the region 234 of the oxide 230b. be able to. Further, the concentration of impurities such as water or hydrogen in the insulator 275 is preferably reduced.

By providing the insulator 272 and the insulator 275 , excess oxygen in the insulator 275 can be supplied to the oxide 230 while suppressing oxidation of the conductor 260 . In other words, excess oxygen in the insulator 275 diffuses into the region 234 of the oxide 230 to reduce oxygen vacancies in the region 234 of the oxide 230, so that the region 234 of the oxide 230 has a higher resistance. do. On the other hand, oxygen vacancies formed in region 231 of oxide 230 are similarly compensated by oxygen supplied from insulator 275 .

However, oxide 230 and the low resistance regions formed in layer 242 are stable due to the metal compound formed therein. Therefore, a lower resistance can be maintained than the region 234 where no metal compound is formed.

An insulator 273 is provided over at least region 231 of oxide 230 and over insulator 275 . By forming the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 275 . Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region. Further, by providing the insulator 273 over the region 231 of the oxide 230 , hydrogen in the oxide 230 can be extracted to the insulator 273 .

For example, as the insulator 273, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like is used. be able to.

In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film having a thickness of 0.5 nm or more and 3.0 nm or less.

In openings formed in the insulators 284, 282, 280, 274, 273, and 275, the conductors 240a and 240b are arranged.

Note that the conductor 240 a is formed in contact with the inner walls of the openings of the insulators 284 , 282 , 280 , 274 , 273 , and 275 . A region 231a of oxide 230 is located in at least part of the bottom of the opening, and a conductor 240a is in contact with region 231a. Similarly, a conductor 240 b is formed in contact with the inner walls of the openings of the insulators 284 , 282 , 280 , 274 , 273 and 275 . A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductor 240b contacts region 231b.

Here, for example, when openings are formed in the insulator 284, the insulator 282, the insulator 280, the insulator 274, the insulator 273, and the insulator 275, in the oxide 230, the region 231 having a low resistance may be removed, exposing the non-low-resistivity oxide 230 . In that case, a metal film, a nitride film containing a metal element, or a metal element is used as a conductor that is in contact with the oxide 230 of the conductor 240 (hereinafter also referred to as a first conductor of the conductor 240). It is preferable to use an oxide film having a That is, when the oxide 230 whose resistance is not lowered and the first conductor of the conductor 240 are in contact with each other, oxygen vacancies are formed in the metal compound or the oxide 230 and the first conductor of the conductor 240 is formed. The contacting oxide 230 becomes low resistance. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, the contact resistance between the oxide 230 and the conductor 240 can be reduced. Therefore, the first conductor of the conductor 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, and tungsten.

In the case where the conductor 240 has a layered structure, the conductors in contact with the insulators 284 , 282 , 280 , 274 , 273 , and 275 are the first conductors of the conductor 205 . It is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen, similarly to a conductor. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. In addition, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from a layer above the insulator 280 can be prevented from entering the oxide 230 through the conductors 240a and 240b.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing a semiconductor device having the transistor 200B according to the present invention will be described with reference to FIGS. 20 to 25, (A) in each figure shows a top view. In addition, (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in (A). (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A). (D) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in (A).

A method for manufacturing the semiconductor device illustrated in FIG. 18 is the same as the method for manufacturing the semiconductor device illustrated in FIG. 1 until the insulator 271 is formed. Therefore, the manufacturing method of the semiconductor device illustrated in FIGS. 3 to 7 can be referred to.

Note that the insulating film 271A is preferably thicker than the insulating film 272A to be formed in a later step. Accordingly, the insulator 271 can be easily left over the conductor 260 when the insulator 272 is formed in a later step. In this embodiment, silicon oxide is deposited by a CVD method as the insulating film 271A.

After the insulator 271 is formed, an insulating film 272A is formed to cover the oxide 230, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 271 (see FIG. 20). .

The insulating film 272A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film 272A is preferably formed by the ALD method, which has excellent coverage. By using the ALD method, even in a stepped portion formed by the conductor 260 or the like, insulation having a uniform thickness can be formed on the side surfaces of the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270. Membrane 272A may be formed. Also, by using the ALD method, a dense thin film can be formed.

On the other hand, as the insulating film 272A, aluminum oxide or the like having a barrier property may be provided. For example, when the conductor 260 is a metal film that is easily oxidized, the use of an insulator having a barrier property can suppress oxidation of the conductor 260 by oxygen from above the insulating film 272A. Thereby, it is possible to suppress an increase in the resistance value of the conductor 260 .

When aluminum oxide is provided as the insulating film 272A by ALD, the film thickness of the insulating film 272A is preferably 0.5 nm or more and 3.0 nm or less. With this structure, excess oxygen in the insulator 275 can be supplied to the oxide 230 and the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, an anisotropic etching treatment is performed on the insulating film 272A to form the insulator 272 on the side surfaces of the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, and the insulator 270 (see FIG. 21). reference).

As the anisotropic etching treatment, dry etching treatment is preferably performed. As a result, the insulator 272 can be formed in a self-aligning manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.

Note that in this step, the insulator 224 may be processed into an island shape. In that case, the insulator 222 can be used as an etching stopper film.

Subsequently, a film 242A is formed over the insulator 224 and the oxide 230 with the oxide 230c, the insulator 250, the metal oxide 252, the conductor 260, the insulator 270, and the insulator 272 interposed therebetween (FIG. 22). The film 242A in Embodiment 1 can be referred to for the material, the film formation method, and the like of the film 242A.

Subsequently, heat treatment is performed (see FIG. 23). The heat treatment in the nitrogen-containing atmosphere causes the metal element that is a component of the film 242A to diffuse from the film 242A into the oxide 230 or the metal element that is a component of the oxide 230 into the film 242A, thereby forming the oxide 230. Then, the film 242A forms a metal compound, and the resistance can be lowered. By forming a metal compound between the oxide 230 and the film 242A, a relatively stable state can be obtained; therefore, a highly reliable semiconductor device can be provided.

Here, the layer 242 is formed by forming a metal compound with the metal element of the film 242A and the metal element of the oxide 230 . Also, a compound layer may be formed at the interface between the film 242A and the oxide 230 . Note that the compound layer is a layer having a metal compound containing a component of the film 242A and a component of the oxide 230. FIG. In addition, in this specification, the layer 242 may include a compound layer. For example, as the compound layer, a layer in which the metal element of the oxide 230 and the metal element of the film 242A are alloyed may be formed. By alloying, the metal elements are in a relatively stable state, and a highly reliable semiconductor device can be provided.

The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Moreover, you may perform heat processing in a pressure-reduced state.

Oxygen near the interface between oxide 230 and layer 242 may also be absorbed by layer 242 . As a result, the vicinity of the interface between oxide 230 and layer 242 becomes low in resistance (see FIG. 23). On the other hand, the layer 242 may be oxidized by oxygen absorbed from the oxide 230, become an insulator, and have a high resistance.

At that time, part of the oxide 230 and the metal element described above may be alloyed. By alloying part of the oxide 230 with the metal element, the metal element added to the oxide 230 is in a relatively stable state, so that a highly reliable semiconductor device can be provided. Also, the layer 242 with increased resistance may be used as an interlayer film.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

Alternatively, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.

Further, when a region having conductivity remains in the layer 242, heat treatment is performed in an oxidizing atmosphere to oxidize the layer 242, so that the layer 242 becomes an insulator and has a high resistance. By leaving the layer 242 as an insulator, it can function as an interlayer film.

In the formation step of the layer 242 or heat treatment, oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the layer 242, so that oxygen vacancies are generated in the regions 231 and 232. may occur. Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are n-type and have a low resistance.

Note that layer 242 may be removed. For example, a dry etching method or a wet etching method can be used as a removing method. By removing the layer 242, hydrogen in the oxide 230 absorbed in the layer 242 can be removed at the same time. Therefore, hydrogen which is an impurity in the transistor 200B can be reduced.

Subsequently, an insulator 275 is deposited over the layer 242 (see FIG. 24). For the material of the insulator 275, the insulating film 275A in Embodiment 1 can be referred to.

Although not shown, the insulator 275 may remain on the side surface of the insulator 224 as well. In that case, it is possible to improve the coating property of an interlayer film or the like to be formed in a later step. In addition, since the structure in which the insulator 275 remains is formed in contact with the side surface of the insulator 224, the insulator 224 can also be provided with an excess oxygen region.

Subsequently, an insulator 273 is formed over the insulator 275 (see FIG. 24). The insulator 273 in Embodiment 1 can be referred to for the material, the deposition method, and the like of the insulator 273 .

In addition, film formation is performed in an oxygen gas atmosphere using a sputtering apparatus, so that oxygen can be introduced into the insulator 275 while the insulator 273 is being formed. In particular, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies is used as the insulator 275, an excess oxygen region tends to be easily formed in the insulator 275. In addition, an oxide film formed by sputtering may extract hydrogen from a structure to be deposited. Therefore, for example, when an oxide film is formed as the insulator 273 by sputtering, an excess oxygen region can be selectively formed in the insulator 275 . Further, by absorbing hydrogen and water from the insulator 275, the concentration of hydrogen in the insulator 275 can be reduced.

The insulator 275 in which the excess oxygen region is formed as described above can effectively supply oxygen from the excess oxygen region to the oxide 230 . In other words, excess oxygen in the insulator 275 diffuses into the region 234 of the oxide 230 to reduce oxygen vacancies in the region 234 of the oxide 230, so that the region 234 of the oxide 230 has a higher resistance. do. On the other hand, oxygen vacancies formed in region 231 of oxide 230 are similarly compensated by oxygen supplied from insulator 275 .

However, oxide 230 and the low resistance regions formed in layer 242 are stable due to the metal compound formed therein. Therefore, a lower resistance can be maintained than the region 234 where no metal compound is formed.

With the above structure, each region of the oxide 230 can be formed in a self-aligned manner. Therefore, miniaturized or highly integrated semiconductor devices can be manufactured with a high yield.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

A heat treatment can then be performed. For the heat treatment, the heat treatment conditions described above can be used. By the heat treatment, hydrogen trapped in oxygen vacancies formed in the region 231 of the oxide 230 is absorbed by the insulator 273, so that hydrogen in the oxide 230 can be reduced.

Next, an insulator 274, an insulator 280, an insulator 282, and an insulator 284 are formed in this order over the insulator 273 (see FIG. 24). Note that the materials, formation methods, and the like of the insulators 274, 280, 282, and 284 are the same as those of the insulators 274, 280, 282, and 284 in Embodiment 1. can be considered.

Openings are then formed in insulator 284 , insulator 282 , insulator 280 , insulator 274 , insulator 273 , and insulator 275 down to oxide 230 . The formation of the opening may be performed using a lithography method. Note that the openings reaching the oxide 230 are formed so that the side surfaces of the oxide 230 are exposed so that the conductors 240 a and 240 b are provided in contact with the side surfaces of the oxide 230 .

Next, a conductive film to be the first conductor of the conductor 240 and a conductive film to be the second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when openings are formed in the insulators 284, 282, 280, 274, 273, and 275, the low-resistance region of the region 231 may be removed. be. In that case, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used as the first conductor of the conductor 240 . That is, since the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen vacancies are formed in the contact region, and the resistance of the contact region between the oxide 230 and the conductor 240 is reduced. be able to. Sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured by reducing the resistance of the oxide 230 that is in contact with the first conductor of the conductor 240 . Therefore, the first conductor of the conductor 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium.

Next, CMP treatment is performed to remove part of the conductive film to be the conductors 240 a and 240 b to expose the insulator 284 . As a result, the conductor 240a and the conductor 240b with flat top surfaces can be formed by leaving the conductive film only in the openings (see FIG. 25).

Through the above steps, a semiconductor device including the transistor 200B can be manufactured. As illustrated in FIGS. 20A to 25B, the transistor 200B can be manufactured by using the method for manufacturing the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

<Modified Example of Semiconductor Device>
Examples of a semiconductor device including a transistor 200B according to one embodiment of the present invention are described below with reference to FIGS.

Here, (A) in each figure shows a top view. In addition, (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in (A). (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A). (D) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A5-A6 in (A). In the top view of each figure (A), some elements are omitted for clarity of illustration.

Note that in the semiconductor devices shown in FIGS. 26 to 29, structures having the same functions as structures forming the semiconductor devices shown in <Structure Example of Semiconductor Device> are denoted by the same reference numerals.

Structures of semiconductor devices are described below with reference to FIGS. Note that in this item as well, the materials described in detail in the above embodiments and <Structure Example of Semiconductor Device> can be used as constituent materials of the semiconductor device.

[Modification 1 of semiconductor device]
In the semiconductor device shown in FIG. 26, the side surface of oxide 230 and the surface parallel to the substrate have a taper angle. Specifically, as shown in FIG. 26B, the taper angle (θ) should be 45° or more and 80° or less, preferably 50° or more and 70° or less. Since the oxide 230 has a tapered structure, the side surface of the oxide 230 can be exposed when the insulator 272 is subjected to anisotropic etching treatment.

Accordingly, the side surfaces of the oxide 230 are also in contact with the film 242A, forming a metal compound and reducing the resistance. That is, regions 231 can also be formed on the sides of oxide 230 . In addition, since the oxide 230 has a tapered structure, the coating property of the structure formed above the oxide 230 can be improved.

[Modification 2 of semiconductor device]
The semiconductor device shown in FIG. 27 differs from the semiconductor device shown in <Structure Example of Semiconductor Device> in that the insulating region of the layer 242 is removed. Specifically, layer 242 may be left only on oxide 230, as shown in FIG. Alternatively, if metal compounds are formed in oxide 230, layer 242 may be removed. Therefore, region 231 may be formed in oxide 230 only.

Note that when the layer 242 has the property of absorbing hydrogen, the hydrogen in the oxide 230 is absorbed into the layer 242 . Therefore, by removing the layer 242, the hydrogen absorbed from the oxide 230 can also be removed. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced.

[Modification 3 of semiconductor device]
The semiconductor device shown in FIG. 28 differs from the semiconductor device shown in <Structure Example of Semiconductor Device> in the shape of the conductor 240 . That is, the semiconductor device shown in <Structure Example of Semiconductor Device> has a structure in which the conductor 240 is provided in contact with the insulators 280, 282, and 284 functioning as interlayer films. On the other hand, in the semiconductor device shown in FIG. 28, the insulator 275, the insulator 273, and the insulator 274 are provided with openings, and the conductor 240 is formed. That is, the conductor 240 has a structure not in contact with the interlayer film. Therefore, impurities in the insulator functioning as an interlayer film can be prevented from diffusing through the conductor 240 to the transistor 200B. Therefore, an insulator having a barrier property is preferably provided over the conductor 240 .

[Modification 4 of semiconductor device]
The semiconductor device shown in FIG. 29 differs from the semiconductor device shown in <Structure Example of Semiconductor Device> in that barriers are provided between the conductor 240 and insulators 280, 282, and 284 functioning as interlayer films. The difference is that insulators 276 (insulators 276a and 276b) functioning as layers are provided. Note that in this structure, the insulator 276 and the insulator 282 preferably have barrier properties against oxygen, hydrogen, and water.

Specifically, as shown in FIG. 29, an insulator 276 is preferably provided between the conductor 240, the insulator 280, and the insulator 282 having a barrier property. In particular, the insulator 276 is preferably provided in contact with the insulator 282 having a barrier property. Since the insulator 276 and the insulator 282 are provided in contact with each other, the insulator 276 extends to the insulator 284, so that diffusion of oxygen and impurities can be further suppressed.

In other words, provision of the insulator 276 can prevent impurities in the insulator 280 from diffusing into the transistor 200B through the conductor 240 and reducing the reliability of the semiconductor device. In addition, by providing the insulator 276, it is possible to widen the selection range of materials for conductors used for plugs and wirings.

A metal oxide can be used for the insulator 276, for example. In particular, it is preferable to use an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Alternatively, silicon nitride formed by a CVD method may be used.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 3)
An example of a semiconductor device including the transistor 200C according to one embodiment of the present invention is described below.

Note that in the semiconductor device described in this embodiment, structures having the same functions as the structures constituting the semiconductor devices described in the previous embodiments are denoted by the same reference numerals. Therefore, differences from the semiconductor device shown in the previous embodiment will be mainly described, and repeated descriptions will be omitted. Further, when there is no particular description of materials, manufacturing methods, and the like of structures denoted by the same reference numerals, the descriptions in the above embodiments can be referred to for the materials, manufacturing methods, and the like of the structures.

<Structure example of semiconductor device>
30A to 30D are a top view and a cross-sectional view of a transistor 200C and its periphery according to one embodiment of the present invention.

FIG. 30A is a top view of a semiconductor device having a transistor 200C. 30B, 30C, and 30D are cross-sectional views of the semiconductor device. Here, FIG. 30B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 30A, and is also a cross-sectional view in the channel length direction of the transistor 200C. FIG. 30C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 30A, and is also a cross-sectional view in the channel width direction of the transistor 200C. FIG. 30D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 30A, and is also a cross-sectional view of the source region or drain region of the transistor 200C. Note that in the top view of FIG. 30A, some elements are omitted for clarity of illustration.

A semiconductor device of one embodiment of the present invention includes a transistor 200C and insulators 210, 212, 280, and 282 functioning as interlayer films. It also includes a conductor 203 that is electrically connected to the transistor 200C and functions as a wiring, and a conductor 240 that functions as a plug.

A first conductor 203a of the conductor 203 is formed in contact with the inner wall of the opening of the insulator 212, and a second conductor 203b of the conductor 203 is further formed inside. Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be made approximately the same. Note that although the transistor 200C shows a structure in which the first conductor 203a of the conductor 203 and the second conductor 203b of the conductor 203 are stacked, the present invention is not limited to this. For example, the conductor 203 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.

In the conductor 240, the first conductor of the conductor 240 is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 282, and the second conductor of the conductor 240 is formed further inside. ing. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 282 can be made approximately the same. Note that although the structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown in the transistor 200C, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.

[Transistor 200C]
As shown in FIG. 30, the transistor 200C includes an insulator 214 and an insulator 216 arranged over a substrate (not shown), and a conductor 205 arranged to be embedded in the insulator 214 and the insulator 216. , an insulator 220 placed over the insulator 216 and the conductor 205, an insulator 222 placed over the insulator 220, an insulator 224 placed over the insulator 222, and an insulator Oxide 230 (oxide 230 a , oxide 230 b , and oxide 230 c ) overlying 224 , insulator 250 overlying oxide 230 , and conductor overlying insulator 250 . 260 (a conductor 260a and a conductor 260b), an insulator 271 disposed over the conductor 260, an oxide 230c, an insulator 250, and a side surface of the conductor 260, and the oxide 230b. An insulator 272 is arranged in contact with part of the upper surface, and an insulator 273 is arranged on the side surface of the conductor 260 with the insulator 272 interposed therebetween.

In the transistor 200C, an oxide semiconductor is preferably used for the oxides 230 (the oxides 230a, 230b, and 230c) including a channel formation region.

Since the transistor 200C including an oxide semiconductor for a channel formation region has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. Further, since an oxide semiconductor can be deposited by a sputtering method or the like, it can be used for the transistor 200C included in a highly integrated semiconductor device.

Here, the oxide semiconductor forms a metal compound with low resistance by adding metal elements such as aluminum, ruthenium, titanium, tantalum, chromium, and tungsten in addition to the elements constituting the oxide semiconductor. become Note that it is preferable to use aluminum, titanium, tantalum, tungsten, or the like. In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, when the film is provided, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film or the like, forming oxygen vacancies and causing oxidation. In some cases, the vicinity of the interface of the material semiconductor becomes low in resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment is preferably performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal element can be diffused from the metal film into the oxide semiconductor, and the metal element can be added to the oxide semiconductor. Note that at that time, the oxide semiconductor and the metal element may be alloyed. By alloying the oxide semiconductor and the metal element, the metal element added to the oxide semiconductor is in a relatively stable state; therefore, a highly reliable semiconductor device can be provided.

In addition, when hydrogen existing in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor and enters oxygen vacancies in the low-resistance region, the hydrogen is in a relatively stable state. Further, hydrogen in the oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and oxygen vacancies existing in the low-resistance region. It is known that it enters into the inside and becomes a relatively stable state. Therefore, by heat treatment, the resistance of the region where the resistance of the oxide semiconductor is reduced or the region where the metal compound is formed is further reduced, and the oxide semiconductor which is not reduced in resistance is purified (impurities such as water and hydrogen). reduction) and tends to increase the resistance.

In addition, the oxide semiconductor has an increased carrier density when an impurity element such as hydrogen or nitrogen is present. Hydrogen in the oxide semiconductor reacts with oxygen that bonds to a metal atom to become water, which may cause oxygen vacancies. Hydrogen entering the oxygen vacancies increases the carrier density. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to an oxide semiconductor, a high-resistance region and a low-resistance region can be provided in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the island-shaped oxide 230 has a region functioning as a semiconductor with low carrier density and a region functioning as a source region or a drain region. A region can be provided.

Here, FIG. 31 shows an enlarged view of a region 239 surrounded by a broken line in FIG.

As shown in FIG. 31, the oxide 230 includes a region 234 functioning as a channel forming region of the transistor 200C, a region 231 (regions 231a and 231b) functioning as a source region or a drain region, and a region 234 and a region 231. and a region 232 (regions 232a and 232b) provided between and.

For example, in addition to the oxide 230, the region 231 preferably contains one or more metal elements selected from metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium. By adding a metal element to the oxide 230, the resistance of the region 231 can be reduced. Note that the region 231 may have a region in which the metal element in the oxide 230 and the added metal element are alloyed.

Region 232 has a region that overlaps insulator 272 . Region 232 preferably has a higher concentration than region 234 of at least one of metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and impurity elements such as hydrogen and nitrogen. In order to form the region 232 , for example, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be provided in contact with the region 231 of the oxide 230 . Accordingly, the metal element in the film may be added to the oxide semiconductor to form a metal compound in the oxide semiconductor. The metal compound may attract hydrogen contained in oxide 230 . As a result, the concentration of hydrogen in the region 232 near the region 231 may increase.

Note that one or both of the regions 232 a and 232 b may have a region overlapping with the conductor 260 . With this structure, the conductor 260 can overlap with the regions 232a and 232b.

Also, although regions 234, 231, and 232 are formed in oxide 230b in FIGS. 30 and 31, the present invention is not limited to this. For example, these regions may be formed in oxide 230a or oxide 230c. Also, in FIGS. 30 and 31, the boundaries of each region are shown substantially perpendicular to the top surface of the oxide 230, but the present embodiment is not limited to this. For example, the region 232 may extend toward the conductor 260 near the surface of the oxide 230b and recede toward the conductor 240a or 240b near the bottom surface of the oxide 230b.

Also, in the oxide 230, it may be difficult to clearly detect the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to stepwise changes between regions, but also change continuously (also referred to as gradation) within each region. may In other words, it is sufficient if the concentrations of metal elements and impurity elements such as hydrogen and nitrogen are reduced in a region closer to the channel formation region.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium, and an impurity is added to a desired region. good. Note that an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used as the impurity. Examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, rare gases, and the like. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon.

Therefore, in the region 231, the carrier density is increased and the resistance is reduced by increasing the content of the metal element that increases conductivity, the element that forms oxygen vacancies, or the element that is captured by oxygen vacancies. be able to.

In order to reduce the resistance of the region 231 , for example, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be formed in contact with the region 231 of the oxide 230 . The metal film, the nitride film containing the metal element, or the oxide film containing the metal element is oxidized through at least the oxide 230 c , the insulator 250 , the conductor 260 , the insulator 271 , the insulator 272 , and the insulator 273 . It is preferably provided on object 230b.

By providing a metal film, a nitride film containing the metal element, or an oxide film containing the metal element in contact with the region 231 of the oxide 230, the metal element diffuses from the film into the region 231 of the oxide 230, A metal compound is formed at 231 to lower the resistance. Further, part of oxygen in the oxide 230 located at or near the interface between the region 231 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is absorbed by the film, Oxygen vacancies may be formed in the region 231 to lower the resistance. Note that in FIG. 31, the regions of the oxide 230 with reduced resistance are represented by oblique lines as an example. Note that in this specification and the like, the shaded range is not limited to the range in FIG. 31 . For example, the low resistance region (or range) is formed in a region near the interface between the oxide 230 and the conductor 240 or in a region from the top surface of the oxide 230 to the bottom surface of the oxide 230 in the region 231. may occur. The same applies to other drawings.

Heat treatment may be performed in an atmosphere containing nitrogen while the region 231 is in contact with the metal film, the nitride film containing the metal element, or the oxide film containing the metal element. By the heat treatment, the metal element can be diffused from the metal film into the region 231 of the oxide 230 and added to the region 231 . At that time, the region 231 of the oxide 230 and the metal element may be alloyed. By alloying the region 231 of the oxide 230 with the metal element, the metal element added to the oxide semiconductor is relatively stable; therefore, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

On the other hand, addition of a metal element to regions (regions 234 and 232 ) of the oxide 230 overlapping with the conductor 260 and the insulator 272 is suppressed by the conductor 260 and the insulator 272 . In addition, in the regions 234 and 232 of the oxide 230, absorption of oxygen atoms in the oxide 230 by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is suppressed. be.

In addition, oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element. Oxygen deficiency may occur at 232 . Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are made low resistance.

Here, if a metal film, a nitride film containing a metal element, or an oxide film containing a metal element has the property of absorbing hydrogen, the hydrogen in the oxide 230 is absorbed by the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Also, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element may be removed together with the hydrogen absorbed from the oxide 230 in a later step.

Note that the metal film, the nitride film containing the metal element, or the oxide film containing the metal element does not necessarily have to be removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230, becomes an insulator, and has a high resistance, it may be left. . In that case, it may function as an interlayer film.

Further, for example, when a conductive region remains in a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, heat treatment is performed in an oxidizing atmosphere to oxidize the film. , becomes an insulator and has a high resistance. By leaving a metal film, a nitride film containing a metal element, or an oxide film containing a metal element as an insulator, it can function as an interlayer film.

Therefore, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is preferably provided with a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 2 nm or less. For example, when aluminum with a thickness of 0.5 nm or more and 5 nm or less is oxidized by heat treatment, aluminum oxide with a thickness of 0.7 nm or more and 8 nm or less may be obtained.

Here, in a transistor including an oxide semiconductor, if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to fluctuate, and reliability may be degraded. In addition, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor tends to have normally-on characteristics. Therefore, oxygen vacancies in the region 234 where the channel is formed are preferably reduced as much as possible.

Therefore, as shown in FIGS. 30 and 31, an insulator 273 containing more oxygen than the stoichiometric composition (also referred to as excess oxygen) is provided over a region 231 of the oxide 230 . is preferred. That is, excess oxygen in the insulator 273 diffuses through the insulator 272, the insulator 280, and the regions 231 and 232 of the oxide 230 into the region 234 of the oxide 230, thereby Oxygen vacancies in 234 can be reduced.

Note that silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes is preferably used for the insulator 272 provided under the insulator 273 . Materials such as silicon oxynitride are prone to the formation of excess oxygen regions. Therefore, for example, oxygen supplied from the insulator 273 may form an excess oxygen region in the insulator 272 . By providing the insulator 272 with the excess oxygen region around the region 234 of the oxide 230 as shown in FIGS. can be supplied

For the insulator 273 serving as an oxygen supply source, an oxide film formed by a sputtering method is preferably used. An oxide film formed by a sputtering method contains a large amount of oxygen and can form an insulator with few impurities such as water or hydrogen. As the oxide, it is particularly preferable to use aluminum oxide.

In the case of using a sputtering method for forming an oxide film, for example, the film is preferably formed using a facing target type sputtering apparatus. Since the facing target type sputtering apparatus can form a film without exposing the film formation surface to the high electric field region between the opposing targets, the film formation surface is less likely to be damaged by plasma. Therefore, damage to the insulator 272 and the oxide 230 during deposition of the insulator to be the insulator 273 can be reduced, which is preferable.

During film formation by the sputtering method, ions and sputtered particles are present between the target and the substrate. For example, the target is connected to a power supply and given a potential E0. A potential E1 such as a ground potential is applied to the substrate. However, the substrate may be electrically floating. A region having potential E2 exists between the target and the substrate. The magnitude relationship between the potentials is E2>E1>E0.

Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, thereby ejecting sputtered particles from the target. The sputtered particles adhere to the film formation surface and accumulate to form a film. In addition, some ions may recoil by the target, pass through the film formed as recoil ions, and be taken into the insulator 272 which is in contact with the deposition surface. Also, the ions in the plasma are accelerated by the potential difference E2-E1 and bombard the surface of the film. At this time, some of the ions reach the inside of the insulator 272 . By capturing ions into the insulator 272 , a region in which ions are captured is formed in the insulator 272 . That is, when the ions are ions containing oxygen, an excess oxygen region is formed in the insulator 272 .

By introducing excess oxygen into the insulator 272 , excess oxygen regions can be formed in the insulator 272 . Excess oxygen in insulator 272 is supplied to oxide 230 in contact with insulator 272 . By supplying the oxygen to the region 234 of the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

By combining the above structure or the above steps, the resistance of the oxide 230 can be selectively reduced.

That is, when the low-resistance region is formed in the oxide 230, the resistance of the oxide 230 is reduced in a self-aligned manner by using the conductor 260, the insulator 272, or the insulator 273 functioning as a gate electrode as a mask. do. Therefore, when a plurality of transistors 200C are formed at the same time, variations in electrical characteristics between transistors can be reduced. In addition, the channel length of the transistor 200C is determined by the width of the conductor 260 and the film thickness of the insulator 272; Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor including an oxide semiconductor for a channel formation region has extremely low leakage current (off-state current) in a non-conducting state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

A structure of the semiconductor device including the transistor 200C according to one embodiment of the present invention, which is different from the semiconductor device including the transistor 200A described in Embodiment 1, will be described below.

The conductor 205 has a first conductor 205a formed in contact with the inner walls of the openings of the insulators 214 and 216, and a second conductor 205b formed inside. Here, the height of the top surface of the first conductor 205a and the second conductor 205b and the height of the top surface of the insulator 216 can be made approximately the same. Note that although the structure in which the first conductor 205a and the second conductor 205b are stacked is shown in the transistor 200C, the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.

Here, the first conductor (the conductor 205a or the conductor 203a) of the conductor 205 or the conductor 203 is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule (N ₂ O, It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as NO, NO ₂ , and copper atoms (the above-mentioned impurities are difficult to permeate). Alternatively, it is preferable to use a conductive material that has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the above-described oxygen hardly permeates). In this specification, the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of either one or all of the impurities or oxygen.

Since the first conductor (the conductor 205a or the conductor 203a) of the conductor 205 or the conductor 203 has the function of suppressing diffusion of oxygen, the second conductor (the conductor 205a or 203a) of the conductor 205 or the conductor 203 can A decrease in conductivity due to oxidation of the body 205b or the conductor 203b) can be suppressed. As the conductive material having a function of suppressing diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example. Therefore, as the first conductor (the conductor 205a or the conductor 203a) of the conductor 205 or the conductor 203, a single layer or a laminate of the above conductive materials may be used. Accordingly, impurities such as hydrogen and water can be prevented from diffusing through the conductors 203 and 205 from the substrate side (below the insulator 210) to the transistor 200C side.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the second conductor 205b of the conductor 205 . Although the second conductor 205b of the conductor 205 is illustrated as a single layer, it may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material.

In addition, since the second conductor 203b of the conductor 203 functions as a wiring, a conductor having higher conductivity than the second conductor 205b of the conductor 205 is preferably used. For example, a conductive material containing copper or aluminum as a main component can be used. In addition, the second conductor 203b of the conductor 203 may have a layered structure, for example, a layered structure of titanium or titanium nitride and any of the above conductive materials.

In particular, it is preferable to use copper for the conductor 203 . Since copper has a low resistance, it is preferably used for wiring and the like. On the other hand, since copper easily diffuses, diffusion into the oxide 230 may degrade the electrical characteristics of the transistor 200C. Therefore, by using a material such as aluminum oxide or hafnium oxide, which has low copper permeability, for the insulator 214, the diffusion of copper can be suppressed.

Note that the conductor 205, the insulator 214, and the insulator 216 are not necessarily provided. In that case, part of the conductor 203 can function as the second gate electrode.

Insulator 220, insulator 222, and insulator 224 function as gate insulators.

Here, as the insulator 224 in contact with the oxide 230, an oxide insulator containing more oxygen than the stoichiometric composition is preferably used. In other words, the insulator 224 preferably has an excess oxygen region. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200C can be improved.

Oxide 230 also has regions 231 , 232 , and 234 . Note that the region 232 has at least a region overlapping with the insulator 272 .

Insulator 250 functions as a gate insulator. Insulator 250 is preferably placed in contact with the top surface of oxide 230c. The insulator 250 is preferably formed using an insulator from which oxygen is released by heating. For example, in TDS analysis, the desorption amount of oxygen in terms of oxygen molecules is 1.0×10 ¹⁸ molecules/cm ³ or more, preferably 1.0×10 ¹⁹ molecules/cm ³ or more, more preferably 2. 0×10 ¹⁹ molecules/cm ³ or 3.0×10 ²⁰ molecules/cm ³ . The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. or higher and 700° C. or lower.

Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies Silicon oxide can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

An insulator from which oxygen is released by heating is provided as the insulator 250 in contact with the top surface of the oxide 230c, whereby oxygen is effectively released from the insulator 250 to the region 234 of the oxide 230b through the oxide 230c. can supply. Further, similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260 in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230 . The metal oxide preferably suppresses diffusion of oxygen from the insulator 250 . By providing the metal oxide that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, reduction in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

Note that the metal oxide may function as part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, the metal oxide is preferably a high-k material with a high dielectric constant. With the laminated structure, a laminated structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness. Also, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced.

The metal oxide may also function as part of the first gate. For example, an oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260 by a sputtering method, the electric resistance value of the metal oxide can be lowered and the conductor (OC electrode) can be obtained.

By including the metal oxide, the on-state current of the transistor 200C can be improved without weakening the influence of the electric field from the conductor 260 . In addition, the physical thickness of the insulator 250 and the metal oxide maintains the distance between the conductor 260 and the oxide 230, thereby reducing the leakage current between the conductor 260 and the oxide 230. can be suppressed. In addition, by providing the insulator 250 and the stacked structure of the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field intensity applied from the conductor 260 to the oxide 230 can be reduced to It can be easily adjusted accordingly.

Specifically, the metal oxide includes one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like. Oxides can be used. Alternatively, an oxide semiconductor that can be used for the oxide 230 can be used as the metal oxide by reducing the resistance thereof.

In particular, it is preferable to use aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing oxides of one or both of aluminum and hafnium. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is preferable because it is difficult to crystallize in the heat history in the subsequent steps.

A conductor 260 functioning as a first gate electrode has a conductor 260a and a conductor 260b over the conductor 260a. The conductor 260a, like the first conductor of the conductor 205, contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO _2, etc.), copper atoms. It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as . Alternatively, a conductive material having a function of suppressing diffusion of oxygen (eg, at least one of oxygen atoms and oxygen molecules) is preferably used.

Since the conductor 260a has a function of suppressing diffusion of oxygen, excess oxygen in the insulator 250 can suppress oxidation of the conductor 260b and reduction in conductivity. As the conductive material having a function of suppressing diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example.

Alternatively, an insulator functioning as a barrier film may be placed over the conductor 260b. An insulating material that has a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used for the insulator. For example, it is preferable to use aluminum oxide or hafnium oxide. Accordingly, oxidation of the conductor 260 by oxygen from above the insulator can be suppressed. In addition, impurities such as water or hydrogen from above the insulator can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250 .

Further, an insulator 271 functioning as a hard mask is preferably provided over the insulator. By providing the insulator 271, when the conductor 260 is processed, the side surface of the conductor 260 is substantially vertical. Preferably, it can be 80° or more and 95° or less. By processing the conductor 260 into such a shape, the insulator 272 to be formed next can be formed into a desired shape.

Note that the insulator 271 may also function as a barrier film by using an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. In that case, the above insulator functioning as a barrier film does not need to be separately provided over the conductor 260b.

As shown in FIG. 30B, the insulator 272 functioning as a barrier film and a buffer layer includes a portion of the top surface of the oxide 230b (a portion overlapping with the region 232) and an oxide layer in the channel length direction of the transistor 200C. It is provided in contact with the side surface of the object 230 c , the side surface of the insulator 250 and the side surface of the conductor 260 . In addition, as shown in FIG. 30C, it is provided in contact with part of the top surface of the insulator 222 in the channel width direction of the transistor 200C.

For example, the insulator 272 is preferably formed using an ALD method. A dense thin film can be formed by using the ALD method.

As the insulator 272, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or a resin etc. is preferable. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.

Alternatively, the insulator 272 may be formed using an insulating material that has a function of suppressing permeation of impurities such as water or hydrogen, and oxygen. For example, aluminum oxide, hafnium oxide, or the like is preferably used. Thereby, diffusion of oxygen in the insulator 250 to the outside can be suppressed. In addition, entry of impurities such as hydrogen and water into the oxide 230 from the edge of the insulator 250 or the like can be suppressed. Therefore, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200C can be improved.

In addition, by providing the insulator 272, side surfaces of the oxide 230c, the insulator 250, and the conductor 260 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. . Accordingly, impurities such as water or hydrogen can be prevented from entering the region 234 of the oxide 230 from above the transistor 200C through the oxide 230c, the insulator 250, and the conductor 260. FIG. Therefore, insulator 272 functions as a side barrier that protects the sides of the gate electrode and gate insulator.

Alternatively, the insulator 272 preferably has an insulator with a low dielectric constant. For example, the insulator 272 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide with vacancies. , or resin. Alternatively, the insulator 272 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

Note that in the case where aluminum oxide is provided as the insulator 272 by an ALD method, the thickness of the insulator 272 is preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm.

In addition, an insulator 273 is provided over part of the top surface of the oxide 230b (the portion overlapping with the region 232), the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 with the insulator 272 interposed therebetween. . With this structure, the insulator 273 serving as an oxygen supply source for the oxide 230 is not in direct contact with the conductor 260 . Therefore, oxidation of the conductor 260 functioning as a gate electrode by oxygen from the insulator 273 can be suppressed.

An insulator 273 is provided over the insulator 272 so as to have a region that overlaps the region 232 of the oxide 230 . By forming the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 272 . Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region.

For example, the insulator 273 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like. can be done.

In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film having a thickness of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide film formed by the sputtering method can function not only as an oxygen supply source but also as a barrier film against impurities such as hydrogen. For example, by using aluminum oxide deposited by a sputtering method for the insulator 273 , the insulator 273 supplies oxygen to the insulator 272 and impurities such as hydrogen from above the insulator 273 are removed from the insulator 273 . It is possible to suppress mixing into the side.

An insulator 280 functioning as an interlayer film is preferably provided over the insulator 273 . Like the insulator 224 and the like, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

An insulator 282 made of the same material as the insulator 273 is preferably provided over the insulator 280 . With this structure, impurities such as hydrogen from above the insulator 282 can be prevented from entering the transistor 200C side. Further, hydrogen contained in the insulator 280 can be extracted to the insulator 282 in some cases. Note that an insulator similar to the insulator 210 may be provided over the insulator 282 .

In openings formed in the insulators 282 and 280, the conductors 240a and 240b are arranged. The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be flush with the top surface of the insulator 282 .

A first conductor of conductor 240 a is formed in contact with the inner walls of the openings of insulator 282 and insulator 280 . A region 231a of oxide 230 is located in at least part of the bottom of the opening, and a conductor 240a is in contact with region 231a. Similarly, a first conductor of conductor 240 b is formed in contact with the inner walls of the openings of insulator 282 and insulator 280 . A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductor 240b contacts region 231b.

Here, for example, when forming the openings in the insulator 282 and the insulator 280 , the low resistance region of the region 231 may be removed in the oxide 230 . In that case, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used as the first conductor of the conductor 240 . That is, when the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen vacancies are formed, and the resistance of the region 231 of the oxide 230 is reduced. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, the contact resistance between the oxide 230 and the conductor 240 can be reduced. The first conductor of conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or the like.

In the case where the conductor 240 has a stacked-layer structure, the conductor in contact with the insulator 280 and the insulator 282 is impervious to impurities such as water or hydrogen, similarly to the first conductor 205a of the conductor 205. It is preferable to use a conductive material having a suppressing function. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. In addition, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from a layer above the insulator 282 can be prevented from entering the oxide 230 through the conductors 240a and 240b.

Further, although not illustrated, a conductor functioning as a wiring may be arranged in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. A conductive material containing tungsten, copper, or aluminum as a main component is preferably used for the conductor functioning as the wiring. Further, the conductor may have a layered structure, for example, a layered structure of titanium, titanium nitride, and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator, similarly to the conductor 203 and the like.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing a semiconductor device having the transistor 200C according to the present invention will be described with reference to FIGS. 32 to 41, (A) in each figure shows a top view. (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in (A), and is also a cross-sectional view in the channel length direction of the transistor 200C. (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200C. (D) of each figure is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in (A) of each figure, and is also a cross-sectional view of the source region or the drain region of the transistor 200C. In addition, in the top view of (A) of each figure, some elements are omitted for clarity of illustration.

First, a substrate (not shown) is prepared, and the insulator 210, the insulator 212, the conductor 203, the insulator 214, the insulator 216, the conductor 205, the insulator 220, and the insulator 222 are sequentially formed over the substrate. Form (see FIG. 32). Note that the materials and forming methods of the insulator 210, the insulator 212, the conductor 203, the insulator 214, the insulator 216, the conductor 205, the insulator 220, and the insulator 222 are the same as those of the insulator in Embodiment 1. The body 210, the insulator 212, the conductor 203, the insulator 214, the insulator 216, the conductor 205, the insulator 220, and the insulator 222 can be referred to.

Next, an insulating film 224 A is formed over the insulator 222 . The insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 32). In this embodiment mode, silicon oxide is deposited by a CVD method as the insulating film 224A.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Moreover, you may perform heat processing in a pressure-reduced state. Alternatively, heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen. may

In this embodiment mode, heat treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere after the insulating film 224A is formed. Impurities such as hydrogen and water contained in the insulating film 224A can be removed by the heat treatment.

Alternatively, the heat treatment can be performed after the insulator 220 is deposited and after the insulator 222 is deposited. Although the above heat treatment conditions can be used for the heat treatment, the heat treatment after the insulator 220 is formed is preferably performed in an atmosphere containing nitrogen.

Here, in order to form an excess oxygen region in the insulating film 224A, plasma treatment containing oxygen may be performed under reduced pressure. For plasma treatment containing oxygen, it is preferable to use an apparatus having a power supply that generates high-density plasma using microwaves, for example. Alternatively, the board may have a power supply for applying RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulating film 224A. can. Alternatively, plasma treatment containing an inert gas may be performed using this apparatus, and then plasma treatment containing oxygen may be performed to compensate for desorbed oxygen. Note that impurities such as hydrogen and water contained in the insulating film 224A can be removed by appropriately selecting conditions for the plasma treatment. In that case, heat treatment may not be performed.

Next, an oxide film 230A to be the oxide 230a and an oxide film 230B to be the oxide 230b are sequentially formed on the insulating film 224A (see FIG. 32). Note that the oxide films 230A and 230B of the first embodiment can be referred to for materials, formation methods, and the like of the oxide films 230A and 230B.

Next, the insulating film 224A, the oxide film 230A, and the oxide film 230B are processed into an island shape to form the insulator 224, the oxide 230a, and the oxide 230b (see FIG. 33).

Here, the insulator 224, the oxide 230a, and the oxide 230b are formed so as to overlap with the conductor 205 at least partially. Side surfaces of the insulator 224 , the oxide 230 a , and the oxide 230 b are preferably substantially perpendicular to the top surface of the insulator 222 . The side surfaces of the insulator 224, the oxide 230a, and the oxide 230b are substantially perpendicular to the top surface of the insulator 222, so that the area can be reduced and the density can be increased when the plurality of transistors 200C are provided. Become. Note that the side surfaces of the insulator 224, the oxides 230a, and 230b and the top surface of the insulator 222 may form an acute angle. In that case, the angle between the side surfaces of the insulator 224, the oxides 230a, and the oxide 230b and the top surface of the insulator 222 is preferably as large as possible.

In addition, curved surfaces are provided between the side surfaces of the oxides 230a and 230b and the top surface of the oxide 230b. That is, it is preferable that the edge of the side surface and the edge of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the oxide 230b. Since the edges do not have corners, the coverage of the film in the subsequent film forming process is improved.

Note that processing of the oxide film may be performed using a lithography method. A dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.

Note that a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material is formed on the oxide film 230B, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask having a desired shape. can do. The insulating film 224A, the oxide film 230A, and the oxide film 230B may be etched after removing the resist mask or may be etched with the resist mask left. In the latter case, the resist mask may disappear during etching. After etching the oxide film, the hard mask may be removed by etching. On the other hand, if the hard mask material does not affect the post-process, or if it can be used in the post-process, it is not always necessary to remove the hard mask.

Further, when the above treatment such as dry etching is performed, impurities caused by an etching gas or the like might adhere to or diffuse onto or inside the insulator 224, the oxides 230a, and the oxides 230b. Impurities include, for example, fluorine or chlorine.

Cleaning is performed to remove the above impurities. As a cleaning method, there are wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, or the like, and the above cleaning may be performed in combination as appropriate.

Wet cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning is performed using pure water or carbonated water.

Subsequently, heat treatment may be performed. As the conditions for the heat treatment, the conditions for the heat treatment described above can be used.

Next, an oxide film to be the oxide film 230C is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b.

An oxide film to be the oxide film 230C can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. An oxide film to be the oxide film 230C may be formed using a film formation method similar to that for the oxide film 230A or the oxide film 230B in accordance with the characteristics required for the oxide 230c. In this embodiment, the oxide film to be the oxide film 230C is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio].

Next, the oxide film to be the oxide film 230C is etched to form the oxide film 230C (see FIG. 34).

Subsequently, an insulating film 250A, a conductive film 260A, a conductive film 260B, and an insulating film 271A are formed in this order on the oxide film 230C (see FIG. 34). Note that the insulating film 250A, the conductive film 260A, the conductive film 260B, and the insulating film 271A in Embodiment 1 are used for the materials, formation methods, and the like of the insulating film 250A, the conductive film 260A, the conductive film 260B, and the insulating film 271A. can be considered.

Note that a metal oxide film may be formed separately before forming the conductive film 260A. As the metal oxide film, an In--Ga--Zn oxide is formed by sputtering, for example. As a method for forming the metal oxide film, a sputtering method is preferably used in an atmosphere containing an oxygen gas. By forming the metal oxide film in an atmosphere containing oxygen gas, an excess oxygen region can be formed in the insulating film 250A. Excess oxygen added to the insulating film 250A supplies oxygen to the oxide 230, so that oxygen vacancies in the oxide 230 can be compensated.

Here, as means for forming the metal oxide film, a sputtering apparatus is used to form the film in an oxygen gas atmosphere. oxygen can be introduced into the Moreover, by using one or both oxides of aluminum and hafnium having barrier properties for the metal oxide film, excess oxygen introduced into the insulating film 250A can be effectively confined.

For example, as the conductive film 260A, a metal nitride may be formed by a sputtering method. For example, when an oxide semiconductor typified by an In--Ga--Zn oxide is formed as the above-described metal oxide film on the insulating film 250A, the metal oxide film is supplied with nitrogen or hydrogen. , the carrier density increases. That is, the metal oxide film functions as an oxide conductor (OC). Therefore, by forming a metal nitride by a sputtering method as the conductive film 260A, constituent elements (especially nitrogen) in the metal nitride diffuse into the metal oxide film, and the resistance of the metal oxide film is lowered. Moreover, the resistance of the metal oxide film is reduced due to damage (for example, sputtering damage) during the formation of the conductive film 260A. Therefore, the carrier density of the metal oxide film is increased, and the conductivity of the metal oxide film is increased.

A heat treatment can then be performed. For the heat treatment, the heat treatment conditions described above can be used. Note that the heat treatment may not be performed in some cases. By this heat treatment, excess oxygen is added to the insulating film 250A from the metal oxide film described above, and an excess oxygen region can be easily formed in the insulating film 250A.

The insulating film 271A is preferably thicker than the insulating film 272A to be formed in a later step. Accordingly, the insulator 271 can be easily left over the conductor 260 when the insulator 272 is formed in a later step.

Note that an insulating film functioning as a barrier film may be separately formed before forming the insulating film 271A. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, it is preferable to use aluminum oxide or hafnium oxide. Thereby, oxidation of the conductor 260 can be suppressed. In addition, entry of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed.

Next, the insulator 271 is formed by etching the insulating film 271A. Here, insulator 271 functions as a hard mask. By providing the insulator 271, the side surface of the oxide 230c, the side surface of the insulator 250, the side surface of the conductor 260a, and the side surface of the conductor 260b can be formed substantially perpendicular to the top surface of the substrate.

Next, using the insulator 271 as a mask, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are etched, and the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260a are etched). 260b) (see FIG. 35).

Note that part of the insulator 222 may be removed by the etching in a region where the insulator 222 and the insulator 250 do not overlap. In this case, the thickness of the region of the insulator 222 that overlaps with the insulator 250 may be greater than the thickness of the region that does not overlap with the insulator 250 .

At least part of the oxide 230 c , the insulator 250 , the conductor 260 , and the insulator 271 overlaps with the conductor 205 and the oxide 230 .

Moreover, the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 are preferably in the same plane.

Also, the same plane shared by the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 is preferably substantially perpendicular to the top surface of the substrate. That is, in the cross-sectional shape, the angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 is preferably acute and large. Note that in the cross-sectional shape, the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 may form an acute angle. In that case, the angle between the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 is preferably as large as possible.

Note that post-processes may be performed without removing the hard mask (insulator 271) after the above processing.

Next, an insulating film 272A is formed to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 271 (see FIG. 36). The insulating film 272A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film 272A is preferably formed by the ALD method, which has excellent coverage. By using the ALD method, the insulating film 272A having a uniform thickness is formed on the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 even in the stepped portion formed by the conductor 260 or the like. be able to. Also, by using the ALD method, a dense thin film can be formed.

As the insulating film 272A, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or It is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.

On the other hand, as the insulating film 272A, aluminum oxide or the like having a barrier property may be provided. For example, when the conductor 260 is a metal film that is easily oxidized, the use of an insulator having a barrier property can suppress oxidation of the conductor 260 by oxygen from above the insulating film 272A. Thereby, it is possible to suppress an increase in the resistance value of the conductor 260 .

When aluminum oxide is provided as the insulating film 272A by ALD, the film thickness of the insulating film 272A is preferably 0.5 nm or more and 3.0 nm or less. With such a structure, excess oxygen contained in the insulator 273 can be supplied to the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, an insulating film 273A is provided on the insulating film 272A (see FIG. 36). The insulating film 273A is preferably formed using aluminum oxide formed by a sputtering method. By using a sputtering method, an aluminum oxide film containing a large amount of oxygen and containing few impurities such as water or hydrogen can be formed.

In addition, by performing film formation in an oxygen gas atmosphere using a sputtering apparatus, oxygen can be introduced into the insulating film 272A while the insulating film 273A is being formed. Thereby, oxygen in the insulating film 273A is supplied to the insulating film 272A using the insulating film 273A as an oxygen supply source, and an excess oxygen region can be formed in the insulating film 272A. Oxygen in the excess oxygen region can be supplied to the oxide 230 by subsequent heat treatment or the like to compensate for oxygen vacancies in the region 234 of the oxide 230 .

Next, the insulating films 272A and 273A are subjected to anisotropic etching treatment to form insulators 272 and 273 on side surfaces of the oxide 230c, the insulator 250, and the conductor 260 (see FIG. 37). .).

As the anisotropic etching treatment, dry etching treatment is preferably performed. As a result, the insulator 272 and the insulator 273 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface. Note that the insulator 222 can be used as an etching stopper film in the treatment.

Subsequently, a film is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b through the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 273. 242A is deposited (see FIG. 38). Note that the film 242A may have a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less. A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used for the film 242A. The film 242A is, for example, a film containing metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium. Note that the film 242A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Moreover, you may perform heat processing in a pressure-reduced state. For example, as heat treatment, treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere after forming the film 242A.

By heat treatment in an atmosphere containing nitrogen, the metal element described above diffuses from the film 242A into the oxide 230, and the metal element can be added to the oxide 230. FIG. Oxygen in the vicinity of the interface between the oxide 230 and the film 242A may be absorbed by the film 242A. As a result, the vicinity of the interface between the oxide 230 and the film 242A becomes a metal compound, resulting in a low resistance. In this case, part of the oxide 230 and the metal element described above may be alloyed. By alloying part of the oxide 230 with the metal element, the metal element added to the oxide 230 is in a relatively stable state, so that a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

Alternatively, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.

Further, when a conductive region remains in the film 242A, heat treatment is performed in an oxidizing atmosphere to oxidize the film 242A so that it becomes an insulator and has a high resistance. By leaving the film 242A as an insulator, it can function as an interlayer film.

Oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the film 242A in the film formation step or the heat treatment of the film 242A. may occur. Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are n-type and have a low resistance.

Subsequently, the film 242A is removed (see FIG. 39). In the drawing, the regions of the oxide 230 whose resistance has been reduced by the above-described processing are indicated by hatching. Note that the metal film, the nitride film containing the metal element, or the oxide film containing the metal element does not necessarily have to be removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230, becomes an insulator, and has a high resistance, it may be left. . In that case, it may function as an interlayer film. A dry etching method or a wet etching method can be used in this step. By removing the film 242A, the hydrogen in the oxide 230 absorbed by the film 242A can be removed at the same time. Therefore, hydrogen which is an impurity in the transistor 200C can be reduced.

A heat treatment can then be performed. For the heat treatment, the heat treatment conditions described above can be used. By the heat treatment, hydrogen captured by oxygen vacancies formed in the region 231 of the oxide 230 is absorbed by the insulator 273 through the insulator 272 or the insulator 280, so that hydrogen in the oxide 230 is reduced. be able to.

Next, an insulator 280 is formed over the insulator 273 . Note that the insulator 280 in Embodiment 1 can be referred to for the material, formation method, and the like of the insulator 280 .

Next, an insulator 282 is formed over the insulator 280 (see FIG. 40). The insulator 282 is preferably made of the same material as the insulator 273 . With this structure, impurities such as hydrogen and water from above the insulator 282 can be prevented from entering the transistor 200C side. Further, hydrogen contained in the insulator 280 can be extracted to the insulator 282 in some cases.

Next, an opening is formed in the insulator 282 and the insulator 280 down to the oxide 230 (see FIG. 41). The formation of the opening may be performed using a lithography method. Note that the openings reaching the oxide 230 are formed so that the side surfaces of the oxide 230 are exposed so that the conductors 240 a and 240 b are provided in contact with the side surfaces of the oxide 230 .

Next, a conductive film to be a first conductor of the conductor 240 and a second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, when forming the openings in the insulator 282 and the insulator 280, the low resistance region of the region 231 in the oxide 230 may be removed. As the first conductor of the conductor 240, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be used. Accordingly, since there is a region where the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen vacancies are formed in the region, and the contact region between the oxide 230 and the conductor 240 has a low resistance. can be Sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured by reducing the resistance of the oxide 230 that is in contact with the first conductor of the conductor 240 . Therefore, the first conductor of the conductor 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium.

Next, CMP treatment is performed to remove part of the conductive film to be the conductors 240 a and 240 b to expose the insulator 282 . As a result, the conductive film remains only in the openings, so that the conductors 240a and 240b with flat top surfaces can be formed (see FIG. 30).

Through the above steps, a semiconductor device including the transistor 200C can be manufactured. As shown in FIGS. 32 to 41, the transistor 200C can be manufactured by using the manufacturing method of the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

<Modified Example of Semiconductor Device>
An example of a semiconductor device including a transistor 200C according to one embodiment of the present invention will be described below with reference to FIGS.

FIG. 42A is a top view of a semiconductor device having a transistor 200C. 42B, 42C, and 42D are cross-sectional views of the semiconductor device. Here, FIG. 42B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 42A, and is also a cross-sectional view in the channel length direction of the transistor 200C. FIG. 42C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 42A, and is also a cross-sectional view in the channel width direction of the transistor 200C. FIG. 42D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 42A, and is also a cross-sectional view of the source region or drain region of the transistor 200C. Note that in the top view of FIG. 42A, some elements are omitted for clarity of illustration.

In the semiconductor device shown in FIG. 42, structures having the same functions as structures forming the semiconductor device (see FIG. 30) shown in <Structure Example of Semiconductor Device> are denoted by the same reference numerals.

The configuration of the transistor 200C will be described below with reference to FIG. Also in this item, the materials described in detail in the above embodiments and <Structure Example of Semiconductor Device> can be used as the material for forming the transistor 200C.

In the semiconductor device shown in FIG. 42, side surfaces of insulator 224, oxides 230a and 230b and surfaces parallel to the substrate surface have taper angles. Specifically, as shown in FIG. 42B, the taper angle should be 45° or more and 80° or less, preferably 50° or more and 70° or less. Since the insulator 224, the oxide 230a, and the oxide 230b have tapered structures, the insulating film 272A and the insulating film 273A are subjected to an anisotropic etching treatment (see FIGS. 36 and 37). Later, the sides of oxide 230a and oxide 230b can be completely exposed.

Therefore, the side surfaces of the oxides 230a and 230b can be reliably in contact with the film 242A (see FIG. 38) as compared with the semiconductor device having a structure without the tapered structure (see FIG. 30). Become. As a result, the metal compound is reliably formed also on the side surfaces of the oxides 230a and 230b, and the resistance can be reduced. In other words, the region 231 can be reliably formed on the side surface of the oxide 230 as well. Further, since the oxide 230a and the oxide 230b have a tapered structure, the coating property of the structure formed above the oxide 230a and the oxide 230b can be improved.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 4)
An example of a semiconductor device including a transistor 200D according to one embodiment of the present invention, which is different from the semiconductor device including the transistor described in Embodiment 3, will be described below.

Note that in the semiconductor device described in this embodiment, structures having the same functions as the structures constituting the semiconductor devices described in the previous embodiments are denoted by the same reference numerals. Therefore, differences from the semiconductor device shown in the previous embodiment will be mainly described, and repeated descriptions will be omitted. Further, when there is no particular description of materials, manufacturing methods, and the like of structures denoted by the same reference numerals, the descriptions in the above embodiments can be referred to for the materials, manufacturing methods, and the like of the structures.

<Structure example of semiconductor device>
43A to 43D are a top view and a cross-sectional view of a transistor 200D and its periphery according to one embodiment of the present invention.

FIG. 43A is a top view of a semiconductor device having a transistor 200D. 43B, 43C, and 43D are cross-sectional views of the semiconductor device. Here, FIG. 43B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 43A, and is also a cross-sectional view in the channel length direction of the transistor 200D. FIG. 43C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 43A, and is also a cross-sectional view in the channel width direction of the transistor 200D. FIG. 43D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 43A, and is also a cross-sectional view of the source region or drain region of the transistor 200D. Note that in the top view of FIG. 1A, some elements are omitted for clarity.

A semiconductor device of one embodiment of the present invention includes a transistor 200D and insulators 210, 212, 280, and 282 functioning as interlayer films. It also includes a conductor 203 that is electrically connected to the transistor 200D and functions as a wiring, and a conductor 240 that functions as a plug.

In the conductor 240, the first conductor of the conductor 240 is formed in contact with the inner walls of the openings of the insulator 275, the insulator 273, the insulator 280, and the insulator 282. A second conductor is formed. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 282 can be made approximately the same. Note that although the structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown in the transistor 200D, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.

[Transistor 200D]
The transistor 200D illustrated in FIG. 43 includes an insulator 277 provided on the side surface of the conductor 260 with the insulator 272 interposed therebetween, the insulator 275 provided on the side surface of the insulator 277 and the oxide 230, and the insulator 275 The transistor 200C is different from the transistor 200C described in Embodiment 3 in that it has an insulator 273 arranged on 275 and .

In the transistor 200, an oxide semiconductor is preferably used for the oxides 230 (the oxides 230a, 230b, and 230c) including a channel formation region.

Since the transistor 200D including an oxide semiconductor for a channel formation region has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. Further, since an oxide semiconductor can be deposited by a sputtering method or the like, it can be used for the transistor 200D included in a highly integrated semiconductor device.

Here, the oxide semiconductor forms a metal compound with low resistance by adding metal elements such as aluminum, ruthenium, titanium, tantalum, chromium, and tungsten in addition to the elements constituting the oxide semiconductor. become Note that it is preferable to use aluminum, titanium, tantalum, tungsten, or the like. In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, when the film is provided, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film or the like, forming oxygen vacancies and causing oxidation. In some cases, the vicinity of the interface of the material semiconductor becomes low in resistance.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment is preferably performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal element can be diffused from the metal film into the oxide semiconductor, and the metal element can be added to the oxide semiconductor. Note that at that time, the oxide semiconductor and the metal element may be alloyed. By alloying the oxide semiconductor and the metal element, the metal element added to the oxide semiconductor is in a relatively stable state; therefore, a highly reliable semiconductor device can be provided.

In addition, when hydrogen existing in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor and enters oxygen vacancies in the low-resistance region, the hydrogen is in a relatively stable state. Further, hydrogen in the oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and oxygen vacancies existing in the low-resistance region. It is known that it enters into the inside and becomes a relatively stable state. Therefore, by heat treatment, the resistance of the region where the resistance of the oxide semiconductor is reduced or the region where the metal compound is formed is further reduced, and the oxide semiconductor which is not reduced in resistance is purified (impurities such as water and hydrogen). reduction) and tends to increase the resistance.

In addition, the oxide semiconductor has an increased carrier density when an impurity element such as hydrogen or nitrogen is present. Hydrogen in the oxide semiconductor reacts with oxygen that bonds to a metal atom to become water, which may cause oxygen vacancies. Hydrogen entering the oxygen vacancies increases the carrier density. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to an oxide semiconductor, a high-resistance region and a low-resistance region can be provided in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the island-shaped oxide 230 has a region functioning as a semiconductor with low carrier density and a region functioning as a source region or a drain region. A region can be provided.

Here, FIG. 44 shows an enlarged view of a region 239 including the selectively low-resistance oxide 230b surrounded by a broken line in FIG. 43(B).

As shown in FIG. 44, the oxide 230 includes a region 234 functioning as a channel forming region of the transistor 200D, a region 231 (regions 231a and 231b) functioning as a source region or a drain region, and a region 234 and a region 231. and a region 232 (regions 232a and 232b) provided between and.

In order to reduce the resistance of the region 231 , for example, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be formed in contact with the region 231 of the oxide 230 . The metal film, the nitride film containing the metal element, or the oxide film containing the metal element is oxidized through at least the oxide 230 c , the insulator 250 , the conductor 260 , the insulator 271 , the insulator 272 , and the insulator 277 . It is preferably provided on object 230b.

By providing a metal film, a nitride film containing the metal element, or an oxide film containing the metal element in contact with the region 231 of the oxide 230, the metal element diffuses from the film into the region 231 of the oxide 230, A metal compound is formed at 231 to lower the resistance. Further, part of oxygen in the oxide 230 located at or near the interface between the region 231 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is absorbed by the film, Oxygen vacancies may be formed in the region 231 to lower the resistance. In FIG. 2, the low-resistance region of the oxide 230 is represented by oblique lines as an example. In this specification and the like, the shaded range is not limited to the range in FIG. For example, the low resistance region (or range) is formed in a region near the interface between the oxide 230 and the conductor 240 or in a region from the top surface of the oxide 230 to the bottom surface of the oxide 230 in the region 231. may occur. The same applies to other drawings.

Heat treatment may be performed in an atmosphere containing nitrogen while the region 231 is in contact with the metal film, the nitride film containing the metal element, or the oxide film containing the metal element. By the heat treatment, the metal element can be diffused from the metal film into the region 231 of the oxide 230 and added to the region 231 . At that time, the region 231 of the oxide 230 and the metal element may be alloyed. By alloying the region 231 of the oxide 230 with the metal element, the metal element added to the oxide semiconductor is relatively stable; therefore, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

On the other hand, addition of a metal element to regions (regions 234 and 232 ) of the oxide 230 overlapping with the conductor 260 and the insulator 272 is suppressed by the conductor 260 and the insulator 272 . In addition, in the regions 234 and 232 of the oxide 230, absorption of oxygen atoms in the oxide 230 by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is suppressed. be.

In addition, oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element. Oxygen deficiency may occur at 232 . Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are made low resistance.

Here, if a metal film, a nitride film containing a metal element, or an oxide film containing a metal element has the property of absorbing hydrogen, the hydrogen in the oxide 230 is absorbed by the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Also, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element may be removed together with the hydrogen absorbed from the oxide 230 in a later step.

Note that the metal film, the nitride film containing the metal element, or the oxide film containing the metal element does not necessarily have to be removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230, becomes an insulator, and has a high resistance, it may be left. . In that case, it may function as an interlayer film.

Further, for example, when a conductive region remains in a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, heat treatment is performed in an oxidizing atmosphere to oxidize the film. , becomes an insulator and has a high resistance. By leaving a metal film, a nitride film containing a metal element, or an oxide film containing a metal element as an insulator, it can function as an interlayer film.

Therefore, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is preferably provided with a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 2 nm or less. For example, when aluminum with a thickness of 0.5 nm or more and 5 nm or less is oxidized by heat treatment, aluminum oxide with a thickness of 0.7 nm or more and 8 nm or less may be obtained.

Here, in a transistor including an oxide semiconductor, if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to fluctuate, and reliability may be degraded. In addition, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor tends to have normally-on characteristics. Therefore, oxygen vacancies in the region 234 where the channel is formed are preferably reduced as much as possible.

Therefore, as shown in FIGS. 43 and 44, it is preferable to provide an insulator 275 containing more oxygen than the stoichiometric composition (also referred to as excess oxygen) in contact with the oxide 230b. That is, excess oxygen in the insulator 275 diffuses into the region 234 of the oxide 230, so that oxygen vacancies in the region 234 of the oxide 230 can be reduced.

Note that silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having holes is preferably used for the insulator 275 . Materials such as silicon oxynitride are prone to the formation of excess oxygen regions. On the other hand, compared to materials such as silicon oxynitride discussed above, oxide 230 tends to be less susceptible to the formation of excess oxygen regions. Therefore, by providing the insulator 275 having the excess oxygen region around the region 234 of the oxide 230 , excess oxygen of the insulator 275 can be effectively supplied to the region 234 of the oxide 230 .

In order to provide the excess oxygen region in the insulator 275, an oxide film is preferably formed as the insulator 273 on and in contact with the insulator 275 by a sputtering method. By using a sputtering method for forming an oxide film, an insulator containing a large amount of oxygen and containing few impurities such as water or hydrogen can be formed. When the sputtering method is used, it is preferable to form the film using, for example, a facing target type sputtering apparatus. Since the facing target type sputtering apparatus can form a film without exposing the film formation surface to the high electric field region between the opposing targets, the film formation surface is less likely to be damaged by plasma. Therefore, damage to the insulator 275 and the oxide 230 during deposition of the insulator to be the insulator 273 can be reduced, which is preferable.

During film formation by the sputtering method, ions and sputtered particles are present between the target and the substrate. For example, the target is connected to a power supply and given a potential E0. A potential E1 such as a ground potential is applied to the substrate. However, the substrate may be electrically floating. A region having potential E2 exists between the target and the substrate. The magnitude relationship between the potentials is E2>E1>E0.

Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, thereby ejecting sputtered particles from the target. The sputtered particles adhere to the film formation surface and accumulate to form a film. In addition, some ions recoil by the target, pass through the film formed as recoil ions, and may be taken into the insulator 275 in contact with the deposition surface. Also, the ions in the plasma are accelerated by the potential difference E2-E1 and bombard the surface of the film. At this time, some of the ions reach the inside of the insulator 275 . By capturing ions into the insulator 275 , a region in which ions are captured is formed in the insulator 275 . That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 275 .

By introducing excess oxygen into the insulator 275 , an excess oxygen region can be formed in the insulator 275 . Excess oxygen in insulator 275 is supplied to oxide 230 in contact with insulator 275 . By supplying the oxygen to the region 234 of the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

Aluminum oxide is preferably used for the insulator 273 . In particular, it is preferable to use aluminum oxide formed by a sputtering method. By using aluminum oxide deposited by a sputtering method, the insulator 273 containing much oxygen can be formed. Thus, the insulator 273 serves as an oxygen supply source, and oxygen can be supplied to the insulator 275 and the region 234 of the oxide 230 as described above.

43 and 44, insulator 275 and conductor 260 are physically separated by insulator 271, insulator 272, and insulator 277. Insulator 271, insulator 272, and insulator 277 are provided. With such a structure of the transistor 200D, oxidation of the conductor 260 functioning as a gate electrode due to oxygen from the insulator 275 can be suppressed.

By combining the above structure or the above steps, the resistance of the oxide 230 can be selectively reduced.

That is, when the low-resistance region is formed in the oxide 230, the conductor 260, the insulator 272, or the insulator 277 functioning as a gate electrode is used as a mask, so that the oxide 230 has a low resistance in a self-aligned manner. do. Therefore, when a plurality of transistors 200D are formed at the same time, variations in electrical characteristics among the transistors can be reduced. In addition, the channel length of the transistor 200D is determined by the width of the conductor 260 and the film thickness of the insulator 272; Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor including an oxide semiconductor for a channel formation region has extremely low leakage current (off-state current) in a non-conducting state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

In the following description, among the structures of the semiconductor device including the transistor 200D according to one embodiment of the present invention, the semiconductor device including the transistor 200A described in Embodiment 1 and the semiconductor device including the transistor 200C described in Embodiment 3 are described. Let me explain the points.

Oxide 230 also has regions 231 , 232 , and 234 . Note that at least part of the region 231 has a region in contact with the insulator 275 . Also, the region 232 has at least a region overlapping with the insulator 272 .

In addition, an insulator 277 is provided over part of the top surface of the oxide 230b (the portion overlapping with the region 232), the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 with the insulator 272 interposed therebetween. . With such a structure, the insulator 275 having the excess oxygen region and the conductor 260 can be reliably isolated from each other by the insulator 272 and the insulator 277 . Therefore, oxidation of the conductor 260 functioning as a gate electrode by oxygen from the insulator 275 can be suppressed.

Insulator 277 preferably has an insulator with a low dielectric constant. For example, the insulator 277 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. , or resin. Alternatively, the insulator 277 is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

Insulator 275 is provided to have at least a region in contact with region 231 of oxide 230 . Insulator 275 preferably has excess oxygen regions. For example, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies is used as the insulator 275, excess oxygen regions are likely to be formed in the insulator 275 when the insulator 273 is formed later. . Since the insulator 275 has the excess oxygen region, oxygen contained in the region can be efficiently supplied to the oxide 230 .

The insulator 273 is provided on the insulator 275 . By forming the insulator 273 by a sputtering method, an excess oxygen region can be provided in the insulator 275 . Thereby, oxygen can be supplied into the oxide 230 from the excess oxygen region.

For example, the insulator 273 can be a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, or the like. can be done.

In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film having a thickness of 0.5 nm or more and 3.0 nm or less. Therefore, the aluminum oxide film formed by the sputtering method can function not only as an oxygen supply source but also as a barrier film against impurities such as hydrogen. For example, by using aluminum oxide deposited by a sputtering method for the insulator 273 , the insulator 273 supplies oxygen to the insulator 275 and impurities such as hydrogen from above the insulator 273 are removed from the insulator 275 . It is possible to suppress mixing into the side.

In addition, the conductors 240 a and 240 b are arranged in the openings formed in the insulators 282 , 280 , 273 , and 275 . The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be flush with the top surface of the insulator 282 .

Note that a first conductor of the conductor 240 a is formed in contact with the inner walls of the openings of the insulators 282 , 280 , 273 , and 275 . A region 231a of oxide 230 is located in at least part of the bottom of the opening, and a conductor 240a is in contact with region 231a. Similarly, a first conductor of conductor 240 b is formed in contact with the inner walls of the openings of insulator 282 , insulator 280 , insulator 273 , and insulator 275 . A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductor 240b contacts region 231b.

Here, for example, when openings are formed in the insulator 282 , the insulator 280 , the insulator 273 , and the insulator 275 , the low-resistance region of the region 231 may be removed in the oxide 230 . In that case, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used as the first conductor of the conductor 240 . That is, when the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen vacancies are formed, and the resistance of the region 231 of the oxide 230 is reduced. Therefore, by reducing the resistance of the oxide 230 in contact with the first conductor of the conductor 240, the contact resistance between the oxide 230 and the conductor 240 can be reduced. The first conductor of conductor 240 preferably contains a metal element such as aluminum, ruthenium, titanium, tantalum, tungsten, or the like.

In the case where the conductor 240 has a layered structure, conductors in contact with the insulator 275, the insulator 273, the insulator 280, and the insulator 282 include the first conductor 205a of the conductor 205 and the like. A conductive material having a function of suppressing permeation of impurities such as water or hydrogen is preferably used. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. In addition, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from a layer above the insulator 282 can be prevented from entering the oxide 230 through the conductors 240a and 240b.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing a semiconductor device having the transistor 200D according to the present invention will be described with reference to FIGS. 45 to 50, (A) in each figure shows a top view. (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in (A), and is also a cross-sectional view in the channel length direction of the transistor 200D. (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200D. (D) of each figure is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in (A) of each figure, and is also a cross-sectional view of the source region or the drain region of the transistor 200D. In addition, in the top view of (A) of each figure, some elements are omitted for clarity of illustration.

The manufacturing method of the semiconductor device shown in FIG. 43 is the same as that of the semiconductor device shown in FIG. It is the same as the manufacturing method. Therefore, the manufacturing method of the semiconductor device illustrated in FIGS. 32 to 35 can be referred to.

Next, an insulating film 272A is formed to cover the oxide 230, the insulator 250, the conductor 260, and the insulator 271 (see FIG. 45). Note that the insulating film 272A in Embodiment 3 can be referred to for the material, the film formation method, and the like of the insulating film 272A.

When aluminum oxide is provided as the insulating film 272A by ALD, the film thickness of the insulating film 272A is preferably 0.5 nm or more and 3.0 nm or less. With such a structure, excess oxygen contained in the insulator 277 can be supplied to the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, an insulating film 277A is provided on the insulating film 272A (see FIG. 45). The insulating film 277A preferably has an insulator with a low dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, resin, or the like is used. It is preferable to have In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies for the insulating film 277A because an excess oxygen region can be easily formed in the insulating film 277 in a later step. In addition, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Next, the insulating films 272A and 277A are subjected to anisotropic etching treatment to form insulators 272 and 277 on side surfaces of the oxide 230c, the insulator 250, and the conductor 260 (see FIG. 46). .).

As the anisotropic etching treatment, dry etching treatment is preferably performed. As a result, the insulator 272 and the insulator 277 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface. Note that the insulator 222 can be used as an etching stopper film in the treatment.

Subsequently, a film is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b through the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 277. 242A is deposited (see FIG. 47). Note that the film 242A may have a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less. A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used for the film 242A. The film 242A is, for example, a film containing metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium. Note that the film 242A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, heat treatment is preferably performed. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Moreover, you may perform heat processing in a pressure-reduced state. For example, as heat treatment, treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere after forming the film 242A.

By heat treatment in an atmosphere containing nitrogen, the metal element described above diffuses from the film 242A into the oxide 230, and the metal element can be added to the oxide 230. FIG. Oxygen in the vicinity of the interface between the oxide 230 and the film 242A may be absorbed by the film 242A. As a result, the vicinity of the interface between the oxide 230 and the film 242A becomes a metal compound, resulting in a low resistance. In this case, part of the oxide 230 and the metal element described above may be alloyed. By alloying part of the oxide 230 with the metal element, the metal element added to the oxide 230 is in a relatively stable state, so that a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

Alternatively, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.

Further, when a conductive region remains in the film 242A, heat treatment is performed in an oxidizing atmosphere to oxidize the film 242A so that it becomes an insulator and has a high resistance. By leaving the film 242A as an insulator, it can function as an interlayer film.

Oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the film 242A in the film formation step or the heat treatment of the film 242A. may occur. Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are n-type and have a low resistance.

Subsequently, the film 242A is removed (see FIG. 48). In the drawing, the regions of the oxide 230 whose resistance has been reduced by the above-described processing are indicated by hatching. Note that the metal film, the nitride film containing the metal element, or the oxide film containing the metal element does not necessarily have to be removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230, becomes an insulator, and has a high resistance, it may be left. . In that case, it may function as an interlayer film. A dry etching method or a wet etching method can be used in this step. By removing the film 242A, the hydrogen in the oxide 230 absorbed by the film 242A can be removed at the same time. Therefore, hydrogen which is an impurity in the transistor 200D can be reduced.

Subsequently, insulation is provided over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b through the oxide 230c, the insulator 250, the conductor 260, the insulator 271, the insulator 272, and the insulator 277. A body 275 is deposited (see FIG. 49). Insulator 275 preferably has an insulator with a low dielectric constant. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, resin, or the like is used. It is preferable to have In particular, it is preferable to use silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies for the insulator 275 because an excess oxygen region can be easily formed in the insulator 275 in a later step. In addition, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

Next, an insulator 273 is formed over the insulator 275 (see FIG. 49). The insulator 273 is preferably formed using aluminum oxide by a sputtering method. By using a sputtering method, an aluminum oxide film containing a large amount of oxygen and containing few impurities such as water or hydrogen can be formed.

Alternatively, deposition is performed in an oxygen gas atmosphere using a sputtering apparatus, so that oxygen can be introduced into the insulator 275 while the insulator 273 is being deposited. Accordingly, oxygen in the insulator 273 is supplied to the insulator 275 using the insulator 273 as an oxygen supply source, so that an excess oxygen region can be formed in the insulator 275 .

As described above, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon oxide having vacancies is used as the insulator 275 , an excess oxygen region tends to be formed in the insulator 275 . On the other hand, compared with the silicon oxide described above, the oxide 230 tends to be less likely to form an excess oxygen region even if an oxide film is formed on the oxide 230 using a sputtering method. Therefore, for example, when the above oxide film is formed as the insulator 275 by sputtering, an excess oxygen region can be selectively formed in the insulator 277 . Further, at this time, since an excess oxygen region is less likely to be formed in the oxide 230, it is possible to suppress the above-described low resistance region in the oxide 230 from increasing in resistance.

The insulator 275 with the excess oxygen regions formed as described above can effectively supply oxygen from the excess oxygen regions to the regions 234 of the oxide 230 .

With the above structure, each region of the oxide 230 can be formed in a self-aligned manner. Therefore, miniaturized or highly integrated semiconductor devices can be manufactured with a high yield.

Therefore, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

A heat treatment can then be performed. For the heat treatment, the heat treatment conditions described above can be used. By the heat treatment, hydrogen captured by oxygen vacancies formed in the region 231 of the oxide 230 is absorbed by the insulator 273 through the insulator 275, so that hydrogen in the oxide 230 can be reduced.

Next, an insulator 280 and an insulator 282 are formed in order on the insulator 273 . Note that the insulator 280 in Embodiment 1 and the insulator 282 in Embodiment 3 can be referred to for materials, formation methods, and the like of the insulators 280 and 282 .

Next, openings are formed in insulator 282, insulator 280, insulator 273, and insulator 275 to reach oxide 230 (see FIG. 50). The formation of the opening may be performed using a lithography method. Note that the openings reaching the oxide 230 are formed so that the side surfaces of the oxide 230 are exposed so that the conductors 240 a and 240 b are provided in contact with the side surfaces of the oxide 230 .

Next, a conductive film to be a first conductor of the conductor 240 and a second conductor of the conductor 240 are formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, the low-resistance region of region 231 in oxide 230 may be removed when openings are formed in insulator 282 , insulator 280 , insulator 273 , and insulator 275 . As the first conductor of the conductor 240, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be used. Accordingly, since there is a region where the oxide 230 and the first conductor of the conductor 240 are in contact with each other, a metal compound or oxygen vacancies are formed in the region, and the contact region between the oxide 230 and the conductor 240 has a low resistance. can be Sufficient ohmic contact between the oxide 230 and the conductor 240 can be ensured by reducing the resistance of the oxide 230 that is in contact with the first conductor of the conductor 240 . Therefore, the first conductor of the conductor 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium.

Next, CMP treatment is performed to remove part of the conductive film to be the conductors 240 a and 240 b to expose the insulator 282 . As a result, the conductor 240a and the conductor 240b with flat top surfaces can be formed by leaving the conductive film only in the openings (see FIG. 43).

Through the above steps, a semiconductor device including the transistor 200D can be manufactured. As shown in FIGS. 45A to 50B, the transistor 200D can be manufactured by using the manufacturing method of the semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

<Modified Example of Semiconductor Device>
An example of a semiconductor device including a transistor 200D according to one embodiment of the present invention will be described below with reference to FIGS.

FIG. 51A is a top view of a semiconductor device having a transistor 200D. 51B, 51C, and 51D are cross-sectional views of the semiconductor device. Here, FIG. 51B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 51A, and is also a cross-sectional view in the channel length direction of the transistor 200D. FIG. 51C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 51A, and is also a cross-sectional view in the channel width direction of the transistor 200D. FIG. 51D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 51A, and is also a cross-sectional view of the source region or drain region of the transistor 200D. Note that in the top view of FIG. 51A, some elements are omitted for clarity of illustration.

In the semiconductor device shown in FIG. 51, structures having the same functions as structures forming the semiconductor device (see FIG. 43) shown in <Structure Example of Semiconductor Device> are denoted by the same reference numerals.

The configuration of the transistor 200D is described below with reference to FIG. Note that also in this item, the materials described in detail in the above embodiments and <Structure Example of Semiconductor Device> can be used as the material for forming the transistor 200D.

In the semiconductor device shown in FIG. 51, side surfaces of insulator 224, oxides 230a and 230b and surfaces parallel to the substrate surface have taper angles. Specifically, as shown in FIG. 51B, the taper angle should be 45° or more and 80° or less, preferably 50° or more and 70° or less. Since the insulator 224, the oxide 230a, and the oxide 230b have tapered structures, the insulating film 272A and the insulating film 277A are etched anisotropically (see FIGS. 45 and 46). Later, the sides of oxide 230a and oxide 230b can be completely exposed.

Therefore, compared to the semiconductor device having no tapered structure (see FIG. 43), the side surfaces of the oxides 230a and 230b are also in contact with the film 242A (see FIG. 47). Become. As a result, the metal compound is reliably formed also on the side surfaces of the oxides 230a and 230b, and the resistance can be reduced. In other words, the region 231 can be reliably formed on the side surface of the oxide 230 as well. Further, since the oxide 230a and the oxide 230b have a tapered structure, the coating property of the structure formed above the oxide 230a and the oxide 230b can be improved.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 5)
An example of a semiconductor device including the transistor 200E according to one embodiment of the present invention, which is different from the semiconductor device including the transistor described in Embodiment 3, will be described below.

Note that, in the semiconductor device described in this embodiment, structures having the same functions as the structures constituting the semiconductor devices described in the previous embodiments may be denoted by the same reference numerals. Therefore, differences from the semiconductor device shown in the previous embodiment will be mainly described, and repeated descriptions will be omitted. Further, when there is no particular description of materials, manufacturing methods, and the like of structures denoted by the same reference numerals, the descriptions in the above embodiments can be referred to for the materials, manufacturing methods, and the like of the structures.

<Structure Example 1 of Semiconductor Device>
52A and 52B are a top view and a cross-sectional view of a transistor 200E and its periphery according to one embodiment of the present invention.

FIG. 52A is a top view of a semiconductor device having a transistor 200E. 52B and 52C are cross-sectional views of the semiconductor device. Here, FIG. 52B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 52A, and is also a cross-sectional view in the channel length direction of the transistor 200E. FIG. 52C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 52A, and is also a cross-sectional view in the channel width direction of the transistor 200E. Note that in the top view of FIG. 52A, some elements are omitted for clarity of illustration.

A semiconductor device of one embodiment of the present invention includes a transistor 200E and insulators 210, 212, 280, and 282 functioning as interlayer films. It also includes a conductor 203 that is electrically connected to the transistor 200E and functions as a wiring, and a conductor 240 that functions as a plug.

Note that the conductor 203 is formed so as to be embedded in the insulator 212 . Here, the height of the upper surface of the conductor 203 and the height of the upper surface of the insulator 212 can be made approximately the same. Note that the conductor 203 has a single layer structure, but the present invention is not limited to this. For example, the conductor 203 may have a multi-layer structure of two or more layers. In addition, when the structure has a laminated structure, an ordinal number may be given in order of formation for distinction.

Also, the conductor 240 is formed in contact with the inner walls of the openings of the insulators 280 and 282 . Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 282 can be made approximately the same. Note that although the transistor 200E has a structure in which the conductor 240 is a single layer, the present invention is not limited to this. For example, the conductor 240 may have a laminated structure of two or more layers. Details of the openings and conductors 240 will be described later.

[Transistor 200E]
A transistor 200E illustrated in FIG. 52 includes an insulator 270 over a conductor 260, an insulator 272 disposed in contact with at least an oxide 230c, an insulator 250, and a side surface of the conductor 260, and an insulator 230b. The transistor 200C is different from the transistor 200C described in Embodiment 3 in that it has an insulator 275 arranged on the side surface of the conductor 260 with the insulator 272 interposed therebetween.

In the transistor 200E, an oxide semiconductor is preferably used for the oxides 230 (the oxides 230a, 230b, and 230c) including a channel formation region.

Since the transistor 200E including an oxide semiconductor for a channel formation region has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. Further, since an oxide semiconductor can be deposited by a sputtering method or the like, it can be used for the transistor 200E included in a highly integrated semiconductor device.

Here, the oxide semiconductor is formed by adding metal elements such as aluminum, ruthenium, titanium, tantalum, chromium, and tungsten in addition to the elements constituting the oxide semiconductor, thereby forming a metal compound and reducing the resistance. sometimes. Note that it is preferable to use aluminum, titanium, tantalum, tungsten, or the like. In order to add a metal element to an oxide semiconductor, for example, a metal film containing the metal element, a nitride film containing the metal element, or an oxide film containing the metal element is preferably provided over the oxide semiconductor. In addition, when the film is provided, part of oxygen in the oxide semiconductor located at or near the interface between the film and the oxide semiconductor is absorbed by the film or the like, forming oxygen vacancies and causing oxidation. In some cases, the vicinity of the interface of the material semiconductor becomes low in resistance.

The periphery of the oxygen vacancies formed in the vicinity of the interface has strain. Further, in the case where the above film is formed by a sputtering method, if a sputtering gas contains a rare gas, the rare gas may enter the oxide semiconductor during formation of the above film. When the rare gas enters the oxide semiconductor, strain or structural disorder occurs near the interface and around the rare gas. In addition, He, Ar, etc. are mentioned as said rare gas. Note that Ar is preferable to He because it has a larger atomic radius. When the Ar enters the oxide semiconductor, distortion or structural disorder is preferably caused. It is believed that in these strained or structurally disordered regions, the number of metal atoms with a small number of bonded oxygens increases. An increase in the number of metal atoms with a small number of bonded oxygen atoms may reduce the resistance in the vicinity of the interface and in the vicinity of the rare gas.

In the case where a crystalline oxide semiconductor is used as the oxide semiconductor, crystallinity is lost in the above strained or structurally disordered region, and the region may be observed as amorphous.

Further, after a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is provided over the oxide semiconductor, heat treatment is preferably performed in an atmosphere containing nitrogen. By heat treatment in an atmosphere containing nitrogen, the metal element can be diffused from the metal film into the oxide semiconductor, and the metal element can be added to the oxide semiconductor.

In addition, when hydrogen existing in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor and enters oxygen vacancies in the low-resistance region, the hydrogen is in a relatively stable state. Further, hydrogen in the oxygen vacancies present in the oxide semiconductor escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the low-resistance region of the oxide semiconductor, and oxygen vacancies existing in the low-resistance region. It is known that it enters into the inside and becomes a relatively stable state. Therefore, by heat treatment, the resistance of the region of the oxide semiconductor whose resistance has been reduced is further reduced, and the oxide semiconductor which has not been reduced in resistance is highly purified (impurities such as water and hydrogen are reduced) and is further increased in resistance. tend to

In addition, the oxide semiconductor has an increased carrier density when an impurity element such as hydrogen or nitrogen is present. Hydrogen in the oxide semiconductor reacts with oxygen that bonds to a metal atom to become water, which may cause oxygen vacancies. Hydrogen entering the oxygen vacancies increases the carrier density. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

Therefore, by selectively adding a metal element and an impurity element such as hydrogen and nitrogen to an oxide semiconductor, a high-resistance region and a low-resistance region can be provided in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 230, the island-shaped oxide 230 has a region functioning as a semiconductor with low carrier density and a region functioning as a source region or a drain region. A region can be provided.

Here, FIG. 60 shows an enlarged view of the region 239 including the selectively low-resistance oxide 230b surrounded by the broken line in FIG. 52(B).

As shown in FIG. 60A, the oxide 230 includes a region 234 functioning as a channel formation region of the transistor 200E, a region 231 functioning as a source region or a drain region (regions 231a and 231b), and a region 234 and a region 232 (a region 232a and a region 232b) provided between the region 231 and the region 232a.

Also, in FIGS. 52 and 60, regions 234, 231, and 232 are formed in oxide 230b, but the invention is not limited to this. For example, these regions may also be formed in oxide 230a and oxide 230c. Also, in FIGS. 52 and 60, the boundaries of each region are shown substantially perpendicular to the top surface of the oxide 230, but the present embodiment is not limited to this. For example, the region 232 may protrude toward the conductor 260 near the surface of the oxide 230b and recede toward the conductor 240a or 240b near the bottom surface of the oxide 230b.

In order to selectively reduce the resistance of the oxide 230, for example, at least one of a metal element that increases conductivity such as aluminum, ruthenium, titanium, tantalum, tungsten, chromium, and indium and an impurity is added to a desired region. do it. Note that an element that forms oxygen vacancies, an element that is captured by oxygen vacancies, or the like may be used as the impurity. Examples of such elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, rare gases, and the like. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon.

Therefore, in the region 231, the carrier density is increased and the resistance is reduced by increasing the content of the metal element that increases conductivity, the element that forms oxygen vacancies, or the element that is captured by oxygen vacancies. be able to.

In order to reduce the resistance of the region 231 , for example, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element may be formed in contact with the region 231 of the oxide 230 . A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is formed over the oxide 230 with at least the insulator 250, the conductor 260, the insulator 270, the insulator 272, and the insulator 275 interposed therebetween. It is preferable to provide

By providing a metal film, a nitride film containing the metal element, or an oxide film containing the metal element in contact with the region 231 of the oxide 230, the metal element diffuses from the film into the region 231 of the oxide 230, A metal compound is formed at 231 to lower the resistance. Further, part of oxygen in the oxide 230 located at or near the interface between the region 231 and the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is absorbed by the film, Oxygen vacancies may be formed in the region 231 to lower the resistance. Note that in FIG. 60, the region of the oxide 230 with reduced resistance is represented by oblique lines as an example. In this specification and the like, the shaded range is not limited to the range in FIG. For example, the low resistance region (or range) is formed in a region near the interface between the oxide 230 and the conductor 240 or in a region from the top surface of the oxide 230 to the bottom surface of the oxide 230 in the region 231. may occur. The same applies to other drawings.

Heat treatment may be performed in an atmosphere containing nitrogen while the region 231 is in contact with the metal film, the nitride film containing the metal element, or the oxide film containing the metal element. By the heat treatment, the metal element can be diffused from the metal film into the region 231 of the oxide 230 and added to the region 231 . At that time, the region 231 of the oxide 230 and the metal element may be alloyed. By alloying the region 231 of the oxide 230 with the metal element, the metal element added to the oxide semiconductor is relatively stable; therefore, a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

On the other hand, addition of a metal element to regions (regions 234 and 232 ) of the oxide 230 overlapping with the conductor 260 and the insulator 272 is suppressed by the conductor 260 and the insulator 272 . In addition, in the regions 234 and 232 of the oxide 230, absorption of oxygen atoms in the oxide 230 by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is suppressed. be.

In addition, oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the metal film, the nitride film containing the metal element, or the oxide film containing the metal element. Oxygen deficiency may occur at 232 . Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are made low resistance.

Here, if a metal film, a nitride film containing a metal element, or an oxide film containing a metal element has the property of absorbing hydrogen, the hydrogen in the oxide 230 is absorbed by the film. Therefore, hydrogen which is an impurity in the oxide 230 can be reduced. Also, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element may be removed together with the hydrogen absorbed from the oxide 230 in a later step.

Note that the metal film, the nitride film containing the metal element, or the oxide film containing the metal element does not necessarily have to be removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230, becomes an insulator, and has a high resistance, it may be left. . In that case, it may function as an interlayer film.

Further, for example, when a conductive region remains in a metal film, a nitride film containing a metal element, or an oxide film containing a metal element, heat treatment is performed in an oxidizing atmosphere to oxidize the film. , becomes an insulator and has a high resistance. By leaving a metal film, a nitride film containing a metal element, or an oxide film containing a metal element as an insulator, it can function as an interlayer film.

Therefore, the metal film, the nitride film containing the metal element, or the oxide film containing the metal element is preferably provided with a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 2 nm or less. For example, when aluminum with a thickness of 0.5 nm or more and 5 nm or less is oxidized by heat treatment, aluminum oxide with a thickness of 0.7 nm or more and 8 nm or less may be obtained.

Here, in a transistor including an oxide semiconductor, if impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded. In addition, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor tends to have normally-on characteristics. Therefore, oxygen vacancies in the region 234 where the channel is formed are preferably reduced as much as possible.

As the insulator 275, an oxide film is preferably formed by a sputtering method. By using a sputtering method for forming an oxide film, an insulator containing few impurities such as water or hydrogen can be formed. When the sputtering method is used, it is preferable to form the film using, for example, a facing target type sputtering apparatus. The facing target type sputtering apparatus can form a film without exposing the film formation surface to the high electric field region between the opposing targets. This is preferable because film damage to the oxide 230 can be reduced when an insulator to be the insulator 275 is formed.

During film formation by the sputtering method, ions and sputtered particles are present between the target and the substrate. For example, the target is connected to a power supply and given a potential E0. A potential E1 such as a ground potential is applied to the substrate. However, the substrate may be electrically floating. A region having potential E2 exists between the target and the substrate. The magnitude relationship between the potentials is E2>E1>E0.

Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, thereby ejecting sputtered particles from the target. The sputtered particles adhere to the film formation surface and accumulate to form a film. In addition, some ions may recoil by the target, pass through the film formed as recoil ions, and be taken into the insulator 272 which is in contact with the deposition surface. Also, the ions in the plasma are accelerated by the potential difference E2-E1 and bombard the surface of the film. At this time, some of the ions reach the inside of the insulator 272 . By capturing ions into the insulator 272 , a region in which ions are captured is formed in the insulator 272 . That is, when the ions are ions containing oxygen, an excess oxygen region is formed in the insulator 272 . Therefore, the insulator 275 is preferably formed using aluminum oxide deposited by a sputtering method.

As shown in FIGS. 52 and 60A, the insulator 275 is in contact with the insulator 272, and the insulator 272 has regions in contact with the insulator 224 and the oxide 230c. As noted above, an insulator 272 may be provided that contains more oxygen than the stoichiometric composition (also referred to as excess oxygen). That is, excess oxygen in the insulator 272 diffuses into the region 234 of the oxide 230, so that oxygen vacancies in the region 234 of the oxide 230 can be reduced.

Further, when heat treatment is performed while the aluminum oxide is in contact with the oxide 230 , hydrogen in the oxide 230 may be extracted. Therefore, the hydrogen concentration in the oxide 230 can be reduced.

By combining the above structure or the above steps, the resistance of the oxide 230 can be selectively reduced.

That is, when the low-resistance region is formed in the oxide 230, the resistance of the oxide 230 is lowered in a self-aligned manner by using the conductor 260 or the insulator 272 functioning as a gate electrode as a mask. Therefore, when a plurality of transistors 200E are formed at the same time, variations in electrical characteristics among the transistors can be reduced. In addition, the channel length of the transistor 200E is determined by the width of the conductor 260 and the film thickness of the insulator 272. By setting the width of the conductor 260 as the minimum processing dimension, the transistor 200E can be miniaturized. Become.

As described above, by appropriately selecting the range of each region, it is possible to easily provide a transistor having electrical characteristics meeting the requirements in accordance with the circuit design.

Further, since an oxide semiconductor can be formed by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device. In addition, since a transistor including an oxide semiconductor for a channel formation region has extremely low leakage current (off-state current) in a non-conducting state, a semiconductor device with low power consumption can be provided.

As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

In the following description, among the structures of the semiconductor device including the transistor 200E according to one embodiment of the present invention, the semiconductor device including the transistor 200A described in Embodiment 1 and the semiconductor device including the transistor 200C described in Embodiment 3 are described. Let me explain the points.

As shown in FIG. 72, the electron affinity or the energy level Ec at the lower end of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level Evac and the energy level Ev at the upper end of the valence band, and the bandgap Eg. can be done. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device. The energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.

Oxide 230 also has regions 231 , 232 , and 234 . Note that at least part of the region 231 has a region in contact with the insulator 273 . Also, the region 232 has at least a region overlapping with the insulator 272 .

By providing an insulator from which oxygen is released by heating as the insulator 250 in contact with the top surface of the oxide 230c, oxygen can be effectively supplied from the insulator 250 to the region 234 of the oxide 230b. . Further, similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

In addition, a metal oxide may be provided over the insulator 250 in order to efficiently supply excess oxygen contained in the insulator 250 to the oxide 230 . Therefore, the metal oxide preferably suppresses diffusion of oxygen from the insulator 250 . By providing the metal oxide that suppresses diffusion of oxygen, diffusion of excess oxygen from the insulator 250 to the conductor 260 is suppressed. That is, reduction in the amount of excess oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to excess oxygen can be suppressed.

Further, an insulator 270 functioning as a barrier film may be placed over the conductor 260b. For the insulator 270, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, it is preferable to use aluminum oxide or hafnium oxide. Accordingly, oxidation of the conductor 260 by oxygen from above the insulator 270 can be suppressed. In addition, impurities such as water or hydrogen from above the insulator 270 can be prevented from entering the oxide 230 through the conductor 260 and the insulator 250 .

Further, the insulator 270 preferably functions as a hard mask. By using the insulator 270 as a hard mask, when the conductor 260 is processed, the side surface of the conductor 260 is substantially vertical. ° or less, preferably 80° or more and 95° or less. By processing the conductor 260 into such a shape, the insulators 272 and 275 to be formed next can be formed into desired shapes.

An insulator 272 functioning as a barrier film and a buffer layer is provided in contact with side surfaces of the oxide 230 c , the insulator 250 , the conductor 260 , and the insulator 270 .

For example, the insulator 272 is preferably formed using an ALD method. A dense thin film can be formed by using the ALD method.

As the insulator 272, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or a resin etc. is preferable. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step. For example, after an insulating film to be the insulator 272 is formed, an insulating film to be the insulator 275 is formed by sputtering aluminum oxide, whereby an excess oxygen region is easily formed in the insulating film to be the insulator 272. be able to.

Alternatively, the insulator 272 may be formed using an insulating material that has a function of suppressing permeation of impurities such as water or hydrogen, and oxygen. For example, aluminum oxide, hafnium oxide, or the like is preferably used. Thereby, diffusion of oxygen in the insulator 250 to the outside can be suppressed. In addition, entry of impurities such as hydrogen and water into the oxide 230 from the edge of the insulator 250 or the like can be suppressed. Therefore, formation of oxygen vacancies at the interface between the oxide 230 and the insulator 250 is suppressed, and the reliability of the transistor 200E can be improved.

Further, by providing the insulator 272, side surfaces of the insulator 250 and the conductor 260 can be covered with an insulator having a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Accordingly, impurities such as water or hydrogen can be prevented from entering the oxide 230 from above the transistor 200E through the insulator 250 and the conductor 260. FIG. Therefore, insulator 272 functions as a side barrier that protects the sides of the gate electrode and gate insulator.

In the case where aluminum oxide is provided as the insulator 272 by an ALD method, the thickness of the insulator 272 is preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm. With this structure, excess oxygen in the insulator 275 can be supplied to the insulator 250 while oxidation of the conductor 260 is suppressed.

In addition, an insulator 275 is provided on side surfaces of the oxide 230c, the insulator 250, and the conductor 260 with the insulator 272 interposed therebetween. It is preferable that the insulator 272 has an excess oxygen region due to the deposition of the insulator that becomes the insulator 275 as described above. Here, when the insulator 224 is processed into an island shape, the insulator 224 and the insulator 272 may be in contact with each other outside the insulator 224 . With this structure, excess oxygen in the insulator 272 can be supplied to the oxide 230 through the insulator 224 .

An insulator 280 functioning as an interlayer film is preferably provided to cover the oxide 230 , the insulator 275 , and the insulator 270 . Like the insulator 224 and the like, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film. Note that an insulator 282 may be provided over the insulator 280 . Insulator 282 is preferably an insulator similar to insulator 210 .

The openings of insulator 282 and insulator 280 are formed so that the inner wall of insulator 280 is in contact with the side surface of insulator 275 . In order to form such a structure, it is preferable to set an opening condition such that the etching rate of the insulator 275 is significantly lower than the etching rate of the insulator 280 when the insulators 282 and 280 are opened. Assuming that the etching rate of the insulator 275 is 1, the etching rate of the insulator 280 is preferably 5 or higher, more preferably 10 or higher. By forming the opening in this way, the opening can be formed in a self-aligned manner, the margin for alignment between the opening and the gate electrode is widened, and the space between the opening and the gate electrode can be designed to be small. Therefore, it is possible to increase the integration density of the semiconductor device.

For example, FIG. 53B shows an example in which the position of the opening is shifted from the designed position to the A2 side. The electric connection between the buried conductor 240a and the region 231a and the electric connection between the conductor 240b buried in the opening and the region 231b are made in a self-aligning manner, so that they are good. Note that FIG. 53B shows an example in which the opening is shifted to the A2 side, but the present invention is not limited to this. For example, the opening may be shifted to the A1 side.

Here, the conductors 240 a and 240 b are arranged in the openings formed in the insulators 282 and 280 . The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be flush with the top surface of the insulator 282 .

Conductor 240a is in contact with region 231a functioning as one of the source and drain regions of transistor 200E, and conductor 240b is in contact with region 231b functioning as the other of the source and drain regions of transistor 200E. Thus, the conductor 240a can function as one of the source and drain electrodes, and the conductor 240b can function as the other of the source and drain electrodes.

A conductor 240 a is formed in contact with the inner walls of the openings of the insulators 282 and 280 . A region 231a of oxide 230 is located in at least part of the bottom of the opening, and a conductor 240a is in contact with region 231a. Similarly, a conductor 240b is formed in contact with the inner walls of the openings of the insulators 282 and 280. As shown in FIG. A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductor 240b contacts region 231b.

FIG. 59 is a cross-sectional view of a portion indicated by a dashed-dotted line A5-A6 in FIG. 52A, which is a cross-sectional view of a region where the conductor 240a in the channel width direction of the transistor 200E is in contact with the oxide 230. is. Note that a region where the conductor 240b and the oxide 230 are in contact has the same structure.

59A, the conductors 240a and 240b are preferably in contact with at least the top surface of the oxide 230 and further in contact with the side surfaces of the oxide 230. In FIG. In particular, the conductors 240a and 240b are preferably in contact with one or both of the A5-side side and the A6-side side on the sides crossing the channel width direction of the oxide 230 . That is, the region where the conductors 240a and 240b and the oxide 230 are in contact has a saddle-like cross-sectional shape (can be called a saddle surface contact). Alternatively, the conductor 240a and the conductor 240b may be in contact with the side surface on the A1 side (A2 side) on the side surface of the oxide 230 that intersects with the channel length direction. The region where the conductors 240a and 240b are in contact with the oxide 230 is not limited to the example shown in FIG. 240 b may have regions that contact the top surface of oxide 230 and the sides of oxide 230 . Alternatively, the conductor 240a and the conductor 240b may be in contact with the side surface on the A1 side (A2 side) on the side surface of the oxide 230 that intersects with the channel length direction. FIG. 59B shows an example of a region in contact with the conductor 240a and the conductor 240b and the side surface of the oxide 230 on the A5 side. It may have a region in contact with the body 240b and the side surface of the oxide 230 on the A6 side. With such a structure, the area of the region where the conductors 240a and 240b are in contact with the oxide 230 can be increased. contact resistance can be lowered. As a result, the on current can be increased while miniaturizing the source electrode and the drain electrode of the transistor. A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductors 240a and 240b. Further, the conductor 240a and the conductor 240b may have a laminated structure.

Further, as shown in FIG. 52B, the transistor 200E has parasitic capacitance between the conductor 260 and the conductor 240a. Similarly, a parasitic capacitance is formed between conductor 260 and conductor 240b. The parasitic capacitance is reduced by increasing the thickness of the insulator interposed between the conductor 260 and the conductor 240a (the conductor 240b) in the channel length direction.

Therefore, by providing the insulator 275 in addition to the insulator 272 in the transistor 200E, the parasitic capacitance can be reduced. The total thickness of the insulators 275 and 272 in the channel length direction in terms of silicon oxide thickness (EOT: Equivalent Oxide Thickness) is 10 nm to 50 nm, preferably 15 nm to 30 nm. As the insulator 275, for example, aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used. By reducing the parasitic capacitance, the transistor 200E can operate at high speed.

Here, as shown in FIG. 60B, for example, when forming the opening in the insulator 280, the region 231 of the oxide 230 having a low resistance may be removed. In that case, as a conductor used for the conductor 240, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is preferably used. In other words, the contact between the oxide 230 and the conductor 240 forms a new low-resistance region in the oxide 230 . The contact resistance between the oxide 230 and the conductor 240 can be reduced by forming the low-resistance region. The conductor 240 preferably contains metal elements such as aluminum, ruthenium, titanium, tantalum, and tungsten. FIG. 60(B) shows the vicinity of the region where the resistance is newly reduced by enclosing it in a frame of a dashed line.

In the case where the conductor 240 has a stacked-layer structure, the conductor in contact with the insulator 280 and the insulator 282 is impervious to impurities such as water or hydrogen, similarly to the first conductor of the conductor 205 . It is preferable to use a conductive material having a suppressing function. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. In addition, the conductive material having a function of suppressing permeation of impurities such as water or hydrogen may be used in a single layer or a stacked layer. By using the conductive material, impurities such as hydrogen and water from a layer above the insulator 282 can be prevented from entering the oxide 230 through the conductors 240a and 240b.

<Structure Example 2 of Semiconductor Device>
54A and 54B are a top view and a cross-sectional view of a transistor 200F and the periphery of the transistor 200F according to one embodiment of the present invention.

FIG. 54A is a top view of a semiconductor device having a transistor 200F. 54B and 54C are cross-sectional views of the semiconductor device. Here, FIG. 54B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 54A, and is also a cross-sectional view in the channel length direction of the transistor 200F. FIG. 54C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 54A, and is also a cross-sectional view in the channel width direction of the transistor 200F. Note that in the top view of FIG. 54A, some elements are omitted for clarity of illustration.

[Transistor 200F]
As shown in FIG. 54, the transistor 200F includes an insulator 214 and an insulator 216 arranged over a substrate (not shown), and a conductor arranged to be embedded in the insulator 214 and the insulator 216. 205, an insulator 220 overlying the insulator 216 and the conductor 205, an insulator 222 overlying the insulator 220, an insulator 224 overlying the insulator 222, an insulator Oxide 230 (oxide 230 a , oxide 230 b , and oxide 230 c ) overlying body 224 , insulator 250 overlying oxide 230 , and a conductive material overlying insulator 250 . a body 260 (a conductor 260a and a conductor 260b); an insulator 270 disposed over the conductor 260; A body 272, an insulator 275 placed on the side surface of the conductor 260 with the insulator 272 interposed therebetween, an insulator 273 placed on the side surface of the insulator 275 and the oxide 230, and a insulator 273 placed on the insulator 273 and an insulator 276 .

It differs from transistor 200E described above in that it has a side surface of insulator 275 and insulator 273 placed on oxide 230 and insulator 276 placed on insulator 273 . Differences from the transistor 200E will be described below.

As shown in FIG. 54B, an insulator 273 is arranged in contact with part of the top surface and part of the side surface of the oxide 230 . An insulator 276 is arranged on and in contact with the insulator 273 . That is, with such a structure over the region 231 , for example, a silicon oxide film is used as the insulator 273 and an aluminum oxide film is used as the insulator 276 by a sputtering method, so that hydrogen contained in the insulator 280 can be reduced. can be prevented from diffusing into oxide 230 . The description of the transistor 200E can be referred to for other structures, effects, and the like.

<Structure Example 3 of Semiconductor Device>
55A and 55B are a top view and a cross-sectional view of a transistor 200G and the periphery of the transistor 200G according to one embodiment of the present invention.

FIG. 55A is a top view of a semiconductor device having a transistor 200G. 55B and 54C are cross-sectional views of the semiconductor device. Here, FIG. 55B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 55A, and is also a cross-sectional view in the channel length direction of the transistor 200G. FIG. 55C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 55A, and is also a cross-sectional view in the channel width direction of the transistor 200G. Note that in the top view of FIG. 55A, some elements are omitted for clarity of illustration.

[Transistor 200G]
As shown in FIG. 55, the transistor 200G includes an insulator 214 and an insulator 216 arranged over a substrate (not shown), and a conductor buried in the insulator 214 and the insulator 216. 205, an insulator 220 overlying the insulator 216 and the conductor 205, an insulator 222 overlying the insulator 220, an insulator 224 overlying the insulator 222, an insulator Oxide 230 (oxide 230 a , oxide 230 b , and oxide 230 c ) overlying body 224 , insulator 250 overlying oxide 230 , and a conductive material overlying insulator 250 . a body 260 (a conductor 260a and a conductor 260b); an insulator 270 disposed over the conductor 260; It has a body 272, an insulator 275 arranged on the side surface of the conductor 260 with the insulator 272 interposed therebetween, and an insulator 274 arranged on the side surface of the insulator 275 and the side surface of the oxide 230c.

It differs from transistor 200E described above in that it has insulator 274 located on the side of insulator 275 and on the side of oxide 230c. Differences from the transistor 200E will be described below.

As shown in FIG. 55B, the openings of insulator 282 and insulator 280 are formed so that the inner wall of insulator 280 is in contact with the side surface of insulator 274 . In order to form such a structure, it is preferable to set an opening condition such that the etching rate of the insulator 274 is significantly lower than the etching rate of the insulator 280 when the insulators 282 and 280 are opened. Assuming that the etching rate of the insulator 274 is 1, the etching rate of the insulator 280 is preferably 5 or higher, more preferably 10 or higher. By forming the opening in this way, the opening can be formed in a self-aligned manner, the margin for alignment between the opening and the gate electrode is widened, and the space between the opening and the gate electrode can be designed to be small. Therefore, it is possible to increase the integration density of the semiconductor device.

For example, even if the position of the opening is shifted to the A1 side or the A2 side from the designed position, the configuration of the transistor 200G allows the electrical connection between the conductor 240a embedded in the opening and the region 231a. Since the electrical connection and the electrical connection between the conductor 240b embedded in the opening and the region 231b are made in a self-aligning manner, they are excellent.

Here, the conductors 240 a and 240 b are arranged in the openings formed in the insulators 282 and 280 . The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be flush with the top surface of the insulator 282 .

Conductor 240a is in contact with region 231a functioning as one of the source and drain regions of transistor 200G, and conductor 240b is in contact with region 231b functioning as the other of the source and drain regions of transistor 200G. Thus, the conductor 240a can function as one of the source and drain electrodes, and the conductor 240b can function as the other of the source and drain electrodes.

A conductor 240 a is formed in contact with the inner walls of the openings of the insulators 282 and 280 . A region 231a of oxide 230 is located in at least part of the bottom of the opening, and a conductor 240a is in contact with region 231a. Similarly, a conductor 240b is formed in contact with the inner walls of the openings of the insulators 282 and 280. As shown in FIG. A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductor 240b contacts region 231b.

Further, as shown in FIG. 55B, the transistor 200G has parasitic capacitance between the conductor 260 and the conductor 240a. Similarly, a parasitic capacitance is formed between conductor 260 and conductor 240b. The parasitic capacitance is reduced by increasing the thickness of the insulator interposed between the conductor 260 and the conductor 240a (the conductor 240b) in the channel length direction.

By providing the insulator 274 in addition to the insulators 272 and 275 in the transistor 200G, parasitic capacitance can be reduced. The thickness of the insulator interposed between the conductor 260 and the conductor 240a (the conductor 240b) in the channel length direction is the same as the thickness of the insulator 275 in the channel length direction and the thickness of the insulator 272 in the channel length direction. and the film thickness of the insulator 274 in the channel length direction, the parasitic capacitance can be further reduced. Equivalent Oxide Thickness (EOT) of all these insulators in the channel length direction is set to 10 nm or more and 50 nm or less, preferably 15 nm or more and 30 nm. As the insulator 274, for example, aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride can be used. By reducing the parasitic capacitance in this way, the transistor 200G can be operated at high speed. The description of the transistor 200E can be referred to for other structures, effects, and the like.

<Structure Example 4 of Semiconductor Device>
56A and 56B are a top view and a cross-sectional view of a transistor 200H and the periphery of the transistor 200H according to one embodiment of the present invention.

FIG. 56A is a top view of a semiconductor device having a transistor 200H. 56B and 56C are cross-sectional views of the semiconductor device. Here, FIG. 56B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 56A, and is also a cross-sectional view in the channel length direction of the transistor 200H. FIG. 56C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 56A, and is also a cross-sectional view in the channel width direction of the transistor 200H. Note that in the top view of FIG. 56A, some elements are omitted for clarity of illustration.

[Transistor 200H]
As shown in FIG. 56, the transistor 200H includes an insulator 214 and an insulator 216 arranged on a substrate (not shown), and a conductor arranged to be embedded in the insulator 214 and the insulator 216. 205, an insulator 220 overlying the insulator 216 and the conductor 205, an insulator 222 overlying the insulator 220, an insulator 224 overlying the insulator 222, an insulator Oxide 230 (oxide 230 a , oxide 230 b , and oxide 230 c ) overlying body 224 , insulator 250 overlying oxide 230 , and a conductive material overlying insulator 250 . a body 260 (a conductor 260a and a conductor 260b); an insulator 270 disposed over the conductor 260; A body 272, an insulator 275 placed on the side surface of the conductor 260 with the insulator 272 interposed therebetween, an insulator 273 placed on the side surface of the insulator 275 and the oxide 230, and a insulator 273 placed on the insulator 273 and an insulator 274 arranged on the side surface of the insulator 275 with the insulators 273 and 276 interposed therebetween.

The transistor 200F differs from the transistor 200F described above in that it has an insulator 274 arranged on the side surface of the insulator 275 with insulators 273 and 276 interposed therebetween. Differences from the transistor 200F will be described below.

As shown in FIG. 56B, the openings of the insulator 282, the insulator 280, the insulator 276, and the insulator 273 are formed so that the inner wall of the insulator 280 is in contact with the side surface of the insulator 274. As shown in FIG. In order to form such a structure, the etching rate of the insulator 274 when the insulators 282 and 280 are opened is set to be extremely lower than the etching rate of the insulators 280, 276 and 273. is preferred. Assuming that the etching rate of the insulator 274 is 1, the etching rates of the insulators 280, 276, and 273 are preferably 5 or higher, more preferably 10 or higher. By forming the opening in this way, the opening can be formed in a self-aligned manner, the margin for alignment between the opening and the gate electrode is widened, and the space between the opening and the gate electrode can be designed to be small. Therefore, it is possible to increase the integration density of the semiconductor device.

For example, even if the position of the opening is shifted to the A1 side or the A2 side from the design position, the configuration of the transistor 200H enables the electrical connection between the conductor 240a embedded in the opening and the region 231a. Since the electrical connection and the electrical connection between the conductor 240b embedded in the opening and the region 231b are made in a self-aligning manner, they are excellent.

Here, the conductors 240 a and 240 b are arranged in openings formed in the insulators 282 , 280 , 276 , and 273 . The conductor 240a and the conductor 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the top surfaces of the conductors 240 a and 240 b may be flush with the top surface of the insulator 282 .

Conductor 240a is in contact with region 231a functioning as one of the source and drain regions of transistor 200H, and conductor 240b is in contact with region 231b functioning as the other of the source and drain regions of transistor 200H. Thus, the conductor 240a can function as one of the source and drain electrodes, and the conductor 240c can function as the other of the source and drain electrodes.

A conductor 240 a is formed in contact with the inner walls of the openings of the insulators 282 , 280 , 276 and 273 . A region 231a of oxide 230 is located in at least part of the bottom of the opening, and a conductor 240a is in contact with region 231a. Similarly, conductors 240b are formed in contact with the inner walls of the openings of insulators 282, 280, 276 and 273, respectively. A region 231b of oxide 230 is located at least partially at the bottom of the opening, and a conductor 240b contacts region 231b.

Further, as shown in FIG. 56B, the transistor 200H has parasitic capacitance between the conductor 260 and the conductor 240a. Similarly, a parasitic capacitance is formed between conductor 260 and conductor 240b. The parasitic capacitance is reduced by increasing the thickness of the insulator interposed between the conductor 260 and the conductor 240a (the conductor 240b) in the channel length direction.

By providing the insulator 273, the insulator 276, and the insulator 274 in addition to the insulator 272 and the insulator 275 in the transistor 200H, parasitic capacitance can be reduced. The thickness of the insulator interposed between the conductor 260 and the conductor 240a (the conductor 240b) in the channel length direction is the same as the thickness of the insulator 275 in the channel length direction and the thickness of the insulator 272 in the channel length direction. In addition to the film thickness of the insulator 273, the insulator 276, and the insulator 274 in the channel length direction, the parasitic capacitance can be further reduced. Equivalent Oxide Thickness (EOT) of all these insulators in the channel length direction is set to 10 nm or more and 50 nm or less, preferably 15 nm or more and 30 nm. As the insulator 274, for example, aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride can be used. By reducing the parasitic capacitance in this way, the transistor 200H can operate at high speed. The description of the transistor 200F can be referred to for other structures, effects, and the like.

<Semiconductor Device Constituent Material>
Constituent materials that can be used for the semiconductor device are described below. Note that, among the structures constituting the semiconductor device shown in this embodiment, the constituent materials of the structures denoted by the same reference numerals as those of the structures shown in the previous embodiment are not described in the above embodiment. The constituent materials described can be taken into consideration.

<<insulator>>
As insulators, there are insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like.

For example, the insulators 275 and 276 are metal containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like. Oxides can be used.

In particular, aluminum oxide has a high barrier property and can suppress the diffusion of hydrogen and nitrogen even in a thin film having a thickness of 0.5 nm or more and 3.0 nm or less. Hafnium oxide has a lower barrier property than aluminum oxide, but the barrier property can be improved by increasing the film thickness. Therefore, by adjusting the film thickness of hafnium oxide, the appropriate amounts of hydrogen and nitrogen to be added can be adjusted.

The insulators 272, 273, and 274 preferably have insulators with a low dielectric constant. For example, insulator 272, insulator 273, and insulator 274 can be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped It is preferable to use silicon oxide, silicon oxide having pores, resin, or the like. Alternatively, the insulators 272, 273, and 274 may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, or carbon and nitrogen are added. It preferably has a layered structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing a semiconductor device having the transistor 200E according to the present invention will be described with reference to FIGS. 61 to 71, (A) in each figure shows a top view. (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 in (A), and is also a cross-sectional view in the channel length direction of the transistor 200E. (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200E. In addition, in the top view of (A) of each figure, some elements are omitted for clarity of illustration.

First, a substrate (not shown) is prepared, and an insulator 210 is formed on the substrate. Note that the insulator 210 in Embodiment 1 can be referred to for the material, the film formation method, and the like of the insulator 210 .

Next, a conductive film to be the conductor 203 is formed over the insulator 210 . A conductive film to be the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, the conductive film to be the conductor 203 can be a multilayer film. In this embodiment mode, a tungsten film is formed as the conductive film to be the conductor 203 .

Next, the conductive film to be the conductor 203 is processed by lithography to form the conductor 203 .

Note that a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed over the conductive film serving as the conductor 203, a resist mask is formed thereover, and the hard mask material is etched to obtain a desired shape. A hard mask can be formed. The etching of the conductive film to be the conductor 203 may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the conductive film to be the conductor 203 is etched. On the other hand, if the hard mask material does not affect the post-process, or if it can be used in the post-process, it is not always necessary to remove the hard mask.

Next, an insulating film to be the insulator 212 is formed over the insulator 210 and the conductor 203 . The insulating film to be the insulator 212 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, the insulating film to be the insulator 212 is formed using silicon oxide by a CVD method.

Here, the thickness of the insulating film to be the insulator 212 is preferably greater than or equal to the thickness of the conductor 203 . For example, if the thickness of the conductor 203 is 1, the thickness of the insulating film to be the insulator 212 is 1 or more and 3 or less. In this embodiment mode, the thickness of the conductor 203 is set to 150 nm, and the thickness of the insulating film to be the insulator 212 is set to 350 nm.

Next, the insulating film to be the insulator 212 is subjected to CMP treatment to remove part of the insulating film to be the insulator 212 and expose the surface of the conductor 203 . Thus, the conductor 203 and the insulator 212 with flat upper surfaces can be formed (see FIG. 61).

Here, a method of forming the conductor 203 different from the above will be described below.

An insulator 212 is deposited over the insulator 210 . The insulator 212 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an opening is formed in the insulator 212 to reach the insulator 210 . The opening includes, for example, grooves and slits. Also, an area in which an opening is formed may be referred to as an opening. A wet etching method may be used to form the opening, but it is preferable to use a dry etching method for fine processing. For the insulator 210, it is preferable to select an insulator that functions as an etching stopper film when the insulator 212 is etched to form a groove. For example, when a silicon oxide film is used for the insulator 212 forming the trench, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used for the insulator 210 .

After forming the opening, a conductive film to be the conductor 203 is formed. The conductive film preferably contains a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductive film to be the conductor 203 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, the conductive film to be the conductor 203 has a multilayer structure. First, a film of tantalum nitride or a film in which titanium nitride is laminated on tantalum nitride is formed by a sputtering method. By using such a metal nitride in the lower layer of the conductive film that serves as the conductor 203, even if a metal that is easily diffused, such as copper, is used as the upper layer of the conductive film that serves as the conductor 203, which will be described later, the metal can be used. can be prevented from diffusing out of the conductor 203 .

Next, a conductive film is formed as an upper layer of the conductive film to be the conductor 203 . The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, a low-resistance conductive material such as copper is deposited as a conductive film over the conductive film to be the conductor 203 .

Next, CMP treatment is performed to remove part of the upper layer of the conductive film that will be the conductor 203 and part of the lower layer of the conductive film that will be the conductor 203 , thereby exposing the insulator 212 . As a result, the conductive film that becomes the conductor 203 remains only in the opening. Thus, the conductor 203 with a flat upper surface can be formed. Note that part of the insulator 212 may be removed by the CMP treatment. The above is a different formation method of the conductor 203 .

Next, an insulator 214 and an insulator 216 are formed in this order over the insulator 212 and the conductor 203 . Note that the insulators 214 and 216 in Embodiment 1 can be referred to for materials, deposition methods, and the like of the insulators 214 and 216 .

Next, an opening reaching the conductor 203 is formed in the insulator 214 and the insulator 216 . A wet etching method may be used to form the opening, but it is preferable to use a dry etching method for fine processing.

After forming the opening, a conductive film to be the conductor 205a is formed. The conductive film to be the conductor 205a preferably contains a conductive material that has a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used. A conductive film to be the conductor 205a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, a tantalum nitride film is formed by a sputtering method as the conductive film to be the conductor 205a.

Next, a conductive film to be the conductor 205b is formed over the conductive film to be the conductor 205a. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, as the conductive film to be the conductor 205b, a titanium nitride film is formed by a CVD method, and tungsten is formed over the titanium nitride film by a CVD method.

Next, CMP treatment is performed to remove part of the conductive film to be the conductor 205a and part of the conductive film to be the conductor 205b, so that the insulator 216 is exposed. As a result, the conductive film to be the conductor 205a and the conductive film to be the conductor 205b remain only in the opening. Thus, conductors 205 including conductors 205a and 205b having flat upper surfaces can be formed (see FIG. 61). Note that part of the insulator 216 is removed by the CMP treatment in some cases.

Next, an insulator 220, an insulator 222, an insulating film 224A, an oxide film 230A to be an oxide 230a, and an oxide film 230B to be an oxide 230b are formed in this order over the insulator 216 and the conductor 205 (FIG. 61). Note that the insulators 220 and 222 in Embodiment 1 can be referred to for the materials, the deposition methods, and the like of the insulators 220 and 222, and the materials and the deposition methods of the insulating film 224A can be referred to. etc. can refer to the insulating film 224A of Embodiment 3, and the oxide films 230A and 230B of Embodiment 1 can be referred to for the materials, formation methods, and the like of the oxide films 230A and 230B. be able to.

Next, oxide film 230A and oxide film 230B are processed into an island shape to form oxide 230a and oxide 230b. Note that in this step, the insulating film 224A may be processed into an island shape (an insulator 224). In that case, the insulator 222 can be used as an etching stopper film (see FIG. 62).

Here, the oxides 230 a and 230 b are formed so that at least part of them overlaps with the conductor 205 . Side surfaces of the oxide 230 a and the oxide 230 b are preferably substantially perpendicular to the top surface of the insulator 222 . Since the side surfaces of the oxides 230a and 230b are substantially perpendicular to the top surface of the insulator 222, the area can be reduced and the density can be increased when a plurality of transistors 200E are provided. Alternatively, the angle formed by the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 may be small. In that case, the angle between the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is preferably 60° or more and less than 70°. Such a shape can prevent the insulators 272 and 275 from being formed on the side surfaces of the oxides 230a and 230b in subsequent steps.

In addition, curved surfaces are provided between the side surfaces of the oxides 230a and 230b and the top surface of the oxide 230b. That is, it is preferable that the edge of the side surface and the edge of the upper surface are curved (hereinafter also referred to as a round shape). For example, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the oxide 230b. Since the edges do not have corners, the coverage of the film in the subsequent film forming process is improved.

Note that processing of the oxide film may be performed using a lithography method. A dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing.

Further, when dry etching or the like is performed, impurities caused by an etching gas or the like may adhere to or diffuse onto or inside the oxides 230a and 230b. Impurities include, for example, fluorine or chlorine.

Cleaning is performed to remove the above impurities. As a cleaning method, there are wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, or the like, and the above cleaning may be performed in combination as appropriate.

Wet cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning is performed using pure water or carbonated water.

Subsequently, heat treatment may be performed. As the conditions for the heat treatment, the conditions for the heat treatment described above can be used.

Next, an oxide film 230C is formed on the insulating film 224A, the oxide 230a, and the oxide 230b (see FIG. 63). Note that the oxide film 230C of the first embodiment can be referred to for the material, film formation method, and the like of the oxide film 230C.

Subsequently, an insulating film 250A, a conductive film 260A, a conductive film 260B, and an insulating film 270A are formed in this order on the oxide film 230C (see FIG. 63).

First, an insulating film 250A is formed. Note that the insulating film 250A in Embodiment 1 can be referred to for the material, formation method, and the like of the insulating film 250A.

Here, a metal oxide film may be formed on the insulating film 250A. As the metal oxide film, an In--Ga--Zn oxide is formed by a sputtering method. As a method for forming the metal oxide film, a sputtering method is preferably used in an atmosphere containing an oxygen gas. By forming the metal oxide film in an atmosphere containing oxygen gas, an excess oxygen region can be formed in the insulating film 250A. Excess oxygen added to the insulating film 250A supplies oxygen to the oxide 230, so that oxygen vacancies in the oxide 230 can be compensated.

Here, as means for forming the metal oxide film, a sputtering apparatus is used to form the film in an oxygen gas atmosphere. oxygen can be introduced into the Further, by using one or both oxides of aluminum and hafnium having barrier properties for the metal oxide film, excess oxygen introduced into the insulating film 250A can be effectively confined.

Next, a conductive film 260A and a conductive film 260B are formed. Note that the conductive films 260A and 260B in Embodiment 1 can be referred to for materials, formation methods, and the like of the conductive films 260A and 260B.

For example, as the conductive film 260A, a metal nitride may be formed by a sputtering method. For example, when an oxide semiconductor typified by an In--Ga--Zn oxide is used as the metal oxide film, the metal oxide film has a high carrier density by being supplied with nitrogen or hydrogen. That is, it functions as an oxide conductor (OC). Therefore, by forming a metal nitride by a sputtering method as the conductive film 260A, constituent elements (especially nitrogen) in the metal nitride diffuse into the previously formed metal oxide film, and the metal oxide film becomes low. resist. In addition, the resistance of the metal oxide film is lowered due to damage (for example, sputtering damage) during the formation of the conductive film 260A. Therefore, the carrier density of the metal oxide film is increased, and the conductivity of the metal oxide film is increased.

A heat treatment can then be performed. For the heat treatment, the heat treatment conditions described above can be used. Note that the heat treatment may not be performed in some cases. By this heat treatment, excess oxygen is added to the insulating film 250A from the metal oxide film, and an excess oxygen region can be easily formed in the insulating film 250A.

The insulating film 270A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film 270A functions as a barrier film, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is used. For example, it is preferable to use aluminum oxide or hafnium oxide. Thereby, oxidation of the conductor 260 can be suppressed. In addition, entry of impurities such as water or hydrogen into the oxide 230 through the conductor 260 and the insulator 250 can be suppressed. In this embodiment mode, the insulating film 270A has a two-layer structure, aluminum oxide is deposited by ALD, and then silicon oxide is deposited by CVD.

Next, the insulating film 270A is etched to form the insulator 270. As shown in FIG. Here, insulator 270 functions as a hard mask. By providing the insulator 270, a side surface of the oxide 230c, a side surface of the insulator 250, a side surface of the conductor 260a, and a side surface of the conductor 260b can be formed substantially perpendicular to the top surface of the substrate.

Next, using the insulator 270 as a mask, the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B are etched to remove the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b). ) (see FIG. 64).

At least part of the oxide 230 c , the insulator 250 , the conductor 260 , and the insulator 270 overlaps with the conductor 205 and the oxide 230 .

Moreover, the side surface of the oxide 230c, the side surface of the insulator 250, and the side surface of the conductor 260 are preferably in the same plane.

Also, the same plane shared by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 is preferably substantially perpendicular to the top surface of the substrate. That is, in the cross-sectional shape, the angle formed by the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 is preferably acute and large. Note that in the cross-sectional shape, the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 may form an acute angle. In that case, the angle between the side surfaces of the oxide 230c, the insulator 250, and the conductor 260 and the top surface of the oxide 230 is preferably as large as possible.

Next, an insulating film 272A is formed covering the oxide 230, the insulator 250, the conductor 260, and the insulator 270 (see FIG. 65). The insulating film 272A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulating film 272A is preferably formed by the ALD method, which has excellent coverage. By using the ALD method, the insulating film 272A having a uniform thickness is formed on the side surfaces of the insulator 250, the conductor 260, and the insulator 270 even in the stepped portion formed by the conductor 260 or the like. be able to. Also, by using the ALD method, a dense thin film can be formed.

As the insulating film 272A, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having holes, or It is preferable to have a resin or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, silicon oxide and silicon oxide having vacancies are preferable because an excess oxygen region can be easily formed in a later step.

On the other hand, as the insulating film 272A, aluminum oxide or the like having a barrier property may be provided. For example, when the conductor 260 is a metal film that is easily oxidized, the use of an insulator having a barrier property can suppress oxidation of the conductor 260 by oxygen from above the insulating film 272A. Thereby, it is possible to suppress an increase in the resistance value of the conductor 260 .

When aluminum oxide is provided as the insulating film 272A by ALD, the film thickness of the insulating film 272A is preferably 0.5 nm or more and 3.0 nm or less. With this structure, excess oxygen contained in the insulator 275 can be supplied to the insulator 250 while suppressing oxidation of the conductor 260 in a later step.

Next, an insulating film 275A is formed. The insulating film 275A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is deposited by a sputtering method as the insulating film 275A. Oxygen can be added to the insulating film 272A by this film formation. The oxygen can be added to the oxide 230 through the insulating film 272A to repair defects in the oxide 230 (see FIG. 66).

Next, the insulating film 272A and the insulating film 275A are subjected to anisotropic etching treatment to form insulators 272 and 275 (see FIG. 67).

As the anisotropic etching treatment, dry etching treatment is preferably performed. As a result, the insulator 272 and the insulator 275 can be formed in a self-aligned manner by removing the insulating film formed on the surface substantially parallel to the substrate surface.

Subsequently, a film 242A is formed over the insulator 222, the insulator 224, and the oxide 230 with the oxide 230c, the insulator 250, the conductor 260, the insulator 270, the insulator 272, and the insulator 275 interposed therebetween. (See FIG. 68). Note that the film 242A may have a thickness of 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 3 nm or less. A metal film, a nitride film containing a metal element, or an oxide film containing a metal element is used for the film 242A. The film 242A is, for example, a film containing metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium. Note that the film 242A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Then, heat treatment is performed. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere. Moreover, you may perform heat processing in a pressure-reduced state. For example, as heat treatment, treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere after forming the film 242A.

By heat treatment in an atmosphere containing nitrogen, the metal element described above diffuses from the film 242A into the oxide 230, and the metal element can be added to the oxide 230. FIG. Oxygen in the vicinity of the interface between the oxide 230 and the film 242A may be absorbed by the film 242A. As a result, the vicinity of the interface between the oxide 230 and the film 242A becomes a metal compound, resulting in a low resistance. In this case, part of the oxide 230 and the metal element described above may be alloyed. By alloying part of the oxide 230 with the metal element, the metal element added to the oxide 230 is in a relatively stable state, so that a highly reliable semiconductor device can be provided.

Further, when hydrogen in the oxide 230 diffuses into the region 231 and enters the oxygen vacancies present in the region 231, it is in a relatively stable state. Further, hydrogen in the oxygen vacancies existing in the region 234 escapes from the oxygen vacancies by heat treatment at 250° C. or higher, diffuses into the region 231, enters the oxygen vacancies existing in the region 231, and is in a relatively stable state. Become. Therefore, the heat treatment reduces the resistance of the region 231, and purifies the region 234 (reduces impurities such as water and hydrogen) and increases the resistance.

Alternatively, after heat treatment in a nitrogen or inert gas atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower.

Further, when a conductive region remains in the film 242A, heat treatment is performed in an oxidizing atmosphere to oxidize the film 242A so that it becomes an insulator and has a high resistance. By leaving the film 242A as an insulator, it can function as an interlayer film.

Oxygen in the region 231 of the oxide 230 and the region 232 adjacent to the region 231 is absorbed by the film 242A in the film formation step or the heat treatment of the film 242A. may occur. Hydrogen in the oxide 230 enters the oxygen vacancies, so that the carrier densities of the regions 231 and 232 are increased. Therefore, regions 231 and 232 of oxide 230 are n-type and have a low resistance.

Subsequently, the film 242A is removed. Note that the metal film, the nitride film containing the metal element, or the oxide film containing the metal element does not necessarily have to be removed. For example, when a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is oxidized by oxygen absorbed from the oxide 230, becomes an insulator, and has a high resistance, it may be left. . In that case, it may function as an interlayer film. A dry etching method or a wet etching method can be used in this step. By removing the film 242A, the hydrogen in the oxide 230 absorbed by the film 242A can be removed at the same time. Therefore, hydrogen as an impurity in the transistor 200E can be reduced (see FIG. 69).

Next, an insulator 280 is deposited. Note that the insulator 280 in Embodiment 1 can be referred to for the material, formation method, and the like of the insulator 280 .

Next, an insulating film to be the insulator 282 may be formed over the insulator 280 . The insulating film to be the insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 282, for example, an aluminum oxide film is preferably formed by a sputtering method. An aluminum oxide film deposited by a sputtering method may extract hydrogen from a structure to be deposited. Therefore, by forming an aluminum oxide film by a sputtering method, diffusion of hydrogen contained in the insulator 280 to the oxide 230 can be suppressed in some cases.

Openings are then formed in insulator 280 and insulator 282 down to region 231 of oxide 230 (see FIG. 70). The formation of the opening may be performed using a lithography method. Here, the opening is formed so that the conductor 240 is provided in contact with the side surface of the insulator 275 . The opening conditions are preferably conditions under which the insulator 275 is hardly etched, that is, the etching rate of the insulator 280 is higher than the etching rate of the insulator 275 . Assuming that the etching rate of the insulator 275 is 1, the etching rate of the insulator 280 is preferably 5 or higher, more preferably 10 or higher. By setting such opening conditions, the opening can be arranged in the region 231 in a self-aligning manner, so that a fine transistor can be manufactured. In addition, in the lithography process, the allowable range for positional deviation between the conductors 260 and the openings is increased, so an improvement in yield can be expected.

For example, even if the position of the opening deviates from the designed position to the A1 side or the A2 side, the electrical connection between the conductor 240a embedded in the opening and the region 231a and the conductor 240b embedded in the opening are achieved in a later step. and the region 231b are electrically connected in a self-aligning manner.

Next, a conductive film to be the conductor 240a and the conductor 240b is formed. The conductive films to be the conductors 240a and 240b preferably have a stacked-layer structure including a conductor that has a function of suppressing permeation of impurities such as water and hydrogen. For example, a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc., can be used. A conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, for example, the low-resistance region of region 231 in oxide 230 may be removed when openings are formed in insulator 280 and insulator 282 . When a conductive film to be the conductors 240a and 240b is formed in the opening, the oxide 230 has a region in contact with the conductive film to be the conductors 240a and 240b. Oxygen vacancies are formed, and the resistance of contact regions between the oxide 230 and the conductive films to be the conductors 240a and 240b can be reduced. By reducing the resistance of the contact region, sufficient ohmic contact between the oxide 230 and the conductors 240a and 240b can be ensured. Therefore, the conductive films that become the conductors 240a and 240b preferably contain metal elements such as aluminum, ruthenium, titanium, tantalum, tungsten, and chromium.

Next, CMP treatment is performed to remove part of the conductive film to be the conductors 240 a and 240 b to expose the insulator 282 . As a result, the conductor 240a and the conductor 240b having flat upper surfaces can be formed by leaving the conductive film only in the openings (see FIGS. 71 and 52).

Alternatively, the conductors 240a and 240b may be formed after aluminum oxide is formed on the side walls of the opening. By forming aluminum oxide on the side walls of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b can be prevented. Further, impurities such as water and hydrogen can be prevented from diffusing to the outside from the conductors 240a and 240b. The aluminum oxide can be formed by forming a film of aluminum oxide in the opening using an ALD method or the like and performing anisotropic etching.

Through the above steps, a semiconductor device including the transistor 200E can be manufactured. As shown in FIGS. 61 to 71, the transistor 200E can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.

Note that FIG. 57 shows a structural example in which the angle formed by the side surfaces of the oxides 230a and 230b and the top surface of the insulator 222 is small. With such a shape, the insulators 272 and 275 are not formed on the side surfaces of the oxides 230a and 230b. can also be formed.

Also, FIG. 58 shows an example of a configuration in which the film 242A remains. A region of the film 242A other than the region in contact with the oxide 230 is made highly resistive and remains as the insulator 242B, so that it can function as an interlayer film.

According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments and examples.

(Embodiment 6)
Hydrogen in an In--Ga--Zn oxide (sometimes referred to as IGZO) that can be used as an oxide semiconductor in the transistor of one embodiment of the present invention is described below.

<1. Movement of Hydrogen Atom>
Here, the susceptibility of hydrogen atoms to migrate in an IGZO crystal was evaluated from the viewpoint of the activation barrier on the migration path of hydrogen atoms. In addition, hopping from one oxygen to another oxygen and movement on one oxygen were assumed as the mode of movement of hydrogen atoms.

FIG. 73 shows a schematic diagram of the division of regions in the InGaZnO ₄ crystal in which the movement paths of hydrogen atoms were studied. Here, the path (in the ab plane direction) in each of the InO ₂ region, the (Ga, Zn) O region, and the region between the InO ₂ plane and the (Ga, Zn) O plane shown in FIG. 73, and each region A crossing path (c-axis direction) was examined.

The activation barrier was evaluated using a first-principles electronic state/molecular dynamics calculation package VASP (Vienna ab initio simulation package), and the NEB (Nudged Elastic Band) method, which is a chemical reaction path search method, was used. The NEB method is a method of searching for the state with the lowest required energy among the states connecting the two states from the initial state and the final state. The activation barrier was the difference between the maximum energy in the pathway and the energy of the most stable structure on the pathway.

<<Region between InO ₂ plane and (Ga, Zn)O plane>>
FIG. 74 shows migration paths of hydrogen atoms in the region between the InO ₂ plane and the (Ga, Zn)O plane, and activation barriers on the paths. However, the most stable structure on the route was used as a reference, and the energy of this structure was used as the origin of energy. 74(A) and 74(C) show how hydrogen atoms move, and are referred to as path A and path B, respectively. Note that numbers in FIGS. 74A to 74D indicate the order of movement of hydrogen atoms. Path A is a straight path for the path from hydrogen atom 3 to 4. On the other hand, in route B, the route from hydrogen atom 3 to 4 is routed via 5.

In addition, FIG. 74(B) shows the calculation result of the activation barrier in path A (the path in which hydrogen atoms move from 1 to 4), and FIG. , 5). Note that the horizontal axis in FIGS. 74B and 74D is the hydrogen migration path, and the unit is arbitrary unit.

The activation barrier on path A shown in FIG. 74(B) was 1.12 eV, and the activation barrier on path B shown in FIG. 74(D) was 0.23 eV. Since the activation barrier on path B is smaller than that on path A, when hydrogen atoms move from 3 to 4, path B with a lower barrier on the path is likely to occur. That is, when hydrogen atoms move in the region between the InO ₂ plane and the (Ga, Zn)O plane, it is presumed that path B, which has a low barrier on the path, is likely to occur.

<<(Ga, Zn) O region>>
Next, FIG. 75 shows migration paths of hydrogen atoms in the (Ga, Zn)O region and activation barriers on the paths. However, the most stable structure on the route was taken as a reference, and this structure was taken as the origin of energy. FIG. 75A shows how hydrogen atoms move in the (Ga, Zn)O region. In FIG. 75A, numbers indicate the order of movement of hydrogen atoms. FIG. 75(B) shows the calculation result of the activation barrier in the path along which the hydrogen atoms move from 1 to 4 in FIG. 75(A).

From FIG. 75(B), the activation barrier on the migration path of hydrogen atoms in the (Ga, Zn)O region is 0.16 eV, which is smaller than the activation barrier shown in FIG. 74(D). I understand. Considering only the barrier height, when hydrogen atoms are present in the (Ga,Zn)O region, compared to the case in which they are present in the region between the _InO2 and (Ga,Zn)O planes, Hydrogen atom migration is expected to occur easily.

<< _InO2 region>>
Next, FIG. 76 shows the movement paths of hydrogen atoms in the InO ₂ region and the activation barriers on the paths. However, the most stable structure on the route was taken as a reference, and this structure was taken as the origin of energy. FIG. 76(A) shows how hydrogen atoms move in the InO ₂ region. In FIG. 76A, numbers indicate the order of movement of hydrogen atoms. FIG. 76(B) shows the calculation result of the activation barrier in the path along which the hydrogen atoms move from 1 to 4 in FIG. 76(A).

From FIG. 76(B), the activation barrier for the transfer of hydrogen atoms from one oxygen to another in the InO ₂ region was 1.2 eV or more. In other words, compared to the activation barriers shown in FIGS. 74(D) and 75(B), it can be seen that the activation barrier on the migration path of hydrogen atoms in the InO ₂ region is much larger. Therefore, it is considered that hydrogen atoms are less likely to migrate in the _InO2 region than in other regions.

Next, FIG. 77 shows migration paths of hydrogen atoms along the c-axis direction and activation barriers on the paths. However, the most stable structure on the route was taken as a reference, and this structure was taken as the origin of energy. FIG. 77A shows how hydrogen atoms move along the c-axis direction. In FIG. 77A, numbers indicate the order of movement of hydrogen atoms. FIG. 77(B) shows the calculation result of the activation barrier in the path along which the hydrogen atoms move from 1 to 8 in FIG. 77(A).

From FIG. 77(B), the activation barrier in the path where hydrogen atoms move from 2 to 5 was 0.9 eV. In other words, it can be seen that there is a large activation barrier when hydrogen atoms enter or leave the (Ga, Zn)O region. It is considered that this is because the movement path of the hydrogen atoms is blocked by the bond between the metal atom and the oxygen atom. Further, from FIG. 77(B), the activation barrier in the path along which the hydrogen atoms move from 7 to 8 was about 1.5 eV. That is, the existence of a large activation barrier is also confirmed for the movement of hydrogen atoms in the _InO2 region. Therefore, it is expected that continuous movement of hydrogen atoms in the c-axis direction is unlikely to occur. Note that one of the reasons for the large activation barrier is considered to be the large ionic radius of In.

Here, the movement frequency (Γ) was calculated from the calculated activation barrier and the following Equation 1.

Here, _Ea is the activation barrier, _kB is the Boltzmann constant, T is the absolute temperature, and ν is the frequency factor.

Finally, Table 1 shows migration frequencies estimated from the maximum value of activation barriers (maximum barriers) on each route.

At both 27 °C and 450 °C, the region between the InO ₂ and (Ga, Zn)O planes and the (Ga, Zn)O region showed the highest frequency of migration in the ab plane direction, while _the c It was found that the frequency of movement in the axial direction tends to be low. That is, it suggests that hydrogen preferentially diffuses along the ab plane in a perfect crystal system. However, it was found that hydrogen sufficiently diffuses in the IGZO film in the heat treatment at 450°C.

<2. Sites where oxygen deficiency _VO is likely to occur>
Since the strength of the bond between a metal atom and an oxygen atom varies depending on the type and valence of the metal, the ease with which oxygen vacancies _VO are formed in IGZO depends on the type, number, distance, etc., of the metals that are bonding partners of the oxygen atoms. It is assumed that there is a difference. Therefore, the easiness of forming oxygen vacancies was calculated for the InGaZnO ₄ crystal model.

An _InGaZnO4 crystal model (112 atoms) was used for the calculations. This model is shown in FIG. Ga and Zn in the (Ga, Zn)O region were arranged so as to be energetically stable. At this time, there are four types of oxygen sites (1 to 4 shown in FIG. 78) based on the binding partner and number. Table 2 shows each oxygen site.

An oxygen vacancy model was created by extracting one oxygen atom from the oxygen site from the above model, and calculations were performed to stabilize (also referred to as optimizing) the structure of the oxygen vacancy model in terms of energy. A comparison of the total energies for the optimized structures was then performed. Table 3 shows the calculation conditions.

A comparison of the total energies for the optimized structures was performed. FIG. 79 shows the relative values of the total energy with the total energy of the oxygen deficiency model of the oxygen site 4 as the reference (0.0 eV). From FIG. 79, it is presumed that oxygen vacancies are likely to be formed at oxygen site 4, and that oxygen site 2 is also relatively likely to be formed. On the other hand, it is presumed that the oxygen sites 1 and 3 are less likely to be formed than the oxygen sites 2 and 4.

<3. Ease of formation and stability of _HO >
<1. Movement of Hydrogen Atom>. Therefore, a calculation was made as to whether hydrogen in the oxygen-deficient V 2 _O escapes from the oxygen-deficient V 2 _O when the oxygen-deficient V 2 _O exists. Here, a state in which a hydrogen atom exists in oxygen deficiency V 2 _O is represented as H 2 _O (sometimes represented as V _{2 O} H).

The InGaZnO ₄ crystal model shown in FIG. 78 was used for the calculation. Here, the activation barrier (E _a ) in the transfer path of hydrogen atoms in oxygen-deficient V 2 _O escapes from V _{2 O} and bonds with oxygen atoms was calculated using the NEB method. Table 4 shows the calculation conditions.

<2 _. site where oxygen deficiency _VO is likely to occur>. Therefore, when oxygen vacancies _VO are present at oxygen sites (4 shown in FIG. 78) bonded to one Ga and two Zn located in the ab plane direction, the hydrogen atoms in the oxygen vacancies _VO are Calculations were made on how to escape from the oxygen-deficient _VO .

The model in the initial state is shown in FIG. 80(A), and the model in the final state is shown in FIG. 80(B). Here, the initial state is a state in which hydrogen atoms are present in the oxygen vacancies _VO (H 2 _O ), and the final state is the oxygen vacancies _VO , one Ga and two Zn atoms. It is a structure having a state (H—O) in which a bonded oxygen atom and a hydrogen atom are bonded. FIG. 81 shows activation barriers in the path along which hydrogen atoms move from the initial state to the final state. In FIG. 81, the left end of the horizontal axis is the initial state, and the right end of the horizontal axis is the final state. Also, the points plotted between the initial state and the final state represent the positions through which the hydrogen atoms moved. Note that the unit of the horizontal axis is arbitrary. Here, the total energy in the initial state was used as a reference (0.0 eV).

As a result of calculation, the activation barrier (E _a ) when hydrogen atoms in oxygen-deficient V 2 _O escape from V 2 _O was about 1.70 eV.

Next, from the calculated activation barrier (E _a ) and Equation 1 above, the average number of times hydrogen atoms in the oxygen vacancies V 2 _O escape from the oxygen vacancies V 2 _O per hour was calculated.

Assuming that the frequency factor ν=10 ¹³ [1/sec], the average number of times the hydrogen atoms in the oxygen-deficient V 2 _O escape from the oxygen-deficient V 2 _O at room temperature and 250° C. was calculated. The average number of times hydrogen atoms migrated from the model shown in FIG. 80(A) to the model shown in FIG. 80(B) was about 1×10 ⁻¹² [times] at room temperature. This suggests that at room temperature, the hydrogen atoms in the oxygen-deficient V 2 _O have a very low probability of escaping from the oxygen-deficient V 2 _O , and the state of H 2 _O is stable. Further, the average number of times hydrogen atoms migrate from the model shown in FIG. 80A to the model shown in FIG. This suggests that hydrogen atoms in the oxygen-deficient V 2 _O can escape from the oxygen-deficient V 2 _O by baking at a temperature of 250° C. or higher for one hour.

From the above, it was found that the hydrogen in the oxygen vacancies V 2 _O present in the channel formation region is released from the oxygen vacancies V 2 _O by the heat treatment. In addition, it was found that hydrogen released from the oxygen vacancies diffuses into the low-resistance region, enters the oxygen vacancies V 2 _O existing in the low-resistance region, and becomes H 2 _O easily. Therefore, the heat treatment makes the channel formation region highly purified (reduces impurities such as water and hydrogen), and normally-off transistor characteristics are obtained.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 7)
An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention is described below.

<Structure example of semiconductor device>
82A, 82B, and 82C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that a memory device including one capacitor and at least one transistor is referred to as a cell in this specification.

FIG. 82A is a top view of a cell 600 including a transistor 200 and a capacitor 100. FIG. 82(B) and 82(C) are cross-sectional views of the cell 600. FIG. Here, FIG. 82B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 82A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 82C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 82A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 82(A), some elements are omitted for clarity of illustration.

[Cell 600]
A semiconductor device of one embodiment of the present invention includes a transistor 200, a capacitor 100, and an insulator 280 functioning as an interlayer film. It also includes a conductor 240 (a conductor 240a and a conductor 240b) that is electrically connected to the transistor 200 and functions as a plug.

In a cell 600 illustrated in FIG. 82, the transistor 200 and the capacitor 100 are provided in the same layer, so that part of the structure forming the transistor 200 is used together with part of the structure forming the capacitor 100. be able to. That is, part of the structure of the transistor 200 functions as part of the structure of the capacitor 100 in some cases.

In addition, part or all of the capacitor 100 overlaps with the transistor 200, so that the total area of the projected area of the transistor 200 and the projected area of the capacitor 100 can be reduced.

In addition, the cell 600 is miniaturized by providing the conductor 240b functioning as a plug or a wiring electrically connected to the transistor 200 and the conductor 207 under the region where the capacitor 100 and the transistor 200 overlap. , or high integration is facilitated. Further, since the conductor 207 can be formed in the same process as the conductor 205 which is one of the components of the transistor 200, the process can be shortened. Further, in the capacitor 100 , a conductor functioning as a wiring may be provided in contact with the bottom surface of the conductor 207 as in the transistor 200 .

Note that in the capacitor 100, the layout of the transistor 200 and the capacitor 100 can be designed as appropriate depending on the required capacitance value.

For example, the area of the capacitor 100 is determined by the area where the region 231b of the oxide 230 and the conductor 120 overlap. Therefore, if the capacitance value required for the cell 600 cannot be obtained with the capacitor 100 shown in FIGS. 82A and 82B, the width in the A3-A4 direction is larger than the width in the A3-A4 direction of the region 234 of the oxides 230a and 230b, the capacitance value can be increased.

Also, for example, the length of the region 231b of the oxide 230 in the A1-A2 direction may be longer than the length of the conductor 120 in the A1-A2 direction. In that case, the conductor 240b can be embedded in the insulator 280. FIG. That is, the region 231b of the oxide 230 and the conductor 240b may be provided so as to be in contact with each other in a region where the region 231b of the oxide 230 and the conductor 120 do not overlap. Therefore, by forming the conductor 240a and the conductor 240b in the same process, the process can be shortened.

By having the above structure, miniaturization or high integration is possible. Also, the degree of freedom in design can be increased. Further, the transistor 200 and the capacitor 100 are formed in the same process. Therefore, since the process can be shortened, the productivity can be improved.

[Transistor 200]
As the structure of the transistor 200, the transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 shown in FIG. 82 is only an example, and the structure is not limited, and an appropriate transistor may be used according to the circuit configuration and driving method.

[Capacitor 100]
As shown in FIG. 82 , the capacitive element 100 has a structure common to that of the transistor 200 . In this embodiment, an example of the capacitor 100 in which the region 231b provided in the oxide 230 of the transistor 200 functions as one electrode of the capacitor 100 is described.

The capacitor 100 has a region 231 b of the oxide 230 , an insulator 278 over the region 231 b, and a conductor 120 over the insulator 278 . Further, conductor 120 is preferably disposed on insulator 278 so that at least a portion of it overlaps region 231b of oxide 230 . Further, it is preferable that a conductor be arranged on and in contact with the conductor 120 .

A region 231 b of the oxide 230 functions as one electrode of the capacitor 100 and the conductor 120 functions as the other electrode of the capacitor 100 . Insulator 278 functions as a dielectric for capacitive element 100 . Region 231b of oxide 230 has been reduced in resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100 .

An insulator with a high dielectric constant is preferably used for the insulator 278, and an insulator that can be used for the insulator 222 or the like may be used. For example, insulators containing oxides of one or both of aluminum and hafnium can be used. As the insulator containing oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. Further, the insulator 278 may have a stacked-layer structure, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), or the like. Therefore, two or more layers may be selected to form a laminated structure. For example, hafnium oxide, aluminum oxide and hafnium oxide are preferably deposited in this order by ALD to form a laminated structure. The film thicknesses of hafnium oxide and aluminum oxide are each set to 0.5 nm or more and 5 nm or less. With such a stacked-layer structure, the capacitor 100 with a large capacitance value and a small leakage current can be obtained.

In addition, although FIG. 82 shows the configuration in which the insulator 278 is provided as the dielectric of the capacitive element 100, the present invention is not limited to this. For example, in addition to the insulator 278 , another insulator may be laminated and used as the dielectric of the capacitor 100 .

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 120 . Although not shown, the conductor 120 may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive materials.

<Cell array structure>
An example of the cell array of this embodiment is shown in FIGS. 83 and 84. FIG. For example, a cell array can be formed by arranging cells 600 each including the transistor 200 and the capacitor 100 illustrated in FIG. 82 in a matrix or rows.

FIG. 83A is a circuit diagram showing one mode in which the cells 600 shown in FIG. 82 are arranged in matrix. In FIG. 83A, one of the sources and drains of the transistors of cells 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). The BL is also electrically connected to one of the source and the drain of the transistor included in the cell 600 arranged in the column direction. On the other hand, the first gates of transistors included in cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). Further, the transistor included in each cell 600 may be provided with a second gate BG. Vth of the transistor can be controlled by the potential applied to BG. Also, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and drain of the transistor. At this time, the first electrode of the capacitor may be part of the structure that constitutes the transistor. Also, the second electrode of the capacitor included in the cell 600 is electrically connected to PL.

FIG. 83B shows a circuit 610 including a cell 600a electrically connected to WL04 and BL02 and a cell 600b electrically connected to WL03 and BL02 as part of a row in FIG. It is an extracted cross-sectional view. FIG. 83B shows cross-sectional views of cells 600a and 600b.

A cell 600a has a transistor 200a and a capacitor 100a. A cell 600b has a transistor 200b and a capacitor 100b.

One of the source and drain of the transistor 200a and one of the source and drain of the transistor 200b are both electrically connected to BL02.

With the above structure, by sharing the wiring electrically connected to one of the source and the drain, the area occupied by the cell array can be further reduced.

FIG. 84A is a circuit diagram showing a circuit in which the cells 600 shown in FIG. 82 are arranged in a matrix, which is different from FIG. 83A. In FIG. 84A, the first gates of transistors included in cells 600 arranged in the row direction are electrically connected to common WL (WL01, WL02, WL03). One of the source and the drain of the transistor included in the cells arranged in the column direction is electrically connected to a common BL (BL01 to BL06). Further, the transistor included in each cell 600 may be provided with a second gate BG. Vth of the transistor can be controlled by the potential applied to BG. Also, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and drain of the transistor. At this time, the first electrode of the capacitor may be part of the structure that constitutes the transistor. Also, the second electrode of the capacitor included in the cell 600 is electrically connected to PL. Here, as shown in FIG. 84A, the second electrode of the capacitor of the cell 600 is electrically connected to the second electrode of the capacitor of the cell 600 adjacent to the cell 600 and the common PL. may be configured.

FIG. 84B shows a circuit 620 including a cell 600a electrically connected to WL02 and BL03 and a cell 600b electrically connected to WL02 and BL04 as part of a row in FIG. It is an extracted cross-sectional view. FIG. 84B shows a cross-sectional view of cells 600a and 600b.

A cell 600a has a transistor 200a and a capacitor 100a. A cell 600b has a transistor 200b and a capacitor 100b.

A common conductor is used for the second electrode of the capacitor 100a and the second electrode of the capacitor 100b, and the conductor is electrically connected to PL.

In addition, the cells 600 may be arranged in layers instead of being arranged in a plane. FIG. 85 shows a sectional view of a configuration in which n+1 layers of cell arrays including the circuit 610 are stacked. As shown in FIG. 85, by stacking a plurality of cell arrays, cells can be integrated and arranged without increasing the area occupied by the cell arrays. That is, a 3D cell array can be constructed.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 8)
An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the semiconductor device described in Embodiment 7, will be described below.

Note that in the examples of the semiconductor devices shown in FIGS. 86 to 89, structures having the same functions as the structures constituting the example of the semiconductor device shown in Embodiment Mode 7 are denoted by the same reference numerals. In the following description, mainly the parts different from the example of the semiconductor device described in Embodiment 7 are described, and the contents described in Embodiment 7 can be referred to for other parts.

<Structure example of semiconductor device>
86A, 86B, and 86C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that a memory device including one capacitor and at least one transistor is referred to as a cell in this specification.

FIG. 86A is a top view of a cell 600 including a transistor 200 and a capacitor 100. FIG. 86B and 86C are sectional views of the cell 600. FIG. Here, FIG. 86B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 86A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 86C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 86A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 86(A), some elements are omitted for clarity of illustration.

[Cell 600]
A semiconductor device of one embodiment of the present invention includes a transistor 200, a capacitor 100, and an insulator 280 functioning as an interlayer film. It also includes a conductor 240 (a conductor 240a and a conductor 240b) that is electrically connected to the transistor 200 and functions as a plug.

[Transistor 200]
As the structure of the transistor 200, the transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 shown in FIG. 86 is an example, and the structure is not limited, and an appropriate transistor may be used according to the circuit configuration and driving method.

[Capacitor 100]
As shown in FIG. 86 , the capacitive element 100 has a configuration in common with the transistor 200 . In this embodiment, an example of the capacitor 100 in which the region 231b provided in the oxide 230 of the transistor 200 functions as one electrode of the capacitor 100 is shown.

The capacitor 100 has a region 231 b of the oxide 230 , an insulator 275 over the region 231 b , an insulator 273 over the insulator 275 , and a conductor 120 over the insulator 273 . Furthermore, conductor 120 is preferably arranged on insulator 273 so that at least a portion of conductor 120 overlaps region 231 b of oxide 230 . Further, it is preferable that a conductor be arranged on and in contact with the conductor 120 .

A region 231 b of the oxide 230 functions as one electrode of the capacitor 100 and the conductor 120 functions as the other electrode of the capacitor 100 . Insulator 275 and insulator 273 function as dielectrics of capacitive element 100 . Region 231b of oxide 230 has been reduced in resistance and is a conductive oxide. Therefore, it can function as one of the electrodes of the capacitor 100 .

In addition, although FIG. 86 shows the configuration in which the insulator 275 and the insulator 273 are provided as the dielectric of the capacitor 100, the present invention is not limited to this. For example, in addition to the insulators 275 and 273, an insulator for a dielectric may be laminated separately.

<Cell array structure>
An example of the cell array of this embodiment is shown in FIGS. 87 and 88. FIG. For example, a cell array can be formed by arranging cells 600 including the transistors 200 and the capacitors 100 illustrated in FIG. 86 in a matrix or rows.

FIG. 87A is a circuit diagram showing one mode in which the cells 600 shown in FIG. 86 are arranged in matrix. In FIG. 87A, one of the sources and drains of the transistors of cells 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). The BL is also electrically connected to one of the source and the drain of the transistor included in the cells arranged in the column direction. On the other hand, the first gates of transistors included in cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). Further, the transistor included in each cell 600 may be provided with a second gate BG. Vth of the transistor can be controlled by the potential applied to BG. Also, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and drain of the transistor. At this time, the first electrode of the capacitor may be part of the structure that constitutes the transistor. Also, the second electrode of the capacitor included in the cell 600 is electrically connected to PL.

FIG. 87B shows a circuit 610 including a cell 600a electrically connected to WL04 and BL02 and a cell 600b electrically connected to WL03 and BL02 as part of a row in FIG. 87A. It is an extracted cross-sectional view. FIG. 87B shows cross-sectional views of cells 600a and 600b.

FIG. 88A is a circuit diagram showing a circuit in which the cells 600 shown in FIG. 86 are arranged in matrix, different from that shown in FIG. 87A. In FIG. 88A, the first gates of transistors included in cells 600 arranged in the row direction are electrically connected to common WL (WL01, WL02, WL03). One of the source and the drain of the transistor included in the cells arranged in the column direction is electrically connected to a common BL (BL01 to BL06). Further, the transistor included in each cell 600 may be provided with a second gate BG. Vth of the transistor can be controlled by the potential applied to BG. Also, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and drain of the transistor. At this time, the first electrode of the capacitor may be part of the structure that constitutes the transistor. Also, the second electrode of the capacitor included in the cell 600 is electrically connected to PL. Here, as shown in FIG. 88A, the second electrode of the capacitor of the cell 600 is electrically connected to the second electrode of the capacitor of the cell 600 adjacent to the cell 600 and the common PL. may be configured.

FIG. 88B shows a circuit 620 including a cell 600a electrically connected to WL02 and BL03 and a cell 600b electrically connected to WL02 and BL04 as part of a row in FIG. 88A. It is an extracted cross-sectional view. FIG. 88B shows a cross-sectional view of cell 600a and cell 600b.

In addition, the cells 600 may be arranged in layers instead of being arranged in a plane. FIG. 89 shows a sectional view of a configuration in which n+1 layers of cell arrays including the circuit 610 are stacked. As shown in FIG. 89, by stacking a plurality of cell arrays, cells can be integrated and arranged without increasing the area occupied by the cell arrays. That is, a 3D cell array can be constructed.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 9)
An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is different from the semiconductor device described in Embodiment 7, will be described below.

In addition, in the examples of the semiconductor devices shown in FIGS. 90 to 97, structures having the same functions as the structures constituting the example of the semiconductor device shown in Embodiment 7 are denoted by the same reference numerals. In the following description, mainly the parts different from the example of the semiconductor device described in Embodiment 7 are described, and the contents described in Embodiment 7 can be referred to for other parts.

<Structure example of semiconductor device>
90A, 90B, and 90C are a top view and a cross-sectional view of the transistor 200, the capacitor 100, and the periphery of the transistor 200 according to one embodiment of the present invention. Note that a memory device including one capacitor and at least one transistor is referred to as a cell in this specification.

FIG. 90A is a top view of a cell 600 including a transistor 200 and a capacitor 100. FIG. 90B and 90C are cross-sectional views of the cell 600. FIG. Here, FIG. 90B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 90A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 90C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 90A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 90(A), some elements are omitted for clarity of illustration.

[Cell 600]
A semiconductor device of one embodiment of the present invention includes a transistor 200, a capacitor 100, and insulators 280 and 282 functioning as interlayer films. It also includes conductors 240 (a conductor 240a, a conductor 240b, and a conductor 240c) that are electrically connected to the transistor 200 and function as plugs.

Note that in the capacitor 100, the layout of the transistor 200 and the capacitor 100 can be designed as appropriate depending on the required capacitance value.

For example, the area of the capacitor 100 is determined by the area where the region 231b of the oxide 230 overlaps with the conductor 120 with the insulator 278 interposed therebetween. Therefore, if the capacitance value required for the cell 600 cannot be obtained with the capacitive element 100 shown in FIGS. By making it larger than the width in the direction, the capacitance value can be increased.

Also, for example, the length of the region 231b in the A1-A2 direction may be longer than the length of the conductor 120 in the A1-A2 direction. In that case, conductor 240b can be embedded in insulator 280 and insulator 282. FIG. That is, the region 231b and the conductor 240b may be provided so as to be in contact with each other in a region where the region 231b and the conductor 120 do not overlap. Therefore, by forming the conductor 240a, the conductor 240b, and the conductor 240c in the same process, the process can be shortened.

Further, with such a configuration, for example, even if the position of the opening deviates from the designed position to the A1 side or the A2 side in FIG. and the electrical connection between the conductor 240c embedded in the opening and the conductor 120 are made in a self-aligning manner. FIG. 91 shows an example in which the opening is shifted to the A2 side.

By having the above structure, miniaturization or high integration is possible. Also, the degree of freedom in design can be increased. Further, the transistor 200 and the capacitor 100 are formed in the same process. Therefore, since the process can be shortened, the productivity can be improved.

[Transistor 200]
As the structure of the transistor 200, the transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 shown in FIG. 90 is only an example, and the structure is not limited, and an appropriate transistor may be used according to the circuit configuration and driving method.

[Capacitor 100]
As shown in FIG. 90 , the capacitive element 100 has a configuration in common with the transistor 200 . In this embodiment, an example of the capacitor 100 in which the region 231b provided in the oxide 230 of the transistor 200 functions as one electrode of the capacitor 100 is shown.

The capacitor 100 has a region 231 b of the oxide 230 , an insulator 278 over the region 231 b, and a conductor 120 over the insulator 278 . Conductor 120 is preferably placed over insulator 278 so that at least a portion of it overlaps region 231b of oxide 230 . Further, it is preferable that the conductor 240c is arranged on and in contact with the conductor 120. FIG.

As shown in FIG. 90(A), the side surface of the insulator 278 is aligned with the side surface of the conductor 120 in top view, but the present invention is not limited to this. For example, insulator 278 may cover transistor 200 without patterning insulator 278 .

<Cell array structure>
An example of the cell array of this embodiment is shown in FIGS. 92 to 96. FIG. For example, a cell array can be formed by arranging cells 600 each including the transistor 200 and the capacitor 100 illustrated in FIG. 90 in a matrix or rows.

FIG. 92A is a circuit diagram showing one mode in which the cells 600 shown in FIG. 90 are arranged in matrix. In FIG. 92A, one of the sources and drains of the transistors of cells 600 adjacent in the row direction is electrically connected to a common BL (BL01, BL02, BL03). The BL is also electrically connected to one of the source and the drain of the transistor included in the cells arranged in the column direction. On the other hand, the first gates of transistors included in cells 600 adjacent in the row direction are electrically connected to different WLs (WL01 to WL06). Further, the transistor included in each cell 600 may be provided with a second gate BG. The threshold of the transistor can be controlled by the potential applied to BG. Also, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and drain of the transistor. At this time, the first electrode of the capacitor may be part of the structure that constitutes the transistor. Also, the second electrode of the capacitor included in the cell 600 is electrically connected to PL.

FIG. 92B shows a circuit 610 including a cell 600a electrically connected to WL04 and BL02 and a cell 600b electrically connected to WL03 and BL02 as part of a row in FIG. It is an extracted cross-sectional view. FIG. 92B shows cross-sectional views of cells 600a and 600b.

With such a configuration, for example, even if the position of the opening deviates from the designed position to the A1 side or the A2 side in FIG. electrical connection with one electrode of BL02, electrical connection between the conductor embedded in the opening and one electrode of the capacitive element 100b, and the conductor embedded in the opening connected to BL02 and the transistor 200a and one of the source and drain of transistor 200b are electrically connected in a self-aligned manner, so that good electrical connection is achieved. FIG. 93 shows an example in which the opening is shifted to the A2 side.

FIG. 94 is a circuit diagram showing one mode in which the cells 600 shown in FIG. 90 are arranged in a matrix with a structure different from that shown in FIG. In the cell array shown in FIG. 94, wiring BL extends in the row direction and wiring WL extends in the column direction.

As shown in FIG. 94, one of the source and the drain of transistors 200a and 200b forming a cell is electrically connected to common wiring BL (BL01, BL02, BL03). The wiring BL is also electrically connected to one of the sources and drains of the transistors 200a and 200b included in the cell 600 arranged in the row direction. On the other hand, the first gate of the transistor 200a and the first gate of the transistor 200b, which form the cell 600, are electrically connected to different wirings WL (WL01 to WL06). These wirings WL are electrically connected to the first gates of the transistors 200a and 200b of the cells 600 arranged in the column direction.

Further, the transistor 200a and the transistor 200b included in each cell 600 may be provided with a second gate BG. The second gate BG and the wiring BGL are electrically connected, and the threshold voltage of the transistor can be controlled by the potential applied to the wiring BGL. In addition, the conductor 120a of the capacitor 100a and the conductor 120b of the capacitor 100b included in the cell 600 are electrically connected to different wirings VL.

95 is a cross-sectional view corresponding to the portion indicated by the dotted line in the circuit diagram shown in FIG. 94. As shown in FIG. As illustrated in FIG. 95, the wiring BL02 and the wirings WL03 to WL06 are orthogonal. Further, as illustrated in FIG. 95, the wiring BL02 and the wiring VL are orthogonal. Further, the wiring VL is provided so as to be shared between adjacent memory cells.

FIG. 96A is a circuit diagram showing a circuit in which the cells 600 shown in FIG. 90 are arranged in matrix, which is different from FIG. 92A. In FIG. 96A, the first gates of transistors included in cells 600 arranged in the row direction are electrically connected to common WL (WL01, WL02, WL03). One of the source and the drain of the transistor included in the cells arranged in the column direction is electrically connected to a common BL (BL01 to BL06). Further, the transistor included in each cell 600 may be provided with a second gate BG. The threshold of the transistor can be controlled by the potential applied to BG. Also, the first electrode of the capacitor included in the cell 600 is electrically connected to the other of the source and drain of the transistor. At this time, the first electrode of the capacitor may be part of the structure that constitutes the transistor. Also, the second electrode of the capacitor included in the cell 600 is electrically connected to PL. Here, as shown in FIG. 96A, the second electrode of the capacitor of the cell 600 is electrically connected to the second electrode of the capacitor of the cell 600 adjacent to the cell 600 and the common PL. may be configured.

FIG. 96B shows a circuit 620 including a cell 600a electrically connected to WL02 and BL03 and a cell 600b electrically connected to WL02 and BL04 as part of a row in FIG. 96A. It is an extracted cross-sectional view. FIG. 96B shows cross-sectional views of cells 600a and 600b.

In addition, the cells 600 may be arranged in layers instead of being arranged in a plane. FIG. 97 shows a sectional view of a configuration in which n+1 layers of cell arrays including the circuit 610 are stacked. As shown in FIG. 97, by stacking a plurality of cell arrays, cells can be integrated and arranged without increasing the area occupied by the cell arrays. That is, a 3D cell array can be configured.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 10)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

<Storage Device 1>
The memory device shown in FIGS. 98 and 99 has a transistor 300, a transistor 200 and a capacitive element 100. FIG. FIG. 98 is a cross-sectional view of transistor 200 and transistor 300 in the channel length direction. FIG. 99 shows a cross-sectional view of the transistor 300 near the transistor 300 in the channel width direction.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

In the memory device shown in FIG. 98, wiring 1001 is electrically connected to the source of transistor 300 and wiring 1002 is electrically connected to the drain of transistor 300 . A wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 1004 is electrically connected to the top gate of the transistor 200, and a wiring 1006 is electrically connected to the bottom gate of the transistor 200. there is The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. .

The memory device shown in FIG. 98 has a characteristic that the potential of the gate of the transistor 300 can be held, so that data can be written, held, and read as follows.

Describe writing and retention of information. First, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the wiring 1003 is applied to the node SN electrically connected to the gate of the transistor 300 and one of the electrodes of the capacitor 100 . That is, a predetermined charge is applied to the gate of the transistor 300 (writing). Here, it is assumed that one of charges that give two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. After that, the potential of the wiring 1004 is set to a potential at which the transistor 200 is turned off so that the transistor 200 is turned off, so that the charge is held in the node SN (holding).

When the off-state current of the transistor 200 is small, the charge of the node SN is retained for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the wiring 1005 while a predetermined potential (constant potential) is applied to the wiring 1001, the wiring 1002 assumes a potential corresponding to the amount of charge held in the node SN. Assuming that the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is given a high-level charge is V th_H when the gate of the transistor 300 is given a low-level charge. This is because it is lower than the apparent threshold voltage V _{th_L} in the case where Here, the apparent threshold voltage refers to the potential of the wiring 1005 required to turn on the transistor 300 . Therefore, by setting the potential of the wiring 1005 to _V0 between _{Vth_H} and _{Vth_L} , the charge applied to the node SN can be determined. For example, in writing, when high-level charge is applied to the node SN, the transistor 300 is turned on when the potential of the wiring 1005 becomes V ₀ (>V _{th — H} ). On the other hand, when low-level charge is applied to the node SN, the transistor 300 remains “off” even when the potential of the wiring 1005 becomes V ₀ (<V _{th — L} ). Therefore, by determining the potential of the wiring 1002, information held in the node SN can be read.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 and 200 .

The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 consisting of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source or drain regions. have

In the transistor 300, as shown in FIG. 99, the upper surface and side surfaces in the channel width direction of the semiconductor region 313 are covered with the conductor 316 with the insulator 315 interposed therebetween. By making the transistor 300 Fin-type in this manner, the effective channel width is increased, so that the on-characteristics of the transistor 300 can be improved. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 300 can be improved.

Transistor 300 can be either p-channel or n-channel.

A region in which a channel of the semiconductor region 313 is formed, a region in the vicinity thereof, low-resistance regions 314a and 314b serving as a source region or a drain region, and the like preferably contain a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

The low-resistance region 314a and the low-resistance region 314b are made of an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron in addition to the semiconductor material applied to the semiconductor region 313. contains elements that

The conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron, a metal material, or an alloy. material, or a conductive material such as a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

Note that the transistor 300 shown in FIG. 98 is only an example, and the structure is not limited, and an appropriate transistor may be used according to the circuit configuration and driving method.

An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order to cover the transistor 300 .

As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. Just do it.

The insulator 322 may function as a planarization film that planarizes a step caused by the transistor 300 or the like provided therebelow. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a CMP method or the like in order to improve planarity.

For the insulator 324, it is preferable to use a film having a barrier property such that hydrogen or impurities do not diffuse from the substrate 311, the transistor 300, or the like to the region where the transistor 200 is provided.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, might degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 200 and the transistor 300 . Specifically, the film that suppresses diffusion of hydrogen is a film from which the amount of desorption of hydrogen is small.

The desorption amount of hydrogen can be analyzed using, for example, TDS. For example, the amount of hydrogen released from the insulator 324 is the amount of hydrogen atoms released per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. , 10×10 ¹⁵ atoms/cm ² or less, preferably 5×10 ¹⁵ atoms/cm ² or less.

Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324 . For example, the dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3. Also, for example, the dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, that of the insulator 324 . By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

In addition, conductors 328, 330, and the like electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326, respectively. Note that the conductors 328 and 330 function as plugs or wirings. In addition, conductors that function as plugs or wiring may have a plurality of structures collectively given the same reference numerals. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as a wiring and a part of the conductor functions as a plug.

As a material of each plug and wiring (the conductor 328, the conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a laminated layer. can be used. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably made of a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.

A wiring layer may be provided over the insulator 326 and the conductor 330 . For example, in FIG. 98, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed over the insulators 350 , 352 , and 354 . The conductor 356 functions as a plug or wiring. Note that the conductor 356 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 350 , for example, an insulator having a barrier property against hydrogen is preferably used, like the insulator 324 . Further, the conductor 356 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

Note that tantalum nitride or the like may be used as the conductor having a barrier property against hydrogen, for example. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while the conductivity of the wiring is maintained. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

A wiring layer may be provided over the insulator 354 and the conductor 356 . For example, in FIG. 98, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed over the insulators 360 , 362 , and 364 . The conductor 366 functions as a plug or wiring. Note that the conductor 366 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 360, for example, an insulator having a barrier property against hydrogen is preferably used, like the insulator 324. Further, the conductor 366 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 364 and the conductor 366 . For example, in FIG. 98, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed over the insulators 370 , 372 , and 374 . The conductor 376 functions as a plug or wiring. Note that the conductor 376 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 370, for example, an insulator having a barrier property against hydrogen is preferably used like the insulator 324. Further, the conductor 376 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A wiring layer may be provided over the insulator 374 and the conductor 376 . For example, in FIG. 98, an insulator 380, an insulator 382, and an insulator 384 are stacked in order. A conductor 386 is formed over the insulators 380 , 382 , and 384 . The conductor 386 functions as a plug or wiring. Note that the conductor 386 can be provided using a material similar to that of the conductors 328 and 330 .

Note that for the insulator 380, for example, an insulator having a barrier property against hydrogen is preferably used like the insulator 324. Further, the conductor 386 preferably contains a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

The wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described above. It is not limited to this. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, or the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

An insulator 210 , an insulator 212 , an insulator 214 , and an insulator 216 are stacked in this order over the insulator 384 and the conductor 386 . Any of the insulator 210, the insulator 212, the insulator 214, and the insulator 216 preferably uses a substance that has a barrier property against oxygen and hydrogen.

For the insulators 210 and 214, for example, a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, a region where the transistor 300 is provided, or the like to a region where the transistor 200 is provided is used. is preferred. Therefore, a material similar to that of the insulator 324 can be used.

As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, diffusion of hydrogen into a semiconductor element including an oxide semiconductor, such as the transistor 200, might degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses diffusion of hydrogen between the transistor 200 and the transistor 300 . Specifically, the film that suppresses diffusion of hydrogen is a film from which the amount of desorption of hydrogen is small.

As a film having a barrier property against hydrogen, for example, the insulators 210 and 214 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

In particular, aluminum oxide has a high shielding effect of preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which cause variations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide forming the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200 .

Further, for example, the insulator 212 and the insulator 216 can be formed using a material similar to that of the insulator 320 . Also, by using a material having a relatively low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, the insulators 212 and 216 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

In addition, the insulator 210 , the insulator 212 , the insulator 214 , and the insulator 216 are embedded with a conductor 218 , a conductor forming the transistor 200 (the conductor 205 ), and the like. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the capacitor 100 or the transistor 300 . Conductor 218 can be provided using a material similar to that of conductor 328 and conductor 330 .

In particular, the conductor 218 in a region in contact with the insulator 210 and the insulator 214 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 can be separated by a layer having barrier properties against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed.

A transistor 200 is provided above the insulator 216 . Note that the transistor included in the semiconductor device described in the above embodiment may be used as the structure of the transistor 200 . Further, the transistor 200 shown in FIG. 98 is an example, and the structure is not limited, and an appropriate transistor may be used according to the circuit configuration and driving method.

An insulator 280 is provided above the transistor 200 .

An insulator 282 is provided on the insulator 280 . The insulator 282 preferably uses a substance that has barrier properties against oxygen and hydrogen. Therefore, a material similar to that of the insulator 214 can be used for the insulator 282 . For example, the insulator 282 is preferably a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

In particular, aluminum oxide has a high shielding effect of preventing the penetration of both oxygen and impurities such as hydrogen and moisture, which cause variations in the electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide forming the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200 .

An insulator 286 is provided over the insulator 282 . A material similar to that of the insulator 320 can be used for the insulator 286 . Also, by using a material having a relatively low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 286 .

A conductor 246, a conductor 248, and the like are embedded in the insulator 220, the insulator 222, the insulator 280, the insulator 282, and the insulator 286, respectively.

The conductors 246 and 248 function as plugs or wirings electrically connected to the capacitor 100 , the transistor 200 , or the transistor 300 . The conductors 246 and 248 can be formed using a material similar to that of the conductors 328 and 330 .

Next, a capacitor 100 is provided above the transistor 200 . Capacitive element 100 includes conductor 110 , conductor 120 , and insulator 130 .

Alternatively, the conductor 112 may be provided over the conductor 246 and the conductor 248 . The conductor 112 functions as a plug or wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300. FIG. The conductor 110 functions as an electrode of the capacitor 100 . Note that the conductor 112 and the conductor 110 can be formed at the same time.

The conductors 112 and 110 are metal films containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or metal nitride films containing any of the above elements as components. (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like can be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon oxide are added. Conductive materials such as indium tin oxide can also be applied.

Although the conductor 112 and the conductor 110 have a single-layer structure in FIG. 98, they are not limited to this structure and may have a laminated structure of two or more layers. For example, between a conductor with a barrier property and a conductor with high conductivity, a conductor with a barrier property and a conductor with high adhesion to the conductor with high conductivity may be formed.

An insulator 130 is provided as a dielectric of the capacitor 100 over the conductors 112 and 110 . The insulator 130 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like. It may be used as long as it is used, and it can be provided as a laminate or a single layer.

For example, the insulator 130 is preferably made of a material with high dielectric strength such as silicon oxynitride. With this structure, since the capacitor 100 includes the insulator 130, dielectric strength is improved and electrostatic breakdown of the capacitor 100 can be suppressed.

A conductor 120 is provided over the insulator 130 so as to overlap with the conductor 110 . Note that a conductive material such as a metal material, an alloy material, or a metal oxide material can be used for the conductor 120 . It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In addition, when forming simultaneously with another structure such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) may be used.

An insulator 150 is provided over the conductor 120 and the insulator 130 . The insulator 150 can be provided using a material similar to that of the insulator 320 . Moreover, the insulator 150 may function as a planarization film covering the uneven shape thereunder.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Storage device 2>
A semiconductor device illustrated in FIG. 100 is a memory device including a transistor 400 , a transistor 200 , and a capacitor 100 . One mode of a storage device is described below with reference to FIG.

FIG. 100A is a circuit diagram showing an example of the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 100B shows a cross-sectional view of a semiconductor device in which the wirings 1003 to 1010 and the like shown in FIG. 100A correspond to each other.

Transistor 200 and transistor 400 formed on a substrate (not shown) have different configurations. For example, the transistor 400 may have a structure in which the drain current when the bottom gate voltage and the top gate voltage are 0 V is smaller than that of the transistor 200 . A structure in which the potential of the bottom gate of the transistor 200 can be controlled by using the transistor 400 as a switching element is employed. Accordingly, the node connected to the bottom gate of the transistor 200 is turned off after the potential of the node connected to the bottom gate of the transistor 200 is set to a desired potential, whereby loss of charge in the node connected to the bottom gate of the transistor 200 can be suppressed. can.

As illustrated in FIG. 100 , the transistor 200 has a gate electrically connected to the wiring 1004 , one of the source and the drain electrically connected to the wiring 1003 , and the other of the source and the drain electrically connected to one electrode of the capacitor 100 . In addition, the other electrode of the capacitor 100 is electrically connected to the wiring 1005 . A drain of the transistor 400 is electrically connected to the wiring 1010 . 100A and 100B, the bottom gate of the transistor 200 and the source, top gate, and bottom gate of the transistor 400 are connected through wirings 1006, 1007, 1008, and 1009. are electrically connected.

Here, by applying a potential to the wiring 1004, the on state and off state of the transistor 200 can be controlled. By applying a potential to the wiring 1003 with the transistor 200 turned on, charge can be supplied to the capacitor 100 through the transistor 200 . At this time, the charge supplied to the capacitor 100 can be held by turning off the transistor 200 . By applying an arbitrary potential to the wiring 1005, the potential of the connection portion between the transistor 200 and the capacitor 100 can be controlled by capacitive coupling. For example, applying a ground potential to the wiring 1005 makes it easier to hold the charge. By applying a negative potential to the wiring 1010, a negative potential is applied to the bottom gate of the transistor 200 through the transistor 400, the threshold voltage of the transistor 200 is made higher than 0 V, and off-state current is reduced. , Icut can be made very small. Here, Icut refers to the drain current when the voltage applied to the top gate is 0V.

The top gate and the bottom gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the bottom gate of the transistor 200 are connected; . When the negative potential of the bottom gate of transistor 200 is held, the voltage between the top gate and source of transistor 400 and the voltage between the bottom gate and source of transistor 400 are 0V. Since the Icut of transistor 400 is very small and the threshold voltage is higher than that of transistor 200, this configuration maintains the negative potential of the bottom gate of transistor 200 for a long time without supplying power to transistor 400. be able to.

Furthermore, by holding the negative potential of the bottom gate of the transistor 200, Icut of the transistor 200 can be significantly reduced without supplying power to the transistor 200. FIG. In other words, charge can be held in the capacitor 100 for a long time without supplying power to the transistors 200 and 400 . For example, by using such a semiconductor device as a memory element, memory can be held for a long time without power supply. Therefore, it is possible to provide a memory device that has a low frequency of refresh operations or does not require refresh operations.

Note that the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 is not limited to that shown in FIGS. The connection relationship can be appropriately changed according to the required circuit configuration.

<Structure of storage device 2>
FIG. 100B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. FIG. In the memory device shown in FIG. 100, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

A memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided in the same layer, and the capacitor 100 is provided above the transistors 200 and 400 .

Note that as the capacitor 100 and the transistor 200, a capacitor and a transistor included in the semiconductor device and the memory device described in the above embodiment and FIG. 98 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIG. 100 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460 a and a conductor 460 b ) functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, an insulator 470 in contact with the conductor 460 , and the conductor 460 . An insulator 475 arranged on the side surfaces, insulators 220, 222, 424, and 450 functioning as gate insulating layers, an oxide 430c having a region where a channel is formed, and a source or drain oxide 431a and oxide 431b functioning as one of the source and oxide 432a and oxide 432b functioning as the other of the source or drain. A conductor 405 functioning as a bottom gate electrode is electrically connected to a conductor 403 functioning as a wiring.

In transistor 400 , conductor 405 is in the same layer as conductor 205 . Insulator 424 is the same layer as insulator 224 . The oxides 431a and 432a are in the same layer as the oxide 230a, and the oxides 431b and 432b are in the same layer as the oxide 230b. Oxide 430c is the same layer as oxide 230c. Insulator 450 is the same layer as insulator 250 . Metal oxide 452 is the same layer as metal oxide 252 . Conductor 460 is the same layer as conductor 260 . Insulator 470 is the same layer as insulator 270 . Further, the insulator 471 is the same layer as the insulator 271 . Further, the insulator 475 is the same layer as the insulator 275 .

The oxide 430c functioning as an active layer of the transistor 400 has reduced oxygen vacancies and reduced impurities such as hydrogen and water, similar to the oxide 230 and the like. Accordingly, the threshold voltage of the transistor 400 can be made higher than 0 V, the off-state current can be reduced, and the drain current when the bottom gate voltage and the top gate voltage are 0 V can be significantly reduced.

Further, as described above, the oxides 431a and 432a are in the same layer as the oxide 230a, and the oxides 431b and 432b are in the same layer as the oxide 230b. Therefore, low-resistance regions corresponding to the regions 231a and 231b are formed in the oxide 431a, the oxide 432a, the oxide 431b, and the oxide 432b.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage Device 3>
A semiconductor device illustrated in FIG. 101 is a memory device including a transistor 300, a transistor 400, a transistor 200, and a capacitor 100. The semiconductor device illustrated in FIG. One mode of a storage device is described below with reference to FIG.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. The transistor described in any of the above embodiments can be formed with high yield even if it is miniaturized; therefore, miniaturization of the transistor 200 can be achieved. By using such a transistor in a memory device, miniaturization or high integration of the memory device can be achieved. Since the transistor described in any of the above embodiments has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

In FIG. 101, a wiring 1001 is electrically connected to the source of the transistor 300 and a wiring 1002 is electrically connected to the drain of the transistor 300 . A wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 1004 is electrically connected to the top gate of the transistor 200, and a wiring 1006 is electrically connected to the bottom gate of the transistor 200. there is The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. . A wiring 1007 is electrically connected to the source of the transistor 400, a wiring 1008 is electrically connected to the top gate of the transistor 400, a wiring 1009 is electrically connected to the bottom gate of the transistor 400, and a wiring 1010 is electrically connected to the transistor 400. electrically connected to the drain. Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

The semiconductor device illustrated in FIG. 101 has a characteristic that the potential of the gate of the transistor 300 can be held, so that data can be written, held, and read as described below.

Describe writing and retention of information. First, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 1003 is applied to the node SN electrically connected to the gate of the transistor 300 and one of the electrodes of the capacitor 100 . That is, a predetermined charge is applied to the gate of the transistor 300 (writing). Here, it is assumed that one of charges that give two different potential levels (hereinafter referred to as low-level charge and high-level charge) is applied. After that, the potential of the fourth wiring 1004 is set to a potential at which the transistor 200 is turned off so that the transistor 200 is turned off, so that the charge is held in the node SN (holding).

When the off-state current of the transistor 200 is small, the charge of the node SN is retained for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 1005 while a predetermined potential (constant potential) is applied to the first wiring 1001, the second wiring 1002 is supplied with the charge held at the node SN. Take a potential corresponding to the amount. Assuming that the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is given a high-level charge is V th_H when the gate of the transistor 300 is given a low-level charge. This is because it is lower than the apparent threshold voltage V _{th_L} in the case where Here, the apparent threshold voltage refers to the potential of the fifth wiring 1005 necessary for making the transistor 300 "on." Therefore, by setting the potential of the fifth wiring 1005 to the potential _V0 between _{Vth_H} and _{Vth_L} , the charge applied to the node SN can be determined. For example, in writing, when high-level charge is applied to the node SN, the transistor 300 is turned on when the potential of the fifth wiring 1005 becomes V ₀ (>V _{th — H} ). On the other hand, when Low-level charge is applied to the node SN, the transistor 300 remains “off” even when the potential of the fifth wiring 1005 becomes V ₀ (<V _{th — L} ). Therefore, by determining the potential of the second wiring 1002, information held in the node SN can be read.

<Structure of storage device 3>

FIG. 101 is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, a transistor 300, and a transistor 400. FIG. The memory device shown in FIG. 101 has the same function as the structure constituting the semiconductor device and the memory device shown in <Structure of Memory Device 1> and <Structure of Memory Device 2> in the previous embodiments. The same reference numerals are given to the structures having the same structure.

A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 , 200 and 400 .

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, capacitors and transistors included in the semiconductor devices and memory devices described in the above embodiments and FIGS. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIG. 101 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

In the memory device shown in FIG. 101, openings 500 are formed in insulators 212, 214, 216, 220, 222, 224, 273, 274, and 280. An example of connecting the insulator 210 and the insulator 282 is shown. With such a structure, the transistors 200 and 400 are surrounded by the insulator 210 and the insulator 282, and thus are less susceptible to impurities such as water and hydrogen. In addition, release of oxygen from oxides and insulators to the outside is reduced. A storage device having such a structure is preferable because it has improved reliability. Note that the opening 500 may not be provided.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

An example of the memory cell array of this embodiment is shown in FIG. By arranging the transistors 200 as memory cells in a matrix, a memory cell array can be formed.

The memory device shown in FIG. 102 is a semiconductor device forming a memory cell array by arranging the memory devices shown in FIGS. 98 and 101 in matrix. Note that one transistor 400 can control bottom gate voltages of a plurality of transistors 200 . Therefore, the number of transistors 400 is preferably less than that of the transistors 200 .

Therefore, the transistor 400 shown in FIG. 101 is omitted in FIG. FIG. 102 is a cross-sectional view of part of a row when the memory devices shown in FIGS. 98 and 101 are arranged in a matrix.

102 differs from FIG. 101 in the configuration of the transistor 300. FIG. In the transistor 300 shown in FIG. 102, a semiconductor region 313 (part of the substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a Fin-type transistor because it utilizes the projections of the semiconductor substrate. Note that an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion. Further, here, the case where a part of the semiconductor substrate is processed to form a convex portion is shown, but a semiconductor film having a convex shape may be formed by processing an SOI substrate.

In the memory device shown in FIG. 102, memory cells 650a and 650b are arranged adjacent to each other. The memory cells 650 a and 650 b each include the transistor 300 , the transistor 200 , and the capacitor 100 and are electrically connected to the wirings 1001 , 1002 , 1003 , 1004 , 1005 , and 1006 . Similarly, in the memory cells 650a and 650b, a node at which the gate of the transistor 300 and one of the electrodes of the capacitor 100 are electrically connected is a node SN. Note that the wiring 1002 is a wiring common to the adjacent memory cells 650a and 650b.

When memory cells are arranged in an array, it is necessary to read out information from desired memory cells at the time of reading. For example, when the memory cell array has a NOR-type structure, only information in a desired memory cell can be read by turning off the transistor 300 of the memory cell from which information is not read. In this case, a potential at which the transistor 300 is turned off regardless of the charge applied to the node SN, that is, a potential lower than _{Vth_H} is applied to the wiring 1005 connected to the memory cell from which data is not read. Just do it. Alternatively, for example, when the memory cell array has a NAND structure, only the information of a desired memory cell can be read by turning on the transistor 300 of the memory cell from which information is not read. In this case, a potential that makes the transistor 300 "conductive" regardless of the charge applied to the node SN, that is, a potential higher than _{Vth_L} is applied to the wiring 1005 connected to the memory cell from which data is not read. good.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 11)
In this embodiment, one mode of a semiconductor device, which is different from one mode of the semiconductor device described in Embodiment 10, will be described with reference to FIGS.

Note that in one mode of the semiconductor device shown in FIGS. 103 to 106, structures having the same functions as the structures constituting one mode of the semiconductor device shown in Embodiment 10 are denoted by the same reference numerals. In the following description, portions different from one mode of the semiconductor device described in Embodiment 10 are mainly described, and the contents described in Embodiment 10 can be referred to for other portions.

<Storage Device 1>
A memory device illustrated in FIG. 103 includes a transistor 300 , a transistor 200 , and a capacitor 100 . FIG. 103 is a cross-sectional view of transistor 200 and transistor 300 in the channel length direction.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

The memory device illustrated in FIG. 103 has a characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read. Note that the description of the above embodiment can be referred to for writing, holding, and reading information.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 and 200 .

As the structure of the transistor 200, the transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 illustrated in FIG. 103 is only an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Storage device 2>
A semiconductor device illustrated in FIG. 104 is a memory device including a transistor 400, a transistor 200, and a capacitor 100. The semiconductor device illustrated in FIG. One mode of a storage device is described below with reference to FIG.

FIG. 104A is a circuit diagram showing an example of the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 104B shows a cross-sectional view of a semiconductor device in which the wirings 1003 to 1010 and the like shown in FIG. 104A correspond to each other.

<Structure of storage device 2>
FIG. 104B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. FIG. In the memory device shown in FIG. 104, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

A memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided in the same layer, and the capacitor 100 is provided above the transistors 200 and 400 .

Note that as the capacitor 100 and the transistor 200, a capacitor and a transistor included in the semiconductor device and the memory device described in the above embodiment and FIG. 103 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIG. 104 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460 a and a conductor 460 b ) functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, an insulator 470 in contact with the conductor 460 , and the conductor 460 . Insulator 472 arranged on the side, insulator 220, insulator 222, insulator 424, and insulator 450 functioning as gate insulating layers, oxide 430c having a region where a channel is formed, source or drain oxide 431a and oxide 431b functioning as one of the source and oxide 432a and oxide 432b functioning as the other of the source or drain. A conductor 405 functioning as a bottom gate electrode is electrically connected to a conductor 403 functioning as a wiring.

In transistor 400 , conductor 405 is in the same layer as conductor 205 . Insulator 424 is the same layer as insulator 224 . The oxides 431a and 432a are in the same layer as the oxide 230a, and the oxides 431b and 432b are in the same layer as the oxide 230b. Oxide 430c is the same layer as oxide 230c. Insulator 450 is the same layer as insulator 250 . Metal oxide 452 is the same layer as metal oxide 252 . Conductor 460 is the same layer as conductor 260 . Also, the insulator 470 is the same layer as the insulator 270 . Further, the insulator 471 is the same layer as the insulator 271 . Further, the insulator 472 is the same layer as the insulator 272 .

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage Device 3>
A semiconductor device illustrated in FIG. 105 is a memory device including a transistor 300, a transistor 400, a transistor 200, and a capacitor 100. The semiconductor device illustrated in FIG. One mode of a storage device is described below with reference to FIG.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. The transistor described in any of the above embodiments can be formed with high yield even if it is miniaturized; therefore, miniaturization of the transistor 200 can be achieved. By using such a transistor in a memory device, miniaturization or high integration of the memory device can be achieved. Since the transistor described in any of the above embodiments has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

<Structure of storage device 3>

105 is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, a transistor 300, and a transistor 400. FIG. The memory device shown in FIG. 105 has the same function as the structure constituting the semiconductor device and the memory device shown in <Structure of Memory Device 1> and <Structure of Memory Device 2> in the previous embodiments. The same reference numerals are given to the structures having the same structure.

A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 , 200 and 400 .

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, capacitors and transistors included in the semiconductor devices and memory devices described in the above embodiment and FIGS. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIG. 105 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

In the memory device shown in FIG. 105, the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 224, the insulator 275, the insulator 273, the insulator 274, and the insulator 280 are An example of providing an opening 500 and connecting the insulator 210 and the insulator 282 is shown. With such a structure, the transistors 200 and 400 are surrounded by the insulator 210 and the insulator 282, and thus are less susceptible to impurities such as water and hydrogen. In addition, release of oxygen from oxides and insulators to the outside is reduced. A storage device having such a structure is preferable because it has improved reliability. Note that the opening 500 may not be provided.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

An example of the memory cell array of this embodiment is shown in FIG. By arranging the transistors 200 as memory cells in a matrix, a memory cell array can be formed.

Note that the memory device shown in FIG. 106 is a semiconductor device forming a memory cell array by arranging the memory devices shown in FIGS. 103 and 105 in matrix. Note that one transistor 400 can control bottom gate voltages of a plurality of transistors 200 . Therefore, the number of transistors 400 is preferably less than that of the transistors 200 .

Therefore, the transistor 400 shown in FIG. 105 is omitted in FIG. FIG. 106 is a cross-sectional view of part of a row when the memory devices shown in FIGS. 103 and 105 are arranged in a matrix.

Note that the description of the transistor 300 illustrated in FIG. 102 can be referred to for the description of the transistor 300 illustrated in FIG.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 12)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

Note that in one mode of the semiconductor device illustrated in FIGS. 107 to 111, structures having the same functions as those of the structures of one mode of the semiconductor device described in the above embodiment are denoted by the same reference numerals. Further, hereinafter, mainly the portions that are different from one mode of the semiconductor device described in the previous embodiment will be described, and the contents described in the above embodiment can be referred to for the other portions. do.

<Storage Device 1>
The memory device illustrated in FIGS. 107 and 108 includes a transistor 300, a transistor 200, and a capacitor 100. FIG. 107 and 108 are cross-sectional views of the transistor 200 and the transistor 300 in the channel length direction.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

In the memory device shown in FIGS. 107 and 108, wiring 1001 is electrically connected to the source of transistor 300 and wiring 1002 is electrically connected to the drain of transistor 300 . A wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 1004 is electrically connected to the top gate of the transistor 200, and a wiring 1006 is electrically connected to the bottom gate of the transistor 200. there is The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. .

The memory devices illustrated in FIGS. 107 and 108 have the characteristic that the potential of the gate of the transistor 300 can be held, so that information can be written, held, and read. Note that the description of the above embodiment can be referred to for writing, holding, and reading information.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 and 200 .

As the structure of the transistor 200, the transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 illustrated in FIG. 107 is only an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modified Example of Storage Device 1>
An example of a memory device according to one embodiment of the present invention is described below with reference to FIG.

FIG. 108 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. FIG. In the memory device shown in FIG. 108, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

The memory device shown in FIG. 108 differs from the memory device shown in <Structure of Memory Device 1> in that the cell 600 described in the previous embodiment is provided.

Specifically, the memory device shown in FIG. 108 is a cell in which part of the configuration of the capacitor 100 and part of the configuration of the transistor 200 are shared, instead of providing the capacitor 100 and the transistor 200 independently. has 600.

With the above structure, part or all of the cell 600 and the transistor 300 overlap with each other, so that the total projected area of the memory device can be reduced. Therefore, miniaturization or high integration of the cell 600 is facilitated. Also, the process can be shortened.

<Storage Device 2>
The semiconductor device shown in FIG. 109 is a memory device having transistors 400, 200, and a capacitor 100. The semiconductor device shown in FIG. One mode of a memory device is described below with reference to FIG.

FIG. 109A is a circuit diagram showing an example of the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 109B shows a cross-sectional view of a semiconductor device in which the wirings 1003 to 1010 and the like shown in FIG. 109A correspond to each other.

<Structure of storage device 2>
FIG. 109B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. FIG. In the memory device shown in FIG. 109, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

A memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided in the same layer, and the capacitor 100 is provided above the transistors 200 and 400 .

Note that as the capacitor 100 and the transistor 200, the capacitors and transistors included in the semiconductor devices and memory devices described in the above embodiments and FIGS. 107 and 108 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIG. 109 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460 a and a conductor 460 b ) functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, insulators 471 and 472 in contact with the conductor 460 . , the insulator 473 arranged on the side surface of the conductor 460 with the insulator 472 interposed therebetween, and the insulators 220, 222, 224, and 450 functioning as gate insulating layers, the channel is formed. It has an oxide 430c with regions, oxides 431a and 431b functioning as one of the source or drain, and oxides 432a and 432b functioning as the other of the source or drain. A conductor 405 functioning as a bottom gate electrode is electrically connected to a conductor 403 functioning as a wiring.

In transistor 400 , insulator 473 is in the same layer as insulator 273 .

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage Device 3>
A semiconductor device illustrated in FIG. 110 is a memory device including a transistor 300, a transistor 400, a transistor 200, and a capacitor 100. The semiconductor device illustrated in FIG. One mode of a memory device is described below with reference to FIG.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. The transistor described in any of the above embodiments can be formed with high yield even if it is miniaturized; therefore, miniaturization of the transistor 200 can be achieved. By using such a transistor in a memory device, miniaturization or high integration of the memory device can be achieved. Since the transistor described in any of the above embodiments has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

<Structure of storage device 3>

110 is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, a transistor 300, and a transistor 400. FIG. Note that the memory device shown in FIG. 110 has the same functions as those of the structure constituting the semiconductor device and the memory device shown in <Structure of Memory Device 1> and <Structure of Memory Device 2> in the previous embodiments. The same reference numerals are given to the structures having the same structure.

A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 , 200 and 400 .

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, capacitors and transistors included in the semiconductor devices and memory devices described in the above embodiments and FIGS. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIG. 110 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

In the memory device shown in FIG. 110, the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, and the insulator 280 are provided with openings 500, and the insulators 210 and 282 are connected. shows an example. With such a structure, the transistors 200 and 400 are surrounded by the insulator 210 and the insulator 282, and thus are less susceptible to impurities such as water and hydrogen. In addition, release of oxygen from oxides and insulators to the outside is reduced. A storage device having such a structure is preferable because it has improved reliability. Note that the opening 500 may not be provided.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

An example of the memory cell array of this embodiment is shown in FIG. By arranging the transistors 200 as memory cells in a matrix, a memory cell array can be formed.

Note that the memory device shown in FIG. 111 is a semiconductor device forming a memory cell array by arranging the memory devices shown in FIGS. 107 and 110 in matrix. Note that one transistor 400 can control bottom gate potentials of a plurality of transistors 200 . Therefore, the number of transistors 400 is preferably less than that of the transistors 200 .

Therefore, the transistor 400 shown in FIG. 110 is omitted in FIG. FIG. 111 is a cross-sectional view of part of a row when the memory devices shown in FIGS. 107 and 110 are arranged in a matrix.

111 differs from FIG. 110 in the configuration of the transistor 300. FIG. In the transistor 300 shown in FIG. 111, a semiconductor region 313 (part of the substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a Fin-type transistor because it utilizes the projections of the semiconductor substrate. Note that an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion. Further, here, the case where a part of the semiconductor substrate is processed to form a convex portion is shown, but a semiconductor film having a convex shape may be formed by processing an SOI substrate.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 13)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

Note that in one mode of the semiconductor device illustrated in FIGS. 112 to 116, structures having the same functions as structures constituting one mode of the semiconductor device described in the above embodiment are denoted by the same reference numerals. Further, hereinafter, mainly the portions that are different from one mode of the semiconductor device described in the above embodiments are described, and the contents described in the above embodiments can be referred to for other portions. do.

<Storage Device 1>
The memory devices illustrated in FIGS. 112 and 113 each include a transistor 300, a transistor 200, and a capacitor 100. FIG. 112 and 113 are cross-sectional views of the transistor 200 and the transistor 300 in the channel length direction.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 and 200 .

As the structure of the transistor 200, the transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 illustrated in FIG. 112 is only an example, and the structure is not limited to that, and an appropriate transistor may be used depending on the circuit configuration and the driving method.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modified Example of Storage Device 1>
An example of a memory device according to one embodiment of the present invention is described below with reference to FIG.

113 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. FIG. In the memory device shown in FIG. 113, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

The memory device shown in FIG. 113 differs from the memory device shown in <Structure of Memory Device 1> in that the cell 600 described in the previous embodiment is provided.

Specifically, in the memory device shown in FIG. 113, instead of providing the capacitor 100 and the transistor 200 independently, a cell shares part of the configuration of the capacitor 100 and part of the configuration of the transistor 200. has 600.

With the above structure, part or all of the cell 600 and the transistor 300 overlap with each other, so that the total projected area of the memory device can be reduced. Therefore, miniaturization or high integration of the cell 600 is facilitated. Also, the process can be shortened.

<Storage device 2>
A semiconductor device illustrated in FIG. 114 is a memory device including a transistor 400, a transistor 200, and a capacitor 100. The semiconductor device illustrated in FIG. One mode of a memory device is described below with reference to FIG.

FIG. 114A is a circuit diagram showing an example of the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 114B shows a cross-sectional view of a semiconductor device in which the wirings 1003 to 1010 and the like shown in FIG. 114A correspond to each other.

<Structure of storage device 2>
FIG. 114B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. FIG. In the memory device shown in FIG. 114, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

A memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided in the same layer, and the capacitor 100 is provided above the transistors 200 and 400 .

Note that as the capacitor 100 and the transistor 200, the capacitors and transistors included in the semiconductor devices and memory devices described in the above embodiments and FIGS. 112 and 113 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIG. 114 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460 a and a conductor 460 b ) functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, insulators 471 and 472 in contact with the conductor 460 . , the insulator 477 arranged on the side surface of the conductor 460 with the insulator 472 interposed therebetween, and the insulators 220, 222, 224, and 450 functioning as gate insulating layers, the channel is formed. It has an oxide 430c with regions, oxides 431a and 431b functioning as one of the source or drain, and oxides 432a and 432b functioning as the other of the source or drain. A conductor 405 functioning as a bottom gate electrode is electrically connected to a conductor 403 functioning as a wiring.

In transistor 400 , insulator 477 is in the same layer as insulator 277 .

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage Device 3>
A semiconductor device illustrated in FIG. 115 is a memory device including a transistor 300, a transistor 400, a transistor 200, and a capacitor 100. The semiconductor device illustrated in FIG. One mode of a memory device is described below with reference to FIG.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. The transistor described in any of the above embodiments can be formed with high yield even if it is miniaturized; therefore, miniaturization of the transistor 200 can be achieved. By using such a transistor in a memory device, miniaturization or high integration of the memory device can be achieved. Since the transistor described in any of the above embodiments has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

<Structure of storage device 3>

115 is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, a transistor 300, and a transistor 400. FIG. The memory device shown in FIG. 115 has the same function as the semiconductor device and the structure constituting the memory device shown in <Structure of Memory Device 1> and <Structure of Memory Device 2> in the previous embodiments. The same reference numerals are given to the structures having the same structure.

A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 , 200 and 400 .

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, capacitors and transistors included in the semiconductor devices and memory devices described in the above embodiments and FIGS. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIG. 115 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

In the memory device shown in FIG. 115, the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 275, the insulator 273, and the insulator 280 are provided with openings 500, An example of connecting 210 and insulator 282 is shown. With such a structure, the transistors 200 and 400 are surrounded by the insulator 210 and the insulator 282, and thus are less susceptible to impurities such as water and hydrogen. In addition, release of oxygen from oxides and insulators to the outside is reduced. A storage device having such a structure is preferable because it has improved reliability. Note that the opening 500 may not be provided.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

An example of the memory cell array of this embodiment is shown in FIG. By arranging the transistors 200 as memory cells in a matrix, a memory cell array can be formed.

Note that the memory device shown in FIG. 116 is a semiconductor device forming a memory cell array by arranging the memory devices shown in FIGS. 112 and 115 in matrix. Note that one transistor 400 can control bottom gate potentials of a plurality of transistors 200 . Therefore, the number of transistors 400 is preferably less than that of the transistors 200 .

Therefore, the transistor 400 shown in FIG. 115 is omitted in FIG. FIG. 116 is a cross-sectional view of part of a row when the memory devices shown in FIGS. 112 and 115 are arranged in a matrix.

116 differs from FIG. 115 in the configuration of the transistor 300. FIG. In the transistor 300 shown in FIG. 116, a semiconductor region 313 (part of the substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a Fin-type transistor because it utilizes the projections of the semiconductor substrate. Note that an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion. Further, here, the case where a part of the semiconductor substrate is processed to form a convex portion is shown, but a semiconductor film having a convex shape may be formed by processing an SOI substrate.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 14)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

Note that in one mode of the semiconductor device illustrated in FIGS. 117 to 121, structures having the same functions as those of the structures of one mode of the semiconductor device described in the above embodiment are denoted by the same reference numerals. Further, hereinafter, mainly the portions that are different from one mode of the semiconductor device described in the above embodiments are described, and the contents described in the above embodiments can be referred to for other portions. do.

<Storage Device 1>
The memory device illustrated in FIGS. 117 and 118 includes a transistor 300, a transistor 200, and a capacitor 100. FIG. 117 and 118 are cross-sectional views of the transistor 200 and the transistor 300 in the channel length direction.

<Structure of storage device 1>
A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 and 200 .

As the structure of the transistor 200, the transistor included in the semiconductor device described in the above embodiment may be used. Further, the transistor 200 illustrated in FIG. 117 is only an example, and the structure is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modified Example of Storage Device 1>
An example of a memory device according to one embodiment of the present invention is described below with reference to FIG.

118 is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 300. FIG. In the memory device shown in FIG. 118, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

The memory device shown in FIG. 118 differs from the memory device shown in <Structure of Memory Device 1> in that the cell 600 described in the previous embodiment is provided.

Specifically, the memory device shown in FIG. 118 is a cell in which part of the structure of the capacitor 100 and part of the structure of the transistor 200 are shared instead of providing the capacitor 100 and the transistor 200 independently. has 600.

With the above structure, part or all of the cell 600 and the transistor 300 overlap with each other, so that the total projected area of the memory device can be reduced. Therefore, miniaturization or high integration of the cell 600 is facilitated. Also, the process can be shortened.

<Storage device 2>
The semiconductor device shown in FIG. 119 is a memory device having transistors 400, 200, and a capacitor 100. The semiconductor device shown in FIG. One mode of a memory device is described below with reference to FIG.

FIG. 119A is a circuit diagram showing an example of the connection relationship between the transistor 200, the transistor 400, and the capacitor 100 in the semiconductor device described in this embodiment. FIG. 119B shows a cross-sectional view of a semiconductor device in which the wirings 1003 to 1010 and the like shown in FIG. 119A correspond to each other.

<Structure of storage device 2>
FIG. 119B is a cross-sectional view of a memory device including the capacitor 100, the transistor 200, and the transistor 400. FIG. In the memory device shown in FIG. 119, structures having the same functions as the structures constituting the semiconductor device and the memory device shown in the previous embodiment and <Structure of Memory Device 1> are denoted by the same reference numerals. do.

A memory device of one embodiment of the present invention includes a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided in the same layer, and the capacitor 100 is provided above the transistors 200 and 400 .

Note that as the capacitor 100 and the transistor 200, a capacitor and a transistor included in the semiconductor device and the memory device described in the above embodiment and FIGS. 117 and 118 may be used. Note that the capacitor 100, the transistor 200, and the transistor 400 illustrated in FIG. 119 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460 a and a conductor 460 b ) functioning as a top gate electrode, a conductor 405 functioning as a bottom gate electrode, insulators 470 and 472 in contact with the conductor 460 . , the insulator 475 arranged on the side surface of the conductor 460 with the insulator 472 interposed therebetween, and the insulators 220, 222, 224, and 450 functioning as gate insulating layers, the channel is formed. It has an oxide 430c with regions, oxides 431a and 431b functioning as one of the source or drain, and oxides 432a and 432b functioning as the other of the source or drain. A conductor 405 functioning as a bottom gate electrode is electrically connected to a conductor 403 functioning as a wiring.

In transistor 400 , insulator 470 is the same layer as insulator 270 . Further, the insulator 472 is the same layer as the insulator 272 .

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Storage Device 3>
A semiconductor device illustrated in FIG. 120 is a memory device including a transistor 300, a transistor 400, a transistor 200, and a capacitor 100. The semiconductor device illustrated in FIG. One mode of a memory device is described below with reference to FIG.

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor, and any of the transistors described in the above embodiments can be used. The transistor described in any of the above embodiments can be formed with high yield even if it is miniaturized; therefore, miniaturization of the transistor 200 can be achieved. By using such a transistor in a memory device, miniaturization or high integration of the memory device can be achieved. Since the transistor described in any of the above embodiments has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.

<Structure of storage device 3>

120 is a cross-sectional view of a memory device including a capacitor 100, a transistor 200, a transistor 300, and a transistor 400. FIG. Note that the memory device shown in FIG. 120 has the same functions as those of the structure constituting the semiconductor device and the memory device shown in <Structure of Memory Device 1> and <Structure of Memory Device 2> in the previous embodiments. The same reference numerals are given to the structures having the same structure.

A memory device of one embodiment of the present invention includes a transistor 300, a transistor 200, a transistor 400, and a capacitor 100 as illustrated in FIG. The transistors 200 and 400 are provided above the transistor 300 , and the capacitor 100 is provided above the transistors 300 , 200 and 400 .

Note that as the capacitor 100, the transistor 200, the transistor 300, and the transistor 400, capacitors and transistors included in the semiconductor devices and memory devices described in the above embodiments and FIGS. Note that the capacitor 100, the transistor 300, the transistor 200, and the transistor 400 illustrated in FIG. 120 are examples, and the structures thereof are not limited, and appropriate transistors may be used depending on the circuit configuration and the driving method.

In the memory device shown in FIG. 120, the insulator 212, the insulator 214, the insulator 216, the insulator 220, the insulator 222, and the insulator 280 are provided with openings 500, and the insulators 210 and 282 are connected. shows an example. With such a structure, the transistors 200 and 400 are surrounded by the insulator 210 and the insulator 282, and thus are less susceptible to impurities such as water and hydrogen. In addition, release of oxygen from oxides and insulators to the outside is reduced. A storage device having such a structure is preferable because it has improved reliability. Note that the opening 500 may not be provided.

With the use of this structure, variation in electrical characteristics can be suppressed and reliability can be improved in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, power consumption can be reduced in a semiconductor device including a transistor including an oxide semiconductor. Alternatively, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, a miniaturized or highly integrated semiconductor device can be provided with high productivity.

<Structure of memory cell array>

An example of the memory cell array of this embodiment is shown in FIG. By arranging the transistors 200 as memory cells in a matrix, a memory cell array can be formed.

Note that the memory device shown in FIG. 127 is a semiconductor device forming a memory cell array by arranging the memory devices shown in FIGS. 117 and 120 in matrix. Note that one transistor 400 can control bottom gate voltages of a plurality of transistors 200 . Therefore, the number of transistors 400 is preferably less than that of the transistors 200 .

Therefore, the transistor 400 shown in FIG. 120 is omitted in FIG. FIG. 121 is a cross-sectional view of part of a row when the memory devices shown in FIGS. 117 and 120 are arranged in a matrix.

121 differs from FIG. 120 in the configuration of the transistor 300. FIG. In the transistor 300 shown in FIG. 121, a semiconductor region 313 (part of the substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a Fin-type transistor because it utilizes the projections of the semiconductor substrate. Note that an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion. Further, here, the case where a part of the semiconductor substrate is processed to form a convex portion is shown, but a semiconductor film having a convex shape may be formed by processing an SOI substrate.

The structures, structures, methods, and the like described in this embodiment can be used in appropriate combination with the structures, structures, methods, and the like described in other embodiments and examples.

(Embodiment 15)
In this embodiment mode, an inverter circuit using the semiconductor device described in the above embodiment mode will be described. In this specification, the high power supply voltage may be called H level (or VDD), and the low power supply voltage may be called L level (or GND).

<Configuration example of inverter circuit>
A circuit INV illustrated in FIG. 122A includes a capacitor C1 and serially connected transistors M1, M2, and M3. The circuit INV has a function as an inverter circuit.

The transistors M1 to M3 are n-channel transistors. Since the circuit INV is composed only of n-channel transistors, the manufacturing cost can be reduced as compared with an inverter circuit composed of CMOS transistors.

As the transistors M1 to M3, the transistor 200 or the like included in the semiconductor device described in any of the above embodiments is preferably used.

Transistor M1 has a first gate and a second gate electrically connected together. The first gate and the second gate have regions that overlap each other with the semiconductor layer interposed therebetween. The same applies to the transistor M2 and the transistor M3. The first gate may be called a top gate, and the second gate may be called a bottom gate.

Circuit INV has terminal IN, terminal OUT, terminal CLK and terminal CLKB. The terminal IN functions as an input terminal, and the terminal OUT functions as an output terminal. A clock signal is input to the terminal CLK, and an inverted signal of the clock signal input to the terminal CLK is input to the terminal CLKB.

Also, the circuit INV is supplied with VDD and VSS as power supply voltages. VDD is a high power supply voltage and is input to the drain of transistor M1. VSS is a low power supply voltage and is input to the source of transistor M3.

In transistor M1, the top and bottom gates are electrically connected to terminal CLK, and the source is electrically connected to the drain of transistor M2.

In the transistor M2, the top gate and bottom gate are electrically connected to the terminal CLKB, and the source is electrically connected to the drain of the transistor M3.

In transistor M3, the top and bottom gates are electrically connected to terminal IN.

A first terminal of the capacitive element C1 is electrically connected to the source of the transistor M1. VSS is input to the second terminal of the capacitive element C1.

A terminal OUT is electrically connected to the source of the transistor M1, the drain of the transistor M2, and the first terminal of the capacitor C1.

Parasitic capacitance of wiring or gate capacitance of a transistor may be substituted for the capacitive element C1. In that case, the area occupied by these semiconductor devices can be reduced.

Next, the operation of the circuit INV will be described.

FIG. 122B is a timing chart for explaining the operation of the circuit INV. They respectively represent potential changes at the terminal IN, the terminal CLK, the terminal CLKB, and the terminal OUT. Further, FIG. 122B is classified into three periods of period P1, period P2, and period P3.

An H level is applied to the terminal IN during periods P1 to P3. That is, the transistor M3 is on during the periods P1 to P3.

In the period P1, the potential VH is input to the terminal CLK, and the potential VL is input to the terminal CLKB. Transistor M1 is turned on and transistor M2 is turned off. At this time, VDD is supplied to the capacitive element C1, and the capacitive element C1 starts charging (precharging).

Note that VH is preferably equal to or higher than the sum of VDD and the threshold voltage (Vth) of the transistor M1 (VDD+Vth). By doing so, VDD can be accurately transmitted to the terminal OUT. VL may be a low power supply voltage (or GND). Note that VH is sometimes called a high potential and VL is called a low potential.

In the period P2, VL is input to the terminal CLK, and VH is input to the terminal CLKB. Transistor M1 is turned off and transistor M2 is turned on. At this time, since the transistor M3 is on, the first terminal of the capacitor C1 and the source of the transistor M3 are brought into conduction, and the capacitor C1 starts discharging. Finally, the terminal OUT outputs L level. That is, the terminal OUT outputs an inverted signal of the signal input to the terminal IN.

In the period P3, VH is input to the terminal CLK, and VL is input to the terminal CLKB. Transistor M1 is turned on and transistor M2 is turned off. As in the period P1, the capacitive element C1 starts precharging again.

When the input to the terminal IN is at L level in the periods P1 to P3, the terminal OUT outputs H level in the period P2. That is, the terminal OUT outputs an inverted signal of the signal input to the terminal IN.

From the above, it can be seen that the circuit INV precharges the capacitive element C1 when the terminal CLK is at VH, and operates as an inverter circuit when the terminal CLK is at VL.

It can also be seen that the circuit INV functions as a dynamic logic circuit that operates by repeating charging and discharging of the capacitive element C1. The transistor M1 functions as a precharge transistor that charges the capacitor C1, and the transistor M2 functions as a discharge transistor that discharges the charge accumulated in the capacitor C1.

Transistors with low off-state current are preferably used as the transistors M1 to M3. As a transistor with low off-state current, a transistor using a metal oxide or an oxide semiconductor for a channel formation region (hereinafter referred to as an OS transistor) can be given. Here, the off-state current of a transistor is preferably 10 ⁻¹⁸ A/μm or less, more preferably 10 ⁻²¹ A/μm or less, and still more preferably 10 ⁻²⁴ A/μm or less. say.

By using OS transistors for the transistors M1 to M3, the circuit INV can reduce through current. As a result, the circuit INV can reduce power consumption.

Further, by using OS transistors for the transistors M1 to M3, the charge precharged in the capacitor C1 can be prevented from being lost due to leakage current. As a result, circuit INV can more accurately convey data.

By electrically connecting the top gate and the bottom gate of the transistor M1, a gate voltage can be applied to the semiconductor layer from the top gate and the bottom gate at the same time, and the on current can be increased. The same is true for transistor M2 and transistor M3. As a result, the circuit INV can realize an inverter circuit with a high operating frequency.

Circuit INV may electrically connect terminal IN to the top and bottom gates of transistor M2 and terminal CLKB to the top and bottom gates of transistor M3.

Further, a potential different from that of the top gate may be applied to the bottom gates of the transistors M1 to M3, respectively. For example, a common fixed potential may be applied to the bottom gates of the transistors M1 to M3. By doing so, the circuit INV can control the threshold voltages of the transistors M1 to M3.

Further, in the circuit INV, all the bottom gates of the transistors M1 to M3 may be omitted depending on the case. In that case, the circuit INV can simplify the manufacturing process.

As described above, the circuit INV can provide an inverter circuit configured by unipolar transistors with low power consumption. Further, an inverter circuit having a high operating frequency and including unipolar transistors can be provided.

The structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, and the like.

(Embodiment 16)
In this embodiment, with reference to FIGS. 123 to 125, a transistor using an oxide as a semiconductor (hereinafter referred to as an OS transistor) and a memory to which a capacitor is applied, according to one embodiment of the present invention. A NOSRAM will be described as an example of the device. NOSRAM (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor RAM" and refers to a RAM having gain cell type (2T type, 3T type) memory cells. Note that, hereinafter, a memory device using an OS transistor, such as a NOSRAM, may be referred to as an OS memory.

The NOSRAM employs a memory device (hereinafter referred to as "OS memory") in which OS transistors are used for memory cells. An OS memory includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the OS transistor has a very low off-current, the OS memory has excellent retention characteristics and can function as a nonvolatile memory.

<<NOSRAM1600>>
FIG. 123 shows a configuration example of the NOSRAM. A NOSRAM 1600 shown in FIG. 123 has a memory cell array 1610 , a controller 1640 , a row driver 1650 , a column driver 1660 and an output driver 1670 . The NOSRAM 1600 is a multilevel NOSRAM that stores multilevel data in one memory cell.

The memory cell array 1610 has multiple memory cells 1611, multiple word lines WWL, multiple word lines RWL, bit lines BL, and source lines SL. Word line WWL is a write word line, and word line RWL is a read word line. In the NOSRAM 1600, one memory cell 1611 stores 3-bit (8-level) data.

The controller 1640 controls the entire NOSRAM 1600 and writes data WDA[31:0] and reads data RDA[31:0]. Controller 1640 processes external command signals (eg, chip enable signals, write enable signals, etc.) to generate control signals for row drivers 1650 , column drivers 1660 and output drivers 1670 .

Row driver 1650 has the function of selecting a row to access. Row driver 1650 has row decoder 1651 and word line driver 1652 .

Column driver 1660 drives source line SL and bit line BL. The column driver 1660 has a column decoder 1661 , a write driver 1662 and a DAC (digital-analog conversion circuit) 1663 .

DAC 1663 converts 3-bit digital data into an analog voltage. The DAC 1663 converts the 32-bit data WDA[31:0] into an analog voltage every 3 bits.

The write driver 1662 has a function of precharging the source line SL, a function of making the source line SL electrically floating, a function of selecting the source line SL, and inputting a write voltage generated by the DAC 1663 to the selected source line SL. a function to precharge the bit line BL, a function to electrically float the bit line BL, and the like.

The output driver 1670 has a selector 1671 , an ADC (analog-digital conversion circuit) 1672 and an output buffer 1673 . The selector 1671 selects the source line SL to access and transmits the voltage of the selected source line SL to the ADC 1672 . The ADC 1672 has a function of converting an analog voltage into 3-bit digital data. The voltage of the source line SL is converted into 3-bit data in the ADC1672, and the output buffer 1673 holds the data output from the ADC1672.

Note that the configurations of the row driver 1650, the column driver 1660, and the output driver 1670 shown in this embodiment are not limited to the above. Depending on the configuration or driving method of memory cell array 1610, the arrangement of these drivers and the wirings connected to the drivers may be changed, or the functions of these drivers and the wirings connected to the drivers may be changed. or may be added. For example, a configuration may be adopted in which a part of the function of the source line SL is provided to the bit line BL.

Note that although the amount of information held in each memory cell 1611 is 3 bits in the above description, the structure of the memory device described in this embodiment is not limited to this. The amount of information held in each memory cell 1611 may be 2 bits or less, or may be 4 bits or more. For example, when the amount of information to be held in each memory cell 1611 is 1 bit, the DAC 1663 and ADC 1672 may be omitted.

<Memory Cells 1611 to 1614>
FIG. 124A is a circuit diagram showing a configuration example of the memory cell 1611. FIG. The memory cell 1611 is a 2T gain cell, and is electrically connected to a word line WWL, a word line RWL, a bit line BL, a source line SL, and a wiring BGL. The memory cell 1611 has a node SN, an OS transistor MO61, a transistor MP61, and a capacitor C61. The OS transistor MO61 is a write transistor. A transistor MP61 is a read transistor, and is composed of, for example, a p-channel Si transistor. Capacitive element C61 is a holding capacitor for holding the potential of node SN. A node SN is a data holding node and corresponds to the gate of the transistor MP61 here.

Since the write transistor of the memory cell 1611 is composed of the OS transistor MO61, the NOSRAM 1600 can hold data for a long time.

In the example of FIG. 124A, the bit line is a common bit line for writing and reading, but as shown in FIG. A bit line RBL may be provided that functions as a

124C to 124E show other structural examples of memory cells. FIGS. 124C to 124E show an example in which a bit line WBL for writing and a bit line RBL for reading are provided. A bit line may be provided.

A memory cell 1612 shown in FIG. 124C is a modification of the memory cell 1611, in which the reading transistor is changed to an n-channel transistor (MN61). The transistor MN61 may be an OS transistor or a Si transistor.

In the memory cells 1611 and 1612, the OS transistor MO61 may be an OS transistor without a bottom gate.

A memory cell 1613 illustrated in FIG. 124D is a 3T gain cell and is electrically connected to a word line WWL, a word line RWL, a bit line WBL, a bit line RBL, a source line SL, a wiring BGL, and a wiring PCL. there is The memory cell 1613 has a node SN, an OS transistor MO62, a transistor MP62, a transistor MP63, and a capacitor C62. The OS transistor MO62 is a write transistor. Transistor MP62 is a read transistor and transistor MP63 is a select transistor.

A memory cell 1614 shown in FIG. 124E is a modification of the memory cell 1613, in which the reading transistor and the selection transistor are changed to n-channel transistors (transistor MN62 and transistor MN63). The transistor MN62 and the transistor MN63 may be OS transistors or Si transistors.

The OS transistors provided in the memory cells 1611 to 1614 may be transistors without bottom gates or transistors with bottom gates.

Although the so-called NOR memory device in which the memory cells 1611 and the like are connected in parallel has been described above, the memory device described in this embodiment is not limited to this. For example, a so-called NAND memory device in which memory cells 1615 as shown below are connected in series may be used.

FIG. 125 is a circuit diagram showing a configuration example of a NAND type memory cell array 1610. As shown in FIG. A memory cell array 1610 shown in FIG. 125 has source lines SL, bit lines RBL, bit lines WBL, word lines WWL, word lines RWL, wirings BGL, and memory cells 1615 . The memory cell 1615 has a node SN, an OS transistor MO63, a transistor MN64, and a capacitor C63. Here, the transistor MN64 is composed of, for example, an n-channel Si transistor. The transistor MN64 is not limited to this, and may be a p-channel Si transistor or an OS transistor.

Memory cell 1615a and memory cell 1615b shown in FIG. 125 will be described below as an example. Here, a wiring connected to either the memory cell 1615a or the memory cell 1615b or a circuit element is denoted by a or b.

In the memory cell 1615a, the gate of the transistor MN64a, one of the source and drain of the OS transistor MO63a, and one of the electrodes of the capacitor C63a are electrically connected. Also, the bit line WBL and the other of the source and drain of the OS transistor MO63a are electrically connected. Also, the word line WWLa and the gate of the OS transistor MO63a are electrically connected. Further, the wiring BGLa and the bottom gate of the OS transistor MO63a are electrically connected. The word line RWLa and the other electrode of the capacitive element C63a are electrically connected.

The memory cell 1615b can be provided symmetrically with the memory cell 1615a with the contact portion with the bit line WBL as the axis of symmetry. Therefore, the circuit element included in the memory cell 1615b is also connected to the wiring in the same manner as the memory cell 1615a.

Further, the source of the transistor MN64a included in the memory cell 1615a is electrically connected to the drain of the transistor MN64b of the memory cell 1615b. The drain of transistor MN64a included in memory cell 1615a is electrically connected to bit line RBL. The source of the transistor MN64b included in the memory cell 1615b is electrically connected to the source line SL through the transistors MN64 included in the memory cells 1615b. Thus, in the NAND-type memory cell array 1610, a plurality of transistors MN64 are connected in series between the bit line RBL and the source line SL.

In the memory device having the memory cell array 1610 shown in FIG. 125, write operation and read operation are performed for each of a plurality of memory cells (hereinafter referred to as memory cell columns) connected to the same word line WWL (or word line RWL). conduct. For example, a write operation can be performed as follows. A potential at which the OS transistor MO63 is turned on is applied to the word line WWL connected to the memory cell column for writing, and the OS transistor MO63 in the memory cell column for writing is turned on. As a result, the potential of bit line WBL is applied to one of the gate of transistor MN64 and the electrode of capacitive element C63 in the specified memory cell column, and a predetermined charge is applied to the gate. Then, by turning off the OS transistor MO63 in the memory cell column, the predetermined charge applied to the gate can be held. In this manner, data can be written to the memory cells 1615 of the specified memory cell column.

Also, for example, the read operation can be performed as follows. First, a word line RWL that is not connected to a memory cell column to be read is applied with a potential that turns on the transistor MN64 regardless of the charge applied to the gate of the transistor MN64. Transistors other than MN64 are turned on. Then, a potential (read potential) is applied to the word line RWL connected to the memory cell column to be read so that the on state or off state of the transistor MN64 is selected by the charge of the gate of the transistor MN64. Then, a constant potential is applied to the source line SL, and the read circuit connected to the bit line RBL is put into an operating state. Here, since the plurality of transistors MN64 between the source line SL and the bit line RBL are in the ON state except for the memory cell column to be read, the conductance between the source line SL and the bit line RBL is It is determined by the state (on state or off state) of transistor MN64 in the memory cell column. Since the conductance of the transistor differs depending on the charge held by the gate of the transistor MN64 in the memory cell column to be read, the potential of the bit line RBL takes on a different value accordingly. By reading the potential of the bit line RBL with the reading circuit, information can be read from the memory cell 1615 in the specified memory cell column.

Since data is rewritten by charging and discharging the capacitive element C61, the capacitive element C62, or the capacitive element C63, the NOSRAM 1600 is theoretically unlimited in number of rewrites and can write and read data with low energy. In addition, since data can be held for a long time, refresh frequency can be reduced.

When the semiconductor device described in any of the above embodiments is used as the memory cell 1611, the memory cell 1612, the memory cell 1613, the memory cell 1614, and the memory cell 1615, the transistor 200 is used as the OS transistor MO61, the OS transistor MO62, and the OS transistor MO63. The capacitor 100 can be used as the elements C61, C62, and C63, and the transistor 300 can be used as the transistors MP61, MP62, MP63, MN61, MN62, MN63, and MN64. As a result, the area occupied by each set of transistor and capacitor can be reduced, so that the storage device according to this embodiment can be further highly integrated. Therefore, the storage capacity per unit area of the storage device according to this embodiment can be increased.

The structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, and the like.

(Embodiment 17)
In this embodiment, a DOSRAM will be described with reference to FIGS. 126 and 127 as an example of a memory device to which an OS transistor and a capacitor according to one embodiment of the present invention are applied. DOSRAM (registered trademark) is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. The OS memory is applied to the DOSRAM as well as the NOSRAM.

<<DOSRAM1400>>
FIG. 126 shows a configuration example of the DOSRAM. As shown in FIG. 126, DOSRAM 1400 has controller 1405, row circuit 1410, column circuit 1415, memory cell and sense amplifier array 1420 (hereinafter referred to as "MC-SA array 1420").

Row circuit 1410 has decoder 1411 , word line driver circuit 1412 , column selector 1413 and sense amplifier driver circuit 1414 . Column circuit 1415 has global sense amplifier array 1416 and input/output circuit 1417 . Global sense amplifier array 1416 has a plurality of global sense amplifiers 1447 . The MC-SA array 1420 has a memory cell array 1422, a sense amplifier array 1423, global bit lines GBLL and global bit lines GBLR.

(MC-SA array 1420)
MC-SA array 1420 has a laminated structure in which memory cell array 1422 is laminated on sense amplifier array 1423 . Global bit lines GBLL and global bit lines GBLR are stacked on the memory cell array 1422 . The DOSRAM 1400 employs a hierarchical bit line structure in which local bit lines and global bit lines are hierarchized as a bit line structure.

The memory cell array 1422 has N (N is an integer of 2 or more) local memory cell arrays 1425<0> to 1425<N−1>. A configuration example of the local memory cell array 1425 is shown in FIG. The local memory cell array 1425 has multiple memory cells 1445, multiple word lines WL, multiple bit lines BLL, and multiple bit lines BLR. In the example of FIG. 127A, the structure of the local memory cell array 1425 is of open bit line type, but may be of folded bit line type.

FIG. 127B shows a circuit configuration example of a pair of memory cells 1445a and 1445b connected to a common bit line BLL (bit line BLR). A memory cell 1445a has a transistor MW1a, a capacitor CS1a, a terminal B1a, and a terminal B2a, and is connected to a word line WLa and a bit line BLL (bit line BLR). A memory cell 1445b has a transistor MW1b, a capacitor CS1b, a terminal B1b, and a terminal B2b, which are connected to a word line WLb and a bit line BLL (bit line BLR). Note that in the following description, if either the memory cell 1445a or the memory cell 1445b is not particularly limited, the memory cell 1445 and its associated components may not be denoted by a or b.

The transistor MW1a has a function of controlling charging/discharging of the capacitive element CS1a, and the transistor MW1b has a function of controlling charging/discharging of the capacitive element CS1b. The transistor MW1a has a gate electrically connected to the word line WLa, a first terminal electrically connected to the bit line BLL (bit line BLR), and a second terminal electrically connected to the first terminal of the capacitive element CS1a. It is The gate of the transistor MW1b is electrically connected to the word line WLb, the first terminal is electrically connected to the bit line BLL (bit line BLR), and the second terminal is electrically connected to the first terminal of the capacitor CS1b. It is connected to the. Thus, the bit line BLL (bit line BLR) is commonly used for the first terminal of the transistor MW1a and the first terminal of the transistor MW1b.

The transistor MW1 has a function of controlling charging/discharging of the capacitive element CS1. A second terminal of the capacitive element CS1 is electrically connected to the terminal B2. A constant potential (for example, a low power supply potential) is input to the terminal B2.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1445a and the memory cell 1445b, the transistor 200a is used as the transistor MW1a, the transistor 200b is used as the transistor MW1b, the capacitor 100a is used as the capacitor CS1a, and the capacitor CS1b is used. 100b can be used. As a result, the area occupied by each set of transistor and capacitor can be reduced, so that the memory device according to this embodiment can be highly integrated. Therefore, the storage capacity per unit area of the storage device according to this embodiment can be increased.

Transistor MW1 has a bottom gate, which is electrically connected to terminal B1. Therefore, the threshold voltage of the transistor MW1 can be changed by the potential of the terminal B1. For example, the potential of the terminal B1 may be a fixed potential (for example, a constant negative potential), or the potential of the terminal B1 may be changed according to the operation of the DOSRAM 1400. FIG.

The bottom gate of transistor MW1 may be electrically connected to the gate, first terminal, or second terminal of transistor MW1. Alternatively, the transistor MW1 may not have a bottom gate.

The sense amplifier array 1423 has N local sense amplifier arrays 1426<0> to 1426<N−1>. The local sense amplifier array 1426 has one switch array 1444 and a plurality of sense amplifiers 1446 . A bit line pair is electrically connected to the sense amplifier 1446 . The sense amplifier 1446 has a function of precharging the bit line pair, a function of amplifying the potential difference of the bit line pair, and a function of holding this potential difference. The switch array 1444 has the function of selecting a bit line pair and making the selected bit line pair and the global bit line pair conductive.

Here, a bit line pair means two bit lines that are simultaneously compared by a sense amplifier. A global bit line pair is two global bit lines that are simultaneously compared by a global sense amplifier. A bit line pair can be called a pair of bit lines, and a global bit line pair can be called a pair of global bit lines. Here, the bit line BLL and the bit line BLR form one bit line pair. Global bit line GBLL and global bit line GBLR form one global bit line pair. Hereinafter, it will also be referred to as a bit line pair (BLL, BLR) and a global bit line pair (GBLL, GBLR).

(Controller 1405)
Controller 1405 has the function of controlling the overall operation of DOSRAM 1400 . The controller 1405 has the function of logically operating command signals input from the outside to determine the operation mode, and the function of generating control signals for the row circuit 1410 and the column circuit 1415 so that the determined operation mode is executed. , has a function of holding an externally input address signal, and a function of generating an internal address signal.

(row circuit 1410)
Row circuit 1410 has the function of driving MC-SA array 1420 . A decoder 1411 has a function of decoding an address signal. The word line driver circuit 1412 generates a selection signal for selecting the word line WL of the row to be accessed.

Column selector 1413 and sense amplifier driver circuit 1414 are circuits for driving sense amplifier array 1423 . The column selector 1413 has a function of generating a selection signal for selecting the bit line of the column to be accessed. A selection signal from the column selector 1413 controls the switch array 1444 of each local sense amplifier array 1426 . A plurality of local sense amplifier arrays 1426 are independently driven by control signals from the sense amplifier driver circuit 1414 .

(column circuit 1415)
The column circuit 1415 has a function of controlling input of data signals WDA[31:0] and a function of controlling output of data signals RDA[31:0]. Data signals WDA[31:0] are write data signals and data signals RDA[31:0] are read data signals.

A global sense amplifier 1447 is electrically connected to a global bit line pair (GBLL, GBLR). The global sense amplifier 1447 has a function of amplifying the potential difference between the global bit line pair (GBLL, GBLR) and a function of holding this potential difference. Data is written to and read from the global bit line pair (GBLL, GBLR) by an input/output circuit 1417 .

An outline of the write operation of the DOSRAM 1400 will be explained. Input/output circuit 1417 writes data to the global bit line pair. Global bit line pair data is held by global sense amplifier array 1416 . The switch array 1444 of the local sense amplifier array 1426 designated by the address signal writes the data of the global bit line pair to the bit line pair of the target column. The local sense amplifier array 1426 amplifies and holds the written data. In the designated local memory cell array 1425, the word line WL of the target row is selected by the row circuit 1410, and the data held in the local sense amplifier array 1426 is written to the memory cell 1445 of the selected row.

An outline of the read operation of the DOSRAM 1400 will be explained. One row of the local memory cell array 1425 is designated by the address signal. In the designated local memory cell array 1425, the word line WL of the target row is selected and the data of the memory cell 1445 is written to the bit line. Local sense amplifier array 1426 detects and holds the potential difference between the bit line pairs in each column as data. The switch array 1444 writes the data of the column designated by the address signal among the data held in the local sense amplifier array 1426 to the global bit line pair. Global sense amplifier array 1416 detects and holds data on global bit line pairs. Data held in the global sense amplifier array 1416 is output to the input/output circuit 1417 . The above completes the read operation.

Since data is rewritten by charging/discharging the capacitive element CS1, the DOSRAM 1400 has no restriction on the number of rewrites in principle and can write and read data with low energy. Further, since the circuit configuration of the memory cell 1445 is simple, it is easy to increase the capacity.

The transistor MW1 is an OS transistor. Since the OS transistor has extremely low off-state current, leakage of charge from the capacitor CS1 can be suppressed. Therefore, the retention time of DOSRAM 1400 is much longer than that of DRAM. Therefore, the refresh frequency can be reduced, so that the power required for the refresh operation can be reduced. Therefore, the DOSRAM 1400 is suitable for a memory device in which a large amount of data is frequently rewritten, such as a frame memory used for image processing.

Since the MC-SA array 1420 has a laminated structure, the bit lines can be shortened to the same length as the local sense amplifier array 1426 . By shortening the bit line, the bit line capacitance is reduced, and the storage capacitance of the memory cell 1445 can be reduced. Also, by providing the switch array 1444 in the local sense amplifier array 1426, the number of long bit lines can be reduced. For the above reasons, the load to be driven when accessing the DOSRAM 1400 is reduced, and power consumption can be reduced.

The structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, and the like.

(Embodiment 18)
In this embodiment, a field programmable gate array (FPGA) will be described with reference to FIGS. 128 to 131 as an example of a semiconductor device to which an OS transistor and a capacitor according to one embodiment of the present invention are applied. . In the FPGA of this embodiment, an OS memory is applied to the configuration memory and registers. Here, such an FPGA is called an "OS-FPGA".

<<OS-FPGA>>
FIG. 128A shows a configuration example of the OS-FPGA. The OS-FPGA 3110 shown in FIG. 128A is capable of NOFF (normally-off) computing that executes context switching with a multi-context structure and fine-grained power gating for each PLE. The OS-FPGA 3110 has a controller 3111 , a word driver 3112 , a data driver 3113 and a programmable area 3115 .

Programmable area 3115 has two input/output blocks (IOB) 3117 and core 3119 . The IOB3117 has multiple programmable input/output circuits. A core 3119 has a plurality of logic array blocks (LAB) 3120 and a plurality of switch array blocks (SAB) 3130 . LAB3120 has several PLE3121. FIG. 128(B) shows an example in which the LAB 3120 is composed of five PLEs 3121 . As shown in FIG. 128(C), the SAB 3130 has a plurality of switch blocks (SB) 3131 arranged in an array. LAB 3120 is connected to its own input terminal and to LAB 3120 in four directions (up, down, left, and right) via SAB 3130 .

The SB3131 will be described with reference to FIGS. 129A to 129C. SB 3131 shown in FIG. 129A receives data, datab, signal context[1:0], and signal word[1:0]. data and datab are configuration data, and data and datab have a complementary logic relationship. The number of contexts of OS-FPGA 3110 is 2, and signals context[1:0] are context selection signals. The signal word[1:0] is a word line selection signal, and the wiring to which the signal word[1:0] is input is the word line.

The SB 3131 has PRS (Programmable Routing Switch) 3133[0] and PRS 3133[1]. PRS3133[0], PRS3133[1] have configuration memory (CM) that can store complementary data. PRS3133[0] and PRS3133[1] are referred to as PRS3133 when not distinguished from each other. The same applies to other elements.

FIG. 129B shows a circuit configuration example of PRS3133[0]. PRS3133[0] and PRS3133[1] have the same circuit configuration. PRS3133[0] and PRS3133[1] differ in the input context selection signal and word line selection signal. The signal context[0] and signal word[0] are input to PRS3133[0], and the signal context[1] and signal word[1] are input to PRS3133[1]. For example, in SB3131, PRS3133[0] becomes active when signal context[0] becomes "H".

PRS3133[0] has CM3135 and Si transistor M31. Si transistor M31 is a pass transistor controlled by CM3135. The CM 3135 has a memory circuit 3137 and a memory circuit 3137B. The memory circuits 3137 and 3137B have the same circuit configuration. The memory circuit 3137 has a capacitor C31, an OS transistor MO31, and an OS transistor MO32. The memory circuit 3137B has a capacitive element CB31, an OS transistor MOB31, and an OS transistor MOB32.

When the semiconductor device described in any of the above embodiments is used for the SAB3130, the transistor 200 can be used as the OS transistor MO31 and the OS transistor MOB31, and the capacitor 100 can be used as the capacitor C31 and the capacitor CB31. As a result, it is possible to reduce the area occupied by each pair of a transistor and a capacitive element in a top view, so that the semiconductor device according to the present embodiment can be highly integrated.

The OS transistor MO31, the OS transistor MO32, the OS transistor MOB31, and the OS transistor MOB32 have bottom gates, which are electrically connected to power supply lines that supply fixed potentials.

The gate of the Si transistor M31 is the node N31, the gate of the OS transistor MO32 is the node N32, and the gate of the OS transistor MOB32 is the node NB32. Node N32 and node NB32 are charge retention nodes of CM3135. The OS transistor MO32 controls conduction between the node N31 and the signal line for the signal context[0]. The OS transistor MOB32 controls conduction between the node N31 and the low potential power supply line VSS.

The logic of data held by the memory circuits 3137 and 3137B is complementary. Therefore, either the OS transistor MO32 or the OS transistor MOB32 becomes conductive.

An operation example of PRS3133[0] will be described with reference to FIG. Configuration data has already been written to PRS3133[0], node N32 of PRS3133[0] is at "H", and node NB32 is at "L".

PRS3133[0] is inactive while signal context[0] is "L". During this period, even if the input terminal (input) of PRS3133[0] transitions to "H", the gate of the Si transistor M31 is maintained at "L", and the output terminal (output) of PRS3133[0] is also at "L". ” is maintained.

PRS3133[0] is active while the signal context[0] is "H". When the signal context[0] transitions to "H", the gate of the Si transistor M31 transitions to "H" according to the configuration data stored by the CM3135.

When the input terminal transitions to "H" while PRS3133[0] is active, the gate voltage of the Si transistor M31 rises due to boosting because the OS transistor MO32 of the memory circuit 3137 is a source follower. do. As a result, the OS transistor MO32 of the memory circuit 3137 loses its driving capability, and the gate of the Si transistor M31 becomes floating.

In PRS 3133 with multi-context function, CM 3135 also has multiplexer function.

FIG. 130 shows a configuration example of the PLE3121. PLE 3121 has lookup table block (LUT block) 3123 , register block 3124 , selector 3125 and CM 3126 . The LUT block 3123 is configured to select and output internal data according to inputs inA, inB, inC, and inD. Selector 3125 selects the output of LUT block 3123 or the output of register block 3124 according to configuration data stored by CM 3126 .

The PLE 3121 is electrically connected through a power switch 3127 to a power supply line for voltage VDD. On/off of the power switch 3127 is set by configuration data stored by the CM 3128 . Fine power gating is possible by providing a power switch 3127 in each PLE 3121 . The fine-grained power gating function enables power gating of PLEs 3121 that are not used after context switching, thus effectively reducing standby power.

To implement NOFF computing, the register block 3124 consists of non-volatile registers. The non-volatile register in the PLE3121 is a flip-flop (hereinafter referred to as [OS-FF]) with OS memory.

Register block 3124 has OS-FF 3140[1] and OS-FF 3140[2]. Signal user_res, signal load, and signal store are input to OS-FF 3140[1] and OS-FF 3140[2]. Clock signal CLK1 is input to OS-FF 3140[1], and clock signal CLK2 is input to OS-FF 3140[2]. FIG. 131A shows a configuration example of the OS-FF 3140. FIG.

OS-FF 3140 has FF 3141 and shadow register 3142 . FF3141 has node CK, node R, node D, node Q, and node QB. A clock signal is input to the node CK. A signal use_res is input to the node R. Signal user_res is a reset signal. Node D is a data input node and node Q is a data output node. Node Q and node QB have complementary logic.

Shadow register 3142 functions as a backup circuit for FF 3141 . The shadow register 3142 backs up the data of the nodes Q and QB according to the signal store, and writes back the backed up data to the nodes Q and QB according to the signal load.

Shadow register 3142 has inverter circuit 3188, inverter circuit 3189, Si transistor M37, Si transistor MB37, memory circuit 3143, and memory circuit 3143B. The memory circuits 3143 and 3143B have the same circuit configuration as the memory circuit 3137 of the PRS3133. The memory circuit 3143 has a capacitor C36, an OS transistor MO35, and an OS transistor MO36. The memory circuit 3143B has a capacitive element CB36, an OS transistor MOB35, and an OS transistor MOB36. A node N36 and a node NB36 are gates of the OS transistor MO36 and the OS transistor MOB36, and are charge retention nodes, respectively. A node N37 and a node NB37 are gates of the Si transistor M37 and the Si transistor MB37.

When the semiconductor device described in any of the above embodiments is used for the LAB 3120, the transistor 200 can be used as the OS transistor MO35 and the OS transistor MOB35, and the capacitor 100 can be used as the capacitor C36 and the capacitor CB36. As a result, it is possible to reduce the area occupied by each pair of a transistor and a capacitive element in a top view, so that the semiconductor device according to the present embodiment can be highly integrated.

The OS transistor MO35, the OS transistor MO36, the OS transistor MOB35, and the OS transistor MOB36 have bottom gates, which are electrically connected to power supply lines that supply fixed potentials.

An example of the operating method of the OS-FF 3140 will be described with reference to FIG. 131(B).

(Backup)
When the "H" signal store is input to the OS-FF 3140, the shadow register 3142 backs up the data of the FF 3141. FIG. The node N36 becomes "L" by writing the data of the node Q, and the node NB36 becomes "H" by writing the data of the node QB. Power gating is then performed to turn off the power switch 3127 . Although the data of the nodes Q and QB of the FF 3141 are lost, the shadow register 3142 retains the backup data even when the power is off.

(Recovery)
Power switch 3127 is turned on to supply power to PLE 3121 . After that, when the "H" signal load is input to the OS-FF 3140 , the shadow register 3142 writes back the backed up data to the FF 3141 . Since the node N36 is "L", the node N37 is maintained at "L", and the node NB36 is "H", so the node NB37 becomes "H". Therefore, the node Q becomes "H" and the node QB becomes "L". That is, the OS-FF 3140 returns to the state during the backup operation.

Combining fine-grained power gating with the backup/recovery operation of OS-FF 3140 can effectively reduce the power consumption of OS-FPGA 3110 .

Errors that can occur in memory circuits include soft errors due to incidence of radiation. Soft errors are secondary cosmic events caused by nuclear reactions between alpha rays emitted from materials that make up memory and packages, and primary cosmic rays that enter the atmosphere from outer space. This is a phenomenon in which a transistor is irradiated with ray neutrons, etc., and electron-hole pairs are generated, causing malfunctions such as inversion of data held in memory. An OS memory using an OS transistor has high resistance to soft errors. Therefore, by mounting the OS memory, it is possible to provide a highly reliable OS-FPGA 3110 .

The structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, and the like.

(Embodiment 19)
In this embodiment, an AI system to which the semiconductor device described in any of the above embodiments is applied will be described with reference to FIG.

FIG. 132 is a block diagram showing a configuration example of the AI system 4041. As shown in FIG. The AI system 4041 has an arithmetic unit 4010 , a control unit 4020 and an input/output unit 4030 .

The arithmetic unit 4010 has an analog arithmetic circuit 4011 , a DOSRAM 4012 , a NOSRAM 4013 and an FPGA 4014 . As the DOSRAM 4012, NOSRAM 4013 and FPGA 4014, the DOSRAM 1400, NOSRAM 1600 and OS-FPGA 3110 shown in the above embodiments can be used.

制御部４０２０は、ＣＰＵ（Ｃｅｎｔｒａｌ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉｔ）４０２１と、ＧＰＵ（Ｇｒａｐｈｉｃｓ Ｐｒｏｃｅｓｓｉｎｇ Ｕｎｉｔ）４０２２と、ＰＬＬ（Ｐｈａｓｅ Ｌｏｃｋｅｄ Ｌｏｏｐ）４０２３と、ＳＲＡＭ（Ｓｔａｔｉｃ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）４０２４と、ＰＲＯＭ（Ｐｒｏｇｒａｍｍａｂｌｅ Ｒｅａｄ Ｏｎｌｙ Ｍｅｍｏｒｙ）４０２５ , a memory controller 4026 , a power supply circuit 4027 , and a PMU (Power Management Unit) 4028 .

The input/output unit 4030 has an external storage control circuit 4031 , an audio codec 4032 , a video codec 4033 , a general purpose input/output module 4034 and a communication module 4035 .

The computing unit 4010 can perform learning or inference by a neural network.

The analog arithmetic circuit 4011 has an A/D (analog/digital) conversion circuit, a D/A (digital/analog) conversion circuit, and a sum-of-products arithmetic circuit.

The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog arithmetic circuit 4011 using OS transistors has an analog memory and can perform sum-of-products calculation required for learning or inference with low power consumption.

The DOSRAM 4012 is a DRAM formed using an OS transistor, and the DOSRAM 4012 is a memory that temporarily stores digital data sent from the CPU 4021 . The DOSRAM 4012 has memory cells including OS transistors and a read circuit section including Si transistors. Since the memory cells and the readout circuit portion can be provided in different stacked layers, the DOSRAM 4012 can reduce the overall circuit area.

Calculations using neural networks may have more than 1000 input data. When the input data is stored in the SRAM, the SRAM has a limited circuit area and a small storage capacity, so the input data must be divided and stored. The DOSRAM 4012 allows memory cells to be highly integrated even with a limited circuit area, and has a larger storage capacity than the SRAM. Therefore, the DOSRAM 4012 can efficiently store the input data.

A NOSRAM 4013 is a nonvolatile memory using an OS transistor. The NOSRAM 4013 consumes less power when writing data than other nonvolatile memories such as flash memory, ReRAM (Resistive Random Access Memory), and MRAM (Magnetoresistive Random Access Memory). In addition, unlike flash memory and ReRAM, the device does not deteriorate when data is written, and there is no limit to the number of times data can be written.

The NOSRAM 4013 can store not only 1-bit binary data but also multi-value data of 2 bits or more. By storing multilevel data, the NOSRAM 4013 can reduce the memory cell area per bit.

Also, the NOSRAM 4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 can also use the NOSRAM 4013 as an analog memory. Since the NOSRAM 4013 can store analog data as it is, it does not require a D/A conversion circuit or an A/D conversion circuit. Therefore, the NOSRAM 4013 can reduce the area of the peripheral circuit. In this specification, analog data refers to data having a resolution of 3 bits (8 values) or more. Analog data may include the multivalued data described above.

Data and parameters used for neural network calculation can be temporarily stored in the NOSRAM 4013 . Although the above data and parameters may be stored in a memory provided outside the AI system 4041 via the CPU 4021, the NOSRAM 4013 provided inside can store the above data and parameters at a higher speed and with lower power consumption. can be stored. Also, since the NOSRAM 4013 can have a longer bit line than the DOSRAM 4012, the memory capacity can be increased.

The FPGA 4014 is an FPGA using OS transistors. The AI system 4041 uses the FPGA 4014 to implement a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, and a deep Boltzmann machine (DBM), which will be described later in hardware. , Deep Belief Networks (DBNs), and other connections of neural networks can be constructed. By constructing the connection of the above neural network with hardware, it can be executed at a higher speed.

FPGA 4014 is an OS-FPGA. An OS-FPGA can have a smaller memory area than an FPGA configured with SRAM. Therefore, even if the context switching function is added, the increase in area is small. Also, the OS-FPGA can transmit data and parameters at high speed by boosting.

AI system 4041 can have analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014 on one die (chip). Therefore, the AI system 4041 can perform neural network calculations at high speed and with low power consumption. Also, the analog arithmetic circuit 4011, DOSRAM 4012, NOSRAM 4013, and FPGA 4014 can be manufactured by the same manufacturing process. Therefore, the AI system 4041 can be manufactured at low cost.

Note that the arithmetic unit 4010 does not need to have all of the DOSRAM 4012, NOSRAM 4013, and FPGA 4014. One or more of the DOSRAM 4012, NOSRAM 4013, and FPGA 4014 may be selected and provided according to the problem that the AI system 4041 wants to solve.

The AI system 4041 is a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN) can be implemented. PROM 4025 can store programs for performing at least one of these techniques. Also, part or all of the program may be stored in the NOSRAM 4013 .

Many existing programs that exist as libraries assume GPU processing. Therefore, AI system 4041 preferably has GPU 4022 . The AI system 4041 can execute rate-determining sum-of-products operations in the computing unit 4010 among sum-of-products operations used in learning and inference, and can perform other sum-of-products operations using the GPU 4022 . By doing so, learning and inference can be executed at high speed.

The power supply circuit 4027 not only generates a low power supply potential for logic circuits, but also generates a potential for analog computation. The power supply circuit 4027 may use an OS memory. The power supply circuit 4027 can reduce power consumption by storing the reference potential in the OS memory.

The PMU 4028 has the function of temporarily turning off the power supply of the AI system 4041 .

The CPU 4021 and GPU 4022 preferably have OS memories as registers. Since the CPU 4021 and the GPU 4022 have OS memories, they can continue to hold data (logical values) in the OS memories even when the power supply is turned off. As a result, the AI system 4041 can save power.

The PLL 4023 has a function of generating clocks. The AI system 4041 operates based on the clock generated by the PLL 4023 . PLL 4023 preferably has an OS memory. Since the PLL 4023 has an OS memory, it can hold an analog potential that controls the clock oscillation cycle.

The AI system 4041 may store data in external memory such as DRAM. Therefore, the AI system 4041 preferably has a memory controller 4026 that functions as an interface with an external DRAM. Also, the memory controller 4026 is preferably arranged near the CPU 4021 or the GPU 4022 . By doing so, data can be exchanged at high speed.

Part or all of the circuitry shown in control unit 4020 can be formed on the same die as arithmetic unit 4010 . By doing so, the AI system 4041 can perform neural network calculations at high speed and with low power consumption.

Data used for neural network calculations are often stored in an external storage device (HDD (Hard Disk Drive), SSD (Solid State Drive), etc.). Therefore, the AI system 4041 preferably has an external storage control circuit 4031 that functions as an interface with the external storage device.

Since learning and inference using neural networks often deal with audio and video, AI system 4041 has audio codec 4032 and video codec 4033 . The audio codec 4032 encodes (encodes) and decodes (decodes) audio data, and the video codec 4033 encodes and decodes video data.

AI system 4041 can learn or make inferences using data obtained from external sensors. Therefore, the AI system 4041 has a general purpose input/output module 4034 . The general-purpose input/output module 4034 includes, for example, USB (Universal Serial Bus) and I2C (Inter-Integrated Circuit).

AI system 4041 can perform learning or inference using data obtained via the Internet. Therefore, AI system 4041 preferably has communication module 4035 .

The analog arithmetic circuit 4011 may use a multilevel flash memory as an analog memory. However, flash memory has a limited number of times it can be rewritten. Moreover, it is very difficult to form a multilevel flash memory by embedding (forming an arithmetic circuit and a memory on the same die).

Further, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times, and has a problem in terms of storage accuracy. Furthermore, since the device has two terminals, the circuit design for separating data writing and reading becomes complicated.

Also, the analog arithmetic circuit 4011 may use an MRAM as an analog memory. However, the MRAM has a low rate of resistance change and has a problem in terms of storage accuracy.

In view of the above, the analog arithmetic circuit 4011 preferably uses an OS memory as an analog memory.

The structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, and the like.

(Embodiment 20)
<Application example of AI system>
In this embodiment, an application example of the AI system shown in the above embodiment will be described with reference to FIG.

FIG. 133(A) shows an AI system 4041A in which the AI systems 4041 described in FIG. 132 are arranged in parallel and signals can be transmitted and received between the systems via a bus line.

An AI system 4041A illustrated in FIG. 133A has a plurality of AI systems 4041_1 to 4041_n (n is a natural number). The AI systems 4041_1 to 4041_n are connected to each other via a bus line 4098 .

Also, FIG. 133(B) is an AI system 4041B in which the AI systems 4041 described in FIG. 132 are arranged in parallel in the same manner as in FIG. be.

The AI system 4041B illustrated in FIG. 133B has a plurality of AI systems 4041_1 to 4041_n. AI systems 4041_1 to 4041_n are connected to each other via a network 4099 .

The network 4099 may have a configuration in which a communication module is provided in each of the AI systems 4041_1 to 4041_n to perform wireless or wired communication. The communication module can communicate via the antenna. For example, the Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Campus Area Network), MAN (Metropolitan Area Network), WAN (Wide Area), which are the foundations of the World Wide Web (WWW). Each electronic device can be connected to a computer network such as GAN (Global Area Network) and GAN (Global Area Network) to perform communication. When performing wireless communication, LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Codes 0 Division 0 Division M0) are used as communication protocols or communication technologies. , W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark).

With the configurations of FIGS. 133A and 133B, analog signals obtained by external sensors or the like can be processed by separate AI systems. For example, like biological information, information such as brain waves, pulse, blood pressure, body temperature, etc. can be acquired by various sensors such as brain wave sensors, pulse wave sensors, blood pressure sensors, and temperature sensors, and analog signals can be processed by separate AI systems. can. By performing signal processing or learning in each of the separate AI systems, the amount of information processing per AI system can be reduced. Therefore, signal processing or learning can be performed with a smaller amount of calculation. As a result, recognition accuracy can be improved. From the information obtained by each AI system, it can be expected that changes in complexly changing biological information can be instantly and comprehensively grasped.

The structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, and the like.

(Embodiment 21)
This embodiment mode shows an example of an IC in which the AI system described in the above embodiment mode is incorporated.

The AI system shown in the above embodiment integrates a digital processing circuit made of Si transistors such as a CPU, an analog arithmetic circuit using an OS transistor, an OS-FPGA and an OS memory such as DOSRAM and NOSRAM on one die. be able to.

FIG. 134 shows an example of an IC incorporating an AI system. An AI system IC 7000 shown in FIG. 134 has leads 7001 and a circuit portion 7003 . The AI system IC 7000 is mounted on a printed circuit board 7002, for example. A plurality of such IC chips are combined and electrically connected to each other on the printed board 7002 to complete a board (mounting board 7004) on which electronic components are mounted. In the circuit portion 7003, various circuits described in the above embodiment modes are provided on one die. The circuit portion 7003 has a laminated structure as shown in the previous embodiment, and is roughly divided into a Si transistor layer 7031 , a wiring layer 7032 and an OS transistor layer 7033 . Since the OS transistor layer 7033 can be stacked on the Si transistor layer 7031, the size of the AI system IC 7000 can be easily reduced.

Although a QFP (Quad Flat Package) is applied to the package of the AI system IC 7000 in FIG. 134, the form of the package is not limited to this.

A digital processing circuit such as a CPU, an analog arithmetic circuit using an OS transistor, an OS memory such as an OS-FPGA, a DOSRAM, and a NOSRAM can all be formed in the Si transistor layer 7031, the wiring layer 7032, and the OS transistor layer 7033. can. That is, the elements constituting the AI system can be formed by the same manufacturing process. Therefore, the IC shown in this embodiment mode does not require an increase in the number of manufacturing processes even if the number of constituent elements increases, and the AI system can be incorporated at a low cost.

The structure described in this embodiment can be combined as appropriate with any of the structures described in other embodiments, examples, and the like.

(Embodiment 22)
<Electronic equipment>
A semiconductor device according to one embodiment of the present invention can be used for various electronic devices. 135 to 137 illustrate specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention.

A robot 2100 shown in FIG. 135(A) includes an arithmetic unit 2110, an illumination sensor 2101, a microphone 2102, an upper camera 2103, a speaker 2104, a display 2105, a lower camera 2106, an obstacle sensor 2107, and a movement mechanism 2108.

A microphone 2102 has a function of detecting a user's speech, environmental sounds, and the like. Also, the speaker 2104 has a function of emitting sound. Robot 2100 can communicate with a user using microphone 2102 and speaker 2104 .

The display 2105 has a function of displaying various information. Robot 2100 can display information desired by the user on display 2105 . The display 2105 may be equipped with a touch panel.

Upper camera 2103 and lower camera 2106 have the function of imaging the surroundings of robot 2100 . Further, the obstacle sensor 2107 can sense the presence or absence of an obstacle in the direction in which the robot 2100 moves forward using the movement mechanism 2108 . Robot 2100 uses upper camera 2103, lower camera 2106 and obstacle sensor 2107 to recognize the surrounding environment and can move safely.

A flying object 2120 shown in FIG. 135(B) has an arithmetic unit 2121, a propeller 2123, and a camera 2122, and has a function of flying independently.

In the flying object 2120 , the above electronic components can be used for the arithmetic device 2121 and the camera 2122 .

FIG. 135(C) is an external view showing an example of an automobile. A car 2980 has a camera 2981 and the like. In addition, the automobile 2980 includes various sensors such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile 2980 can analyze the image captured by the camera 2981, judge the surrounding traffic conditions such as the presence of pedestrians, and automatically drive.

FIG. 135(D) shows a situation in which simultaneous interpretation is performed by the portable electronic device 2130 in communication between a plurality of people speaking in different languages.

The portable electronic device 2130 has a microphone, a speaker, etc., and has a function of recognizing the user's speech and translating it into the language spoken by the other party.

Also, in FIG. 135(D), the user has a portable microphone 2131 . The portable microphone 2131 has a wireless communication function and a function of transmitting detected sound to the portable electronic device 2130 .

FIG. 136(A) is a schematic cross-sectional view showing an example of a pacemaker.

The pacemaker body 5300 has at least a battery 5301a, a battery 5301b, a regulator, a control circuit, an antenna 5304, a wire 5302 to the right atrium, and a wire 5303 to the right ventricle.

The pacemaker main body 5300 is surgically installed in the body, and two wires are passed through the subclavian vein 5305 and the superior vena cava 5306 of the human body, and one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium. be done.

Further, power can be received by the antenna 5304, and the power is charged in the batteries 5301a and 5301b, so that the pacemaker replacement frequency can be reduced. Since the pacemaker main body 5300 has a plurality of batteries, the safety is high, and even if one of them fails, the other can still function, so it also functions as an auxiliary power supply.

In addition to the antenna 5304 capable of receiving electric power, an antenna capable of transmitting physiological signals may be provided. A system may be configured to monitor various cardiac activity.

A sensor 5900 shown in FIG. 136B is attached to the human body using an adhesive pad or the like. The sensor 5900 gives a signal to an electrode 5931 or the like attached to the human body through a wiring 5932 to acquire biological information such as a heart rate and an electrocardiogram. The acquired information is transmitted to a terminal such as a reader as a radio signal.

FIG. 137 is a schematic diagram showing an example of a cleaning robot.

The cleaning robot 5100 has a display 5101 arranged on the top surface, a plurality of cameras 5102 arranged on the side surface, a brush 5103 and an operation button 5104 . Although not shown, the cleaning robot 5100 has tires, a suction port, and the like on its underside. The cleaning robot 5100 also includes various sensors such as an infrared sensor, an ultrasonic sensor, an acceleration sensor, a piezo sensor, an optical sensor, and a gyro sensor. The cleaning robot 5100 also has wireless communication means.

The cleaning robot 5100 can run by itself, detect dust 5120, and suck the dust from a suction port provided on the bottom surface.

Also, the cleaning robot 5100 can analyze the image captured by the camera 5102 and determine the presence or absence of obstacles such as walls, furniture, or steps. Further, when an object such as wiring that is likely to get entangled in the brush 5103 is detected by image analysis, the rotation of the brush 5103 can be stopped.

The display 5101 can display the remaining amount of the battery, the amount of sucked dust, and the like. The route traveled by cleaning robot 5100 may be displayed on display 5101 . Alternatively, the display 5101 may be a touch panel and the operation buttons 5104 may be provided on the display 5101 .

The cleaning robot 5100 can communicate with a portable electronic device 5140 such as a smart phone. An image captured by the camera 5102 can be displayed on the portable electronic device 5140 . Therefore, the owner of the cleaning robot 5100 can know the state of the room even from outside. In addition, the display on the display 5101 can also be checked with a portable electronic device 5140 such as a smartphone.

For example, a storage device using the semiconductor device of one embodiment of the present invention can retain control information, control programs, and the like of the above electronic devices for a long period of time. With the use of the semiconductor device of one embodiment of the present invention, a highly reliable electronic device can be achieved.

Further, for example, an IC in which the AI system is incorporated can be used in an arithmetic unit of the electronic device described above. Thus, the electronic device described in this embodiment can operate accurately according to the situation with low power consumption by the AI system.

This embodiment can be implemented in appropriate combination with structures described in other embodiments, examples, and the like.

(Embodiment 23)
<Electronic equipment>
A semiconductor device according to one embodiment of the present invention can be used for various electronic devices. 138 and 139 illustrate specific examples of electronic devices using the semiconductor device of one embodiment of the present invention.

A robot 2000 shown in FIG. 138A includes an arithmetic unit 2001, a sensor 2002, a light 2003, a lift 2004, a driving unit 2005, and a moving mechanism 2011, and can take still images and moving images while moving. Such robots can be used as security systems and surveillance systems.

The robot 2000 may further include communication means 2006, a speaker 2007, a microphone 2008, a display section 2009, a light emitting section 2010, and the like.

A semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 2001 . An IC in which the AI system according to one embodiment of the present invention is incorporated can be used for the arithmetic device 2001 . The sensor 2002 has a function as a camera that photographs the surroundings of the robot 2000 . The light 2003 can be used as a light when the sensor 2002 captures an image around the robot 2000 . Note that when the sensor 2002 captures a still image, the light 2003 preferably functions as a flashlight. Sensor 2002 is connected to the robot body via lift 2004 . The height of sensor 2002 can be adjusted by lift 2004 . Lift 2004 is preferably telescoping. Also, the lift 2004 may be of a foldable type composed of a plurality of booms. Further, since the robot 2000 is provided with the drive unit 2005 and the movement mechanism 2011 connected to the drive unit 2005, the range of imaging by the sensor 2002, that is, the range of monitoring is increased, which is preferable.

A communication unit 2006 can transmit information captured by the sensor 2002 to an administrator or a server owned by the administrator. Information picked up by the sensor 2002 is analyzed by the arithmetic unit 2001, and if it is determined that there is an emergency such as a crime, accident, or fire, the information is sent to security companies, police, fire departments, medical institutions, land and building owners. can be contacted. A speaker 2007 can transmit information around the robot, such as a warning to a criminal, a question to an injured person or a suddenly sick person, guidance for evacuation, and the like. A microphone 2008 can be used to capture sounds around the robot 2000 . Also, by using the communication means 2006 and the speaker 2007 together, the robot 2000 can function as a telephone. People around the robot 2000 can converse with the administrator or any other person. The display unit 2009 can display arbitrary information. In the event of an emergency, disaster information and evacuation routes can be displayed. Also, by using the communication means 2006, the speaker 2007, and the microphone 2008 together, the robot 2000 can function as a videophone. People around the robot 2000 can have a conversation with the administrator or any other person while looking at the display unit 2009 .

The light emitting unit 2010 can indicate the traveling direction and the stop state of the robot 2000 with characters or light. It may also indicate an emergency.

FIG. 138B is a block diagram showing the configuration of robot 2000. As shown in FIG. The arithmetic unit 2001 turns on/off the light 2003 and adjusts the brightness based on information such as images obtained by the sensor 2002 . It also adjusts the height of the lift 2004 or controls the drive unit 2005 to align the robot 2000 and sensor 2002 . Further, the operation status of the driving portion 2005 can be indicated using the light emitting portion 2010 . In addition, using the communication means 2006, the information around the robot 2000 obtained from the sensor 2002 and the microphone 2008 can be transmitted to the administrator or a server owned by the administrator. Further, information can be transmitted around the robot 2000 using the arithmetic unit 2001 or the speaker 2007 or the display unit 2009 based on the judgment of the administrator.

The light 2003 may not be provided when a sensor capable of capturing an image even in a dark environment is used as the sensor 2002 . As such a sensor, an image sensor using selenium (Se) in a light receiving portion can be used.

Such a robot 2000 can be used for security of commercial facilities and offices. Information obtained from the sensor 2002 and the microphone 2008 is stored in the arithmetic device 2001 and server. The stored information is analyzed by an AI system to determine the presence or absence of abnormalities such as lost or damaged items, intrusion by suspicious persons, and disasters such as fires. Deep learning may be used to analyze the information. When it is determined that an abnormality has occurred, the robot 2000 contacts the administrator, transmits information to the surroundings, and records the surrounding conditions.

Also, the robot 2000 may be used to monitor the growing conditions of agricultural crops. A robot 2000 installed in a rice field or a field monitors the shape, size, and color of leaves or fruits of agricultural crops using a sensor 2002 to determine whether they are diseased or have insect pests. Since the robot 2000 is provided with a moving mechanism 2011, it can monitor the growing conditions of agricultural products over a wide range. In addition, since the robot 2000 is provided with a lift 2004, it is possible to monitor leaves and fruits at arbitrary heights regardless of the type of crops or growth conditions. The monitoring results are sent to the producer using the communication means 2006, and the producer can determine the type, amount, and timing of application of fertilizers and agricultural chemicals required for crops. Also, using the computing device 2001, the monitoring results may be analyzed by an AI system to determine the type, amount, and timing of application of fertilizers and pesticides required for crops, and notify the producer. Deep learning may be used to analyze the monitoring results.

FIG. 139(A) shows a sorting system 3000 using a robot 3001. FIG. The robot 3001 has an arithmetic device 3002 , a boom 3003 and an arm 3004 . Also, the robot 3001 may be equipped with wired or wireless communication means 3011 . The sorting system 3000 also includes a housing 3008 having a sensor 3009 . Housing 3008 has communication means 3010 . Enclosure 3008 is provided in the sorting system 3000 or in the ceiling, walls, and beams (none of which are shown) of the sorting work area. Also, the housing 3008 may be provided in the robot 3001 . For example, it may be provided on boom 3003 or arm 3004 . When housing 3008 is provided in robot 3001 , information obtained by sensor 3009 may be sent to arithmetic device 3002 and processed without communication means 3010 and 3011 .

Boom 3003 is movable, and arm 3004 can be placed at a desired position. Also, the arm 3004 may be telescopic. After an arm placed on a desired article 3007 is extended to grab the desired article 3007 and the arm 3004 is retracted, the arm 3004 may be moved by the boom 3003 .

Sortation system 3000 can move items 3007 in container 3005 to container 3006 . The container 3005 and the container 3006 may have the same shape or different shapes. Also, a plurality of articles 3007 put in one container 3005 may be distributed to a plurality of containers 3006 and moved.

As containers 3005 and 3006, containers, cardboard boxes, boxes for packing products, cases, films or bags, bats for food storage, lunch boxes, and the like are used. At least one of container 3005 and container 3006 may be cooking utensils such as pots and frying pans.

A semiconductor device according to one embodiment of the present invention can be used for the arithmetic device 3002 . For the arithmetic device 3002, an IC in which the AI system according to one embodiment of the present invention is incorporated can be used.

The sensor 3009 reads the position of the container 3005 , the position of the container 3006 , the state inside the container 3005 and the article 3007 inside the container 3005 , and transmits the information to the computing device 3002 using the communication means 3010 . Information is transmitted wirelessly or by wire. Alternatively, the information may be transmitted by wire without using the communication means 3010 . Arithmetic device 3002 analyzes the transmitted information. Here, the state of the articles 3007 refers to the shape, number, overlap of the articles 3007, and the like. The computing device 3002 performs analysis based on the information from the sensor 3009 and derives detailed information on the article 3007 . The three-dimensional shape and hardness (softness) of the article 3007 are derived by comparing with the data stored in the computing device 3002 or the server that can communicate with the robot 3001 . Also, the shape of the arm 3004 can be changed according to the three-dimensional shape and hardness (softness) of the article 3007 .

Analysis using an AI system can be used to derive detailed information about the item 3007 . Deep learning may be used to analyze the information.

FIG. 139(B) shows an arm in which a pair of plates 3021 can move horizontally to sandwich an article 3007 . The article 3007 can be sandwiched by the pair of plates 3021 moving horizontally toward the center. Such an arm can grasp the article 3007 from the surface, and is suitable for grasping the article 3007 having a columnar shape such as a cube or rectangular parallelepiped. FIG. 139(C) is an arm in which a plurality of bars 3022 can move horizontally to pinch an article 3007 therebetween. A plurality of bars 3022 can move horizontally toward the center to pinch an article 3007 . Such an arm can grasp the article 3007 at a point, and is suitable for grasping an article 3007 having a spherical shape, or an article 3007 having an irregular shape, that is, an irregular-shaped article 3007 . Although the number of bars 3022 is four in FIG. 139C, this embodiment is not limited to this. The number of bars 3022 may be three, or five or more. FIG. 139(D) shows an arm capable of sandwiching an article 3007 by rotating a pair of plates 3023 about a common axis so that they approach each other. Such an arm can grasp the article 3007 on its surface, and is suitable for grasping an article 3007 having a thin film shape such as paper or film. FIG. 139(E) is an arm capable of sandwiching an article 3007 by rotating a pair of hook-shaped plates 3024 around a common axis so that the tips thereof approach each other. Such an arm can grasp the article 3007 as a point or a line, and is suitable for grasping an article 3007 having a thin film shape, such as paper or a film, or an article 3007 having a smaller granular shape. . Alternatively, as shown in FIG. 139(F), a spatula 3025 may be attached to the tip of the arm to scoop up articles 3007 having smaller granular shapes.

The arms illustrated in FIGS. 139A to 139F are examples, and one embodiment of the present invention is not limited to these shapes. Further, the description of the application of each arm is also an example, and one embodiment of the present invention is not limited to these descriptions.

Robot 3001 moves boom 3003 and moves arm 3004 onto desired article 3007 in container 3005 based on signals from computing device 3002 . In the case of a telescoping arm 3004 , extend the arm 3004 and lower the tip of the arm 3004 to the height of the article 3007 . Move the tip of the arm to grab the desired item 3007 . The arm is retracted while gripping the article 3007 . The boom 3003 is moved again to move the arm 3004 to the desired position above the container 3006 . At this time, arm 3004 may be rotated to adjust the angle of article 3007 with respect to container 3006 . Arm 3004 is extended to place item 3007 in container 3006 and arm 3004 releases item 3007 . By repeating the above operation, the robot 3001 can move the article 3007 from the container 3005 to the container 3006 .

Since the position information of the container 3005 and the container 3006 and the state of the article 3007 are analyzed using the AI system, the article 3007 can be reliably moved regardless of the shape and hardness of the article 3007 . Examples of the goods 3007 include not only goods packed in boxes or cases of any shape, such as cubes, rectangular parallelepipeds, but also molded processed foods such as eggs, hamburgers and croquettes, and amorphous vegetables such as potatoes and tomatoes. Foods such as, machine parts such as screws and nuts, and thin films such as paper and films. Since the sorting system 3000 shown in this embodiment can change the shape of the arms in consideration of the shape and hardness of the articles 3007, the articles 3007 exemplified above can be handled as containers regardless of their shape and hardness. 3005 to container 3006.

For example, a storage device using the semiconductor device of one embodiment of the present invention can retain control information, control programs, and the like of the above electronic devices for a long period of time. With the use of the semiconductor device of one embodiment of the present invention, a highly reliable electronic device can be achieved.

Further, for example, an IC in which the AI system is incorporated can be used in an arithmetic unit of the electronic device described above. Thus, the electronic device described in this embodiment can operate accurately according to the situation with low power consumption by the AI system.

This embodiment can be implemented in appropriate combination with structures described in other embodiments, examples, and the like.

In this example, changes in sheet resistance of an oxide were measured when a metal compound was formed on the oxide. The sheet resistance measuring instrument has a measurement upper limit of 6.0×10 ⁶ Ω/sq. was used. FIG. 140 shows changes in the sheet resistance of the oxide. The samples used for evaluation of changes in sheet resistance are described below.

A method for manufacturing Sample 1 will be described. A surface of a substrate containing silicon was heat-treated in a hydrogen chloride (HCl) atmosphere to form a silicon oxide film with a thickness of 100 nm on the substrate. Next, over the silicon oxide film, a 5-nm-thick oxide is formed by a sputtering method using a target of In:Ga:Zn=1:3:4 [atomic ratio], and then In:Ga :Zn=4:2:4.1 [atomic ratio] was used to form an oxide with a film thickness of 15 nm. Next, the formed oxide is subjected to heat treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, and continuously heat treatment at a temperature of 400° C. for 1 hour in an oxygen atmosphere. heat treatment was performed. When the sheet resistance of the oxide of Sample 1 was measured, it was found to be over range, and the sheet resistance of the oxide was 6.0×10 ⁶ Ω/sq. That's all it turned out to be.

Next, a method for manufacturing Sample 2 will be described. As in Sample 1, a silicon oxide film and an oxide were formed over a substrate, and first heat treatment was performed. After the first heat treatment, a metal compound with a thickness of 2 nm was formed on the oxide by a sputtering method using a target of Ti:Al=1:1 [atomic ratio] in an atmosphere containing nitrogen. The resulting metal compound contains titanium, aluminum and nitrogen and can be denoted as TiAlNx. When the sheet resistance of the oxide of sample 2 was measured, it was 3.8×10 ³ Ω/sq. Met. Forming the metal compound on the oxide reduced the sheet resistance of the oxide.

Next, a method for manufacturing Sample 3 will be described. As in Sample 2, a silicon oxide film and an oxide were formed over a substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After forming the metal compound, a second heat treatment was performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. When the sheet resistance of the oxide of sample 3 was measured, it was 2.9×10 ³ Ω/sq. Met. Compared to sample 2, the sheet resistance of the oxide in sample 3 was reduced, although there was little change in the sheet resistance of the oxide, which was reduced by the formation of the metal compound.

Next, a method for manufacturing Sample 4 will be described. As in Sample 3, a silicon oxide film and an oxide were formed over a substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After formation of the metal compound, a second heat treatment was performed. After the second heat treatment, a 20-nm-thick aluminum oxide film was formed by a sputtering method using a target containing aluminum oxide (Al ₂ O ₃ ) in an atmosphere containing argon and oxygen. It is believed that the formation of aluminum oxide provides oxygen (excess oxygen) to the oxide. Here, when oxygen is supplied to the oxide, the resistance value of the oxide increases and may approach an I-type semiconductor. When the sheet resistance of the oxide of sample 4 was measured, it was 1.9×10 ³ Ω/sq. Met. In Sample 4, the measurement of the sheet resistance of the oxide was performed after removing the aluminum oxide. In the oxide in which the sheet resistance value was reduced due to the formation of the metal compound, the sheet resistance value was not increased due to the formation of aluminum oxide. .

Next, a method for manufacturing Sample 5 will be described. As in Sample 4, a silicon oxide film and an oxide were formed over a substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After formation of the metal compound, a second heat treatment was performed. Aluminum oxide was formed after the second heat treatment. After the aluminum oxide is formed, heat treatment is performed at 400° C. for 1 hour in a nitrogen atmosphere, and then heat treatment is performed at 400° C. for 1 hour in an oxygen atmosphere. bottom. It is considered that oxygen contained in aluminum oxide diffuses into the oxide by the third heat treatment. When the sheet resistance of the oxide of sample 5 was measured, it was 1.5×10 ³ Ω/sq. Met. In sample 5, the sheet resistance of oxide was measured after aluminum oxide was removed. In the oxide whose sheet resistance value was reduced by the formation of the metal compound, the formation of aluminum oxide and the increase in the sheet resistance value due to the third heat treatment were not observed. Also, the sheet resistance value of the oxide of sample 5 was reduced compared to samples 3 and 4.

This embodiment can be implemented in appropriate combination with structures described in other embodiments, examples, and the like.

Example 1 In this example, the results of evaluating the hydrogen concentration in an oxide of a sample in which a metal compound is provided over an oxide and a metal oxide is provided over the metal compound will be described. SSDP (Substrate Side Depth Profile)-SIMS analysis was used to evaluate the hydrogen concentration.

A method for producing samples 6 and 7 used for SSDP-SIMS analysis is described below.

A method for manufacturing Sample 6 will be described. A surface of a substrate containing silicon was heat-treated in a hydrogen chloride (HCl) atmosphere to form a silicon oxide film with a thickness of 100 nm on the substrate. Next, a 50-nm-thick oxide was formed over the silicon oxide film by a sputtering method using a target of In:Ga:Zn=4:2:4.1 [atomic ratio]. Next, the formed oxide is subjected to heat treatment at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, and successively, a first heat treatment is performed at a temperature of 400° C. for 1 hour in an oxygen atmosphere. rice field. After the first heat treatment, a metal compound with a thickness of 2 nm was formed on the oxide by a sputtering method using a target of Ti:Al=1:1 [atomic ratio] in an atmosphere containing nitrogen. After forming the metal compound, a second heat treatment was performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere. After the second heat treatment, a target containing aluminum oxide (Al ₂ O ₃ ) was formed by a sputtering method in an atmosphere containing argon and oxygen to form a 20-nm-thick aluminum oxide film, whereby sample 6 was obtained.

Next, a method for manufacturing Sample 7 will be described. As in Sample 6, a silicon oxide film and an oxide were formed over a substrate, and first heat treatment was performed. After the first heat treatment, a metal compound was formed over the oxide. After formation of the metal compound, a second heat treatment was performed. Aluminum oxide was formed after the second heat treatment. After forming aluminum oxide, heat treatment was performed at 400° C. for 1 hour in a nitrogen atmosphere, and then third heat treatment was performed at 400° C. for 1 hour in an oxygen atmosphere.

FIG. 141 shows the results of detecting hydrogen by performing SSDP-SIMS analysis on samples 6 and 7 manufactured as described above. In FIG. 141, the horizontal axis represents depth (Depth) [nm], and the vertical axis represents hydrogen concentration (H concentration) [atoms/cm ³ ]. The hydrogen concentration of sample 6 is indicated by a dashed line, and the hydrogen concentration of sample 7 is indicated in practice. The background level of hydrogen concentration in this SSDP-SIMS analysis is 3.8×10 ¹⁸ atoms/cm ³ , which is indicated by the long dashed line in the graph. The SSDP-SIMS analyzes of samples 6 and 7 were carried out by digging the samples from the silicon wafer side. Further, in the SSDP-SIMS analysis of samples 6 and 7, the oxide (denoted as IGZO in the figure) was quantified and the hydrogen concentration of the oxide (IGZO) was converted. For SIMS analysis, a quadrupole mass spectrometer (ADEPT1010) manufactured by ULVAC-PHI was used. Also, the detection areas of samples 6 and 7 were set to 60 μm×60 μm.

As shown in FIG. 141, in sample 6, hydrogen is detected in the oxide (IGZO). On the other hand, in the heat-treated sample 7, the hydrogen concentration in the oxide (IGZO) is reduced, and in particular, the hydrogen concentration on the metal compound side is reduced to the background level.

As described above, in the sample in which the metal compound was provided over the oxide and the metal oxide was provided over the metal compound, the hydrogen concentration in the oxide was reduced by heat treatment. This evaluation suggested that the hydrogen in the oxide was extracted by the metal oxide through the metal compound. In other words, it was suggested that hydrogen in the oxide is extracted by the metal oxide by providing the metal oxide in the vicinity of the oxide. Such a phenomenon in which a metal oxide abstracts hydrogen from the oxide can be called gettering.

This embodiment can be implemented in appropriate combination with structures described in other embodiments, examples, and the like.

Example 1 In this example, a transistor 200A including a metal compound illustrated in FIG. 1, which is one embodiment of the present invention, was manufactured (referred to as Sample 1A), and electrical characteristics were measured.

A method for manufacturing Sample 1A will be described below.

First, a silicon oxide film having a thickness of 400 nm was formed on a p-type silicon single crystal wafer by a thermal oxidation method. A 40-nm-thick aluminum oxide film was formed as the insulator 210 over the silicon oxide film by a sputtering method.

As a conductive film to be the conductor 203, a tungsten film was formed with a thickness of 150 nm over the insulator 210 by a sputtering method. Next, a part of the conductive film was etched by lithography. Dry etching was used for the etching.

Next, as an insulating film to be the insulator 212, a silicon oxynitride film was formed with a thickness of 350 nm by a CVD method. Next, by a first CMP process, the insulating film was polished to reach the upper surface of the conductive film, thereby forming conductors 203 and insulators 212 functioning as plug electrodes and wiring layers.

Next, as the insulator 216, a silicon oxynitride film was formed with a thickness of 160 nm by a CVD method.

A tungsten film with a thickness of 35 nm was formed over the insulator 216 by a sputtering method. Next, the tungsten film was processed by lithography to form a hard mask having the tungsten film.

Next, the insulator 216 was processed by the damascene method using the hard mask to form grooves for contact holes and wiring. In the contact hole and the groove, a tantalum nitride film is formed as a conductive film to be the first conductor of the conductor 205 by a sputtering method. , a titanium nitride film is formed by ALD as a conductive film to be the second conductor of the conductor 205 , and a third conductive film of the conductor 205 is formed on the conductive film to be the second conductor of the conductor 205 . A tungsten film was formed by a CVD method as a conductive film serving as a conductor.

Next, by a second CMP process, part of the conductive film that will become the conductor 205 and the hard mask are polished until the upper surface of the insulator 216 is reached, and the conductor 205 is formed in the contact hole and the trench. Buried, plug electrodes, wiring layers, and second gate electrodes were formed.

Next, as the insulator 220, a silicon oxynitride film with a thickness of 10 nm is formed by a CVD method, and as the insulator 222, a hafnium oxide film is formed with a thickness of 10 nm by an ALD method. As 224, a silicon oxynitride film was formed with a thickness of 10 nm by a CVD method. The insulators 220, 222, and 224 function as second gate insulating films.

Next, a first heat treatment was performed. The first heat treatment was performed at a temperature of 400° C. for 1 hour in an atmosphere containing nitrogen.

Next, an oxide film 230A and an oxide film 230B were formed continuously. As the oxide film 230A, an In--Ga--Zn oxide was deposited with a thickness of 5 nm by a sputtering method. The oxide film 230A was formed using a target of In:Ga:Zn=1:3:4 [atomic ratio] under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200.degree.

As the oxide film 230B, an In--Ga--Zn oxide was deposited with a thickness of 15 nm by a sputtering method. The oxide film 230B was formed using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] under conditions of an argon gas flow rate of 40 sccm, an oxygen gas flow rate of 5 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130.degree. The film was formed at

A second heat treatment was then performed. The second heat treatment was performed in an atmosphere containing nitrogen at a temperature of 400° C. for 1 hour, and then in an atmosphere containing oxygen at a temperature of 400° C. for 1 hour.

Next, a tungsten film having a thickness of 10 nm was formed on the oxide film 230B by a sputtering method. Next, the tungsten film was processed by lithography to form a hard mask having the tungsten film.

Next, the oxide film 230B and part of the oxide film 230A were sequentially etched by lithography using the hard mask to form oxides 230a and 230b. A dry etching method was used for the etching. After that, the hard mask was removed using a dry etching method.

Next, as the oxide film 230C, an In--Ga--Zn oxide was formed with a thickness of 5 nm by a sputtering method. The oxide film 230C was formed using a target of In:Ga:Zn=1:3:4 [atomic ratio] under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200.degree.

Next, a portion of the oxide film 230C is etched by lithography to form an oxide 230c. A wet etching method was used for the etching.

Next, as the insulating film 250A, a silicon oxynitride film was formed with a thickness of 10 nm by the CVD method.

Next, as the metal oxide film 252A, an In--Ga--Zn oxide film was formed with a thickness of 10 nm by a sputtering method. The metal oxide film 252A is formed using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200°C. bottom.

Next, a titanium nitride film with a thickness of 10 nm is formed as the conductive film 260A over the metal oxide film 252A by a sputtering method, and a tungsten film is formed as the conductive film 260B over the conductive film 260A by a sputtering method. A film was formed with a film thickness of 30 nm. The conductive film 260A and the conductive film 260B were formed continuously.

Next, an aluminum oxide film was formed with a thickness of 7 nm as an insulating film 270A over the conductive film 260B by ALD.

Next, a silicon oxynitride film was formed with a thickness of 100 nm as an insulating film 271A on the insulating film 270A by a CVD method.

Next, the insulating film 271A, the insulating film 270A, the conductive film 260B, and part of the conductive film 260A are sequentially etched by lithography to remove the insulator 271, the insulator 270, and the conductor 260 (the conductor 260b and the conductor 260b). A conductor 260a) was formed. A dry etching method is used for etching the insulating film 271A, the insulating film 270A, the conductive film 260B, and the conductive film 260A.

Next, a portion of the metal oxide film 252A was etched by lithography to form the metal oxide 252 . A wet etching method was used to etch the metal oxide film 252A. Metal oxide 252 and conductor 260 function as a first gate electrode.

Next, part of the insulating film 250A was etched by lithography to form an insulator 250 functioning as a first gate insulator. A dry etching method is used for etching the insulating film 250A.

Next, as the insulating film 275A, a silicon oxynitride film was formed with a thickness of 15 nm by a CVD method.

Next, an insulator 275 was formed by etching part of the insulating film 275A. A dry etching method is used for the etching of the insulating film 275A.

Next, as the film 242A, a metal compound containing titanium, aluminum, and nitrogen (referred to as TiAlNx) was deposited with a thickness of 2 nm by a sputtering method. TiAlNx was deposited using a target of Ti:Al=1:1 [atomic ratio] under the conditions of an argon gas flow rate of 41 sccm, a nitrogen gas flow rate of 9 sccm, a pressure of 0.4 Pa, and a substrate temperature of room temperature.

A third heat treatment was then performed to form layer 242 . The third heat treatment was performed at a temperature of 400° C. for 1 hour in an atmosphere containing nitrogen.

Next, as the insulator 273, an aluminum oxide film was formed to a thickness of 10 nm by a sputtering method under the conditions of an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250.degree.

Next, a fourth heat treatment was performed. The fourth heat treatment was performed in an atmosphere containing nitrogen at a temperature of 400° C. for 1 hour, and then in an atmosphere containing oxygen at a temperature of 400° C. for 1 hour.

Next, as the insulator 274, a silicon nitride film with a thickness of 40 nm was formed by a CVD method under the conditions of a silane (SiH ₄ ) gas flow rate of 5 sccm, a nitrogen gas flow rate of 125 sccm, and a substrate temperature of 300°C.

Next, as the insulator 280, a silicon oxynitride film was formed with a thickness of 470 nm by a CVD method. Next, a third CMP treatment was performed to polish the insulator 280 and planarize the surface of the insulator 280 .

Next, an aluminum oxide film was formed as an insulator 282 on the insulator 280 by sputtering under the conditions of an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250° C. to a thickness of 40 nm. A film was formed.

Next, a fifth heat treatment was performed. The fifth heat treatment was performed at a temperature of 350° C. for 1 hour in an atmosphere containing oxygen.

Next, as an insulator 284, a silicon oxynitride film was formed with a thickness of 150 nm by a CVD method.

Next, a tungsten film with a thickness of 90 nm was formed over the insulator 284 by a sputtering method. Next, the tungsten film was processed by lithography to form a hard mask having the tungsten film.

Next, a contact hole reaching the conductor 205 or the conductor 203, a contact hole reaching the conductor 260, and a contact hole reaching the oxide 230b were formed by lithography using the hard mask.

Next, as a conductive film to be the first conductor of the conductor 240, a tungsten film is formed with a thickness of 10 nm by a sputtering method. A titanium film was formed with a thickness of 20 nm by an ALD method, and a tungsten film was formed with a thickness of 250 nm by a CVD method as a conductive film to be the third conductor of the conductor 240 .

Next, a fourth CMP process is performed to polish the conductive film to be the conductor 240 and the hard mask until the insulator 284 is reached, thereby forming a plug in which the conductor 240 is embedded in each contact hole. bottom.

Next, a first titanium film with a thickness of 20 nm, a first titanium nitride film with a thickness of 30 nm, an aluminum film with a thickness of 100 nm, and a second titanium film with a thickness of 5 nm are formed by a sputtering method. A second titanium nitride film was continuously formed to a thickness of 45 nm.

Next, the first titanium film, the second titanium nitride film, the aluminum film, the second titanium film and the second titanium nitride film were processed by lithography to form a wiring layer.

Next, a photosensitive polyimide film having a thickness of 1.6 μm was formed by a coating method, and portions of the photosensitive polyimide film that would become measurement terminals (measurement pads) were removed by a lithography method.

Finally, the photosensitive polyimide film was heat-treated at 300° C. for 1 hour.

The sample 1A was produced by the above.

Next, the electrical properties of Sample 1A were measured. Source-drain voltage (hereinafter referred to as drain voltage Vd) was set to 0.1V and 1.2V, and source-gate voltage (hereinafter referred to as gate voltage Vg) was varied from -3.3V to +3.3V. A change in the source-drain current (hereinafter referred to as drain current Id) was measured. That is, the Id-Vg characteristics were measured. The gate voltage Vg indicates the voltage of the first gate electrode (top gate electrode), and the same applies hereinafter. In this measurement, the voltage of the second gate electrode (back gate electrode) was set to 0V. In addition, in this measurement, the Id-Vg characteristics of the transistor of Sample 1A were measured. FIG. 142 shows the Id-Vg characteristics of Sample 1A.

Sample 1A was found to have transistor characteristics. Therefore, by providing a transistor with a metal compound as described in the above embodiment mode, a semiconductor device having favorable electrical characteristics can be manufactured.

This embodiment can be implemented in appropriate combination with structures described in other embodiments, examples, and the like.

Example 1 In this example, a transistor 200A including a metal compound illustrated in FIG. 1, which is one embodiment of the present invention, was manufactured (referred to as Sample 2A), and electrical characteristics were measured.

A method for manufacturing Sample 2A is described below.

First, a silicon oxide film having a thickness of 400 nm was formed on a p-type silicon single crystal wafer by a thermal oxidation method. A 40-nm-thick aluminum oxide film was formed as the insulator 210 over the silicon oxide film by a sputtering method.

As a conductive film to be the conductor 203, a tungsten film was formed with a thickness of 150 nm over the insulator 210 by a sputtering method. Next, a part of the conductive film was etched by lithography. Dry etching was used for the etching.

Next, as an insulating film to be the insulator 212, a silicon oxynitride film was formed with a thickness of 350 nm over the insulator 210 and the conductive film by a CVD method. Next, by a first CMP process, the insulating film is polished until it reaches the upper surface of the conductive film, and the conductor 203 functioning as the plug electrode, the wiring layer, and the second gate electrode, and the insulator are polished. 212 was formed.

Next, as the insulator 220, a silicon oxynitride film with a thickness of 10 nm is formed by a CVD method, and as the insulator 222, a hafnium oxide film is formed with a thickness of 10 nm by an ALD method. As 224, a silicon oxynitride film was formed with a thickness of 10 nm by a CVD method. The insulators 220, 222, and 224 function as second gate insulating films.

Next, a first heat treatment was performed. The first heat treatment was performed at a temperature of 400° C. for 1 hour in an atmosphere containing nitrogen.

Next, an oxide film 230A and an oxide film 230B were formed continuously. As the oxide film 230A, an In--Ga--Zn oxide was deposited with a thickness of 5 nm by a sputtering method. The oxide film 230A was formed using a target of In:Ga:Zn=1:3:4 [atomic ratio] under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200.degree.

As the oxide film 230B, an In--Ga--Zn oxide was deposited with a thickness of 15 nm by a sputtering method. The oxide film 230B was formed using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] under conditions of an argon gas flow rate of 40 sccm, an oxygen gas flow rate of 5 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130.degree. The film was formed at

A second heat treatment was then performed. The second heat treatment was performed in an atmosphere containing nitrogen at a temperature of 400° C. for 1 hour, and then in an atmosphere containing oxygen at a temperature of 400° C. for 1 hour.

Next, a tungsten film having a thickness of 10 nm was formed on the oxide film 230B by a sputtering method. Next, the tungsten film was processed by lithography to form a hard mask having the tungsten film.

Next, the oxide film 230B and part of the oxide film 230A were sequentially etched by lithography using the hard mask to form oxides 230a and 230b. A dry etching method was used for the etching. After that, the hard mask was removed using a dry etching method.

Next, as the oxide film 230C, an In--Ga--Zn oxide was formed with a thickness of 5 nm by a sputtering method. The oxide film 230C was formed using a target of In:Ga:Zn=1:3:4 [atomic ratio] under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200.degree.

Next, a portion of the oxide film 230C is etched by lithography to form an oxide 230c. A wet etching method was used for the etching.

Next, as the insulating film 250A, a silicon oxynitride film was formed with a thickness of 10 nm by the CVD method.

Next, as the metal oxide film 252A, an In--Ga--Zn oxide film was formed with a thickness of 10 nm by a sputtering method. The metal oxide film 252A is formed using a target of In:Ga:Zn=4:2:4.1 [atomic ratio] under conditions of an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 200°C. bottom.

Next, a titanium nitride film with a thickness of 10 nm is formed as the conductive film 260A over the metal oxide film 252A by a sputtering method, and a tungsten film is formed as the conductive film 260B over the conductive film 260A by a sputtering method. A film was formed with a film thickness of 30 nm. The conductive film 260A and the conductive film 260B were formed continuously.

Next, an aluminum oxide film was formed with a thickness of 7 nm as an insulating film 270A over the conductive film 260B by ALD.

Next, a silicon oxynitride film was formed with a thickness of 100 nm as an insulating film 271A on the insulating film 270A by a CVD method.

Next, the insulating film 271A, the insulating film 270A, the conductive film 260B, and part of the conductive film 260A are sequentially etched by lithography to remove the insulator 271, the insulator 270, and the conductor 260 (the conductor 260b and the conductor 260b). A conductor 260a) was formed. A dry etching method is used for etching the insulating film 271A, the insulating film 270A, the conductive film 260B, and the conductive film 260A.

Next, a portion of the metal oxide film 252A was etched by lithography to form the metal oxide 252 . A wet etching method was used to etch the metal oxide film 252A. Metal oxide 252 and conductor 260 function as a first gate electrode.

Next, part of the insulating film 250A was etched by lithography to form an insulator 250 functioning as a first gate insulator. A dry etching method is used for etching the insulating film 250A.

Next, as the insulating film 275A, a silicon oxynitride film was formed with a thickness of 15 nm by a CVD method.

Next, an insulator 275 was formed by etching part of the insulating film 275A. A dry etching method is used for the etching of the insulating film 275A.

Next, as the film 242A, an aluminum film having a thickness of 2 nm was formed by a sputtering method. The film 242A was formed using an AI target under conditions of an argon gas flow rate of 50 sccm, a pressure of 0.4 Pa, and a substrate temperature of room temperature.

A third heat treatment was then performed to form layer 242 . The third heat treatment was performed at a temperature of 350° C. for 1 hour in an atmosphere containing nitrogen.

Layer 242 was then removed using a wet etching method.

Next, as the insulator 273, an aluminum oxide film was formed to a thickness of 10 nm by a sputtering method under the conditions of an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250.degree.

Next, a fourth heat treatment was performed. The fourth heat treatment was performed at a temperature of 350° C. for 1 hour in an atmosphere containing oxygen.

Next, as the insulator 274, a silicon nitride film with a thickness of 40 nm was formed by a CVD method under the conditions of a silane (SiH ₄ ) gas flow rate of 5 sccm, a nitrogen gas flow rate of 125 sccm, and a substrate temperature of 300°C.

Next, as the insulator 280, a silicon oxynitride film was formed with a thickness of 470 nm by a CVD method. Next, a second CMP treatment was performed to polish the insulator 280 and planarize the surface of the insulator 280 .

Next, an aluminum oxide film was formed as an insulator 282 on the insulator 280 by sputtering under the conditions of an argon gas flow rate of 25 sccm, an oxygen gas flow rate of 25 sccm, a pressure of 0.4 Pa, and a substrate temperature of 250° C. to a thickness of 40 nm. A film was formed.

Next, a fifth heat treatment was performed. The fifth heat treatment was performed at a temperature of 350° C. for 1 hour in an atmosphere containing oxygen.

Next, as an insulator 284, a silicon oxynitride film was formed with a thickness of 150 nm by a CVD method.

Next, a tungsten film with a thickness of 90 nm was formed over the insulator 284 by a sputtering method. Next, the tungsten film was processed by lithography to form a hard mask having the tungsten film.

Next, a contact hole reaching the conductor 203, a contact hole reaching the conductor 260, and a contact hole reaching the oxide 230b were formed by lithography using the hard mask.

Next, as a conductive film to be the first conductor of the conductor 240, a tungsten film is formed with a thickness of 10 nm by a sputtering method. A titanium film was formed with a thickness of 20 nm by an ALD method, and a tungsten film was formed with a thickness of 250 nm by a CVD method as a conductive film to be the third conductor of the conductor 240 .

Next, a third CMP process is performed to polish the conductive film to be the conductor 240 and the hard mask until the insulator 284 is reached, thereby forming plugs in which the conductor 240 is embedded in each contact hole. bottom.

Next, a first titanium film with a thickness of 20 nm, a first titanium nitride film with a thickness of 30 nm, an aluminum film with a thickness of 100 nm, and a second titanium film with a thickness of 5 nm are formed by a sputtering method. A second titanium nitride film was continuously formed to a thickness of 45 nm.

Next, the first titanium film, the first titanium nitride film, the aluminum film, the second titanium film and the second titanium nitride film were processed by lithography to form a wiring layer.

Next, a photosensitive polyimide film having a thickness of 1.6 μm was formed by a coating method, and portions of the photosensitive polyimide film that would become measurement terminals (measurement pads) were removed by a lithography method.

Finally, the photosensitive polyimide film was heat-treated at 300° C. for 1 hour.

Sample 2A was produced in the above manner.

Next, the electrical properties of sample 2A were measured. Source-drain voltage (hereinafter referred to as drain voltage Vd) was set to 0.1V and 1.2V, and source-gate voltage (hereinafter referred to as gate voltage Vg) was varied from -3.3V to +3.3V. A change in the source-drain current (hereinafter referred to as drain current Id) was measured. That is, the Id-Vg characteristics were measured. The gate voltage Vg indicates the voltage of the first gate electrode (top gate electrode), and the same applies hereinafter. In this measurement, the voltage of the second gate electrode (back gate electrode) was set to 0V. Further, in this measurement, the Id-Vg characteristics of the transistor of Sample 2A were measured. FIG. 143 shows the Id-Vg characteristics of Sample 2A.

Sample 2A was found to have transistor characteristics. Therefore, by providing a transistor with a metal compound as described in the above embodiment mode, a semiconductor device having favorable electrical characteristics can be manufactured.

This embodiment can be implemented in appropriate combination with structures described in other embodiments, examples, and the like.

100: capacitive element, 100a: capacitive element, 100b: capacitive element, 110: conductor, 112: conductor, 120: conductor, 120a: conductor, 120b: conductor, 130: insulator, 150: insulator, 200: Transistor, 200a: Transistor, 200A: Transistor, 200b: Transistor, 200B: Transistor, 200C: Transistor, 200D: Transistor, 200E: Transistor, 200F: Transistor, 200G: Transistor, 200H: Transistor, 203: Conductor, 203a : Conductor 203b: Conductor 205: Conductor 205a: Conductor 205b: Conductor 207: Conductor 210: Insulator 212: Insulator 214: Insulator 216: Insulator 218 : Conductor, 220: Insulator, 222: Insulator, 224: Insulator, 224A: Insulating film, 230: Oxide, 230a: Oxide, 230A: Oxide film, 230b: Oxide, 230B: Oxide film, 230c : oxide 230C: oxide film 231: region 231a: region 231b: region 232: region 232a: region 232b: region 234: region 239: region 240: conductor 240a: conductor , 240b: Conductor, 240c: Conductor, 242: Layer, 242A: Film, 242B: Insulator, 246: Conductor, 248: Conductor, 250: Insulator, 250A: Insulating film, 252: Metal oxide, 252A: Metal oxide film, 260: Conductor, 260a: Conductor, 260A: Conductive film, 260b: Conductor, 260B: Conductive film, 270: Insulator, 270A: Insulating film, 271: Insulator, 271A: Insulating film , 272: Insulator, 272A: Insulating film, 273: Insulator, 273A: Insulating film, 274: Insulator, 275: Insulator, 275A: Insulating film, 276: Insulator, 276a: Insulator, 276b: Insulator , 277: Insulator, 277A: Insulating film, 278: Insulator, 280: Insulator, 282: Insulator, 284: Insulator, 286: Insulator, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a : low resistance region 314b: low resistance region 315: insulator 316: conductor 320: insulator 322: insulator 324: insulator 326: insulator 328: conductor 330: conductor , 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 360: Insulator, 362: Insulator, 364: Insulator, 366: Conductor, 370: Insulator, 372: Insulator , 37 4: insulator, 376: conductor, 380: insulator, 382: insulator, 384: insulator, 386: conductor, 400: transistor, 403: conductor, 405: conductor, 424: insulator, 430c : oxide, 431a: oxide, 431b: oxide, 432a: oxide, 432b: oxide, 450: insulator, 452: metal oxide, 460: conductor, 460a: conductor, 460b: conductor, 470: Insulator, 471: Insulator, 472: Insulator, 473: Insulator, 475: Insulator, 477: Insulator, 500: Opening, 600: Cell, 600a: Cell, 600b: Cell, 610: Circuit , 620: circuit, 650a: memory cell, 650b: memory cell, 1001: wiring, 1002: wiring, 1003: wiring, 1004: wiring, 1005: wiring, 1006: wiring, 1007: wiring, 1008: wiring, 1009: wiring , 1010: wiring, 1400: DOSRAM, 1405: controller, 1410: row circuit, 1411: decoder, 1412: word line driver circuit, 1413: column selector, 1414: sense amplifier driver circuit, 1415: column circuit, 1416: global sense amplifier array, 1417: input/output circuit, 1420: MC-SA array, 1422: memory cell array, 1423: sense amplifier array, 1425: local memory cell array, 1426: local sense amplifier array, 1444: switch array, 1445: memory cell, 1445a: memory cell, 1445b: memory cell, 1446: sense amplifier, 1447: global sense amplifier, 1600: NOSRAM, 1610: memory cell array, 1611: memory cell, 1612: memory cell, 1613: memory cell, 1614: memory cell, 1615: memory cell, 1615a: memory cell, 1615b: memory cell, 1640: controller, 1650: row driver, 1651: row decoder, 1652: word line driver, 1660: column driver, 1661: column decoder, 1662: driver, 1663 : DAC, 1670: Output driver, 1671: Selector, 1672: ADC, 1673: Output buffer, 2000: Robot, 2001: Arithmetic device, 2002: Sensor, 2003: Light, 2004: Lift, 2005: Actuator, 2006: Communication means, 2007: speaker, 2008: microphone, 2009: display unit, 2010: light emitting unit, 2011: transfer Movement mechanism 2100: Robot 2101: Illuminance sensor 2102: Microphone 2103: Upper camera 2104: Speaker 2105: Display 2106: Lower camera 2107: Obstacle sensor 2108: Movement mechanism 2110: Computing device 2120: Flying object, 2121: Computing device, 2122: Camera, 2123: Propeller, 2130: Portable electronic device, 2131: Portable microphone, 2980: Automobile, 2981: Camera, 3000: System, 3001: Robot, 3002: Computing device , 3003: boom, 3004: arm, 3005: container, 3006: container, 3007: article, 3008: housing, 3009: sensor, 3010: communication means, 3011: communication means, 3021: plate, 3022: bar, 3023: Board 3024: Board 3025: Spatula 3110: OS-FPGA 3111: Controller 3112: Word driver 3113: Data driver 3115: Programmable area 3117: IOB 3119: Core 3120: LAB 3121: PLE , 3123: LUT block, 3124: register block, 3125: selector, 3126: CM, 3127: power switch, 3128: CM, 3130: SAB, 3131: SB, 3133: PRS, 3135: CM, 3137: memory circuit, 3137B : memory circuit, 3140: OS-FF, 3141: FF, 3142: shadow register, 3143: memory circuit, 3143B: memory circuit, 3188: inverter circuit, 3189: inverter circuit, 4010: arithmetic unit, 4011: analog arithmetic circuit, 4012: DOSRAM; 4013: NOSRAM; 4014: FPGA; Output unit 4031: External storage control circuit 4032: Audio codec 4033: Video codec 4034: General-purpose input/output module 4035: Communication module 4041: AI system 4041_n: AI system 4041_1: AI system 4041A: AI System, 4041B: AI system, 4098: Bus line, 4099: Network, 5100: Cleaning robot, 5101: Display, 5102: Camera, 5103: Brush, 5104: Operation button 5120: Garbage 5140: Portable electronic device 5300: Pacemaker body 5301a: Battery 5301b: Battery 5302: Wire 5303: Wire 5304: Antenna 5305: Subclavian vein 5306: Superior vena cava 5900: Sensor, 5931: Electrode, 5932: Wiring, 7000: AI system IC, 7001: Lead, 7002: Printed board, 7003: Circuit part, 7004: Mounting board, 7031: Si transistor layer, 7032: Wiring layer, 7033: OS transistor layer

Claims (3)

A semiconductor device having a transistor having a metal oxide in a channel formation region and wiring,
The transistor is
a first metal oxide layer on the first insulating layer;
a second insulating layer on the first metal oxide layer;
a second metal oxide layer on the second insulating layer;
a first conductive layer on the second metal oxide layer;
a third insulating layer on the first conductive layer;
A fourth insulation having regions in contact with each of a side surface of the second insulation layer, a side surface of the second metal oxide layer, a side surface of the first conductive layer , and a side surface of the third insulation layer. layer and
a layer containing a metal element,
the first metal oxide layer has a laminated structure having a first layer, a second layer on the first layer, and a third layer on the second layer;
In a cross-sectional view in the channel length direction of the transistor, an end portion of the third layer is positioned on the second layer,
the fourth insulating layer has a region in contact with the side surface of the third layer and a region in contact with the top surface of the second layer;
In a cross-sectional view in the channel length direction of the transistor, an end portion of the second insulating layer is positioned on the second layer ,
the first conductive layer overlaps with each of the first to third layers via the second metal oxide layer and the second insulating layer ;
the layer containing the metal element has a region in contact with the fourth insulating layer and a region in contact with the upper surface of the second layer ;
The first metal oxide layer is
The channel formation region overlapping with the second insulating layer, a first region overlapping with the fourth insulating layer, and a second region overlapping with the layer containing the metal element and in contact with the first region. and
the second region has a lower oxygen concentration than the channel forming region and the first region;
the first region has a lower oxygen concentration than the channel forming region;
The semiconductor device, wherein the wiring is electrically connected to the second region. A semiconductor device having a transistor having a metal oxide in a channel formation region and wiring,
The transistor is
a first metal oxide layer on the first insulating layer;
a second insulating layer on the first metal oxide layer;
a second metal oxide layer on the second insulating layer;
a first conductive layer on the second metal oxide layer;
a third insulating layer on the first conductive layer;
A fourth insulation having regions in contact with each of a side surface of the second insulation layer, a side surface of the second metal oxide layer, a side surface of the first conductive layer , and a side surface of the third insulation layer. layer and
a layer containing a metal element,
the first metal oxide layer has a laminated structure having a first layer, a second layer on the first layer, and a third layer on the second layer;
In a cross-sectional view in the channel length direction of the transistor, an end portion of the third layer is positioned on the second layer,
the fourth insulating layer has a region in contact with the side surface of the third layer and a region in contact with the top surface of the second layer;
In a cross-sectional view in the channel length direction of the transistor, an end portion of the second insulating layer is positioned on the second layer ,
the first conductive layer overlaps with each of the first to third layers via the second metal oxide layer and the second insulating layer ;
the layer containing the metal element has a region in contact with the fourth insulating layer and a region in contact with the upper surface of the second layer ;
The second metal oxide layer has at least one selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium,
The first metal oxide layer is
The channel formation region overlapping with the second insulating layer, a first region overlapping with the fourth insulating layer, and a second region overlapping with the layer containing the metal element and in contact with the first region. and
the second region has a lower oxygen concentration than the channel forming region and the first region;
the first region has a lower oxygen concentration than the channel forming region;
The semiconductor device, wherein the wiring is electrically connected to the second region. In claim 1 or 2,
The fourth insulating layer is
The side surface of the second insulating layer, the side surface of the second metal oxide layer, the side surface of the first conductive layer, the side surface of the third insulating layer, the side surface of the third layer , and the second a third layer having regions contacting each of the top surfaces of the layer ;
a fourth layer on the third layer;
The semiconductor device, wherein the fourth layer contains more oxygen than a stoichiometric composition.

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