TW201839870A - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TW201839870A
TW201839870A TW106131634A TW106131634A TW201839870A TW 201839870 A TW201839870 A TW 201839870A TW 106131634 A TW106131634 A TW 106131634A TW 106131634 A TW106131634 A TW 106131634A TW 201839870 A TW201839870 A TW 201839870A
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contact pad
buffer layer
integrated circuit
layout
layer
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TW106131634A
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TWI706481B (zh
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辛格 葛貝夫
李智銘
林其諺
郭文昌
劉洲宗
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置的製造方法包含形成第一接觸襯墊及第二接觸襯墊在第一鈍化層上、沉積第一緩衝層在第一接觸襯墊及第二接觸襯墊上，以及沉積第二緩衝層在第一緩衝層及第二接觸襯墊上。第一接觸襯墊係在電路區域內，且第二接觸襯墊係在非電路區域內。第二接觸襯墊之邊緣係被暴露，而第一接觸襯墊之周圍及第二接觸襯墊之邊緣係被第一緩衝層覆蓋。

Description

半導體裝置的製造方法
本揭露是關於一種半導體裝置，特別是關於一種半導體結構、半導體裝置的製造方法以及設計佈局的方法。
在積體電路(Integrated Circuit，IC)裝置完成製程後，IC裝置係被封裝，以利用在例如印刷電路板(printed circuit board，PCB)上，做為大型電路的一部分。接觸襯墊(也可當作連接襯墊)係形成在內連接結構上，且係暴露在半導體晶片之表面上。電性連接係透過接觸襯墊形成，以連接半導體晶片至封裝基材或其他晶片。在一些例示中，接觸襯墊係用以引線接合(wire bonding)或覆晶接合(flip-chip bonding)。在晶圓級尺寸封裝(wafer level chip scale packaging，WLCSP)中，利用後鈍化內連接(post passivation interconnect，PPI)以連接接觸襯墊及凸塊底層金屬(under-bump metallurgy，UBM)結構。
本揭露之一態樣是關於一種半導體裝置的製造方法。方法包含形成第一接觸襯墊及第二接觸襯墊在第一鈍化層上、沉積第一緩衝層在第一接觸襯墊及第二接觸襯墊上，以及沉積第二緩衝層在第一緩衝層及第二接觸襯墊上，其中第一接觸襯墊係在電路區域內，第二接觸襯墊係在非電路區域內，第二接觸襯墊之邊緣係被暴露，且第一接觸襯墊之周圍及第二接觸襯墊之邊緣係被第一緩衝層覆蓋。
100/300‧‧‧半導體裝置
110/310‧‧‧電路區域
112/312‧‧‧組裝隔離區域
114/314‧‧‧密封環區域
116/316‧‧‧虛擬圖案區域
118/318‧‧‧切割道區域
120‧‧‧基材
122‧‧‧金屬間介電質層
124‧‧‧接觸插塞
125a‧‧‧第一密封環結構
125b‧‧‧第二密封環結構
126/326t/327a/327b‧‧‧導電線路
128‧‧‧介層窗插塞
130/330/330a/330b/330c‧‧‧介層窗插塞
140/340‧‧‧第一鈍化層
142/342‧‧‧第二鈍化層
150/154a/154b/156/350/354a/354b/356‧‧‧接觸襯墊
160/360‧‧‧第一緩衝層
162/362‧‧‧第二緩衝層
164/364/366‧‧‧邊緣
170‧‧‧後鈍化內連接結構
31‧‧‧覆蓋
32‧‧‧最大寬度
200‧‧‧方法
210‧‧‧形成第一接觸襯墊及第二接觸襯墊在第一鈍化層上，其中第一接觸襯墊係在電路區域內，且第二接觸襯墊係在非電路區域內之操作
220‧‧‧沉積第二鈍化層在第一接觸襯墊、第二接觸襯墊及第一鈍化層上之操作
230‧‧‧沉積第一高分子層，以部分覆蓋第二接觸襯墊，其中此覆蓋係自電路區域延伸至非電路區域之操作
240‧‧‧沉積第二高分子層在第一高分子層及第二接觸襯墊上之操作
400‧‧‧方法
410‧‧‧決定第一佈局圖案，其中第一佈局圖案對應至複數個接觸襯墊之操作
420‧‧‧產生第二佈局圖案之操作
430‧‧‧檢查第二佈局圖案之每一個邊緣是否與第一佈局圖案重疊之操作
440‧‧‧操作
440a‧‧‧延伸第二佈局圖案之至少一個邊緣，以與第一佈局圖案重疊之操作
440b‧‧‧延伸第一佈局圖案之接觸襯墊，以與第二佈局圖案重疊之操作
450‧‧‧輸出第一佈局圖案及第二佈局圖案之操作
500‧‧‧半導體裝置
510‧‧‧電路區域
512‧‧‧組裝隔離區域
514‧‧‧密封環區域
516‧‧‧虛擬圖案區域
518‧‧‧切割道區域
540‧‧‧第一鈍化層
542‧‧‧第二鈍化層
550/554a/554b‧‧‧接觸襯墊
554a-1/554a-2‧‧‧部分
560‧‧‧第一緩衝層
562‧‧‧第二緩衝層
564‧‧‧邊緣
570‧‧‧後鈍化內連接結構
51‧‧‧寬度
52/52a/52b/52c/52’‧‧‧方向
53‧‧‧長度
54/54’‧‧‧寬度
55‧‧‧角度
600‧‧‧系統
602‧‧‧處理器
604‧‧‧記憶體
606‧‧‧電腦程式碼
607‧‧‧指令
608‧‧‧母線
610‧‧‧輸入/輸出介面
612‧‧‧網路介面
614‧‧‧網路
616‧‧‧第n個設計規則
618‧‧‧第(n+1)個設計規則
620‧‧‧元件資料庫
622‧‧‧佈局
700‧‧‧積體電路製造系統
720‧‧‧設計廠
722‧‧‧積體電路設計
730‧‧‧光罩廠
732‧‧‧資料準備
744‧‧‧光罩製作
750‧‧‧晶圓廠
752‧‧‧晶圓
760‧‧‧積體電路裝置
根據以下詳細說明並配合附圖閱讀，使本揭露的態樣獲致較佳的理解。需注意的是，如同業界的標準作法，許多特徵並不是按照比例繪示的。事實上，為了進行清楚討論，許多特徵的尺寸可以經過任意縮放。
[圖1]係繪示根據一或多個實施例之半導體裝置的剖面視圖。
[圖2]係繪示根據一或多個實施例之半導體裝置的製造方法的流程圖。
[圖3A]至[圖3F]係繪示根據一或多個實施例之半導體裝置在各製程階段的剖面視圖。
[圖4]係繪示根據一些實施例之積體電路佈局的設計方法的流程圖。
[圖5A]係繪示根據一或多個實施例之半導體裝置的剖面視圖。
[圖5B]至[圖5E]係繪示根據一或多個實施例之接觸襯墊的上視圖。
[圖6]係繪示根據一或多個實施例之積體電路設計系統的功能方塊圖。
[圖7]係繪示根據一些實施例之積體電路製造系統及積體電路製造流程的方塊圖。
以下揭露提供許多不同實施例或例示，以實施發明的不同特徵。以下敘述之成份、數值、操作、材料、排列方式或類似者的特定例示是為了簡化本揭露。這些當然僅是做為例示，其目的不在構成限制係被考慮的。其他成份、數值、操作、材料、排列方式或類似者。舉例而言，第一特徵形成在第二特徵之上或上方的描述包含第一特徵和第二特徵有直接接觸的實施例，也包含有其他特徵形成在第一特徵和第二特徵之間，以致第一特徵和第二特徵沒有直接接觸的實施例。許多特徵的尺寸可以不同比例繪示，以使其簡化且清晰。除此之外，本揭露在各種例示中會重複元件符號及/或字母。此重複的目的是為了簡化和明確，並不表示所討論的各種實施例及/或配置之間有任何關係。
再者，空間相對性用語，例如「下方(beneath)」、「在...之下(below)」、「低於(lower)」、「在...之上(above)」、「高於(upper)」等，是為了易於描述圖式中所繪示的元素或特徵和其他元素或特徵的關 係。空間相對性用語除了圖式中所描繪的方向外，還包含元件在使用或操作時的不同方向。
積體電路(Integrated Circuit，IC)結構包含半導體晶片，半導體晶片係先彼此隔離，然後再透過內連接結構與彼此及/或其他IC結構電性耦合，以產生功能性電路，其中半導體晶片包含如電晶體及二極體的主動元件，以及如電容及電阻的被動元件。然後，一或多個鈍化層係形成在內連接結構上，以保護IC結構免於被破壞。複數個接觸襯墊(在一些例示中亦可當作係結合襯墊)係形成在鈍化層上，且係被二個應力緩衝層(stress buffer layer)所覆蓋。應力緩衝層係配置為減少封裝製程中發生的應力失配(stress mismatch)。
在晶圓級中完成完整組裝製程的封裝係稱為晶圓級尺寸封裝(wafer level chip scale packaging，WLCSP)。隨著封裝尺寸減少，由二個緩衝層之間的界面所造成的應力隨之增加。在一些實施例中，內緩衝層之邊緣係在接觸襯墊之中心部分上。在一些實施例中，接觸襯墊係在非電路區域，例如密封環區域、虛擬圖案區域或組裝隔離區域。相較於其他方法，施加在鈍化層的應力係減少約40%至約60%，進而優化IC結構的可靠性及穩定性。舉例而言，因為在鈍化層上的抗拉應力(tensile stress)被吸收，且被接觸襯墊所產生的抗壓應力(compressive stress)所補償，使得在鈍化層內發生缺陷(例如：剝離及/或破裂)的風險減少。
圖1係繪示根據一或多個實施例之半導體裝置100的剖面視圖。半導體裝置100包含電路區域110、組裝隔離區域112、密封環區域114、虛擬圖案區域116及切割道(scribe line)區域118。電路區域110包含各種電路裝置，例如被動元件或主動元件。電路裝置係形成在基材120內，且電路裝置係藉由內連線結構與彼此或其他電路電性連接，其中內連線結構係透過金屬間介電質(inter-metal dielectric，IMD)層122堆疊及設置。在一些實施例中，內連線結構包含接觸插塞124、導電線路126及/或介層窗插塞128。內連線結構包含鋁、銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、金屬矽化物、上述之組合或其他合適材料的至少一者。在一些實施例中，內連線結構更包含設置在金屬間介電層上的介層窗插塞130、以及接觸襯墊150、接觸襯墊154a、接觸襯墊154b(合稱為接觸襯墊154)及接觸襯墊156。接觸襯墊150係在電路區域110內。接觸襯墊154係在密封環區域114內。接觸襯墊156係在虛擬圖案區域116內。
以俯視平面視圖觀之，組裝隔離區域112係包圍電路區域110，且組裝隔離區域112係被密封環區域114所包圍。在一些實施例中，組裝隔離區域112係配置以提供電路區域110內的元件及密封環區域114內的元件之間的物理性及電性隔離。在至少一實施例中，組裝隔離區域112之寬度範圍為約3微米至約10微米。在一些例示中，若組裝隔離區域112之寬度太大，則晶片的佔用區域增加，導致產量較低。在一些例示中，若寬度太小，則提供給電路區域110 的物理性及電性隔離不足。
密封環區域114包含第一密封環結構125a及第二密封環結構125b，其係配置以保護電路區域110，以避免在晶圓切割及封裝製程中的濕度降解、離子性汙染及破壞。特別地，接觸襯墊154a對應至第一密封環結構125a，且接觸襯墊154b對應至第二密封環結構125b。在一些實施例中，第一密封環結構125a及第二密封環結構125b係與電路區域110內的內連線結構同時形成。在一些實施例中，電路區域110內的內連線結構及密封環區域114內的密封環結構係繞行或延伸至組裝隔離區域112內，藉以在組裝隔離區域112內形成至少一電性元件。在一些實施例中，密封環區域114具有二個以上或僅一個密封環結構。當密封環區域114具有多個密封環結構，內密封環結構(例如：第一密封環結構125a)係配置為連接被動元件，以增加抗噪度及電路區域110內裝置的隔離帶寬(isolation bandwidth)。
以俯視平面視圖觀之，虛擬圖案區域116係包圍密封環區域114，且虛擬圖案區域116係被切割道區域118包圍。在一些實施例中，虛擬圖案區域116包含虛擬長條、線端的虛設長條、角落圓化的虛設長條、虛擬襯墊及/或其他圖案。在一些實施例中，虛擬圖案區域116內的結構係利用例如雙重金屬鑲嵌技術的方法，並與電路區域110內的內連線結構同時形成。切割道區域118定義出光罩上的每一個曝光區域及晶圓上的每一個半導體晶片。在一些實施例中，切割道區域118包含每一個曝光區域的曝光區域對準標 記、每一個晶片的晶片對準標記及/或用以監控製程的待測裝置。
切割道區域118分離相鄰的半導體晶片，以考慮到鋸切製程的刀片寬度。在一些實施例中，切割道區域118不具有內連接結構。在一些實施例中，包含多個測試襯墊(通常當作是測試元件)的一或多個測試電路係在切割道區域118內，以在製程中監測物理性特徵及/或核對電性特徵。
半導體裝置100更包含第一鈍化層140、第二鈍化層142、接觸襯墊150至接觸襯墊156、第一緩衝層160及第二緩衝層162。第一鈍化層140係在最高的金屬間介電質層122上，以保護下方的內連接結構及電性裝置免於破壞及汙染。在一些實施例中，第一鈍化層140更對下方的電性裝置提供保護，以幫助防止或減少濕氣損壞、機械性破壞及輻射損壞。第二鈍化層142係在第一鈍化層140及接觸襯墊150至接觸襯墊156上。在一些實施例中，第二鈍化層142係配置以保護接觸襯墊150至接觸襯墊156免於被破壞。在一些實施例中，第二鈍化層142係配置以吸收或釋放在晶圓切割及封裝製程中的熱及/或機械壓力。
第一緩衝層160係在接觸襯墊150之周圍上，換言之，接觸襯墊150之中心部分係與後鈍化內連接(post passivation interconnect，PPI)結構170[在一些例示中，也可當作重新分佈線(redistribution line，RDL)]接觸。除此之外，第一緩衝層160係部分在接觸襯墊154a上，換言 之，第一緩衝層160之邊緣164係在接觸襯墊154a之中心部分上。在一些實施例中，第一緩衝層160自電路區域110延伸至切割道區域118。在一些實施例中，在垂直於第一鈍化層140之頂表面的方向上，邊緣164係與第一密封環結構125a之堆疊層重疊。在一些實施例中，第一緩衝層160填充第二鈍化層142內的開口。第一緩衝層160包含聚乙醯胺(polyimide，PI)、苯並環丁烯(benzocyclobutene，BCB)、聚苯並噁唑(polybenzoxazole，PBO)、環氧化合物、矽氧烷、丙烯酸酯、奈米填充酚醛樹脂(nano-filled phenolic resin)或其他合適材料之至少一者。第二緩衝層162係完全在第一緩衝層160上，並覆蓋接觸襯墊154a被第一緩衝層160暴露出的部分。除此之外，第二緩衝層162係部分在接觸襯墊154b上。在一些實施例中，第一緩衝層160及第二緩衝層162之組合係配置以做為應力失配的緩衝，其中應力失配係由於半導體晶片及基材之熱膨脹係數(coefficients of thermal expansion，CTE)不同。在一些實施例中，第一緩衝層160係配置以減少應力延伸至後鈍化內連接結構170上；而第二緩衝層162係配置以減少應力延伸至後續的結構(例如：形成在第二緩衝層162上的金屬凸塊)上。在一些實施例中，第一緩衝層160及第二緩衝層162之組合的配置更是為了結構的支撐及在封裝製程時導電凸塊的物理性間隔。
在製程中，第一緩衝層160係在熱處理下硬化。舉例而言，熱處理係在填充惰性氣體且溫度簵圍為約 200℃至約400℃的烘箱中進行。如此，在第一緩衝層160內造成抗拉應力/收縮應力。因此，相較於其他方法，施加在例如第二鈍化層142及/或第一鈍化層的下方層之應力係減少約40%至約60%，因為應力分布係分散在整個接觸襯墊154a上。
圖2係根據一或多個實施例之半導體裝置的製造方法200的流程圖。本領域中具有通常知識者應理解的是，可在圖2所述之方法200之前、之間及/或之後，進行其他的操作。根據一些實施例，以下配合圖3A至圖3F提供製程的其他細節。
方法200包含操作210，形成第一接觸襯墊(例如：圖1中的接觸襯墊154a)及第二接觸襯墊(例如：圖1中的接觸襯墊154b)在第一鈍化層(例如：圖1中的第一鈍化層140)上。第一接觸襯墊係在電路區域(例如：圖1中的電路區域110)內，且第二接觸襯墊係在非電路區域(例如：圖1中的密封環區域114、虛擬圖案區域116或組裝隔離區域112)內。在一些實施例中，第一鈍化層係形成在內連接結構之最上方的導電線路及相應的金屬間介電質層上。在一些實施例中，第一鈍化層具有之介電常數κ係大於3.9。在一些實施例中，第一鈍化層係包含氧化矽膜及氮氧化矽膜的複合層。在一些實施例中，第一鈍化層包含非孔洞性介電材料，例如未摻雜矽玻璃(undoped silicate glass，USG)、氟矽玻璃(fluorinated silicate glass，FSG)、氮化矽、上述之組合或其他合適的材料。第一鈍化層係利用沉積製程所 形成，其中沉積製程可例如化學氣相沉積法(chemical vapor deposition，CVD)、電漿輔助化學氣相沉積法(plasma-enhanced chemical vapor deposition，PECVD)或高密度電漿化學氣相沉積法(high density plasma chemical vapor deposition，HDPCVD)、旋轉塗佈或其他合適的製程。在一些實施例中，第一鈍化層之厚度範圍為約500奈米至約1200奈米。在一些例示中，較厚的第一鈍化層增加製程成本，但不具有益處。在一些例示中，較薄的第一鈍化層提供的緩衝不足以減少應力失配。
第一接觸襯墊及第二接觸襯墊係形成在第一鈍化層上，且係電性連接對應的下方內連接結構。第一接觸襯墊及第二接觸襯墊係與對應之形成在第一鈍化層內的介層窗插塞電性接觸。在各種實施例中，第一接觸襯墊及第二接觸襯墊之上部分形成凹陷，其中凹陷係突出且對準下方的介層窗插塞。另外，第一接觸襯墊及第二接觸襯墊係與對應的內連接結構之最上方的導電線路直接接觸。在一些實施例中，第一接觸襯墊及第二接觸襯墊包含鋁、銅、鋁-銅、上述之組合或其他合適的導電材料。在一些實施例中，第一接觸襯墊及第二接觸襯墊的形成包含沉積製程、微影製程及蝕刻製程。沉積製程包含蒸鍍、物理氣相沉積法(physical vapor deposition，PVD)、化學氣相沉積法、原子層沉積法(atomic layer deposition，ALD)、無電式電鍍法(electroless plating)或其他合適的製程。在第一鈍化層包含暴露最上方之導電線路的開口之一些實施例中，沉積製程 填充開口以形成電性連接。蝕刻製程包含濕式蝕刻、乾式蝕刻或上述之組合。在一些實施例中，第一接觸襯墊及第二接觸襯墊之厚度範圍為約50奈米至約10微米。在一些例示中，較厚的接觸襯墊增加填充第二鈍化層的風險。在一些例示中，較薄的接觸襯墊增加在後續後鈍化內連接製程中被破壞的風險。
方法200繼續至操作220，沉積第二鈍化層(例如：在圖1中的第二鈍化層142)在第一接觸襯墊、第二接觸襯墊及第一鈍化層上。第二鈍化層係形成在第一鈍化層、第一接觸襯墊及第二接觸襯墊上。在一些實施例中，形成第二鈍化層與第一鈍化層係利用相同的製程，例如電漿輔助化學氣相沉積法。在一些實施例中，形成第二鈍化層與第一鈍化層係利用不同的製程，舉例而言，沉積第二鈍化層係利用高密度電漿化學氣相沉積法，而沉積第一鈍化層係利用電漿輔助化學氣相沉積。在一些實施例中，第二鈍化層與第一鈍化層包含相同材料。在一些實施例中，第二鈍化層與第一鈍化層包含不同材料。在一些實施例中，為了與後續後鈍化內連接結構形成電性連接，施加微影製程及蝕刻製程，選擇性地圖案化第二鈍化層，以暴露出第一接觸襯墊或第二接觸襯墊之至少一者。後鈍化內連接結構係配置以提供導電路徑給電路及半導體裝置之輸入/輸出線端，例如導電凸塊。在各種實施例中，後鈍化內連接結構包含鋁、銅、銅合金或其他合適的導電材料，且係利用蒸鍍、物理氣相沉積法、化學氣相沉積法、無電式電鍍或其他合適的製程所沉積。
方法200繼續進行操作230，沉積第一高分子層(例如：圖1中的第一緩衝層160)，以部分覆蓋第二接觸襯墊，其中此覆蓋係自電路區域延伸至非電路區域。第一高分子層係利用例如旋轉塗佈或其他合適製程的沉積製程形成在第二鈍化層上。第一高分子層的邊緣係位於第二接觸襯墊之中心部分上。在一些實施例中，第二接觸襯墊係在密封環區域內。在一些實施例中，第二接觸襯墊係在虛擬圖案區域內。在一些實施例中，第二接觸襯墊係在組裝隔離區域內。當半導體晶片具有矩形外觀，在一些實施例中，第一高分子層之每一個邊緣係在相同或不同區域內。舉例而言，第一高分子層之一邊緣係在密封環區域內的一第二接觸襯墊上，而第一高分子層的另一邊緣係在組裝隔離區域內的另一第二接觸襯墊上。以密封環區域包含多個密封環結構的另一具體例而言，第一高分子層之一邊緣係在對應密封環結構之一第二接觸襯墊上，而第一高分子層之另一邊緣係在對應另一密封環結構之另一第二接觸襯墊上。以另一具體例而言，第一高分子層的每一個邊緣係在密封環區域內或組裝隔離區域內。第一高分子層係利用沉積製程所形成，例如旋轉塗佈、乾膜疊層製程(dry film lamination process)或其他合適的製程。在一些實施例中，第一高分子層係以液態形式配製，並利用硬化製程(例如：熱處理)被硬化。在一些實施例中，熱處理係在約200℃至約400℃的溫度範圍下進行。根據一些例示，硬化製程係持續約1分鐘至約90分鐘。在一些實施例中，硬化製程係進行超過90分鐘。在一些實施例中， 第一高分子層係利用微影製程及蝕刻製程被圖案化，以暴露出後鈍化內連接結構之至少一部分。
方法200繼續進行操作240，沉積第二高分子層(例如：圖1中的第二緩衝層162)在第一高分子層及第二接觸襯墊上。第二高分子層包含聚乙醯胺、苯並環丁烯、聚苯並噁唑、環氧化合物、矽氧烷、丙烯酸酯或其他合適材料之至少一者。在一些實施例中，第二高分子層的沉積包含旋轉塗佈、乾膜疊層製程或其他合適的製程。在各種實施例中，覆蓋接觸襯墊的第二高分子層之一部分突出至形成在接觸襯墊之上部分的凹陷。第二高分子層之一部分係藉由微影製程及蝕刻製程被移除。在一些實施例中，移除製程包含雷射製程或利用樣板固定夾。在一些實施例中，形成第二高分子層與第一高分子層係利用相同的製程。在一些實施例中，形成第二高分子層係利用不同的製程。在一些實施例中，額外的操作係包括在方法200中，例如：在操作240之後，形成凸塊下金屬(under bump metal，UBM)結構在第二高分子層上。在一些實施例中，第二高分子層係以液態形式配製，並利用硬化製程(例如：熱處理)被硬化。在一些實施例中，熱處理係在約200℃至約400℃的溫度範圍下進行。根據一些例示，硬化製程係持續約1分鐘至約90分鐘。在一些實施例中，硬化製程係進行超過90分鐘。在一些實施例中，第二高分子層的硬化製程及第一高分子層的硬化製程係在單一步驟中進行。在一些實施例中，每一個硬化製程係獨立進行。
圖3A至圖3F係根據一或多個實施例之在製程各階段中半導體裝置300的剖面視圖。半導體裝置300包含類似半導體裝置100的元件，且相似元件的最後二位數字為相同。圖3A為進行操作210後的半導體裝置300的剖面視圖。從半導體晶片的中心至邊界，半導體裝置300包含電路區域310、組裝隔離區域312、密封環區域314、虛擬圖案區域316及切割道區域318。電路區域310包含形成在最高的導電線路326t上的第一鈍化層340，其係做為物理性隔離及結構性支撐。在一些實施例中，第一鈍化層340包含無機絕緣材料，例如：氧化矽、氮化矽、氮氧化矽或碳氮化矽，或有機絕緣材料，例如：聚乙醯胺、苯並環丁烯、聚苯並噁唑或環氧化合物。複數個開口係利用微影製程及蝕刻製程形成在第一鈍化層340內，藉以暴露出最高的導電線路326t之一部分。接觸襯墊350係透過介層窗插塞330電性連接最高的導電線路326t。在一些實施例中，接觸襯墊350包含鋁、銅、鋁-銅、金、錫、鎳或其他導電材料。在密封環區域314內，接觸襯墊354a及接觸襯墊354b係以類似方法形成在接觸襯墊350上。接觸襯墊354a係電性連接第一密封環結構之最高的導電線路327a，而接觸襯墊354b係電性連接第二密封環結構之最高的導電線路327b。在一些實施例中，以俯視平面視圖觀之，接觸襯墊354a係被第一密封環結構之邊界包圍。在一些實施例中，以俯視平面視圖觀之，接觸襯墊354a係自第一密封環結構之邊界向外突出。
圖3B為進行操作220後的半導體裝置300的剖 面視圖。第二鈍化層342係在第一鈍化層340、接觸襯墊350、接觸襯墊354a及接觸襯墊354b上。在一些實施例中，第二鈍化層342包含無機絕緣材料，例如：氧化矽、氮化矽、氮氧化矽或碳氮化矽，或有機絕緣材料，例如：聚乙醯胺、苯並環丁烯、聚苯並噁唑或環氧化合物。在一些實施例中，第二鈍化層342與第一鈍化層340包含相同的材料。在一些實施例中，第二鈍化層342與第一鈍化層340包含不同的材料。
圖3C為進行操作230後的半導體裝置300的剖面視圖。第一緩衝層360係在第二鈍化層342、接觸襯墊350及接觸襯墊354a上。在一些實施例中，為了給後鈍化內連接結構暴露出接觸襯墊350之中心部分，開口係形成在第一緩衝層360內。第一緩衝層360之邊緣364係在接觸襯墊354a上，即第一緩衝層360的覆蓋係自電路區域310延伸至密封環區域314。在一些實施例中，第一緩衝層360在接觸襯墊354a上的覆蓋31範圍為接觸襯墊354a之最大寬度32的約25%至約75%。在一些例示中，較大或較小的比例改變第一緩衝層360施加在第二鈍化層342的應力。在一些實施例中，，覆蓋31為最大寬度32的約50%。在一些實施例中，第一緩衝層360之邊緣364係對準介層窗插塞330a之中心部分，其中介層窗插塞330a連接接觸襯墊354a。在一些實施例中，第一緩衝層360之邊緣364係對準最高的導電線路327a之中心部分。
圖3D為進行操作240後的半導體裝置300的剖 面視圖。第二緩衝層362係在第一緩衝層360上。特別地，第二緩衝層362覆蓋邊緣364。第二緩衝層362之邊緣366係對準介層窗插塞330b之中心部分，其中介層窗插塞330a連接接觸襯墊354b。在一些實施例中，第二緩衝層362之邊緣366係對準最高的導電線路327b之中心部分。
圖3E為進行操作240後的半導體裝置300的另一剖面視圖。相較於圖3D，第一緩衝層360之邊緣364係在密封環區域314內，且在接觸襯墊354b上。在密封環區域314包含第三密封環結構的一些實施例中，邊緣364係在接觸襯墊354b上，其中接觸襯墊354b係在第三密封環結構上。在一些實施例中，接觸襯墊354b被第一緩衝層360覆蓋之範圍為接觸襯墊354b之最大寬度的約25%至約75%。在半導體裝置300包含形成在密封環區域314內之第三密封環結構的一些實施例中，邊緣364係以一數量範圍覆蓋第三密封環結構之接觸襯墊，且此數量範圍係相似於接觸襯墊354b所述之數量範圍。
圖3F為進行操作240後的半導體裝置300的再一剖面視圖。相較於圖3D，第一緩衝層360之邊緣364係在虛擬圖案區域316內，且係在接觸襯墊356上。在一些實施例中，接觸襯墊356被第一緩衝層360覆蓋之範圍為接觸襯墊356之最大寬度的約25%至約75%。
圖4係根據一些實施例之設計積體電路佈局的方法400的流程圖。本領域中具有通常知識者應理解的是，可在圖4所述之方法400之前、之間及/或之後，進行其他的 操作。根據一些實施例，以下配合圖5A至圖5E提供製程的其他細節。
方法400包含操作410，決定第一佈局圖案，其中第一佈局圖案對應至複數個接觸襯墊，例如圖1中的接觸襯墊154a、接觸襯墊154b及接觸襯墊156。在一些實施例中，第一佈局圖案對應至排列在相同區域(例如：密封環區域及虛擬圖案區域)的接觸襯墊。佈局圖案包含形成在半導體晶片上的多角形或開口。第一佈局圖案係藉由電子設計自動化(electronic design automation，EDA)工具所產生，其中電子設計自動化工具可例如Synopsis®的Synphony、Cadence Systems®的Virtuoso及Mentor Graphics®的IC station。佈局資料係藉由電腦可讀取媒體利用標準佈局格式(例如GDSII)所提供。在一些實施例中，當方法係藉由電子設計自動化系統執行時，佈局資料係透過軟體介面所提供。方法400接著進行操作420，產生第二佈局圖案。第二佈局圖案對應至緩衝層，例如圖1中的第一緩衝層160。
在操作430中，檢查第二佈局圖案之每一個邊緣是否與第一佈局圖案重疊。在一些實施例中，裝載設計規則手冊(Design Rule Manual，DRM)及執行設計審查驗證(Design Review Check，DRC)。設計規則手冊係包含一或複數個設計規則的檔案，其中設計規則係包含積體電路設計者在電路設計時遵守的限制。在一些實施例中，一或多個設計規則係光罩製造者使用的一系列參數，其係可使設計者 核對光罩組的正確性。設計審查驗證係用以描述圖案特徵及產生違規位置的標示，其中違規位置的標示包含從所選擇設計規則手冊接收所選擇之特徵相關的圖案及通路。若第二佈局圖案之每一個邊緣未與第一佈局圖案重疊，則一或多個錯誤標示係呈現在設計審查驗證的輸出檔案，且使用者或處理器提供第一佈局圖案或第二佈局圖案調整的選擇。
如自操作430中以「否」的箭頭所指示，若操作430的檢查未通過，即第二佈局圖案之至少一個邊緣與第一佈局圖案未重疊(分開)，則方法400繼續進行操作440，調整第二佈局圖案或第一佈局圖案之至少一者，以使第二佈局圖案之每一個邊緣與第一佈局圖案重疊。操作440包含選擇性的操作440a，延伸第二佈局圖案之至少一個邊緣，以與第一佈局圖案重疊；以及選擇性操作440b，延伸第一佈局圖案之接觸襯墊，以與第二佈局圖案重疊。以下利用圖5A至圖5E詳細討論選擇性操作440a的各種實施例。在一些實施例中，當進行選擇性操作440b，延伸的接觸襯墊突出至電路區域及非電路區域之間的組裝隔離區域。在一些實施例中，僅進行選擇性操作440a或選擇性操作440b之其中一者。在一些實施例中，選擇性操作440a及選擇性操作440b係同時進行或做為連續步驟。
在一些實施例中，決定一或多個佈局圖案對應至下方的內連接結構。舉例而言，為了進一步補償在接觸襯墊上的較多應力分布，在操作440之前，計算下方的內連接結構的密度分布。如此一來，在操作440a時，第二佈局圖 案之延伸的邊緣不僅與第一佈局圖案之接觸襯墊重疊，更對準一或多個佈局圖案的最大密度分布。舉例而言，當對應至介層窗插塞的第三佈局圖案被決定，除非設計規則的違反無法被執行，第二佈局圖案之邊緣應位於接觸襯墊上，並對準下方的介層窗插塞，其中介層窗插塞係在接觸襯墊正下方，並與接觸襯墊接觸。在另一具體例中，為了延伸第二佈局圖案之至少一個邊緣，以與具有最大密度分布的地區重疊，進一步地計算對應至內連接結構之最高導電線路的第四佈局圖案以及第三佈局圖案。在一些實施例中，額外佈局圖案的決定以及密度分布的計算係在操作430之前進行。在一些實施例中，額外佈局圖案的決定以及密度分布的計算係在操作430之後進行。
另外，在操作430中，若第二佈局圖案之每一個邊緣與第一佈局圖案重疊，如自操作430中以「否」的箭頭所指示，方法400繼續進行操作450，輸出第一佈局圖案及第二佈局圖案，以在半導體製程中完成。
圖5A係根據一或多個實施例之在操作440之後半導體裝置500的剖面視圖。半導體裝置500與半導體裝置100包含類似的元件，且相似元件之最後二位數字為相同。在一些實施例中，基於選擇性操作440b，接觸襯墊554a係水平地延伸，因此接觸襯墊554a包含在密封環區域514內的原有部分554a-1以及在組裝隔離區域512內的延伸部分544a-2。在一些實施例中，在選擇性操作440a下，第一緩衝層560之邊緣564係同時延伸。在一些實施例中，延伸的 接觸襯墊係安置在不同密封環結構內的接觸襯墊，例如接觸襯墊554b，或接觸襯墊係安置在不同非電路區域內，例如虛擬圖案區域516。
圖5B至圖5E係根據一或多個實施例之接觸襯墊554a的俯視圖。在圖5B中，當接觸襯墊554a係在密封環區域514內時，接觸襯墊554a及接觸襯墊554b之每一者為環繞組裝隔離區域512的連續線或不連續線。在一些實施例中，起始部分544a-1係朝組裝隔離區域512延伸。在一些實施例中，在選擇性操作440b時，接觸襯墊554a之一部分或整體係沿著方向52a至方向52c之至少一者。在一些實施例中，接觸襯墊554b係朝接觸襯墊554a延伸。在圖5C中，當接觸襯墊554a係在組裝隔離區域512或虛擬圖案區域516內時，起始部分544a-1具有八角形外觀，且係沿著方向52延伸。在至少一實施例中，方向52係正交於半導體晶片的邊緣。在一些實施例中，起始部分544a-1具有圓形外觀、六角形外觀、矩形外觀或其他合適的多邊形外觀。延伸的部分544a-2具有長度53及寬度54。在一些實施例中，長度53之範圍為約1微米至約25微米。在一些例示中，較長的長度53會增加襯墊550電性短路的風險。在一些例示中，較短的長度53不足以提供第一緩衝層足夠的長度以座落。由於寬度54係等於起始部分544a-1的寬度51，接觸襯墊544a具有八角形外觀。在圖5D中，在一些例示中，當寬度54違反無法執行的設計規則時，寬度54’係小於寬度51。在圖5E中，在一些例示中，考量後鈍化內連接結構570的路徑，延伸的 部分544a-2朝方向52’延伸，並形成相對於起始部分544a-1之邊緣的角度55。在一些實施例中，角度55的範圍為約0度至約60度。在一些例示中，較大的角度55增加另一襯墊或後鈍化內連接結構電性短路的風險。
圖6係根據一或多個實施例之積體電路設計系統的功能方塊圖600。系統600包含硬體處理電路602(亦可當作處理器)以及編碼(例如儲存)電腦程式碼607(例如一組可執行指令)之非暫時性的電腦可讀取儲存媒體604。電腦可讀取儲存媒體604亦編碼接合製造裝置的指令607，其中製造裝置係根據佈局產生半導體裝置。處理器602係透過母線608與電腦可讀取儲存媒體604電性耦合。網路介面612亦透過母線608與處理器602電性連接。網路介面612係連接網路614，以使處理器602及電腦可讀取儲存媒體604可以透過網路614連接外部元件。處理器602係配置以執行編碼在電腦可讀取儲存媒體604中的電腦程式碼606，以使系統600可用以進行方法400所述之部分操作或所有操作。
在一些實施例中，處理器602為中央處理單元(central processing unit，CPU)、多處理器、分散式處理系統、特定功能積體電路(application specific integrated circuit，ASIC)及/或合適的處理單元。
在一些實施例中，電腦可讀取儲存媒體604為非暫時性電子、磁、光學、電磁、紅外線及/或半導體系統(或設備或裝置)。舉例而言，電腦可讀取儲存媒體604包含半導體或固態記憶體(solid-state memory)、磁帶(magnetic tape)、可移除式電腦磁片(removable computer diskette)、隨機存取記憶體(random access memory，RAM)、唯讀記憶體(read-only memory，ROM)、剛性磁盤(rigid magnetic disk)及/或光碟。在使用光碟的一些實施例中，電腦可讀取儲存媒體604包含唯讀光碟(compact disk-read only memory，CD-ROM)、可讀寫光碟(compact disk-read/write，CD-R/W)及/或數位光碟(digital video disk，DVD)。
在一些實施例中，儲存媒體604儲存電腦程式碼606，其中電腦程式碼606係配置為使系統600進行方法400。在一些實施例中，儲存媒體604也儲存進行方法400所需要的資訊以及在進行方法400時產生的資訊，例如設計規則檢查參數616、圖案調整參數618、元件資料庫參數620、佈局參數622及/或一組進行方法400之操作的可執行指令。
在一些實施例中，儲存媒體604儲存接合製造裝置的指令607。指令607使處理器602產生可被製造裝置讀取的製造指令，以在製造過程的電路設計製程中有效地實施方法400。
系統600包含輸入/輸出介面(I/O interface)610。輸入/輸出介面610係連接外部電路。在一些實施例中，輸入/輸出介面610包含鍵盤、小鍵盤、滑鼠、軌跡球、觸控板及/或游標方向鍵，其係用以傳遞資訊及指令至處理器602。
系統600亦包含連接至處理器602的網路介面612。網路介面612允許系統600以網路614傳遞至連接的一或多個其他電腦系統。網路介面612包含無線網路介面，例如藍芽(BLUETOOTH)、無線網路(WIFI)、全球互通微波存取(WIMAX)、通用封包無線服務(GPRS)或寬頻多重分碼存取(WCDMA)；或有線網路介面，例如乙太網路(ETHERNET)、通用系列匯流排(USB)或IEEE-1394。在一些實施例中，方法400係實施在二個或以上的系統600中，並透過網路614在不同系統600之間互換資訊，例如實體間隔規則、色彩間隔規則、元件資料庫或佈局。
系統600係配置為透過輸入/輸出介面610或網路介面612接收實體間隔規則的相關資訊。資訊係透過母線608傳輸至處理器602，以決定設計規則，例如：二個佈局圖案之間的重疊。接著，設計規則係被儲存在電腦可讀取媒體604中，當作參數616。系統600係配置為透過輸入/輸出介面610或網路介面612接收圖案調整的相關資訊，例如：延伸佈局圖案之邊緣。資訊係被儲存在電腦可讀取媒體604中，當作圖案調整參數618。系統600係配置為透過輸入/輸出介面610或網路介面612接收元件資料庫的相關資訊。資訊係被儲存在電腦可讀取媒體604中，當作元件資料庫參數620。系統600係配置為透過輸入/輸出介面610或網路介面612接收佈局相關資訊。資訊係被儲存在電腦可讀取媒體604中，當作佈局參數622。
在操作時，處理器602執行一組指令，以根據 儲存的參數616至參數622，指定色彩組合選擇路線並指定色彩至傳導元件。在一些實施例中，系統600係配置為產生控制製造裝置的指令，以依據於方法400的期間所修飾的佈局參數622形成光罩。
圖7係根據一些實施例之積體電路製造系統700及其相關的積體電路製造流程的方塊圖。積體電路製造系統700產生佈局(例如對應圖5B的佈局500或類似者)。根據佈局，系統700製造(a)一或多個光罩或(b)初期半導體積體電路之一層中的至少一成分其中的至少一者。
積體電路製造系統700包含實體，例如設計廠720、光罩廠730及積體電路生產處/製造處[晶圓廠(fab)]750，實體係在製造積體電路裝置760相關的設計、發展及製造週期及/或服務中與彼此相互作用。系統700中的實體係與通訊網路連接。在一些實施例中，通訊網路為單一網路。在一些實施例中，通訊網路是各種不同網路，例如內部網路及網際網路。通訊網路包含有線及/或無線通訊通道。每一個實體係與一或多個其他實體相互作用，並向一或多個其他實體提供服務及/或接收服務。在一些實施例中，設計廠720、光罩廠730及積體電路晶圓廠750之二者或以上係由單一較大公司擁有。在一些實施例中，設計廠720、光罩廠730及積體電路晶圓廠750之二者或以上係共存於一個共同的設備中，並使用共同的資源。
設計廠(或設計小組)720產生積體電路設計佈局722。積體電路設計佈局722包含設計為積體電路裝置 760的各種幾何圖案。幾何圖案係對應至導體、介電質或半導體層的圖案，以組成要被製造之積體電路裝置760的各種元件。結合各層以形成各種積體電路特徵。舉例而言，積體電路設計佈局722之部分係形成在半導體基材上(例如矽晶圓)，此部分係包含各種積體電路特徵，例如主動區、閘極電極、源極及汲極、層間互連的金屬線或介層窗及接合墊的開口，並設置各種材料層在半導體基材上。設計廠720執行適當的設計步驟，以形成積體電路設計佈局722。設計步驟包含一或多個邏輯設計、實體設計或間距及通路。積體電路設計佈局722係呈現在一或多個具有幾何圖案之資訊的數據檔案中。舉例而言，積體電路設計佈局722係表達在GDSII檔案格式或DFII檔案格式中。
光罩廠730包含資料準備732及光罩製作744。光罩廠730係利用積體電路設計佈局722，根據積體電路設計佈局722，製造用以製作積體電路裝置760之各層的一或多個光罩。光罩廠730進行光罩資料準備732，其中積體電路佈局722係被轉譯成代表資料檔案(representative data file，RDF)。光罩資料準備732提供代表資料檔案至光罩製作744。光罩製作744包含光罩繪圖機(mask writer)。光罩繪圖機將代表資料檔案轉化成在基材(例如光罩或半導體晶圓)上的影像。積體電路設計佈局722係被光罩資料準備732所操控，以遵守光罩繪圖機的特徵及/或積體電路晶圓廠750的要求。在圖7中，光罩資料準備732及光罩製作744係繪示為分開的元件。在一些實施例 中，光罩資料準備732及光罩製作744係共同被當作是光罩資料準備。
在一些實施例中，光罩資料準備732包含光學鄰近校正(optical proximity correction，OPC)，其係利用微影增強技術補償影像錯誤，例如因折射、干涉、其他製程影響或類似因素而增加之此些影像錯誤。光學鄰近校正調整積體電路設計佈局722。在一些實施例中，光罩資料準備732包含進一步的解析度增加技術(resolution enhancement technique，RET)，例如偏軸照射(off-axis illumination)、次解析度輔助特徵(sub-resolution assist features)、相位移光罩、其他合適的技術、或類似者或其中的組合。在一些實施例中，亦可使用反向式微影科技(inverse lithography technology，ILT)，其係將光學鄰近校正當作反向影像問題進行處理。
在一些實施例中，光罩資料準備732包含光罩規則檢查器(mask rule checker，MRC)，以檢查積體電路設計佈局，其係經歷具有一組光罩創作規則之光學鄰近校正的製程，其中光罩創作規則包含特定幾何及/或連接限制，以確保足夠的邊界、以解釋半導體製程的變化或類似者。在一些實施例中，光罩規則檢查器修飾積體電路設計佈局，以補償光罩製作744時的限制，此些限制係為了滿足光罩製作規則，而藉由光學鄰近校正所進行之修飾的取消部分。
在一些實施例中，光罩資料準備732包含微影製程檢查(lithography process checking，LPC)，其係模 仿積體電路晶圓廠750實行，以製作積體電路裝置760的製程。微影製程檢查係基於積體電路設計佈局722模仿前述製程，以創造模擬製造裝置，例如積體電路裝置760。微影製程檢查模擬中的製程參數可包含與積體電路製作週期之各種製程相關的參數、與用以製造積體電路的工具相關的參數及/或其製程其他態樣。微影製程檢查須考慮各種因素，例如空中圖像對比、焦點深度、光罩錯誤增強因子(mask error enhancement factor，MEEF)、其他合適的因素、或類似因素或其中的組合。在一些實施例中，在模擬製造裝置已被微影製程檢查創造之後，若模擬裝置的形狀仍不夠相近以滿足設計規則，重複光學鄰近校正及/或光罩規則檢查，以進一步改善積體電路設計佈局722。
須理解的是，上述光罩資料準備732係為了明確的目的而被簡化。在一些實施例中，資料準備732係包含例如邏輯運算(logic operation，LOP)的額外特徵，以根據製造規則修飾積體電路設計佈局。除此之外，在資料準備732時施加在積體電路設計佈局722的製程可以各種不同的順序執行。
在光罩資料準備732之後，且在光罩製作744時，根據修飾的積體電路設計佈局，製造一個光罩或一組光罩。在一些實施例中，利用電子束或多電子束的機制，以根據修飾的積體電路設計佈局，形成圖案在光罩上。光罩係以各種技術所形成。在一些實施例中，光罩係利用二元技術所形成。在一些實施例中，光罩圖案包含不透明區域和透明區 域。輻射光束(例如紫外光光束)係被不透明區域阻擋，並穿透過透明區域，其中輻射光束係被利用以曝光已塗佈在晶圓上的影像敏感材料層(例如光阻)。在一具體例中，二元光罩包含透明基材(例如熔融石英)及塗佈在光罩的不透明區域上的不透明材料(例如鉻)。在另一具體例中，光罩係利用相位移技術所形成。在相位移遮罩中，形成在光罩上之圖案中的各種特徵係配置為具有適當的相位差，以增加解析度及影像品質。由光罩製作744產生的光罩係被使用在各種製程中。舉例而言，光罩係用於離子佈植製程中，以形成各種摻雜區域在半導體晶圓中、用於蝕刻製程，以形成各種蝕刻區域在半導體晶圓中，及/或其他合適的製程。
積體電路晶圓廠750係包含一或多個用以製造各種不同積體電路產品之製造設備的積體電路製造公司。在一些實施例中，積體電路晶圓廠750為半導體代工廠。舉例而言，有用以前端製造複數個積體電路產品[前端(front-end-of-line，FEOL)製程]的製造設備，而第二製造設備可提供用以內連接及封裝積體電路產品的後端製程[後端(back-end-of-line，BEOL)製程]，且第三製造設備可提供代工廠公司其他服務。
積體電路晶圓廠750使用光罩廠730製造的光罩，以製造積體電路裝置760。因此，積體電路晶圓廠750係至少非直接地使用積體電路設計佈局722，以製造積體電路裝置760。在一些實施例中，半導體晶圓752係由積體電路晶圓廠750利用光罩所製造，以製造積體電路裝置760。 半導體晶圓752包含矽基材或其他具有材料層形成於其上的合適基材。半導體晶圓更包含各種摻雜區域、介電特徵、多層內連接或類似物(在後續製造步驟中形成)之一者或多者。
關於積體電路製造系統(例如圖7的系統700)及其相關的積體電路製造流程的詳細敘述已記載於例如美國專利號US 9,256,709(2016年2月9日核准)、美國早期公開號US 20150278429(2015年10月1日公開)、美國早期公開號US 20140040838(2014年2月6日公開)、美國專利號US 7,260,442(2007年8月21日核准)，上述全文併入本案以供參考。
本敘述的一態樣是關於一種半導體裝置的製造方法。方法包含形成第一接觸襯墊及第二接觸襯墊在第一鈍化層上、沉積第一緩衝層在第一接觸襯墊及第二接觸襯墊上，以及沉積第二緩衝層在第一緩衝層及第二接觸襯墊上，其中第一接觸襯墊係在電路區域內，第二接觸襯墊係在非電路區域內，第二接觸襯墊之邊緣係被暴露，且第一接觸襯墊之周圍及第二接觸襯墊之邊緣係被第一緩衝層覆蓋。在一些實施例中，形成第一接觸襯墊及第二接觸襯墊之操作包含形成第二接觸襯墊在密封環區域內。在一些實施例中，形成第一接觸襯墊及第二接觸襯墊之操作包含形成第二接觸襯墊在組裝隔離區域內。在一些實施例中，形成第一接觸襯墊及第二接觸襯墊之操作包含形成第二接觸襯墊在虛擬圖案區域內。在一些實施例中，沉積第一緩衝層之操作包含將第一 緩衝層之邊緣對準介層窗插塞之中間部分，其中介層窗插塞係在第二接觸襯墊之下。在一些實施例中，方法更包含形成第三接觸襯墊在第一鈍化層上以及沉積第一緩衝層在第三接觸襯墊上，其中第三接觸襯墊係在非電路區域內，並介於第一接觸襯墊及第二接觸襯墊之間。在一些實施例中，形成第三接觸襯墊之操作包含形成第三接觸襯墊及第二接觸襯墊在密封環區域內。在一些實施例中，方法更包含沉積第二鈍化層在第一接觸襯墊、第二接觸襯墊及第一鈍化層上。在一些實施例中，沉積第一緩衝層之操作包含沉積第一緩衝層，以使第一緩衝層對第二鈍化層具有抗拉應力或抗壓應力。
本敘述的另一態樣是關於一種設計佈局的方法。方法包含決定第一佈局圖案、利用硬體處理電路產生第二佈局圖案、檢查第二佈局圖案之每一個邊緣是否與第一佈局圖案重疊、調整第二佈局圖案或第一佈局圖案之至少一者，使第二佈局圖案之邊緣與第一佈局圖案重疊，以回應第二佈局圖案之至少一邊緣與第一佈局圖案分離的測定，以及輸出第一佈局圖案及第二佈局圖案，其中第一佈局圖案係對應至複數個接觸襯墊。在一些實施例中，調整第二佈局圖案或第一佈局圖案之至少一者之操作包含延伸第二佈局圖案之至少一邊緣，以與第一佈局圖案重疊。在一些實施例中，延伸第二佈局圖案之至少一邊緣之操作包含延伸第二佈局圖案之至少一邊緣，以使第二佈局圖案之至少一邊緣係自電路區域朝向非電路區域實質1微米至實質25微米之長度。在 一些實施例中，調整第二佈局圖案或第一佈局圖案之至少一者之操作包含延伸第一佈局圖案之至少一個接觸襯墊，以與第二佈局圖案重疊。
本敘述的再一態樣是關於一種半導體結構。半導體結構係包含在第一鈍化層上的第一接觸襯墊及第二接觸襯墊，以及在第一接觸襯墊及第二接觸襯墊上的第一緩衝層，其中第一接觸襯墊係在電路區域內，第二接觸襯墊係在非電路區域內，且第一緩衝層之邊緣係在第二接觸襯墊上。在一些實施例中，第二接觸襯墊係在密封環區域內。在一些實施例中，第一緩衝層之邊緣係對準密封環結構之內連接結構。在一些實施例中，第一緩衝層之邊緣係在組裝隔離區域內。在一些實施例中，第一緩衝層之邊緣係在虛擬圖案區域內。在一些實施例中，第一緩衝層之邊緣係對準虛擬圖案結構。在一些實施例中，半導體結構更包含在第一接觸襯墊及第二接觸襯墊上的第二鈍化層，以及在第一緩衝層及第二接觸襯墊上的第二緩衝層，其中第二鈍化層係與第一緩衝層接觸。
上述摘要許多實施例的特徵，因此本領域具有通常知識者可更了解本揭露的態樣。本領域具有通常知識者應理解利用本揭露為基礎可以設計或修飾其他製程和結構以實現和所述實施例相同的目的及/或達成相同優勢。本領域具有通常知識者也應了解與此同等的架構並沒有偏離本揭露的精神和範圍，且可以在不偏離本揭露的精神和範圍下做出各種變化、交換和取代。

Claims (1)

  1. 一種半導體裝置的製造方法，該製造方法包含：形成一第一接觸襯墊及一第二接觸襯墊在一第一鈍化層上，其中該第一接觸襯墊係在一電路區域內，且該第二接觸襯墊係在一非電路區域內；沉積一第一緩衝層在該第一接觸襯墊及該第二接觸襯墊上，其中該第二接觸襯墊之一邊緣係被暴露，且該第一接觸襯墊之一周圍及該第二接觸襯墊之另一邊緣係被該第一緩衝層覆蓋；以及沉積一第二緩衝層在該第一緩衝層及該第二接觸襯墊上。
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