TW201836084A - Manufacturing method of semiconductor package structure - Google Patents

Abstract

A manufacturing method including the following steps is provided. First, a first photoresist layer is formed on a first active surface of a wafer and the wafer is divided into a plurality of chip region via a plurality of predetermined cutting line. After that, a part of the first photoresist layer is removed through the photolithography process to form a plurality of second photoresist layers separated from each other. After that, the wafer is cut along the predetermined cutting lines to obtained a plurality of chips and each of the second photoresist layers partially covers a second active surface of the corresponding chip. After that, an encapsulant is formed to cover anyone of the chips and the second photoresist layer is exposed outside. Afterwards, the second photoresist layer is removed to expose a portion of the second active surface of the chip.

Description

Manufacturing method of semiconductor packaging structure

The invention relates to a manufacturing method of a packaging structure, and more particularly to a manufacturing method of a semiconductor packaging structure.

In the existing semiconductor packaging process, after the chip is electrically connected to the circuit carrier board by wire bonding, the sealing step is usually continued. For example, the electrically connected chip and the circuit carrier board are placed in a mold. The encapsulating gel is filled into the mold, so that the cured encapsulating gel covers at least part of the wafer, the electrical junction of the chip and the conductor, and the electrical junction of the circuit carrier board and the conductor, so as to prevent the conductor from being wet or external force. Destroyed.

Taking the semiconductor package structure where the active surface of the wafer is partially exposed as an example, the inner wall surface of the mold facing the active surface of the wafer is usually provided with a concave-convex structure, and the buffer film is attached to the concave-convex structure to avoid the convexity of the concave-convex structure. The part directly touches the active surface of the chip. However, the above-mentioned sealing step has the following disadvantages: (1) The convex portion of the concave-convex structure abuts against the active surface of the wafer through the buffer film. If the buffer film does not closely adhere to the active surface of the wafer, the encapsulating gel before curing is easy to flow in Between the buffer film and the active surface of the wafer, encapsulation gel remains on the active surface of the wafer; (2) The size of the wafer is different, and the uneven structure on the inner wall surface of the mold needs to be adjusted according to the wafers of different sizes, so that The cost has increased significantly.

The invention provides a method for manufacturing a semiconductor package structure, which is helpful for reducing manufacturing costs and improving product yield.

The invention provides a method for manufacturing a semiconductor package structure, which includes the following steps. First, a first photoresist layer is formed on a first active surface of a wafer, and the wafer is divided into a plurality of wafer regions by a plurality of predetermined cutting lines. Then, a part of the first photoresist layer is removed through a lithography process to form a plurality of second photoresist layers separated from each other, and the second photoresist layers are respectively located in the wafer regions. Next, the wafer is cut along these predetermined cutting lines to obtain a plurality of wafers, and each second photoresist layer partially covers the second active surface of the corresponding wafer. Next, a packaging gel is formed to cover any one of the wafers, and a second photoresist layer partially covering the second active surface of the wafer is exposed to the outside. Then, the second photoresist layer is removed through a lithography process to expose a part of the second active surface of the wafer.

In an embodiment of the present invention, the method for manufacturing a semiconductor package structure described above further includes electrically connecting the chip to the circuit carrier board before forming a package gel to cover any chip.

In an embodiment of the present invention, the chip is electrically connected to the circuit carrier board through a plurality of wires, and one end of each wire is bonded to a region outside the area covered by the second photoresist layer on the second active surface of the chip. .

In an embodiment of the present invention, the upper surface of the second photoresist layer is exposed outside the packaging gel and is flush with the top surface of the packaging gel.

In an embodiment of the present invention, when the encapsulation gel is formed to cover the wafer, the upper surface of the second photoresist layer is contacted through the mold.

The invention provides another method for manufacturing a semiconductor package structure, which includes the following steps. First, a first photoresist layer is formed on the active surface of the wafer. Then, a portion of the first photoresist layer is removed through a lithography process to form a second photoresist layer, and the second photoresist layer partially covers the active surface of the wafer. Next, a packaging gel is formed to cover the wafer, and the second photoresist layer partially covering the active surface of the wafer is exposed to the outside. After that, the second photoresist layer is removed through a lithography process to expose a part of the active surface of the wafer.

Based on the above, the manufacturing method of the semiconductor package structure of the present invention is that the photoresist layer partially covers the active surface of the wafer before the sealing step, and after the sealing step, the photoresist layer is removed through the lithography process to make the active chip Part of the face is exposed outside the encapsulant. Therefore, the manufacturing method of the semiconductor package structure of the present invention not only helps to reduce manufacturing costs, but also improves product yield.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

1A to 1H are schematic cross-sectional views illustrating a manufacturing process of a semiconductor package structure according to an embodiment of the present invention. Please refer to FIG. 1A, a wafer 10 is provided, wherein the wafer 10 is divided into a plurality of wafer regions 11 by a plurality of predetermined cutting lines L, and then, the first active surface 12 of the wafer 10 is comprehensively printed or coated. A first photoresist layer 20 is formed. The first photoresist layer 20 covers all the first active surfaces 12 in the chip region 11. Next, a photomask 30 having a specific pattern is disposed above the first active surface 12 of the wafer 10, and a lithography process is performed to remove a portion of the first photoresist layer 20. After removing part of the first photoresist layer 20, a plurality of second photoresist layers 21 separated from each other may be formed, as shown in FIG. 1B. In detail, a second photoresist layer 21 is provided in each wafer region 11, and each second photoresist layer 21 partially covers the first active surface 12 in the corresponding wafer region 11.

Next, referring to FIGS. 1C and 1D, the wafer 10 is cut along these predetermined cutting lines L to disconnect any two adjacent wafer regions 11. Each wafer region 11 and the first active surface 12 therein form a wafer 110 and a second active surface 111 thereof. Before the wafer 10 is cut along these predetermined cutting lines L, the first active surface 12 in each wafer region 11 is partially covered by the corresponding second photoresist layer 21, and the wafer is cut along these predetermined cutting lines L After obtaining a plurality of wafers 110, the second active surface 111 of each wafer 110 is partially covered by the corresponding second photoresist layer 21. Taking one of the chips 110 as an example, the chip 110 is set on the circuit carrier board 120, and then, the chip 110 is electrically connected to the circuit carrier board 120 through a plurality of wires 130 in a wire bonding manner. One end is bonded to the area outside the area covered by the second photoresist layer 21 of the second active surface 111 of the wafer 110. For example, a pad (not shown) is usually provided outside the area covered by the second active surface 111 of the chip 110 by the second photoresist layer 21 for the wires 130 to be bonded thereto.

Next, referring to FIG. 1E and FIG. 1F, the electrically connected chip 110 and the circuit substrate 120 are placed in the mold 40, and the inner wall surface 41 of the mold 40 abuts the upper surface 21 a of the second photoresist layer 21. Therefore, a gap D can be maintained between the inner wall surface 41 of the mold 40 and the second active surface 111 of the wafer 110, and the gap D is substantially equal to the thickness of the second photoresist layer 21. After the electrically connected chip 110 and the circuit carrier board 120 are placed in the mold 40, the encapsulant 140 is filled in the mold 40, and the area covered by the second active surface 111 by the second photoresist layer 21 will not There is contact with the encapsulant 140. Therefore, the cured encapsulant 140 covers the area of the second active surface 111 of the wafer 110 that is not covered by the second photoresist layer 21, and simultaneously covers the electrical properties of the second active surface 111 of the wafer 110 and the wires 130. The conductive junction, the electrical junction of the circuit carrier board 120 and the wire 130, and at least part of the circuit carrier board 120 are used to prevent the wire 130 from being damaged by moisture or external force. Further, since the second photoresist layer 21 can closely abut against the second active surface 111 of the chip 110, the encapsulant 140 before curing cannot flow into the second photoresist layer 21 and the second active surface 111 of the chip 110. between.

After that, referring to FIG. 1G and FIG. 1H, the mold 40 is removed. The upper surface 21 a of the second photoresist layer 21 is exposed to the outside of the encapsulant 140 and is flush with the top surface 141 of the encapsulant 140. Finally, the second photoresist layer 21 is removed through a lithography process to expose a part of the second active surface 111 of the wafer 110. So far, the semiconductor package structure 100 has been substantially completed, and there is a distance between the top surface 141 of the packaging gel 140 and the second active surface 111 of the chip 110.

The manufacturing process described above is applicable to wafers of different sizes, and it is not necessary to produce corresponding molds according to wafers of various sizes, so the manufacturing cost can be reduced. On the other hand, during the encapsulation step, the encapsulant 140 before curing cannot flow between the second photoresist layer 21 and the second active surface 111 of the wafer 110, so the wafer 110 in the semiconductor package structure 100 is fabricated. No encapsulant 140 remains on the second active surface 111.

2A to 2B are schematic cross-sectional views of a part of a manufacturing process of a semiconductor package structure according to another embodiment of the present invention. Please refer to FIG. 2A and FIG. 2B. The difference between the manufacturing process of this embodiment and the manufacturing process of the above embodiment lies in that before forming the first photoresist layer 20 on the first active surface 12 of the wafer 10 in FIG. 1A, The wafer 10 of FIG. 1A is diced to obtain a plurality of wafers 110. Taking one of the wafers 110 as an example, a first photoresist layer 201 is comprehensively formed on the second active surface 111 of the wafer 110. Next, a photomask 301 having a specific pattern is disposed above the second active surface 111 of the wafer 110, and a lithography process is performed to remove a portion of the first photoresist layer 201. After removing part of the first photoresist layer 201, a second photoresist layer 211 may be formed, and the second photoresist layer 211 partially covers the second active surface 111 of the wafer 110. Subsequent manufacturing processes are substantially the same as or similar to those in FIG. 1D to FIG. 1H, and therefore are not described in detail.

In summary, the manufacturing method of the semiconductor package structure of the present invention is to first partially cover the active surface of the wafer with the photoresist layer, and then perform a sealing step, so that the packaging colloid will not be formed on the active surface of the wafer by the photoresist layer. Covered area. After that, by removing the photoresist layer through the lithography process, the active surface of the chip can be partially exposed to the outside of the encapsulant. Therefore, the manufacturing method of the semiconductor package structure of the present invention not only helps to reduce manufacturing costs, but also improves product yield.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10‧‧‧ wafer

11‧‧‧Chip Area

12‧‧‧ the first active face

20, 201‧‧‧ the first photoresist layer

21, 211‧‧‧Second photoresist layer

21a‧‧‧upper surface

30, 301‧‧‧Mask

40‧‧‧mould

41‧‧‧Inner wall surface

100‧‧‧Semiconductor Package Structure

110‧‧‧Chip

111‧‧‧Second active face

120‧‧‧line carrier board

130‧‧‧Wire

140‧‧‧ encapsulated colloid

141‧‧‧Top

D‧‧‧ Clearance

L‧‧‧ Scheduled cutting line

1A to FIG. 1H are schematic cross-sectional views illustrating a manufacturing process of a semiconductor package structure according to an embodiment of the present invention. FIG. 2A to FIG. 2B are schematic cross-sectional views of a part of a manufacturing process of a semiconductor package structure according to another embodiment of the present invention.

Claims (10)

A method for manufacturing a semiconductor package structure includes: forming a first photoresist layer on a first active surface of a wafer, and the wafer is divided into a plurality of wafer regions by a plurality of predetermined cutting lines; and a lithography process is adopted. Removing part of the first photoresist layer to form a plurality of second photoresist layers separated from each other, and the second photoresist layers are respectively located in the wafer regions; cutting the wafer along the predetermined cutting lines to obtain A plurality of wafers, and each of the second photoresist layers partially covers a corresponding second active surface of the wafer; forming a packaging gel to cover any of the wafers and partially covering the second active surface of the wafer The second photoresist layer is exposed to the outside; and the second photoresist layer is removed through a lithography process to expose a part of the second active surface of the wafer. The method for manufacturing a semiconductor package structure described in item 1 of the patent application scope further includes: before forming the packaging gel to cover any of the chips, electrically connecting the chip to the circuit carrier board. The method for manufacturing a semiconductor package structure according to item 2 of the scope of patent application, wherein the chip is electrically connected to the circuit carrier board through a plurality of wires, and one end portion of each of the wires is bonded to the second driver of the chip. Outside the area covered by the second photoresist layer. According to the manufacturing method of the semiconductor package structure described in item 1 of the patent application scope, an upper surface of the second photoresist layer is exposed from the packaging gel and is flush with a top surface of the packaging gel. The manufacturing method of the semiconductor package structure according to item 1 of the scope of the patent application, wherein when the packaging colloid is formed to cover the wafer, a mold is used to abut against an upper surface of the second photoresist layer. A method for manufacturing a semiconductor package structure includes: forming a first photoresist layer on an active surface of a wafer; removing a portion of the first photoresist layer through a lithography process to form a second photoresist layer; Two photoresist layers partially cover the active surface of the wafer; forming a packaging gel to cover the wafer, and exposing the second photoresist layer partially covering the active surface of the wafer to the outside; and moving through a lithography process The second photoresist layer is removed to expose a part of the active surface of the wafer. The method for manufacturing a semiconductor package structure according to item 6 of the patent application scope further comprises: before forming the packaging gel to cover the chip, electrically connecting the chip to the circuit carrier board. The method for manufacturing a semiconductor package structure according to item 7 of the scope of patent application, wherein the chip is electrically connected to the circuit carrier board through a plurality of wires, and one end of each of the wires is bonded to the active surface of the chip Outside the area covered by the second photoresist layer. The method for manufacturing a semiconductor package structure according to item 6 of the scope of the patent application, wherein an upper surface of the second photoresist layer is exposed from the packaging gel and is flush with a top surface of the packaging gel. According to the manufacturing method of the semiconductor package structure described in item 6 of the patent application scope, when forming the packaging colloid to cover the wafer, a mold is used to abut against an upper surface of the second photoresist layer.