TW201436128A - Heat-dissipating structure, semiconductor package and fabricating method thereof - Google Patents
Heat-dissipating structure, semiconductor package and fabricating method thereof Download PDFInfo
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- TW201436128A TW201436128A TW102108970A TW102108970A TW201436128A TW 201436128 A TW201436128 A TW 201436128A TW 102108970 A TW102108970 A TW 102108970A TW 102108970 A TW102108970 A TW 102108970A TW 201436128 A TW201436128 A TW 201436128A
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- heat sink
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000000034 method Methods 0.000 title claims abstract description 6
- 230000017525 heat dissipation Effects 0.000 claims abstract description 59
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 22
- 239000008393 encapsulating agent Substances 0.000 claims description 32
- 230000002787 reinforcement Effects 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 239000010432 diamond Substances 0.000 claims description 5
- 238000007650 screen-printing Methods 0.000 claims description 4
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000007787 solid Substances 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 8
- 150000001875 compounds Chemical class 0.000 abstract 2
- 238000000465 moulding Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 32
- 235000012431 wafers Nutrition 0.000 description 24
- 239000000758 substrate Substances 0.000 description 22
- 239000012790 adhesive layer Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 239000000084 colloidal system Substances 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
- H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
本發明係關於一種散熱結構、半導體封裝件及其製法，特別是指一種具有結合加強層之散熱結構、半導體封裝件及其製法。 The present invention relates to a heat dissipation structure, a semiconductor package, and a method of fabricating the same, and more particularly to a heat dissipation structure having a bonding enhancement layer, a semiconductor package, and a method of fabricating the same.
隨著電子元件之輸出入接點的數目愈來愈多，以及電子產品走向輕薄短小的趨勢，傳統使用導線架作為承載件之封裝體已不符合需求，因而發展出以基板作為承載件，並以錫球作為輸出入接點之球柵陣列(Ball Grid Array；BGA)封裝體。球柵陣列封裝體之技術的優點，在於相同尺寸之面積下，引腳數可以設置較多，且封裝面積及重量只需四方扁平封裝體(Quad Flat Package；QFP)的一半。 With the increasing number of input and output contacts of electronic components and the trend of thinner and lighter electronic products, the conventional use of lead frames as a package for the carrier has not met the requirements, and thus the development of the substrate as a carrier, and A solder ball is used as a Ball Grid Array (BGA) package for the input and output contacts. The advantage of the technology of the ball grid array package is that the number of pins can be set more in the same size area, and the package area and weight are only half of the quad flat package (QFP).
在球柵陣列封裝體之技術中，又發展出所謂的薄型球柵陣列(Thin & Fine-pitch Ball Grid Array；TFBGA)封裝體，相較於球柵陣列封裝體，該薄型球柵陣列封裝體具有輸出入接點之間距較小且體積較薄之優點。 In the technology of the ball grid array package, a so-called Thin & Fine-Pitch Ball Grid Array (TFBGA) package has been developed, compared to the ball grid array package, the thin ball grid array package It has the advantages of small distance between the input and output contacts and thin volume.
但是，由於電子元件的輸出入信號愈來愈多，使得電子元件在運作時所產生之熱量愈來愈多，因此如何將電子 元件所產生之熱源快速又有效地排放至周遭環境，以確保電子元件之工作溫度不會超過其承受範圍而造成產品信賴性之問題，實為重要的研究課題。 However, due to the increasing number of input and output signals of electronic components, the heat generated by electronic components is increasing, so how to use electrons It is an important research topic that the heat source generated by the component is quickly and efficiently discharged to the surrounding environment to ensure that the operating temperature of the electronic component does not exceed its tolerance range and the reliability of the product is caused.
對此，現已發展出薄型球柵陣列封裝體結合散熱片之應用方式，但在對該薄型球柵陣列封裝體進行切單(singulation)作業時，藉由刀具切割該薄型球柵陣列封裝體的過程中，容易造成該散熱片與封裝膠體間產生剝離(peeling)之問題，因而導致該薄型球柵陣列封裝體無法通過檢驗而報廢，以致增加不少的製造成本。 In this regard, a thin ball grid array package combined with a heat sink has been developed, but the thin ball grid array package is cut by a cutter during singulation of the thin ball grid array package. In the process, the problem of peeling between the heat sink and the encapsulant is easily caused, and thus the thin ball grid array package cannot be scrapped by inspection, so that a lot of manufacturing cost is increased.
第1A圖係繪示習知技術中半導體封裝件1之剖視示意圖，第1B圖係依據第1A圖繪示習知技術中具有散熱片16之半導體封裝件1之剖視示意圖。 1A is a cross-sectional view showing a semiconductor package 1 in a prior art, and FIG. 1B is a cross-sectional view showing a semiconductor package 1 having a heat sink 16 in the prior art according to FIG.
如1A圖所示，該半導體封裝件1係具有基板10、晶片11、黏著層12、銲線13、封裝膠體14以及銲球15。該晶片11係藉由該黏著層12設置於該基板10之上表面，並藉由該銲線13電性連接該基板10。該封裝膠體14係包覆該基板10之上表面、晶片11、黏著層12與銲線13，該銲球15係植設於該基板10之下表面。 As shown in FIG. 1A, the semiconductor package 1 has a substrate 10, a wafer 11, an adhesive layer 12, a bonding wire 13, an encapsulant 14, and a solder ball 15. The wafer 11 is disposed on the upper surface of the substrate 10 by the adhesive layer 12, and is electrically connected to the substrate 10 by the bonding wire 13. The encapsulant 14 covers the upper surface of the substrate 10, the wafer 11, the adhesive layer 12 and the bonding wires 13, and the solder balls 15 are implanted on the lower surface of the substrate 10.
如第1B圖所示，該封裝膠體14之上表面設置有散熱片16，用以提升該晶片11之散熱效果。 As shown in FIG. 1B, a heat sink 16 is disposed on the upper surface of the encapsulant 14 to enhance the heat dissipation effect of the wafer 11.
上述半導體封裝件1之缺點，在於對該半導體封裝件1進行切單作業時，易於該散熱片16與該封裝膠體14間產生剝離之情形，如第1B圖之剝離處17所示，因而導致該半導體封裝件1被報廢而增加不少的成本。 The semiconductor package 1 has a disadvantage in that when the semiconductor package 1 is diced, the peeling between the heat sink 16 and the encapsulant 14 is facilitated, as shown by the peeling portion 17 of FIG. 1B, thereby causing The semiconductor package 1 is scrapped and adds a lot of cost.
因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失，本發明係提供一種散熱結構，其包括：散熱片，係為一體成型，具有周緣、相對之第一側與第二側，該周緣、第一側與第二側分別形成有階部、第一凸部及凹部；以及結合加強層，係形成於該散熱片之第一側之至少部分表面上。 In view of the above-mentioned various deficiencies of the prior art, the present invention provides a heat dissipating structure comprising: a heat sink integrally formed having a circumference, opposite first and second sides, the circumference, the first side and the second side The side is respectively formed with a step portion, a first convex portion and a concave portion; and a bonding reinforcing layer is formed on at least a part of the surface of the first side of the heat sink.
本發明亦提供一種半導體封裝件，其包括：半導體裝置，係具有晶片；封裝膠體，係形成於該半導體裝置上，並包覆該晶片；以及散熱結構，係形成於該封裝膠體上，並具有散熱片與結合加強層，該結合加強層形成於該散熱片之表面上，且位於該散熱片與該封裝膠體之間。 The present invention also provides a semiconductor package comprising: a semiconductor device having a wafer; an encapsulant formed on the semiconductor device and covering the wafer; and a heat dissipation structure formed on the encapsulant and having The heat sink and the bonding reinforcement layer are formed on the surface of the heat sink and located between the heat sink and the encapsulant.
本發明另提供一種半導體封裝件之製法，其包括：提供具有晶片之半導體裝置及具有散熱片與結合加強層之散熱結構，該散熱片係具有周緣、相對之第一側與第二側，該周緣、第一側與第二側分別形成有階部、第一凸部及凹部，該結合加強層係形成於該第一側之表面上；以及形成封裝膠體於該半導體裝置與該散熱結構之間，以包覆該晶片、第一凸部與結合加強層。 The present invention further provides a method of fabricating a semiconductor package, comprising: providing a semiconductor device having a wafer and a heat dissipation structure having a heat sink and a bonding reinforcement layer, the heat sink having a circumference, an opposite first side and a second side, a circumference, a first protrusion and a recess are respectively formed on the periphery, the first side and the second side, the bonding reinforcement layer is formed on the surface of the first side; and the encapsulant is formed on the semiconductor device and the heat dissipation structure To cover the wafer, the first protrusion and the bonding reinforcement layer.
由上可知，本發明之散熱結構、半導體封裝件及其製法，主要係在散熱片之周緣、第一側與第二側分別形成有階部、第一凸部及凹部，並將結合加強層形成於該散熱片之第一側之至少部分表面上。藉此，本發明能提升該晶片 之散熱效果，並強化該散熱片與該封裝膠體間之結合力，以避免進行切單作業時產生剝離之情形。 It can be seen from the above that the heat dissipation structure, the semiconductor package and the manufacturing method thereof are mainly formed on the periphery of the heat sink, the first side and the second side respectively have a step portion, a first convex portion and a concave portion, and the reinforcing layer is combined Formed on at least a portion of the surface of the first side of the heat sink. Thereby, the present invention can enhance the wafer The heat dissipation effect is enhanced, and the bonding force between the heat sink and the encapsulant is strengthened to avoid the occurrence of peeling during the singulation operation.
1‧‧‧半導體封裝件 1‧‧‧Semiconductor package
10‧‧‧基板 10‧‧‧Substrate
11‧‧‧晶片 11‧‧‧ wafer
12‧‧‧黏著層 12‧‧‧Adhesive layer
13‧‧‧銲線 13‧‧‧welding line
14‧‧‧封裝膠體 14‧‧‧Package colloid
15‧‧‧銲球 15‧‧‧ solder balls
16‧‧‧散熱片 16‧‧‧ Heat sink
17‧‧‧剝離處 17‧‧‧ peeling
2‧‧‧散熱結構 2‧‧‧heating structure
20‧‧‧散熱片 20‧‧‧ Heat sink
201‧‧‧周緣 201‧‧‧ Periphery
202a‧‧‧第一側 202a‧‧‧ first side
202b‧‧‧第二側 202b‧‧‧ second side
203‧‧‧階部 203‧‧‧
204‧‧‧第一凸部 204‧‧‧First convex
205‧‧‧第二凸部 205‧‧‧second convex
206‧‧‧凹部 206‧‧‧ recess
207‧‧‧導角 207‧‧‧ lead angle
208‧‧‧角落 208‧‧‧ corner
209‧‧‧溝槽 209‧‧‧ trench
21‧‧‧結合加強層 21‧‧‧Combined reinforcement
3‧‧‧半導體封裝件 3‧‧‧Semiconductor package
30‧‧‧半導體裝置 30‧‧‧Semiconductor device
31‧‧‧基板 31‧‧‧Substrate
32‧‧‧晶片 32‧‧‧ wafer
33‧‧‧黏著層 33‧‧‧Adhesive layer
34‧‧‧銲線 34‧‧‧welding line
35‧‧‧封裝膠體 35‧‧‧Package colloid
36‧‧‧銲球 36‧‧‧ solder balls
41‧‧‧上模 41‧‧‧上模
42‧‧‧下模 42‧‧‧Down
421‧‧‧壓縮件 421‧‧‧Compressed parts
422‧‧‧容置空間 422‧‧‧ accommodating space
43‧‧‧離型膜 43‧‧‧ release film
44‧‧‧第一方向 44‧‧‧First direction
45‧‧‧第二方向 45‧‧‧second direction
AA,BB,CC,DD‧‧‧剖面線 AA, BB, CC, DD‧‧‧ hatching
H1,H2‧‧‧厚度 H1, H2‧‧‧ thickness
SS‧‧‧切割線 SS‧‧‧ cutting line
第1A圖係繪示習知技術中半導體封裝件之剖視示意圖；第1B圖係依據第1A圖繪示習知技術中具有散熱片之半導體封裝件之剖視示意圖；第2A圖係繪示本發明之散熱結構之第一實施例之俯視示意圖；第2B圖係依據第2A圖之剖面線AA繪示本發明之散熱結構之一態樣之剖視示意圖；第3A圖係繪示本發明之散熱結構之第二實施例之俯視示意圖；第3B圖係依據第3A圖之剖面線BB繪示本發明之散熱結構之一態樣之剖視示意圖；第3B'圖係依據第3A圖之剖面線BB繪示本發明之散熱結構之另一態樣之剖視示意圖；第4A圖係繪示本發明之散熱結構之第三實施例之俯視示意圖；第4B圖係依據第4A圖之剖面線CC繪示本發明之散熱結構之一態樣之剖視示意圖；第4B'圖係依據第4A圖之剖面線CC繪示本發明之散熱結構之另一態樣之剖視示意圖；第5A圖係繪示本發明之散熱結構之第四實施例之俯 視示意圖；第5B圖係依據第5A圖之剖面線DD繪示本發明之散熱結構之一態樣之剖視示意圖；第5B'圖係依據第5A圖之剖面線DD繪示本發明之散熱結構之另一態樣之剖視示意圖；第6A圖至第6F圖係繪示本發明之半導體封裝件及其製法之第一實施例之剖視示意圖；以及第7圖係繪示本發明之半導體封裝件之第二實施例之剖視示意圖。 1A is a cross-sectional view showing a semiconductor package in a prior art; FIG. 1B is a cross-sectional view showing a semiconductor package having a heat sink in the prior art according to FIG. 1A; FIG. 2A is a schematic view FIG. 2B is a schematic cross-sectional view showing one aspect of the heat dissipation structure of the present invention according to a section line AA of FIG. 2A; FIG. 3A is a cross-sectional view showing the present invention. FIG. 3B is a schematic cross-sectional view showing one aspect of the heat dissipation structure of the present invention according to a section line BB of FIG. 3A; FIG. 3B is a diagram according to FIG. 3A. FIG. 4A is a schematic cross-sectional view showing another embodiment of the heat dissipation structure of the present invention; FIG. 4A is a top plan view showing a third embodiment of the heat dissipation structure of the present invention; FIG. 4B is a cross-sectional view according to FIG. 4A Figure CC is a cross-sectional view showing one aspect of the heat dissipation structure of the present invention; Figure 4B is a cross-sectional view showing another aspect of the heat dissipation structure of the present invention according to the section line CC of Figure 4A; The figure shows the fourth embodiment of the heat dissipation structure of the present invention. 5B is a cross-sectional view showing one aspect of the heat dissipation structure of the present invention according to a section line DD of FIG. 5A; FIG. 5B' is a diagram showing the heat dissipation of the present invention according to a section line DD of FIG. 5A. FIG. 6A to FIG. 6F are schematic cross-sectional views showing a first embodiment of a semiconductor package of the present invention and a method of fabricating the same; and FIG. 7 is a cross-sectional view showing the first embodiment of the present invention; A schematic cross-sectional view of a second embodiment of a semiconductor package.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」、「表面」、「周緣」及「階部」等用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. At the same time, the terms "upper", "one", "first", "second", "surface", "circumference" and "order" are used in this manual for the convenience of description. Rather than limiting the scope of the invention, it is to be understood that the scope of the invention may be practiced.
第2A圖係繪示本發明之散熱結構2之第一實施例之俯視示意圖，第2B圖係依據第2A圖之剖面線AA繪示本發明之散熱結構2之一態樣之剖視示意圖。如圖所示，散熱結構2係包括散熱片20以及結合加強層21。 2A is a top plan view showing a first embodiment of the heat dissipation structure 2 of the present invention, and FIG. 2B is a cross-sectional view showing an aspect of the heat dissipation structure 2 of the present invention according to a section line AA of FIG. 2A. As shown, the heat dissipation structure 2 includes a heat sink 20 and a bonding reinforcement layer 21.
該散熱片20係為一體成型，具有周緣201、相對之第一側202a與第二側202b，該周緣201、第一側202a與第二側202b分別形成有階部(step)203、第一凸部204及凹部206。 The heat sink 20 is integrally formed with a peripheral edge 201, a first side 202a and a second side 202b opposite to each other. The peripheral edge 201, the first side 202a and the second side 202b are respectively formed with a step 203, first The convex portion 204 and the concave portion 206.
該結合加強層21可為防焊層(solder mask)，並可藉由網版印刷或其他方式塗佈於該第一側202a之至少部分表面上。 The bonding reinforcement layer 21 can be a solder mask and can be applied to at least a portion of the surface of the first side 202a by screen printing or other means.
在第2A圖中，該散熱片20可具有導角207，係形成於該周緣201之至少一角落208。當進行封裝時，該導角207可使該散熱片20易於定位至模具之預定位置上(圖中未繪示)。同時，該結合加強層21係形成於該第一凸部204之整個表面上，並包括具有導角(類似導角207)之矩形之圖案，該矩形可為方形(如長方形或正方形)。 In FIG. 2A, the heat sink 20 can have a lead angle 207 formed in at least one corner 208 of the perimeter 201. The lead angle 207 allows the heat sink 20 to be easily positioned to a predetermined position of the mold (not shown) when packaged. At the same time, the bonding reinforcing layer 21 is formed on the entire surface of the first convex portion 204, and includes a rectangular pattern having a guiding angle (like the guiding angle 207), which may be a square (such as a rectangle or a square).
在第2B圖中，該階部203係為二階之結構，並形成於該散熱片20之周邊或周圍。但在其他實施例中，該階部203亦可為三階或三階以上之結構。 In FIG. 2B, the step portion 203 is a second-order structure and is formed around or around the heat sink 20. However, in other embodiments, the step 203 may also be a third-order or third-order structure.
第3A圖係繪示本發明之散熱結構2之第二實施例之俯視示意圖，第3B圖係依據第3A圖之剖面線BB繪示本發明之散熱結構2之一態樣之剖視示意圖。第3A-3B圖與上述第2A-2B圖之散熱結構2大致相同，其主要差異如下： 在第3A-3B圖中，該結合加強層21係形成於該第一凸部204上之部分表面上，並包括複數方形且互相間隔之圖案，該方形可為長方形或正方形。但在其他實施例中，該結合加強層21亦可包括複數口字形、環狀、菱形或各種不同的圖案。當進行封裝時，該結合加強層21之每一圖案可對應至半導體封裝件之每一晶片(圖中未繪示)。 3A is a schematic plan view showing a second embodiment of the heat dissipation structure 2 of the present invention, and FIG. 3B is a cross-sectional view showing an aspect of the heat dissipation structure 2 of the present invention according to a section line BB of FIG. 3A. The 3A-3B diagram is substantially the same as the heat dissipation structure 2 of the above 2A-2B diagram, and the main differences are as follows: In the 3A-3B diagram, the bonding reinforcing layer 21 is formed on a part of the surface of the first convex portion 204, and includes a plurality of square and spaced patterns, which may be rectangular or square. However, in other embodiments, the bonding reinforcement layer 21 may also include a plurality of chevrons, rings, diamonds, or various patterns. Each of the bonding enhancement layers 21 may correspond to each of the semiconductor packages (not shown) when packaged.
第3B'圖係依據第3A圖之剖面線BB繪示本發明之散熱結構2之另一態樣之剖視示意圖。第3B'圖與上述第3B圖之散熱結構2大致相同，其主要差異如下：在第3B'圖中，該階部203係為三階之結構。該散熱片20之第一凸部204上可形成有複數第二凸部205，該些第二凸部205之間形成有溝槽209，該結合加強層21形成於該些第二凸部205之表面上。 FIG. 3B is a cross-sectional view showing another aspect of the heat dissipation structure 2 of the present invention according to a section line BB of FIG. 3A. The 3B' diagram is substantially the same as the heat dissipation structure 2 of the above-described 3B diagram, and the main difference is as follows: In the 3B' diagram, the step portion 203 is a third-order structure. A plurality of second protrusions 205 may be formed on the first protrusions 204 of the heat sink 20 , and a trench 209 is formed between the second protrusions 205 . The combination reinforcement layer 21 is formed on the second protrusions 205 . On the surface.
另外，在第3B圖中，該散熱片20之第一凸部204之表面至凹部206之表面之厚度為H1。但在第3B'圖中，該散熱片20之第二凸部205之表面至凹部206之表面之厚度為H2，且該厚度H2大於該厚度H1。當封裝完成時，該第二凸部205可使該散熱片20更接近晶片，藉以提升該散熱片20對該晶片之散熱效果(圖中未繪示)。 Further, in FIG. 3B, the thickness of the surface of the first convex portion 204 of the heat sink 20 to the surface of the concave portion 206 is H1. However, in FIG. 3B', the surface of the second convex portion 205 of the heat sink 20 has a thickness H2 to the surface of the concave portion 206, and the thickness H2 is greater than the thickness H1. When the package is completed, the second protrusion 205 can bring the heat sink 20 closer to the wafer, thereby improving the heat dissipation effect of the heat sink 20 on the chip (not shown).
第4A圖係繪示本發明之散熱結構2之第三實施例之俯視示意圖，第4B圖係依據第4A圖之剖面線CC繪示本發明之散熱結構2之一態樣之剖視示意圖，第4B'圖係依據第4A圖之剖面線CC繪示本發明之散熱結構2之另一態樣之剖視示意圖。第4A-4C圖與上述第3A-3C圖之散熱結 構2大致相同，其主要差異如下：在第4A-4B圖中，該結合加強層21係包括複數口字形或環狀之圖案。而在第4C圖中，該結合加強層21係形成於該些第二凸部205之表面之周圍上。 4A is a top plan view showing a third embodiment of the heat dissipation structure 2 of the present invention, and FIG. 4B is a cross-sectional view showing an aspect of the heat dissipation structure 2 of the present invention according to a section line CC of FIG. 4A. 4B' is a cross-sectional view showing another aspect of the heat dissipation structure 2 of the present invention according to a section line CC of FIG. 4A. 4A-4C and the above 3A-3C heat dissipation junction The structure 2 is substantially the same, and the main difference is as follows: In the 4A-4B diagram, the bonding reinforcing layer 21 includes a plurality of chevron or ring patterns. In FIG. 4C, the bonding reinforcing layer 21 is formed on the periphery of the surfaces of the second convex portions 205.
第5A圖係繪示本發明之散熱結構2之第四實施例之俯視示意圖，第5B圖係依據第5A圖之剖面線DD繪示本發明之散熱結構2之一態樣之剖視示意圖，第5B'圖係依據第5A圖之剖面線DD繪示本發明之散熱結構2之另一態樣之剖視示意圖。第5A-5C圖與上述第3A-3C圖之散熱結構2大致相同，其主要差異如下：在第5A-5B圖中，該結合加強層21係包括複數由菱形互相間隔排列之圖案。而在第5C圖中，該些圖案係分別形成於該些第二凸部205之部分表面上。 5A is a top plan view showing a fourth embodiment of the heat dissipation structure 2 of the present invention, and FIG. 5B is a cross-sectional view showing an aspect of the heat dissipation structure 2 of the present invention according to a section line DD of FIG. 5A. FIG. 5B is a cross-sectional view showing another aspect of the heat dissipation structure 2 of the present invention according to a section line DD of FIG. 5A. 5A-5C is substantially the same as the heat dissipation structure 2 of the above-mentioned 3A-3C diagram, and the main difference is as follows: In the 5A-5B diagram, the bonding reinforcement layer 21 includes a plurality of patterns which are arranged at intervals by diamonds. In FIG. 5C, the patterns are formed on portions of the second protrusions 205, respectively.
第6A圖至第6F圖係繪示本發明之半導體封裝件3及其製法之第一實施例之剖視示意圖。 6A to 6F are schematic cross-sectional views showing a first embodiment of the semiconductor package 3 of the present invention and a method of manufacturing the same.
如第6A圖所示，先提供半導體裝置30與模具之上模41。該半導體裝置30可具有基板31、複數晶片32、黏著層33與複數銲線34，該晶片32係藉由該黏著層33設置於該基板31上，並藉由該銲線34電性連接該基板31，但不以此為限。在其他實施例中，該半導體裝置30亦可具有其他的元件或為各種不同的結構。 As shown in Fig. 6A, the semiconductor device 30 and the mold upper mold 41 are first provided. The semiconductor device 30 can have a substrate 31, a plurality of wafers 32, an adhesive layer 33 and a plurality of bonding wires 34. The wafer 32 is disposed on the substrate 31 by the adhesive layer 33, and is electrically connected by the bonding wire 34. The substrate 31 is not limited thereto. In other embodiments, the semiconductor device 30 can have other components or be of a variety of different configurations.
接著，將該半導體裝置30以其基板31設置於該上模41之下側，使該晶片32朝向該基板31之下方。 Next, the semiconductor device 30 is disposed on the lower side of the upper mold 41 with its substrate 31 such that the wafer 32 faces the lower side of the substrate 31.
如第6B圖所示，提供散熱結構2、離型膜43與模具 之下模42。該散熱結構2係具有散熱片20與結合加強層21，該散熱片20可具有周緣201、相對之第一側202a與第二側202b，該周緣201、第一側202a與第二側202b分別形成有階部203、第一凸部204及凹部206，該結合加強層21係形成於該第一側202a之表面上。 As shown in FIG. 6B, the heat dissipation structure 2, the release film 43 and the mold are provided. Lower mold 42. The heat dissipating structure 2 has a heat sink 20 and a bonding reinforcing layer 21, and the heat sink 20 may have a circumference 201, a first side 202a and a second side 202b opposite to each other, and the circumference 201, the first side 202a and the second side 202b respectively A step portion 203, a first convex portion 204, and a concave portion 206 are formed, and the bonding reinforcing layer 21 is formed on a surface of the first side 202a.
在本實施例中，該結合加強層21係形成於該第一凸部204之表面上。但在其他實施例中，例如第3B'圖所示，該散熱片20之第一凸部204上可形成有複數第二凸部205，該些第二凸部205之間形成有溝槽209，該結合加強層21形成於該些第二凸部205之表面上。當封裝完成時，該第二凸部205可使該散熱片20更接近該晶片32，藉以提升該散熱片20對該晶片32之散熱效果。 In the embodiment, the bonding reinforcing layer 21 is formed on the surface of the first convex portion 204. In other embodiments, for example, as shown in FIG. 3B′, a plurality of second protrusions 205 may be formed on the first protrusions 204 of the heat sink 20 , and a trench 209 is formed between the second protrusions 205 . The bonding reinforcing layer 21 is formed on the surfaces of the second protrusions 205. When the package is completed, the second protrusion 205 can bring the heat sink 20 closer to the wafer 32, thereby improving the heat dissipation effect of the heat sink 20 on the wafer 32.
接下來，將離型膜43設置於該下模42之容置空間422內，使該離型膜43黏合於該下模42之底部、側壁及頂面等表面。 Next, the release film 43 is placed in the accommodating space 422 of the lower mold 42, and the release film 43 is bonded to the bottom, the side wall, and the top surface of the lower mold 42.
然後，依據該散熱片20之導角的位置，將該散熱結構2設置及定位於該容置空間422之底部之離型膜43上，使該散熱片20之部分階部203黏合於該離型膜43上。 Then, according to the position of the lead angle of the heat sink 20, the heat dissipation structure 2 is disposed and positioned on the release film 43 at the bottom of the accommodating space 422, so that part of the step 203 of the heat sink 20 is adhered to the distance On the type film 43.
如第6C圖所示，將封裝膠體35注入該下模42之容置空間422內，並將該晶片32對準該結合加強層21，再使該上模41密合於該下模42，俾使該封裝膠體35形成於該半導體裝置30與該散熱結構2之間，以包覆該基板31、晶片32、黏著層33、銲線34、第一凸部204、結合加強層21與未黏合之階部203。 As shown in FIG. 6C, the encapsulant 35 is injected into the accommodating space 422 of the lower mold 42 and the wafer 32 is aligned with the bonding reinforcing layer 21, and the upper mold 41 is adhered to the lower mold 42. The encapsulant 35 is formed between the semiconductor device 30 and the heat dissipation structure 2 to cover the substrate 31, the wafer 32, the adhesive layer 33, the bonding wires 34, the first protrusions 204, and the bonding reinforcement layer 21 and The step 203 of bonding.
由於該散熱片20之部分階部203係黏合於該離型膜43，故該階部203能防止該散熱結構2受該封裝膠體35流動而造成偏移，並使該封裝膠體35無法溢出或滲透至該散熱片20之凹部206之表面，藉此避免因溢膠而導致該散熱片20之外觀不佳。 Since the portion of the step 203 of the heat sink 20 is adhered to the release film 43 , the step 203 can prevent the heat dissipation structure 2 from being displaced by the flow of the encapsulant 35 and prevent the encapsulant 35 from overflowing or The surface of the recess 206 of the heat sink 20 is infiltrated, thereby preventing the appearance of the heat sink 20 from being poor due to overflow.
再來，自第一方向44(由內往外)對該封裝膠體35進行抽真空，以將該模具或該封裝膠體35內之氣體排出外部。 Further, the encapsulant 35 is evacuated from the first direction 44 (from the inside to the outside) to discharge the gas in the mold or the encapsulant 35 to the outside.
如第6D圖所示，藉由該下模42之壓縮件421，自第二方向45(由下往上)對該封裝膠體35進行壓縮，以使該封裝膠體35形成固態之封裝膠體35並壓縮至預定之厚度。於其他實施例中，該散熱結構2亦可設置於模具之上模中，而該半導體裝置30以其基板31設置於下模中，並藉由轉移成型(transfer molding)形成封裝膠體於該半導體裝置30與該散熱結構2之間。 As shown in FIG. 6D, the encapsulant 35 is compressed from the second direction 45 (from bottom to top) by the compressing member 421 of the lower mold 42 so that the encapsulant 35 forms a solid encapsulant 35 and Compressed to a predetermined thickness. In other embodiments, the heat dissipation structure 2 may also be disposed in the upper mold of the mold, and the semiconductor device 30 is disposed in the lower mold with the substrate 31 thereof, and forms an encapsulant on the semiconductor by transfer molding. The device 30 is disposed between the heat dissipation structure 2.
如第6E圖所示，移除該上模41、下模42與離型膜43，並藉由切割工具沿著各切割線SS進行切單作業，以形成複數半導體封裝件3。 As shown in FIG. 6E, the upper mold 41, the lower mold 42 and the release film 43 are removed, and a singulation operation is performed along each of the cutting lines SS by a cutting tool to form a plurality of semiconductor packages 3.
如第6F圖所示，係顯示切單後之半導體封裝件3，且該基板31上植設有複數銲球36。 As shown in FIG. 6F, the semiconductor package 3 after singulation is shown, and a plurality of solder balls 36 are implanted on the substrate 31.
本發明另提供一種半導體封裝件3，如第6F圖所示。該半導體封裝件3可為球柵陣列封裝體、薄型球柵陣列封裝體或各種不同的封裝體，並包括半導體裝置30、封裝膠體35以及散熱結構2。 The present invention further provides a semiconductor package 3 as shown in Fig. 6F. The semiconductor package 3 can be a ball grid array package, a thin ball grid array package or a variety of different packages, and includes a semiconductor device 30 , an encapsulant 35 , and a heat dissipation structure 2 .
該半導體裝置30係具有基板31、晶片32、黏著層33、 銲線34與銲球36，該晶片32藉由該黏著層33設置於該基板31之上表面，並藉由該銲線34電性連接該基板31，該銲球36係植設於該基板31之下表面，但不以此為限。在其他實施例中，該半導體裝置30亦可具有其他的元件，或為各種不同的結構。 The semiconductor device 30 has a substrate 31, a wafer 32, an adhesive layer 33, a bonding wire 34 and a solder ball 36. The wafer 32 is disposed on the upper surface of the substrate 31 by the adhesive layer 33, and is electrically connected to the substrate 31 by the bonding wire 34. The solder ball 36 is implanted on the substrate. 31 below the surface, but not limited to this. In other embodiments, the semiconductor device 30 can have other components or a variety of different configurations.
該封裝膠體35係形成於該半導體裝置30上，並包覆該基板31、晶片32、黏著層33與銲線34。 The encapsulant 35 is formed on the semiconductor device 30 and covers the substrate 31, the wafer 32, the adhesive layer 33, and the bonding wires 34.
該散熱結構2係形成於該封裝膠體35上，並具有散熱片20與結合加強層21。該結合加強層21形成於該散熱片20之至少部分表面上，且位於該散熱片20與該封裝膠體35之間。該結合加強層21可為防焊層，並藉由網版印刷或其他方式塗佈於該散熱片20之表面上，以構成至少一方形之圖案。但在其他實施例中，該結合加強層21亦可構成至少一口字形、環狀、菱形或各種不同的圖案。 The heat dissipation structure 2 is formed on the encapsulant 35 and has a heat sink 20 and a bonding reinforcement layer 21. The bonding reinforcement layer 21 is formed on at least a portion of the surface of the heat sink 20 and is located between the heat sink 20 and the encapsulant 35. The bonding reinforcing layer 21 may be a solder resist layer and applied to the surface of the heat sink 20 by screen printing or the like to form at least one square pattern. However, in other embodiments, the bonding reinforcement layer 21 may also be formed in at least one letter shape, a ring shape, a diamond shape or a variety of different patterns.
第7圖係繪示本發明之半導體封裝件3之第二實施例之剖視示意圖。第7圖與上述第6F圖之半導體封裝件3大致相同，其主要差異如下：該結合加強層21係為口字形或環狀之圖案，並形成於該散熱片20之表面之周圍上。 Figure 7 is a cross-sectional view showing a second embodiment of the semiconductor package 3 of the present invention. The seventh drawing is substantially the same as the semiconductor package 3 of the above-mentioned FIG. 6F, and the main difference is as follows: the bonding reinforcing layer 21 is a pattern of a square shape or a ring shape and is formed on the periphery of the surface of the heat sink 20.
此外，在其他實施例中，如第5A圖所示，該結合加強層21可為菱形之圖案，並間隔排列於該散熱片20之表面上。該結合加強層21亦可為各種不同的圖案，並規則或不規則排列於該散熱片20之表面上。 In addition, in other embodiments, as shown in FIG. 5A, the bonding reinforcing layer 21 may be a diamond-shaped pattern and arranged on the surface of the heat sink 20 at intervals. The bonding reinforcing layer 21 may also be in various patterns and regularly or irregularly arranged on the surface of the heat sink 20.
由上可知，本發明之散熱結構、半導體封裝件及其製 法，主要係在散熱片之周緣、第一側與第二側分別形成有階部、凹部與第一凸部，亦可在該第一凸部形成有第二凸部，且將結合加強層形成於該第一凸部或該第二凸部之至少部分表面上。藉此，本發明能提升該晶片之散熱效果，並強化該散熱片與該封裝膠體間之結合力，以避免進行切單作業時產生剝離之情形。 It can be seen from the above that the heat dissipation structure, the semiconductor package and the system thereof of the present invention The method is mainly characterized in that a step portion, a concave portion and a first convex portion are respectively formed on the periphery of the heat sink, the first side and the second side, and a second convex portion may be formed on the first convex portion, and the reinforcing layer is combined Formed on at least part of the surface of the first protrusion or the second protrusion. Thereby, the invention can improve the heat dissipation effect of the wafer, and strengthen the bonding force between the heat sink and the encapsulant to avoid the occurrence of peeling during the singulation operation.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
2‧‧‧散熱結構 2‧‧‧heating structure
20‧‧‧散熱片 20‧‧‧ Heat sink
201‧‧‧周緣 201‧‧‧ Periphery
203‧‧‧階部 203‧‧‧
204‧‧‧第一凸部 204‧‧‧First convex
206‧‧‧凹部 206‧‧‧ recess
21‧‧‧結合加強層 21‧‧‧Combined reinforcement
30‧‧‧半導體裝置 30‧‧‧Semiconductor device
31‧‧‧基板 31‧‧‧Substrate
32‧‧‧晶片 32‧‧‧ wafer
33‧‧‧黏著層 33‧‧‧Adhesive layer
34‧‧‧銲線 34‧‧‧welding line
35‧‧‧封裝膠體 35‧‧‧Package colloid
41‧‧‧上模 41‧‧‧上模
42‧‧‧下模 42‧‧‧Down
421‧‧‧壓縮件 421‧‧‧Compressed parts
43‧‧‧離型膜 43‧‧‧ release film
44‧‧‧第一方向 44‧‧‧First direction
45‧‧‧第二方向 45‧‧‧second direction
Claims (17)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102108970A TW201436128A (en) | 2013-03-14 | 2013-03-14 | Heat-dissipating structure, semiconductor package and fabricating method thereof |
| CN201310089577.XA CN104051373B (en) | 2013-03-14 | 2013-03-20 | Heat dissipation structure and manufacturing method of semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
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| TW102108970A TW201436128A (en) | 2013-03-14 | 2013-03-14 | Heat-dissipating structure, semiconductor package and fabricating method thereof |
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| TW201436128A true TW201436128A (en) | 2014-09-16 |
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| TW (1) | TW201436128A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9875991B2 (en) | 2015-06-05 | 2018-01-23 | Delta Electronics, Inc. | Package module having exposed heat sink |
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| TWI695970B (en) * | 2015-09-17 | 2020-06-11 | 日月光半導體製造股份有限公司 | Optical device, electrical device and passive optical component |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001077278A (en) * | 1999-10-15 | 2001-03-23 | Amkor Technology Korea Inc | Semiconductor package, lead frame thereof, manufacture of semiconductor package and mold thereof |
| KR20010037247A (en) * | 1999-10-15 | 2001-05-07 | 마이클 디. 오브라이언 | Semiconductor package |
| DE10129388B4 (en) * | 2001-06-20 | 2008-01-10 | Infineon Technologies Ag | Method for producing an electronic component |
| JP3888439B2 (en) * | 2002-02-25 | 2007-03-07 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
| JP5280102B2 (en) * | 2008-05-26 | 2013-09-04 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN101980359A (en) * | 2010-09-07 | 2011-02-23 | 日月光半导体制造股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN202996814U (en) * | 2012-11-30 | 2013-06-12 | 华东科技股份有限公司 | Heat-dissipation type semiconductor packaging structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9875991B2 (en) | 2015-06-05 | 2018-01-23 | Delta Electronics, Inc. | Package module having exposed heat sink |
| US10204882B2 (en) | 2015-06-05 | 2019-02-12 | Delta Electronics, Inc. | Stacked package module having an exposed heat sink surface from the packaging |
Also Published As
| Publication number | Publication date |
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| CN104051373B (en) | 2019-04-02 |
| CN104051373A (en) | 2014-09-17 |
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