TW201640635A - Package structure and manufactruing method thereof - Google Patents

Abstract

A package structure includes a substrate, a chip and an encapsulant. The substrate includes a core layer having first and second surfaces, a solder resist layer, first and second patterned metal layers respectively disposed on the first and second surfaces. The second patterned metal layer includes bond pads having a first thickness and a metal pad having a maximum thickness larger than the first thickness. The solder resist layer covers the second surface and partially exposes the bond pads and the metal pad. A maximum thickness of the solder resist layer equals the maximum thickness of the metal pad. The chip disposed on the first surface is electrically connected to the first patterned metal layer. A distribution area of the metal pad on the second surface overlaps with a footprint area of the chip on the second surface. The encapsulant covers the chip and the first patterned metal layer.

Description

Package structure and manufacturing method thereof

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a package structure of a wafer and a method of fabricating the same.

Integrated Circuits (ICs) can almost be said to be ubiquitous in our daily lives. In order to meet the requirements of high-speed processing, multi-function, integration, small size and light weight of electronic devices, semiconductor process technology is also constantly moving towards miniaturization and high density, and the circuit design of the substrate also follows the function of the chip. The development and packaging needs are also complicated. However, with the miniaturization of the substrate and the complication of its wiring, the existing substrate has encountered many new problems in the manufacturing process. As the number of signal contacts of electronic devices has gradually increased, the early use of a pin grid array (PGA) as a signal transmission interface has become insufficient for use, thus developing a Land Grid Array (LGA). As a signal transmission interface for the substrate. The contacts used in the LGA type package structure are the pad-shaped terminals arranged in many planar arrays on the bottom surface of the LGA substrate.

2 is a cross-sectional view showing a conventional LGA type package structure. Figure. The package structure 50 includes a substrate 500, a solder resist layer 550, a wafer 600, and an encapsulant 700. The substrate 500 includes a core layer 510, a first patterned metal layer 520, and a second patterned metal layer 530. The first patterned metal layer 520 and the second patterned metal layer 530 are respectively disposed on the upper and lower sides of the core layer 510. surface. The second metal layer 530 can include a plurality of pads 532 having a signal transmission function and a metal pad 534. The wafer 600 is disposed on the upper surface of the core layer 510 and electrically connected to the first patterned metal layer 520, and the solder resist layer 550 covers the lower surface of the core layer 510 and has a plurality of openings 550a respectively exposing the second portion The pad 532 and the metal pad 534 of the patterned metal layer 530, such that the pad 532 can serve as a pad contact for electrically connecting the package structure 50 to external electronic components, and the metal pad 534 is located below the wafer 600. The wafer 600 can be supported on the one hand, and can be used as a heat dissipation pad. In order to effectively dissipate the heat energy generated by the wafer 600 during operation, the solder mask 550 partially exposes the opening 550a of the metal pad 534 as generally as possible to make the metal pad The exposed area of 534 is as wide as possible.

However, the wafer 600 disposed on the upper surface of the core layer 510 is being played In the wire processing or encapsulation process, the thickness of the solder resist layer 550 on the lower surface of the core layer 510 and the metal pad 534 under the wafer 600 are different, that is, between the bottom surface of the solder resist layer 550 and the bottom surface of the metal pad 534. With a height difference, the solder resist layer 550 provides support at the bottom surface, but does not provide support at the opening 550a of the exposed metal pad 534, causing the substrate 500 to be subjected to the underlying stress of the wire bonding or sealing. The uneven support force produces a warpage phenomenon, which in turn causes the wafer 600 to warp due to the positive instantaneous pressure and the underlying support member (ie, the substrate 500). The deformation, even the phenomenon of brittle cracking as shown in FIG. 2, causes damage to the wafer 600, reducing the reliability of the conventional package structure 50.

The invention provides a package structure and a manufacturing method thereof, which can improve the structural reliability of the package structure and the process yield.

The package structure of the present invention comprises a substrate, a wafer and an encapsulant. The substrate includes a core layer, a first patterned metal layer, a second patterned metal layer, and a solder resist layer. The core layer includes a first surface and a second surface opposite the first surface. The first patterned metal layer is disposed on the first surface. The second patterned metal layer is disposed on the second surface. The second patterned metal layer includes a plurality of pads and a metal pad. The pad has a first thickness and the maximum thickness of the metal pad is greater than the first thickness.

The solder resist layer covers the second surface and has a first opening and a plurality of second openings. The first opening partially exposes the metal pad, and the second opening partially exposes the pad. The maximum thickness of the solder mask is equal to the maximum thickness of the metal pad. The wafer is disposed on the first surface and electrically connected to the first patterned metal layer. A distribution of the first opening at least partially overlaps an orthographic projection of the wafer on the second surface. The encapsulant is disposed on the first surface and covers the wafer and the first patterned metal layer.

The method of fabricating the package structure of the present invention includes the following steps. First, a substrate is provided. The substrate includes a core layer, a first metal layer, and a second metal layer. The core layer includes a first surface and a second surface. The first metal layer and the second metal layer are respectively disposed on the first surface and the second surface. Next, the first metal layer A patterning process is performed with the second metal layer to form a first patterned metal layer and a second patterned metal layer, respectively. The second patterned metal layer includes a plurality of pads and a metal pad. The pad has a first thickness and the maximum thickness of the metal pad is greater than the first thickness. Next, a solder resist layer is formed. The solder resist layer covers the second surface and has a first opening and a plurality of second openings. The first opening partially exposes the metal pad, and the second opening partially exposes the pad. The maximum thickness of the solder mask is equal to the maximum thickness of the metal pad. Next, the wafer is placed on the first surface. The wafer is electrically connected to the first patterned metal layer, and a distribution range of the first opening at least partially overlaps with an orthographic projection of the wafer on the second surface. Next, an encapsulant is formed on the first surface. The encapsulant covers the wafer and the first patterned metal layer.

Based on the above, the package structure of the present invention and the manufacturing method thereof are through two segments The process of forming a second patterned metal layer having a plurality of pads and a metal pad, wherein the maximum thickness of the metal pad is greater than the thickness of the pad and is equivalent to the maximum thickness of the solder resist layer such that the metal pad faces away from the second The bottom surface of the surface and the lower surface of the solder resist layer facing away from the second surface are coplanar. In this way, when the wire bonding and the sealing process are performed, by the coplanar configuration of the bottom surface of the metal pad and the lower surface of the solder resist layer, uniform support can be provided when the substrate and the wafer are subjected to the forward stress, thereby avoiding stress Concentration of substrate warpage and wafer cracking caused by the edge of the metal pad (ie, at the boundary of the first opening). Therefore, the present invention can effectively improve the structural reliability of the package structure and the yield of the process.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

10, 50‧‧‧Package structure

100, 500‧‧‧ substrate

105‧‧‧Substrate

110, 510‧‧‧ core layer

112‧‧‧ first surface

114‧‧‧ second surface

120, 520‧‧‧ first patterned metal layer

120a‧‧‧First metal layer

130, 530‧‧‧Second patterned metal layer

130a‧‧‧Second metal layer

132, 532‧‧‧ solder pads

132a‧‧‧pad parts

134, 534‧‧‧Metal pads

134a‧‧‧Metal pad

134b‧‧‧ Main Body

134c‧‧‧Flange

134d‧‧‧ bottom surface

136‧‧‧opening

140‧‧‧Connecting column

150, 550‧‧‧ solder mask

150a‧‧‧first opening

150b‧‧‧second opening

152‧‧‧ lower surface

200, 600‧‧‧ wafer

300, 700‧‧‧Package colloid

400‧‧‧ wire

550a‧‧‧ openings

T1‧‧‧first thickness

T2, T3‧‧‧ maximum thickness

A1‧‧‧ distribution range

P1‧‧‧ orthographic projection

1A-1F are schematic cross-sectional views showing a process of fabricating a package structure in accordance with an embodiment of the invention.

2 is a cross-sectional view showing a conventional LGA type package structure.

The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the embodiments of the invention. The directional terms mentioned in the following embodiments, such as "upper", "lower", "front", "back", "left", "right", etc., are only directions referring to the additional schema. Therefore, the directional terminology used is for the purpose of illustration and not limitation. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

1A-1F are schematic cross-sectional views showing a process of fabricating a package structure in accordance with an embodiment of the invention. The manufacturing method of the package structure of this embodiment includes the following steps. First, a substrate 105 as shown in FIG. 1A is provided. The substrate 105 includes a core layer 110, a first metal layer 120a, and a second metal layer 130a. The core layer 110 includes a first surface 112 and a second surface 114 opposite to the first surface 112. The metal layer 120a and the second metal layer 130a are disposed on the first surface 112 and the second surface 114, respectively. In addition, the substrate 105 further includes a plurality of via posts 140 formed by first forming a plurality of vias in the core layer 110, wherein the vias may extend through the core layer 110, for example, to communicate the first metal layer 120a with the second metal layer. 130a. Then, the via hole is subjected to an electroplating process to form a plurality of via posts 140, wherein the via posts 140 are electrically connected to the first metal layer 120a and the second metal layer 130a.

Next, please refer to FIG. 1B and FIG. 1C simultaneously, for the first metal layer 120a. A patterning process is performed with the second metal layer 130a to form a first patterned metal layer 120 and a second patterned metal layer 130 as shown in FIG. 1C, respectively. In detail, the step of patterning the second metal layer 130a may include: first, performing a first patterning process on the second metal layer 130a to form a plurality of pads connected to each other as shown in FIG. 1B. The portion 132a and a metal pad portion 134a, wherein the thickness of the metal pad portion 134a is greater than the thickness of the pad portion 132a. Then, a second patterning process is performed on the second metal layer 130a to form a plurality of openings 136 between the metal pad portion 134a and the pad portion 132a and between the pad portions 132a to define The pads 132 and the metal pads 134 are separated from each other as shown in FIG. 1C. Moreover, the first metal layer 120a can be patterned at the same time to form the first patterned metal layer 120 as shown in FIG. 1C. In the present embodiment, the pad 132 has a first thickness T1, and the maximum thickness T2 of the metal pad 134 is greater than the first thickness T1. Further, the metal pad 134 has a flange portion 134c and a body portion 134b. The flange portion 134c surrounds the body portion 134b, and the flange portion 134c has a first height relative to the second surface 114, and the first height That is, it is equal to the first thickness T1 of the pad 132; the body portion 134b has a second height relative to the second surface 114, which is equal to the maximum thickness T2 of the metal pad 134. In this embodiment, the patterning process performed on the first metal layer 120a may be performed simultaneously with the second patterning process performed on the second metal layer 130a. Of course, the invention is not limited thereto, and in other embodiments. Medium to the first metal The patterning process performed by layer 120a can also be performed separately from the second patterning process.

Next, referring to FIG. 1D, a solder resist layer 150 is formed. The solder resist layer 150 covers the second surface 114 and has a first opening 150a and a plurality of second openings 150b. The first opening 150a partially exposes the metal pad 134, and the second opening 150b exposes the pad 132 partially. Specifically, the solder resist layer 150 covers the flange portion 134c of the metal pad 134, and the first opening 150a exposes the bottom surface 134d of the body portion 134b facing away from the second surface 114. The maximum thickness T3 of the solder resist layer 150 is equal to the maximum thickness T2 of the metal pad 134. In other words, the bottom surface 134d of the body portion 134b of the metal pad 134 and the lower surface 152 of the solder resist layer 150 facing away from the second surface 114 are coplanar. In addition, in the present embodiment, the solder resist layer 150 further covers the first surface 112 of the core layer 110 and partially exposes the first patterned metal layer 120 as shown in FIG. 1D. Thus, the substrate 100 as shown in FIG. 1D is formed.

Next, referring to FIG. 1E , the wafer 200 is disposed on the first surface 112 and electrically connected to the wafer 200 and the first patterned metal layer 120 . In detail, the wafer 200 is disposed on the solder resist layer 150 on the first surface 112 and electrically connected to the first patterned metal layer 120 exposed by the solder resist layer 150. In this embodiment, the wafer 200 can be electrically connected to the first patterned metal layer 120 through a plurality of wires 400, that is, electrically connected to the substrate 100 by wire bonding. Of course, the present invention is not limited thereto. this. In other embodiments, the wafer 200 can also be electrically connected to the substrate 100 through flip chip bonding. In particular, a distribution range A1 of the first opening 150a that partially exposes the metal pad 134 at least partially overlaps an orthographic projection P1 of the wafer 200 on the second surface 114. More specifically, the distribution of the first opening 150a The perimeter A1 can be located within the range of the orthographic projection P1 of the wafer 200 on the second surface 114 as shown in FIG. 1E, that is, the orthographic projection P1 of the wafer 200 on the second surface 114 can completely cover the distribution of the first opening 150a. Range A1. In this case, the bottom surface 134d of the main body portion 134b of the metal pad 134 and the lower surface 152 of the solder resist layer 150 are coplanar, so that when the substrate 100 is subjected to the forward stress, the supporting force under the substrate is relatively uniform. The situation in which the stress of the substrate 100 is warped and the wafer 200 is cracked due to stress concentration at the edge of the metal pad 134 (ie, at the boundary of the first opening 150a) is avoided. In this embodiment, the metal pad 134 can be a heat dissipation pad, so that the thermal energy generated by the wafer 200 can be dissipated to the outside through the metal pad 134.

Next, referring to FIG. 1F , an encapsulant 300 is formed on the first surface 112 , wherein the encapsulant 300 covers the wafer 200 and the first patterned metal layer 120 . When the encapsulant 300 is formed to cover the wafer 200, the substrate 100 and the wafer 200 are subjected to the forward stress applied by the encapsulant 300. At this time, the bottom surface 134d of the metal pad 134 and the lower surface 152 of the solder resist 150 are common. The planar configuration can provide uniform support of the substrate 100, thereby avoiding the phenomenon that stress concentration causes the substrate 100 to warp and the wafer 200 to crack. As such, the fabrication of the package structure 10 is substantially complete.

Structurally, the package structure 10 formed by the above manufacturing method can be The substrate 100, the wafer 200, and the encapsulant 300 are included as shown in FIG. 1F. The substrate 100 includes a core layer 110, a first patterned metal layer 120, a second patterned metal layer 130, and a solder resist layer 150. The core layer 110 includes opposing first and second surfaces 112, 114. The first patterned metal layer 120 and the second patterned metal layer 130 are disposed on the first surface 112 and the second surface 114, respectively. The second patterned metal layer 130 includes a plurality of The pad 132 and a metal pad 134, wherein the maximum thickness T2 of the metal pad 134 is greater than the first thickness T1 of the pad 132, and the solder resist layer 150 covers the second surface 114, and has a first opening 150a and a plurality of The second opening 150b, wherein the first opening 150a partially exposes the metal pad 134, and the second opening 150b exposes the pad 132 partially. The maximum thickness T3 of the solder resist layer 150 is equal to the maximum thickness T2 of the metal pad 134. That is, the bottom surface 134d of the metal pad 134 facing away from the second surface 114 and the lower surface 152 of the solder resist layer 150 facing away from the second surface 114 are coplanar. The wafer 200 is disposed on the first surface 112 and electrically connected to the first patterned metal layer 120. The distribution range A1 of the first opening 150a at least partially overlaps the orthographic projection P1 of the wafer 200 on the second surface 114. The encapsulant 300 is formed on the first surface 112 and covers the wafer 200 and the first patterned metal layer 120.

In summary, the package structure of the present invention and the manufacturing method thereof are through two segments The process of forming a second patterned metal layer having a plurality of pads and a metal pad, wherein the maximum thickness of the metal pad is greater than the thickness of the pad and is equivalent to the maximum thickness of the solder resist layer such that the metal pad faces away from the second The bottom surface of the surface and the lower surface of the solder resist layer facing away from the second surface are coplanar. In this way, when the wire bonding and the sealing process are performed, by the coplanar configuration of the bottom surface of the metal pad and the lower surface of the solder resist layer, uniform support can be provided when the substrate and the wafer are subjected to the forward stress, thereby avoiding stress The problem of concentration can further reduce the occurrence of substrate warpage and wafer cracking. Therefore, the present invention can effectively improve the structural reliability of the package structure and the yield of the process.

Although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. Invention, any person having ordinary knowledge in the art, without departing from the invention In the spirit and scope, the scope of protection of the present invention is subject to the definition of the appended patent application.

10‧‧‧Package structure

100‧‧‧Substrate

110‧‧‧ core layer

120‧‧‧First patterned metal layer

130‧‧‧Second patterned metal layer

132‧‧‧ solder pads

134‧‧‧Metal pad

134d‧‧‧ bottom surface

140‧‧‧Connecting column

150‧‧‧ solder mask

150a‧‧‧first opening

150b‧‧‧second opening

152‧‧‧ lower surface

200‧‧‧ wafer

300‧‧‧Package colloid

400‧‧‧ wire

T1‧‧‧first thickness

T2, T3‧‧‧ maximum thickness

A1‧‧‧ distribution range

P1‧‧‧ orthographic projection

Claims (14)

A package structure comprising: a substrate comprising: a core layer comprising a first surface and a second surface opposite to the first surface; a first patterned metal layer disposed on the first surface; a second a patterned metal layer disposed on the second surface, the second patterned metal layer includes a plurality of pads and a metal pad, the pads having a first thickness, the maximum thickness of the metal pad being greater than the first thickness And a solder mask covering the second surface and having a first opening and a plurality of second openings, the first opening partially exposing the metal pad, and the second openings respectively partially exposing the pads The maximum thickness of the solder resist layer is equal to the maximum thickness of the metal pad; a wafer is disposed on the first surface and electrically connected to the first patterned metal layer, a distribution range of the first opening and the wafer An orthographic projection on the second surface at least partially overlaps; and an encapsulant disposed on the first surface and covering the wafer and the first patterned metal layer. The package structure of claim 1, wherein the metal pad has a flange portion and a body portion, the flange portion having a first height relative to the second surface, the first height being equal to the first A thickness, the body portion having a second height relative to the second surface, the second height being equal to a maximum thickness of the metal pad. The package structure of claim 2, wherein the solder resist layer covers the flange portion of the metal pad and the first opening exposes a bottom surface of the body portion facing away from the second surface, the bottom surface and The solder mask is coplanar away from the lower surface of the second surface. The package structure of claim 1, wherein the first opening has a distribution range within an orthographic projection of the wafer on the second surface. The package structure of claim 1, wherein the metal pad is a heat dissipation pad. The package structure of claim 1, wherein the solder resist layer covers the first surface and partially exposes the first patterned metal layer, the wafer is disposed on the solder resist layer and electrically connected The first patterned metal layer is formed. The package structure of claim 1, wherein the substrate further comprises a plurality of conductive pillars disposed on the core layer to electrically connect the first patterned metal layer and the second patterned metal layer. A method of fabricating a package structure includes: providing a substrate, the substrate comprising a core layer, a first metal layer, and a second metal layer, the core layer including an opposite first surface and a second surface The first metal layer and the second metal layer are respectively disposed on the first surface and the second surface; the first metal layer and the second metal layer are patterned to form a first patterned metal a layer and a second patterned metal layer, the second patterned metal layer comprising a plurality of pads and a metal pad, the pads having a first thickness, the gold The maximum thickness of the mat is greater than the first thickness; forming a solder resist layer covering the second surface and having a first opening and a plurality of second openings, the first opening partially exposing the metal pad The second openings respectively expose the pads, and the maximum thickness of the solder resist layer is equal to the maximum thickness of the metal pad; a wafer is disposed on the first surface, and the wafer is electrically connected to the first Patterning a metal layer, and a distribution of the first opening at least partially overlaps an orthographic projection of the wafer on the second surface; and forming an encapsulant on the first surface, the encapsulant covering the wafer and The first patterned metal layer. The method for fabricating a package structure according to claim 8 , wherein the step of performing the patterning process on the second metal layer further comprises: performing a first patterning process on the second metal layer to form each other Connecting a metal pad portion and a plurality of pad portions; and performing a second patterning process on the second metal layer to form a plurality of openings between the metal pad portion and the pad portions to define And the metal pads and the pads, wherein the metal pads have a flange portion and a body portion, the flange portion having a first height relative to the second surface, the first height being equal to the first A thickness, the body portion having a second height relative to the second surface, the second height being equal to a maximum thickness of the metal pad. The method of fabricating a package structure according to claim 9, wherein the solder resist layer covers the flange portion of the metal pad and the first opening exposes the body The portion faces away from the bottom surface of the second surface, the bottom surface being coplanar with the lower surface of the solder resist layer facing away from the second surface. The method of fabricating a package structure according to claim 8, wherein the first opening has a distribution range within an orthographic projection of the wafer on the second surface. The method for fabricating a package structure according to claim 8, wherein the metal pad is a heat dissipation pad. The method for fabricating a package structure according to claim 8, wherein the solder resist layer covers the first surface and partially exposes the first patterned metal layer, and the wafer is disposed on the solder resist layer and electrically The first patterned metal layer exposed by the connection. The method for fabricating a package structure according to claim 8 , further comprising: forming a plurality of through holes in the core layer, the through holes connecting the first metal layer and the second metal layer; The via hole performs an electroplating process to form a plurality of via posts electrically connected to the first metal layer and the second metal layer.