TW201830617A - Fan-out semiconductor package - Google Patents

Fan-out semiconductor package Download PDF

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TW201830617A
TW201830617A TW107116224A TW107116224A TW201830617A TW 201830617 A TW201830617 A TW 201830617A TW 107116224 A TW107116224 A TW 107116224A TW 107116224 A TW107116224 A TW 107116224A TW 201830617 A TW201830617 A TW 201830617A
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fan
layer
semiconductor package
hole
pattern
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TW107116224A
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TWI655726B (en
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李文熙
鄭注奐
鄭栗敎
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南韓商三星電機股份有限公司
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Priority claimed from KR1020160166951A external-priority patent/KR102016492B1/en
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Publication of TWI655726B publication Critical patent/TWI655726B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.

Description

扇出型半導體封裝Fan-out semiconductor package

[相關申請案的交叉引用][Cross reference to related applications]

本申請案主張2016年4月25日在韓國智慧財產局申請的韓國專利申請案第10-2016-0049830號、2016年9月12日申請的第10-2016-0117321號以及2016年12月8日申請的第10-2016-0166951號的優先權權益，上述申請案的全部揭露內容特此以引用的方式併入。This application claims Korean Patent Application No. 10-2016-0049830 filed with the Korea Intellectual Property Office on April 25, 2016, 10-2016-0117321 filed on September 12, 2016, and December 8, 2016 The priority rights and interests of No. 10-2016-0166951 filed in Japan, the entire disclosure content of the above application is hereby incorporated by reference.

本發明是關於一種半導體封裝，且更特定言之，是關於一種扇出型半導體封裝，其中連接端子可朝安置有半導體晶片的區之外延伸。The present invention relates to a semiconductor package, and more specifically, to a fan-out type semiconductor package in which connection terminals may extend outside the area where the semiconductor wafer is placed.

近來，與半導體晶片有關的技術開發的重要趨勢是減小半導體晶片的大小。因此，在封裝技術的領域中，根據對小型半導體晶片或其類似者的需求的快速增加，已需要具有緊密大小同時包含多個接腳的半導體封裝的實施。Recently, an important trend in technology development related to semiconductor wafers is to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, in accordance with the rapid increase in demand for small-sized semiconductor chips or the like, there has been a need for implementation of semiconductor packages having a compact size while containing multiple pins.

所建議的用以滿足如上文所描述的技術需求的一種類型的封裝技術為扇出型封裝。此類扇出型封裝具有緊密大小，且可允許藉由將連接端子向安置有半導體晶片的區之外重佈來實施多個接腳。One type of packaging technology proposed to meet the technical requirements as described above is a fan-out packaging. Such a fan-out package has a compact size and can allow multiple pins to be implemented by redistributing the connection terminals out of the area where the semiconductor chip is placed.

本發明的態樣可提供扇出型半導體封裝，其中可藉由簡單程序有效地耗散由半導體晶片產生的熱。The aspect of the present invention can provide a fan-out semiconductor package in which the heat generated by the semiconductor chip can be efficiently dissipated by a simple procedure.

根據本發明的態樣，可提供扇出型半導體封裝，其中圖案層形成於囊封半導體晶片的囊封體上且藉由穿透囊封體的通孔連接到半導體晶片的非主動表面。According to an aspect of the present invention, a fan-out semiconductor package can be provided in which a pattern layer is formed on an encapsulation body encapsulating a semiconductor chip and connected to a non-active surface of the semiconductor chip through a through hole penetrating the encapsulation body.

根據本發明的態樣，扇出型半導體封裝可包含：第一連接構件，其具有穿孔；半導體晶片，其安置於第一連接構件的穿孔中且具有其上安置有連接墊的主動表面及與主動表面對置的非主動表面；囊封體，其囊封第一連接構件及半導體晶片的非主動表面的至少部分；圖案層，其安置於囊封體上且覆蓋鄰近於半導體晶片的非主動表面的囊封體的至少部分；通孔，其穿透囊封體且將圖案層與半導體晶片的非主動表面彼此連接；以及第二連接構件，其安置於第一連接構件及半導體晶片的主動表面上且包含電連接至半導體晶片的連接墊的重佈層。According to an aspect of the present invention, the fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole of the first connection member and having an active surface on which a connection pad is disposed and a The active surface is opposed to the inactive surface; the encapsulation body encapsulates the first connection member and at least part of the inactive surface of the semiconductor wafer; the pattern layer is disposed on the encapsulation body and covers the inactive surface adjacent to the semiconductor wafer At least part of the surface encapsulation body; a through hole that penetrates the encapsulation body and connects the pattern layer and the non-active surface of the semiconductor wafer to each other; and a second connection member that is disposed on the first connection member and the active part of the semiconductor wafer A redistribution layer on the surface and containing connection pads electrically connected to the semiconductor wafer.

在下文中，將參考附圖詳細描述本發明中的例示性實施例。在附圖中，為了清楚起見，可放大或縮小組件的形狀、大小以及其類似者。Hereinafter, exemplary embodiments in the present invention will be described in detail with reference to the drawings. In the drawings, the shape, size, and the like of components may be enlarged or reduced for clarity.

本文中，下部側面、下部部分、下部表面以及其類似者用以指相關於圖式的橫截面的朝向扇出型半導體封裝的安裝表面的方向，而上部側面、上部部分、上部表面以及其類似者用以指方向的對置方向。然而，為了解釋方便，對此等方向加以界定，且申請專利範圍不受上文描述所定義的方向特定限制。Herein, the lower side surface, the lower portion, the lower surface, and the like are used to refer to the direction of the cross-section of the drawing toward the mounting surface of the fan-out semiconductor package, and the upper side surface, the upper portion, the upper surface, and the like Used to refer to the opposite direction of the direction. However, for convenience of explanation, these directions are defined, and the scope of patent application is not specifically limited by the directions defined in the above description.

在描述中的組件至另一組件的「連接」的涵義包含經由黏著層的間接連接及兩個組件之間的直接連接。另外，「電連接」意謂包含實體連接及實體斷開連接的概念。可理解，當藉由「第一」及「第二」指代元件時，元件並不受限於此。僅可出於將元件與其他元件區分的目的使用「第一」及「第二」，且可不限制元件的順序或重要性。在一些情況下，在不脫離本文中所闡述的申請專利範圍的範疇的情況下，第一元件可被稱作第二元件。類似地，第二元件亦可被稱作第一元件。The meaning of "connection" from a component to another component in the description includes indirect connection through an adhesive layer and direct connection between two components. In addition, "electrical connection" is meant to include the concepts of physical connection and physical disconnection. Understandably, when the elements are referred to by "first" and "second", the elements are not limited thereto. The "first" and "second" can only be used for the purpose of distinguishing the element from other elements, and the order or importance of the elements may not be limited. In some cases, the first element may be referred to as the second element without departing from the scope of the patent application scope set forth herein. Similarly, the second element may also be referred to as the first element.

本文中所使用的術語「例示性實施例」並不指同一例示性實施例，且提供例示性實施例以強調與另一例示性實施例的特定特徵或特性不同的特定特徵或特性。然而，認為能夠藉由整體或部分地與另一例示性實施例組合來實施本文中所提供的例示性實施例。舉例而言，特定例示性實施例中所描述的一個元件即使未在另一例示性實施例中加以描述，亦可被理解為與另一例示性實施例有關的描述，除非其中提供相反或矛盾的描述。The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, and the exemplary embodiment is provided to emphasize specific features or characteristics that are different from those of another exemplary embodiment. However, it is believed that the exemplary embodiments provided herein can be implemented by combining in whole or in part with another exemplary embodiment. For example, an element described in a specific exemplary embodiment can be understood as a description related to another exemplary embodiment even if it is not described in another exemplary embodiment, unless the contrary or contradiction is provided therein description of.

使用本文中所使用的術語僅為了描述例示性實施例而非限制本發明。在此情況下，除非在上下文中以其他方式解譯，否則單數形式包含複數形式。電子裝置 The terminology used herein is used only to describe exemplary embodiments and not to limit the present invention. In this case, unless otherwise interpreted in context, the singular form includes the plural form. Electronic device

圖1為說明電子裝置系統的實例的示意性方塊圖。FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

參看圖1，電子裝置1000可在其中容納母板1010。母板1010可包含實體連接或電連接至其的晶片相關組件1020、網路相關組件1030、其他組件1040以及其類似者。此等組件可連接至下文待描述的其他組件以形成各種信號線1090。Referring to FIG. 1, the electronic device 1000 may accommodate a motherboard 1010 therein. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, and the like that are physically or electrically connected thereto. These components may be connected to other components to be described below to form various signal lines 1090.

晶片相關組件1020可包含記憶體晶片，諸如揮發性記憶體（例如動態隨機存取記憶體（dynamic random access memory；DRAM））、非揮發性記憶體（例如唯讀記憶體（read only memory；ROM））、快閃記憶體或其類似者；應用程式處理器晶片，諸如中央處理器（例如中央處理單元（central processing unit；CPU））、圖形處理器（例如圖形處理單元（graphics processing unit；GPU））、數位信號處理器、密碼編譯處理器、微處理器、微控制器或其類似者；以及邏輯晶片，諸如類比/數位（analog-to-digital；ADC）轉換器、特殊應用積體電路（application-specific integrated circuit；ASIC）或其類似者。然而，晶片相關組件1020不限於此，而是亦可包含其他類型的晶片相關組件。另外，晶片相關組件1020可彼此組合。The chip-related components 1020 may include memory chips, such as volatile memory (such as dynamic random access memory (DRAM)) and non-volatile memory (such as read only memory; ROM) )), flash memory or the like; application processor chips, such as a central processing unit (such as a central processing unit (CPU)), a graphics processor (such as a graphics processing unit (GPU) )), digital signal processors, cryptographic processors, microprocessors, microcontrollers or the like; and logic chips, such as analog-to-digital (ADC) converters, integrated circuits for special applications (Application-specific integrated circuit; ASIC) or similar. However, the wafer-related components 1020 are not limited thereto, but may also include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

網路相關組件1030可包含諸如以下各者的協定：無線保真（wireless fidelity；Wi-Fi）（電機電子工程師學會（Institute of Electrical and Electronics Engineers；IEEE）802.11系列或其類似者）、全球互通微波存取（worldwide interoperability for microwave access；WiMAX）（IEEE 802.16系列或其類似者）、IEEE 802.20、長期演進（long term evolution；LTE）、唯資料演進（evolution data only；Ev-DO）、高速封包存取+（high speed packet access +；HSPA+）、高速下行鏈路封包存取+（high speed downlink packet access +；HSDPA+）、高速上行鏈路封包存取+（high speed uplink packet access +；HSUPA+）、增強型資料GSM環境（enhanced data GSM environment；EDGE）、全球行動通信系統（global system for mobile communications；GSM）、全球定位系統（global positioning system；GPS）、通用封包無線電服務（general package radio service；GPRS）、分碼多重存取（code division multiplex access；CDMA）、分時多重存取（time division multiple access；TDMA）、數位增強型無線電信（digital enhanced cordless telecommunications；DECT）、藍芽、3G協定、4G協定、5G協定以及在上述協定之後指定的任何其他無線及有線協定。然而，網路相關組件1030不限於此，而是亦可包含多種其他無線或有線標準或協定。另外，網路相關組件1030可與上文所描述的晶片相關組件1020一起彼此組合。The network-related components 1030 may include agreements such as: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series or the like), global interoperability Worldwide Interoperability for microwave access (WiMAX) (IEEE 802.16 series or similar), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packets Access + (high speed packet access +; HSPA+), high speed downlink packet access + (high speed downlink packet access +; HSDPA+), high speed uplink packet access + (high speed uplink packet access +; HSUPA+) , Enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general package radio service (general package radio service; GPRS), code division multiplex access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement , 4G agreement, 5G agreement and any other wireless and wired agreements specified after the above agreement. However, the network-related components 1030 are not limited thereto, but may also include various other wireless or wired standards or protocols. In addition, the network related components 1030 may be combined with each other together with the chip related components 1020 described above.

其他組件1040可包含高頻電感器、鐵氧體電感器、功率電感器、鐵氧體珠粒、低溫共燒陶瓷（low temperature co-fired ceramic；LTCC）、電磁干擾（electromagnetic interference；EMI）濾波器、多層陶瓷電容器（multilayer ceramic capacitor；MLCC）或其類似者。然而，其他組件1040不限於此，而是亦可包含出於各種其他目的而使用的被動組件或其類似者。另外，與上文所描述的晶片相關組件1020或網路相關組件1030一起，其他組件1040可彼此組合。Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (EMI) filtering Device, multilayer ceramic capacitor (MLCC) or the like. However, other components 1040 are not limited thereto, but may also include passive components used for various other purposes or the like. In addition, together with the chip-related components 1020 or the network-related components 1030 described above, other components 1040 may be combined with each other.

取決於電子裝置1000的類型，電子裝置1000可包含可或可不實體連接或電連接至母板1010的其他組件。此等其他組件可包含（例如）攝影機模組1050、天線1060、顯示裝置1070、電池1080、音訊編解碼器（圖中未示出）、視訊編解碼器（圖中未示出）、功率放大器（圖中未示出）、羅盤（圖中未示出）、加速計（圖中未示出）、陀螺儀（圖中未示出）、揚聲器（圖中未示出）、大容量儲存單元（例如，硬碟機）（圖中未示出）、緊密光碟（compact disk；CD）機（圖中未示出）、數位化通用光碟（digital versatile disk；DVD）機（圖中未示出）或其類似者。然而，此等其他組件不限於此，而是取決於電子裝置1000的類型亦可包含出於各種目的而使用的其他組件或其類似者。Depending on the type of electronic device 1000, electronic device 1000 may include other components that may or may not be physically or electrically connected to motherboard 1010. These other components may include, for example, camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (Not shown in the figure), compass (not shown in the figure), accelerometer (not shown in the figure), gyroscope (not shown in the figure), speaker (not shown in the figure), mass storage unit (For example, a hard disk drive) (not shown in the figure), a compact disk (CD) machine (not shown in the figure), a digital versatile disk (DVD) machine (not shown in the figure) ) Or similar. However, these other components are not limited thereto, but may also include other components used for various purposes or the like depending on the type of the electronic device 1000.

電子裝置1000可為智慧型電話、個人數位助理（personal digital assistant；PDA）、數位視訊攝影機、數位靜態攝影機、網路系統、電腦、監視器、平板PC、膝上型PC、迷你筆記型PC、電視、視訊遊戲機、智慧型手錶、汽車組件或其類似者。然而，電子裝置1000不限於此，且可為處理資料的任何其他電子裝置。The electronic device 1000 may be a smart phone, personal digital assistant (PDA), digital video camera, digital still camera, network system, computer, monitor, tablet PC, laptop PC, mini-notebook PC, TVs, video game consoles, smart watches, car components or the like. However, the electronic device 1000 is not limited thereto, and may be any other electronic device that processes data.

圖2為說明電子裝置的實例的示意性透視圖。2 is a schematic perspective view illustrating an example of an electronic device.

參看圖2，可出於各種目的而在如上文所描述的各種電子裝置1000中使用半導體封裝。舉例而言，主板1110可容納於智慧型電話1100的本體1101中，且各種電子組件1120可實體連接或電連接至主板1110。另外，可或可不實體連接或電連接至主板1110的其他組件（諸如，攝影機模組1130）可容納於本體1101中。電子組件1120中的一些可為晶片相關組件，且半導體封裝100可為（例如）晶片相關組件間的應用程式處理器，但不限於此。電子裝置未必限於智慧型電話1100，而是可為如上文所描述的其他電子裝置。半導體封裝 Referring to FIG. 2, semiconductor packages may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 can be accommodated in the body 1101 of the smartphone 1100, and various electronic components 1120 can be physically or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically or electrically connected to the main board 1110 (such as the camera module 1130) may be accommodated in the body 1101. Some of the electronic components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor between chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor packaging

通常，大量精細電路整合於半導體晶片中。然而，半導體晶片自身可不充當已完成的半導體產品，且可能歸因於外部物理或化學影響而受損。因此，無法單獨地使用半導體晶片，而是可經封裝且在經封裝狀態下使用於電子裝置或其類似者中。Generally, a large number of fine circuits are integrated in semiconductor chips. However, the semiconductor wafer itself may not serve as a completed semiconductor product, and may be damaged due to external physical or chemical influence. Therefore, the semiconductor wafer cannot be used alone, but can be packaged and used in an electronic device or the like in a packaged state.

此處，歸因於半導體晶片與電子裝置的主板之間存在電連接方面的電路寬度差異而需要半導體封裝。詳言之，半導體晶片的連接墊的大小及半導體晶片的連接墊之間的間隔極細，但電子裝置中所使用的主板的組件安裝墊的大小及主板的組件安裝墊之間的間隔顯著大於半導體晶片的連接墊的大小及半導體晶片的連接墊之間的間隔。因此，可能難以直接地將半導體晶片安裝於主板上，且需要用於緩衝半導體晶片與主板之間的電路寬度差異的封裝技術。Here, a semiconductor package is required due to a difference in circuit width in terms of electrical connection between the semiconductor wafer and the main board of the electronic device. In detail, the size of the connection pads of the semiconductor chip and the spacing between the connection pads of the semiconductor chip are extremely fine, but the size of the component mounting pads of the motherboard and the spacing between the component mounting pads of the motherboard used in the electronic device are significantly larger than that of the semiconductor The size of the connection pads of the wafer and the spacing between the connection pads of the semiconductor wafer. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technology for buffering the difference in circuit width between the semiconductor chip and the main board is required.

由封裝技術製造的半導體封裝可取決於結構及其目的而分類為扇入型半導體封裝或扇出型半導體封裝。Semiconductor packages manufactured by packaging technology may be classified as fan-in semiconductor packages or fan-out semiconductor packages depending on the structure and purpose.

將在下文中參看圖式更詳細地描述扇入型半導體封裝及扇出型半導體封裝。扇入型半導體封裝 The fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail below with reference to the drawings. Fan-in semiconductor package

圖3A及圖3B為說明在被封裝之前及被封裝之後的扇入型半導體封裝的狀態的示意性橫截面圖。3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged.

圖4為說明扇入型半導體封裝的封裝程序的示意性橫截面圖。4 is a schematic cross-sectional view illustrating a packaging procedure of a fan-in semiconductor package.

參考圖式，半導體晶片2220可為（例如）處於裸露狀態的積體電路（integrated circuit；IC），包含：本體2221，其包含矽（Si）、鍺（Ge）、砷化鎵（GaAs）或其類似者；連接墊2222，其形成於本體2221的一個表面上且包含導電材料，諸如鋁（Al）或其類似者；以及鈍化層2223，諸如氧化物薄膜、氮化物薄膜或其類似者，其形成於本體2221的一個表面上且覆蓋連接墊2222的至少部分。在此情況下，由於連接墊2222極小，所以難以將積體電路（IC）安裝於中間層級印刷電路板（printed circuit board；PCB）上以及電子裝置的主板或其類似者上。Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state, including: a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs) or The like; the connection pad 2222, which is formed on one surface of the body 2221 and contains a conductive material, such as aluminum (Al) or the like; and the passivation layer 2223, such as an oxide film, a nitride film, or the like, It is formed on one surface of the body 2221 and covers at least part of the connection pad 2222. In this case, since the connection pad 2222 is extremely small, it is difficult to mount an integrated circuit (IC) on an intermediate-level printed circuit board (PCB) and a motherboard of an electronic device or the like.

因此，可取決於半導體晶片2220上的半導體晶片2220的大小而形成連接構件2240，以便重佈連接墊2222。可藉由使用諸如光可成像介電質（photoimagable dielectric；PID）樹脂的絕緣材料在半導體晶片2220上形成絕緣層2241，形成敞開連接墊2222的通路孔2243h以及隨後形成佈線圖案2242及通孔2243來形成連接構件2240。接著，可形成保護連接構件2240的鈍化層2250，可形成開口2251，且可形成凸塊下金屬層2260或其類似者。意即，可經由一系列程序製造包含（例如）半導體晶片2220、連接構件2240、鈍化層2250以及凸塊下金屬層2260的扇入型半導體封裝2200。Therefore, the connection member 2240 may be formed depending on the size of the semiconductor wafer 2220 on the semiconductor wafer 2220 so as to redistribute the connection pad 2222. An insulating layer 2241 can be formed on the semiconductor wafer 2220 by using an insulating material such as photoimagable dielectric (PID) resin, a via hole 2243h opening the connection pad 2222, and then forming a wiring pattern 2242 and a via hole 2243 To form the connecting member 2240. Next, a passivation layer 2250 protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 or the like may be formed. That is, the fan-in semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under-bump metal layer 2260 can be manufactured through a series of procedures.

如上文所描述，扇入型半導體封裝可具有半導體晶片的所有連接墊（例如輸入/輸出（input/output；I/O）端子）均安置於半導體晶片的內部的封裝形式，且可具有極佳的電特性，並且可以低成本生產。因此，已以扇入型半導體封裝形式製造安裝於智慧型電話中的許多元件。詳言之，已開發安裝於智慧型電話中的許多元件以實施快速信號傳送同時具有緊密大小。As described above, the fan-in semiconductor package may have a package form in which all connection pads of the semiconductor wafer (such as input/output (I/O) terminals) are arranged inside the semiconductor wafer, and may have excellent Electrical characteristics, and can be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smart phones have been developed to implement fast signal transmission while having a compact size.

然而，由於所有I/O端子需要安置於扇入型半導體封裝中的半導體晶片內部，所以扇入型半導體封裝具有大的空間限制。因此，難以將此結構應用於具有大量I/O端子的半導體晶片或具有緊密大小的半導體晶片。另外，歸因於上文所描述的缺點，不可直接地在電子裝置的主板上安裝及使用扇入型半導體封裝。原因為，即使在藉由重佈程序增加半導體晶片的I/O端子的大小及半導體晶片的I/O端子之間的間隔的情況下，半導體晶片的I/O端子的大小及半導體晶片的I/O端子之間的間隔也不能足以直接地將扇入型半導體封裝安裝於電子裝置的主板上。However, since all I/O terminals need to be placed inside the semiconductor wafer in the fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of I/O terminals or a semiconductor wafer having a compact size. In addition, due to the disadvantages described above, it is not possible to directly install and use a fan-in semiconductor package on the motherboard of an electronic device. The reason is that even in the case of increasing the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip through the redistribution procedure, the size of the I/O terminals of the semiconductor chip and the I of the semiconductor chip The spacing between the /O terminals cannot be sufficient to directly mount the fan-in semiconductor package on the motherboard of the electronic device.

圖5為說明扇入型半導體封裝安裝於插入式基板上且最終安裝於電子裝置的主板上的情況的示意性橫截面圖。FIG. 5 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

圖6為說明扇入型半導體封裝嵌入於插入式基板中且最終安裝於電子裝置的主板上的情況的示意性橫截面圖。6 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

參看圖式，在扇入型半導體封裝2200中，半導體晶片2220的連接墊2222（意即，I/O端子）可經由插入式基板2301重佈，且扇入型半導體封裝2200可在其安裝於插入式基板2301上的狀態下最終安裝於電子裝置的主板2500上。在此情況下，焊球2270以及其類似者可由底部填充樹脂2280或其類似者固定，且半導體晶片2220的外側可藉由模製材料2290或其類似者覆蓋。或者，扇入型半導體封裝2200可嵌入於單獨的插入式基板2302中，半導體晶片2220的連接墊2222（意即，I/O端子）可在扇入型半導體封裝2200嵌入於插入式基板2302中的狀態下由插入式基板2302重佈，且扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。Referring to the drawings, in the fan-in semiconductor package 2200, the connection pads 2222 (that is, I/O terminals) of the semiconductor chip 2220 can be redistributed via the interposer substrate 2301, and the fan-in semiconductor package 2200 can be mounted on The plug-in board 2301 is finally mounted on the main board 2500 of the electronic device. In this case, the solder balls 2270 and the like can be fixed by the underfill resin 2280 or the like, and the outside of the semiconductor wafer 2220 can be covered by the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pad 2222 (that is, the I/O terminal) of the semiconductor chip 2220 may be embedded in the interposer substrate 2302 in the fan-in semiconductor package 2200 In the state of being redistributed by the interposer substrate 2302, and the fan-in semiconductor package 2200 can be finally installed on the motherboard 2500 of the electronic device.

如上文所描述，可能難以直接地在電子裝置的主板上安裝及使用扇入型半導體封裝。因此，扇入型半導體封裝可經由封裝程序安裝於單獨的插入式基板上且隨後安裝於電子裝置的主板上；或者可在扇入型半導體嵌入於插入式基板中的狀態下在電子裝置的主板上被安裝及使用。扇出型半導體封裝 As described above, it may be difficult to directly install and use a fan-in semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate plug-in substrate through the packaging procedure and then mounted on the main board of the electronic device; or it can be on the main board of the electronic device with the fan-in semiconductor embedded in the plug-in substrate It is installed and used. Fan-out semiconductor package

圖7為說明扇出型半導體封裝的示意性橫截面圖。7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

參看圖式，在扇出型半導體封裝2100中，例如，半導體晶片2120的外側可由囊封體2130保護，且半導體晶片2120的連接墊2122可藉由連接構件2140向半導體晶片2120之外重佈。在此情況下，鈍化層2150可進一步形成於連接構件2140上，且凸塊下金屬層2160可進一步形成於鈍化層2150的開口中。焊球2170可進一步形成於凸塊下金屬層2160上。半導體晶片2120可為積體電路（IC），包含本體2121、連接墊2122、鈍化層（圖中未示出）以及其類似者。連接構件2140可包含：絕緣層2141；重佈層2142，其形成於絕緣層2141上；以及通孔2143，其將連接墊2122與重佈層2142彼此電連接。Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 can be protected by the encapsulant 2130, and the connection pads 2122 of the semiconductor chip 2120 can be redistributed outside the semiconductor chip 2120 by the connection member 2140. In this case, the passivation layer 2150 may be further formed on the connection member 2140, and the under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC), including a body 2121, a connection pad 2122, a passivation layer (not shown in the figure), and the like. The connection member 2140 may include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and a through hole 2143 that electrically connects the connection pad 2122 and the redistribution layer 2142 to each other.

如上文所描述，扇出型半導體封裝可具有半導體晶片的I/O端子經由形成於半導體晶片上的連接構件朝半導體晶片之外重佈且安置的形式。如上文所描述，在扇入型半導體封裝中，半導體晶片的所有I/O端子需要安置於半導體晶片內部。因此，當半導體晶片的大小減小時，需要減少球的大小及間距，以使得標準化球佈局可能不被用於扇入型半導體封裝中。另一方面，扇出型半導體封裝可具有半導體晶片的I/O端子經由形成於半導體晶片上的連接構件朝半導體晶片之外重佈且安置的形式，如上文所描述。因此，即使在半導體晶片的大小減小的情況下，標準化球佈局也可原樣用於扇出型半導體封裝中，以使得扇出型半導體封裝可安裝於電子裝置的主板上而無需使用單獨的插入式基板，如下文所描述。As described above, the fan-out type semiconductor package may have a form in which the I/O terminals of the semiconductor wafer are redistributed and arranged outside the semiconductor wafer via the connection member formed on the semiconductor wafer. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor wafer need to be placed inside the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls need to be reduced, so that the standardized ball layout may not be used in a fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package may have a form in which the I/O terminals of the semiconductor wafer are redistributed and arranged outside the semiconductor wafer via the connection member formed on the semiconductor wafer, as described above. Therefore, even in the case where the size of the semiconductor wafer is reduced, the standardized ball layout can be used as it is in the fan-out semiconductor package, so that the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate insert Type substrate, as described below.

圖8為說明扇出型半導體封裝安裝於電子裝置的主板上的情況的示意性橫截面圖。8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device.

參看圖式，扇出型半導體封裝2100可經由焊球2170或其類似者安裝於電子裝置的主板2500上。意即，如上文所描述，扇出型半導體封裝2100包含連接構件2140，連接構件2140形成於半導體晶片2120上且能夠將連接墊2122重佈至超出半導體晶片2120的大小範圍的扇出區，以使得標準化球佈局可原樣用於扇出型半導體封裝2100中。因此，扇出型半導體封裝2100可安裝於電子裝置的主板2500上而無需使用單獨的插入式基板或其類似者。Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on the motherboard 2500 of the electronic device via solder balls 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of redistributing the connection pad 2122 to a fan-out area that exceeds the size range of the semiconductor wafer 2120 to The standardized ball layout can be used as it is in the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate plug-in substrate or the like.

如上文所描述，由於扇出型半導體封裝可安裝於電子裝置的主板上而無需使用單獨的插入式基板，所以扇出型半導體封裝可以小於使用插入式基板的扇入型半導體封裝的厚度實施扇出型半導體封裝。因此，扇出型半導體封裝可被小型化及薄化。另外，扇出型半導體封裝具有極佳的熱特性及電特性，以使得其特別適合於行動產品。因此，可使用印刷電路板（PCB）以比一般疊層封裝（package-on-package；POP）類型的形式更緊密的形式來實施扇出型半導體封裝，且扇出型半導體封裝可解決歸因於發生彎曲現象的問題。As described above, since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate plug-in substrate, the fan-out semiconductor package can be implemented with a thickness smaller than that of the fan-in semiconductor package using the plug-in substrate Out-type semiconductor package. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, fan-out semiconductor packages have excellent thermal and electrical characteristics, making them particularly suitable for mobile products. Therefore, the printed circuit board (PCB) can be used to implement the fan-out semiconductor package in a more compact form than the general package-on-package (POP) type, and the fan-out semiconductor package can solve the attribution Due to the problem of bending phenomenon.

同時，扇出型半導體封裝指代用於如上文所描述的將半導體晶片安裝於電子裝置的主板或其類似者上且保護半導體晶片免受外部影響的封裝技術，且為與諸如插入式基板或其類似者的印刷電路板（PCB）的概念不同的概念，PCB具有與扇出型半導體封裝的規模、目的以及其類似者不同的規模、目的以及其類似者且嵌入有扇入型半導體封裝。Meanwhile, the fan-out type semiconductor package refers to a packaging technology used to mount a semiconductor chip on a motherboard of an electronic device or the like as described above and protect the semiconductor chip from external influences, and is a device such as an interposer substrate or the like The concept of a similar printed circuit board (PCB) is different. The PCB has a different scale, purpose, and the like from a fan-out type semiconductor package, and a fan-in type semiconductor package is embedded.

將在下文中參看圖式描述可有效地耗散由半導體晶片產生的熱的扇出型半導體封裝。A fan-out type semiconductor package that can effectively dissipate heat generated by a semiconductor wafer will be described below with reference to the drawings.

圖9為說明扇出型半導體封裝的實例的示意性橫截面圖。9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

圖10為沿圖9的扇出型半導體封裝的線I-I'截取的示意性平面圖。FIG. 10 is a schematic plan view taken along line II′ of the fan-out semiconductor package of FIG. 9.

參看圖式，在本發明中根據例示性實施例的扇出型半導體封裝100A可包含：第一連接構件110，其具有穿孔110H；半導體晶片120，其安置於第一連接構件110的穿孔110H中且具有其上安置有連接墊122的主動表面及與主動表面對置的非主動表面；囊封體130，其囊封第一連接構件110及半導體晶片120的非主動表面的至少部分；第二連接構件140，其安置於第一連接構件110及半導體晶片120的主動表面上；鈍化層150，其安置於第二連接構件140上；凸塊下金屬層160，其形成於鈍化層150的開口151中；以及連接端子170，其形成於凸塊下金屬層160上。覆蓋鄰近於半導體晶片120的非主動表面的囊封體130的至少部分的圖案層132可安置於囊封體130上，且可藉由穿透囊封體130的通孔133連接至半導體晶片120的非主動表面。可經由通孔133及圖案層132輕易地朝外耗散由半導體晶片120產生的熱（由箭頭表示）。Referring to the drawings, the fan-out type semiconductor package 100A according to an exemplary embodiment in the present invention may include: a first connection member 110 having a through hole 110H; a semiconductor chip 120 disposed in the through hole 110H of the first connection member 110 And has an active surface on which the connection pad 122 is disposed and an inactive surface opposite to the active surface; an encapsulation body 130 that encapsulates at least part of the inactive surface of the first connection member 110 and the semiconductor chip 120; the second The connection member 140, which is disposed on the active surface of the first connection member 110 and the semiconductor wafer 120; the passivation layer 150, which is disposed on the second connection member 140; and the under bump metal layer 160, which is formed in the opening of the passivation layer 150 151; and the connection terminal 170, which is formed on the under bump metal layer 160. The pattern layer 132 covering at least part of the encapsulation body 130 adjacent to the inactive surface of the semiconductor chip 120 may be disposed on the encapsulation body 130 and may be connected to the semiconductor chip 120 through the through hole 133 penetrating the encapsulation body 130 Non-active surface. The heat generated by the semiconductor wafer 120 (indicated by the arrow) can be easily dissipated outward through the via hole 133 and the pattern layer 132.

一般的扇出型半導體封裝具有使用諸如環氧模製化合物（epoxy molding compound；EMC）或其類似者的囊封體簡單地模製半導體晶片且藉由上述諸如環氧模製化合物（EMC）或其類似者的囊封體圍繞半導體晶片的結構。在此情況下，由半導體晶片產生的大部分熱沿重佈層朝下釋放，且僅極少量的熱經傳導至具有低熱導率的囊封體，以使得散熱特性惡化。A general fan-out type semiconductor package has a simple molding of a semiconductor chip using an encapsulation body such as an epoxy molding compound (EMC) or the like, and a method such as the above-mentioned epoxy molding compound (EMC) or The encapsulation of its analogous surrounds the structure of the semiconductor wafer. In this case, most of the heat generated by the semiconductor wafer is released downward along the redistribution layer, and only a very small amount of heat is conducted to the encapsulation body with low thermal conductivity to deteriorate the heat dissipation characteristics.

另一方面，在如在根據例示性實施例的扇出型半導體封裝100A中的圖案層132連接至半導體晶片120的非主動表面且通孔133安置於鄰近於半導體晶片120的非主動表面的位置中的情況下，由半導體晶片120產生的熱（由箭頭表示）可易於耗散，以使得散熱特性可改良。另外，圖案層132可解決電磁干擾（EMI）。On the other hand, the pattern layer 132 in the fan-out semiconductor package 100A as in the exemplary embodiment is connected to the inactive surface of the semiconductor wafer 120 and the through hole 133 is disposed at a position adjacent to the inactive surface of the semiconductor wafer 120 In the case of, the heat generated by the semiconductor wafer 120 (indicated by the arrow) can be easily dissipated, so that the heat dissipation characteristics can be improved. In addition, the pattern layer 132 may solve electromagnetic interference (EMI).

同時，由於半導體封裝120的非主動表面經由通孔133連接至圖案層132，所以在扇出型半導體封裝100A包含多個半導體晶片120的情況下，通孔133僅可選擇性連接至產生大量熱的某些半導體晶片120或僅可集中地形成於在其間產生大量熱的半導體晶片120中。另外，通孔133及圖案層132可使用相同材料同時形成且彼此整合，並且於其間無邊界。因此，形成通孔133及圖案層132的程序可為簡單的，且通孔133與圖案層132之間的連接的可靠性可為極佳的。Meanwhile, since the inactive surface of the semiconductor package 120 is connected to the pattern layer 132 via the via 133, in the case where the fan-out semiconductor package 100A includes a plurality of semiconductor chips 120, the via 133 can only be selectively connected to generate a large amount of heat Some of the semiconductor wafers 120 may only be concentratedly formed in the semiconductor wafers 120 that generate a large amount of heat therebetween. In addition, the through hole 133 and the pattern layer 132 can be simultaneously formed using the same material and integrated with each other, and there is no boundary therebetween. Therefore, the procedure for forming the via 133 and the pattern layer 132 can be simple, and the reliability of the connection between the via 133 and the pattern layer 132 can be excellent.

將在下文中更詳細地描述包含於根據例示性實施例的扇出型半導體封裝100A中的各別組件。The respective components included in the fan-out semiconductor package 100A according to the exemplary embodiment will be described in more detail below.

第一連接構件110可取決於某些材料而維持扇出型半導體封裝100A的剛度，且用以確保囊封體130的厚度的均勻性。第一連接構件110可具有穿孔110H。穿孔110H可使安置於其中的半導體晶片120以預定距離與第一連接構件110間隔開。半導體晶片120的側表面可由第一連接構件110圍繞。然而，此形式僅為實例，且可經各種修改而具有其他形式，且扇出型半導體封裝100A可取決於此形式而執行另一功能。The first connection member 110 may depend on certain materials to maintain the rigidity of the fan-out semiconductor package 100A and to ensure the uniformity of the thickness of the encapsulation body 130. The first connection member 110 may have a through hole 110H. The through hole 110H may allow the semiconductor wafer 120 disposed therein to be spaced apart from the first connection member 110 by a predetermined distance. The side surface of the semiconductor wafer 120 may be surrounded by the first connection member 110. However, this form is only an example, and may have other forms through various modifications, and the fan-out semiconductor package 100A may perform another function depending on this form.

第一連接構件110可包含絕緣層111。絕緣層111的材料不受特定限制。舉例而言，絕緣材料可用作絕緣層111的材料。在此情況下，絕緣材料可為熱固性樹脂（諸如，環氧樹脂）、熱塑性樹脂（諸如，聚醯亞胺樹脂）、熱固性樹脂或熱塑性樹脂與無機填充劑一起浸漬於諸如玻璃布（或玻璃織物）的核心材料中的樹脂，例如預浸體、味之素累積膜（Ajinomoto Build up Film；ABF）、FR-4、雙馬來醯亞胺三嗪（Bismaleimide Triazine；BT）或其類似者。The first connection member 110 may include an insulating layer 111. The material of the insulating layer 111 is not particularly limited. For example, an insulating material can be used as the material of the insulating layer 111. In this case, the insulating material may be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide resin), a thermosetting resin or a thermoplastic resin and an inorganic filler impregnated into a glass cloth (or glass fabric, for example) ) In the core material, such as prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (BT) or similar.

半導體晶片120可為以整合於單一晶片中的數百至數百萬個元件或更多的量提供的積體電路（IC）。IC可為（例如）應用程式處理器晶片，諸如中央處理器（例如，CPU）、圖形處理器（例如，GPU）、數位信號處理器、密碼編譯處理器、微處理器、微控制器或其類似者，但不限於此。The semiconductor chip 120 may be an integrated circuit (IC) provided in an amount of hundreds to millions of elements or more integrated in a single chip. The IC may be, for example, an application processor chip such as a central processing unit (eg, CPU), graphics processor (eg, GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or Similar, but not limited to this.

可基於主動晶圓而形成半導體晶片120。在此情況下，本體121的基底材料可為矽（Si）、鍺（Ge）、砷化鎵（GaAs）或其類似者。各種電路可形成於本體121上。連接墊122可將半導體晶片120電連接至其他組件。連接墊122的材料可為導電材料，諸如鋁（Al）或其類似者。可在本體121上形成暴露連接墊122的鈍化層123，且鈍化層123可為氧化物薄膜、氮化物薄膜或其類似者；或者可為氧化物層與氮化物層的雙層。連接墊122的下部表面可具有相對於囊封體130的下部表面的穿過鈍化層123的階梯。因此，可改良囊封體130的滲移情況。絕緣層（圖中未示出）以及其類似者亦可進一步安置於其他所需位置中。The semiconductor wafer 120 may be formed based on the active wafer. In this case, the base material of the body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body 121. The connection pad 122 can electrically connect the semiconductor chip 120 to other components. The material of the connection pad 122 may be a conductive material, such as aluminum (Al) or the like. A passivation layer 123 exposing the connection pad 122 may be formed on the body 121, and the passivation layer 123 may be an oxide film, a nitride film, or the like; or may be a double layer of an oxide layer and a nitride layer. The lower surface of the connection pad 122 may have a step through the passivation layer 123 relative to the lower surface of the encapsulation body 130. Therefore, the migration of the encapsulation body 130 can be improved. The insulating layer (not shown in the figure) and the like can be further arranged in other desired positions.

囊封體130可保護第一連接構件110及/或半導體晶片120。囊封體130的囊封形式不受特定限制，但可為囊封體130圍繞第一連接構件110及/或半導體晶片120的至少部分的形式。舉例而言，囊封體130可覆蓋第一連接構件110及半導體晶片120的非主動表面，且填充穿孔110H的壁與半導體晶片120的側表面之間的空間。另外，囊封體130亦可填充半導體晶片120的鈍化層123與第二連接構件140之間的空間的至少部分。同時，囊封體130可填充穿孔110H，因此充當黏著劑且減少半導體晶片120的取決於某些材料的屈曲。The encapsulation body 130 can protect the first connection member 110 and/or the semiconductor chip 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be a form in which the encapsulation body 130 surrounds at least part of the first connection member 110 and/or the semiconductor wafer 120. For example, the encapsulation body 130 may cover the inactive surface of the first connection member 110 and the semiconductor wafer 120 and fill the space between the wall of the through hole 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulation body 130 may also fill at least part of the space between the passivation layer 123 of the semiconductor wafer 120 and the second connection member 140. At the same time, the encapsulation body 130 may fill the through holes 110H, thus acting as an adhesive and reducing the buckling of the semiconductor wafer 120 depending on certain materials.

囊封體130的某些材料不受特定限制。舉例而言，可將絕緣材料用作囊封體130的材料。在此情況下，絕緣材料可為包含無機填充劑及絕緣樹脂的材料，絕緣樹脂例如諸如環氧樹脂的熱固性樹脂、諸如聚醯亞胺樹脂的熱塑性樹脂、具有諸如浸漬於熱固性樹脂以及熱塑性樹脂中的無機填充劑的加強材料的樹脂，諸如ABF、FR-4、BT、EMC或其類似者。作為一種選擇，亦可將熱固性樹脂或熱塑性樹脂與無機填充劑一起浸漬在諸如玻璃織物的核心材料中的材料用作絕緣材料。作為一種選擇，亦可使用光可成像介電質（PID）樹脂作為絕緣材料。Certain materials of the encapsulation body 130 are not particularly limited. For example, an insulating material can be used as the material of the encapsulation body 130. In this case, the insulating material may be a material containing an inorganic filler and an insulating resin, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide resin, a resin such as being impregnated in the thermosetting resin and the thermoplastic resin The resin of the reinforcing material of the inorganic filler, such as ABF, FR-4, BT, EMC or the like. As an option, a material in which a thermosetting resin or a thermoplastic resin is impregnated together with an inorganic filler in a core material such as glass fabric can also be used as an insulating material. As an option, photo-imageable dielectric (PID) resin can also be used as the insulating material.

圖案層132可經形成於囊封體130的表面上。圖案層132可為包含已知導電材料的金屬層。舉例而言，圖案層132可包含銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金。圖案層132可藉由已知的電鍍法與通孔133一起形成。圖案層132可為與半導體晶片120的連接墊122電絕緣的圖案，意即散熱圖案，但不限於此。意即，圖案層132在執行接地（GND）功能的情形下為散熱圖案時，可視需要電連接至半導體晶片120的連接墊122。The pattern layer 132 may be formed on the surface of the encapsulation body 130. The pattern layer 132 may be a metal layer containing known conductive materials. For example, the pattern layer 132 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or the like alloy. The pattern layer 132 can be formed together with the through hole 133 by a known plating method. The pattern layer 132 may be a pattern electrically insulated from the connection pad 122 of the semiconductor chip 120, which means a heat dissipation pattern, but is not limited thereto. That is, when the pattern layer 132 is a heat dissipation pattern in the case of performing a ground (GND) function, it may be electrically connected to the connection pad 122 of the semiconductor chip 120 as needed.

通孔133可形成於通路孔中，所述通路孔形成於囊封體130中。通路孔可自囊封體130的一個表面穿透至半導體晶片120的非主動表面。因此，通孔133可接觸半導體晶片120的非主動表面。取決於囊封體130的材料，通路孔可為雷射鑽孔的通路孔或光蝕刻通路孔。舉例而言，通路孔可為在囊封體130為包含無機填充劑及絕緣樹脂的ABF的情況下使用已知雷射鑽孔方法而形成的雷射鑽孔通路孔，且可為在囊封體130包含感光性絕緣材料的情況下藉由已知光微影方法而形成的光蝕刻通路孔。通孔133可包含導電材料，諸如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金，且可藉由電鍍法與圖案層132一起形成。The through hole 133 may be formed in a via hole formed in the encapsulation body 130. The via hole may penetrate from one surface of the encapsulation body 130 to the inactive surface of the semiconductor wafer 120. Therefore, the through hole 133 may contact the inactive surface of the semiconductor wafer 120. Depending on the material of the encapsulation 130, the via hole may be a laser drilled via hole or a photo-etched via hole. For example, the via hole may be a laser drilled via hole formed using a known laser drilling method in the case where the encapsulation body 130 is an ABF including an inorganic filler and an insulating resin, and may be an encapsulated When the body 130 includes a photosensitive insulating material, a photoetched via hole is formed by a known photolithography method. The through hole 133 may include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Alloy, and can be formed together with the pattern layer 132 by electroplating.

在藉由電鍍法一起形成圖案層132與通孔133的情況下，圖案層132與通孔133可彼此整合，且於其間可能不具有邊界。另外，圖案層132與通孔133可包含相同的導電材料，諸如銅（Cu）。亦即，圖案層132與通孔133之間可不需要單獨的黏著材料。因此，程序可為簡單的，且散熱構件可經實施以具有較低厚度。在圖案層132與通孔133彼此整合且其間無邊界以直接接觸彼此的情況下，經由半導體晶片120的非主動表面耗散的熱可更有效地朝外耗散。In the case where the pattern layer 132 and the through hole 133 are formed together by an electroplating method, the pattern layer 132 and the through hole 133 may be integrated with each other, and there may be no boundary therebetween. In addition, the pattern layer 132 and the through hole 133 may contain the same conductive material, such as copper (Cu). That is, a separate adhesive material may not be required between the pattern layer 132 and the through hole 133. Therefore, the procedure can be simple, and the heat dissipation member can be implemented to have a lower thickness. In the case where the pattern layer 132 and the through hole 133 are integrated with each other and there is no boundary therebetween to directly contact each other, the heat dissipated through the inactive surface of the semiconductor wafer 120 can be dissipated outward more effectively.

第二連接構件140可經組態以重佈半導體晶片120的連接墊122。具有各種功能的數十至數百個連接墊122可由第二連接構件140重佈，且可取決於功能而經由下文待描述的連接端子170實體連接或電連接至外部源。第二連接構件140可包含：絕緣層141；重佈層142，其安置於絕緣層141上；以及通孔143，其穿透絕緣層141且將重佈層142彼此連接。在根據例示性實施例的扇出型半導體封裝100A中，第二連接構件140可包含單個層，但亦可包含多個層。The second connection member 140 may be configured to redistribute the connection pads 122 of the semiconductor chip 120. Dozens to hundreds of connection pads 122 having various functions may be redistributed by the second connection member 140, and may be physically or electrically connected to an external source via connection terminals 170 to be described below depending on the function. The second connection member 140 may include: an insulating layer 141; a redistribution layer 142, which is disposed on the insulating layer 141; and a through hole 143, which penetrates the insulating layer 141 and connects the redistribution layer 142 to each other. In the fan-out semiconductor package 100A according to the exemplary embodiment, the second connection member 140 may include a single layer, but may also include multiple layers.

可使用絕緣材料作為絕緣層141的材料。在此情況下，亦可使用感光性絕緣材料（諸如，光可成像介電質（PID）樹脂）作為絕緣材料。亦即，絕緣層141可為感光性絕緣層。在絕緣層141具有感光特性的情況下，絕緣層141可形成為具有較小厚度，且可較易於達成通孔143的精細間距。絕緣層141可為包含絕緣樹脂及無機填充劑的感光性絕緣層。當絕緣層141為多個層時，絕緣層141的材料視需要可彼此相同，且亦可彼此不同。當絕緣層141為多個層時，絕緣層141可取決於程序而與彼此整合，以使得其間的邊界亦可不顯而易見。An insulating material can be used as the material of the insulating layer 141. In this case, a photosensitive insulating material such as photo-imageable dielectric (PID) resin may also be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. In the case where the insulating layer 141 has photosensitive characteristics, the insulating layer 141 may be formed to have a smaller thickness, and the fine pitch of the through holes 143 may be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer containing an insulating resin and an inorganic filler. When the insulating layer 141 is a plurality of layers, the materials of the insulating layer 141 may be the same as each other, and may also be different from each other. When the insulating layer 141 is a plurality of layers, the insulating layers 141 may be integrated with each other depending on procedures, so that the boundary therebetween may not be obvious.

重佈層142可實質上用以重佈連接墊122。重佈層142中的每一者的材料可為導電材料，諸如，銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金。重佈層142可取決於其對應層的設計而執行各種功能。舉例而言，重佈層142可包含接地（GND）圖案、功率（PWR）圖案、信號（S）圖案以及其類似者。此處，信號（S）圖案可包含除了接地（GND）圖案、功率（PWR）圖案以及其類似者以外的各種信號圖案，諸如資料信號圖案以及其類似者。另外，重佈層142可包含通孔墊、連接端子墊以及其類似者。The redistribution layer 142 can be used to redistribute the connection pad 122 substantially. The material of each of the redistribution layers 142 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead ( Pb), titanium (Ti) or its alloys. The redistribution layer 142 may perform various functions depending on the design of its corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, power (PWR) pattern, and the like, such as the data signal pattern and the like. In addition, the redistribution layer 142 may include via pads, connection terminal pads, and the like.

視需要，表面處理層（圖中未示出）可形成於經暴露的重佈層142的表面上。舉例而言，表面處理層可藉由以下各者形成：電解金電鍍、無電金電鍍、有機可焊性保護劑（organic solderability preservative；OSP）或無電錫電鍍、無電銀電鍍、無電鎳電鍍/替代的金電鍍、直接浸金（direct immersion gold；DIG）電鍍、熱空氣焊料調平（hot air solder leveling；HASL）或其類似者，但不限於此。If necessary, a surface treatment layer (not shown in the figure) may be formed on the surface of the exposed redistribution layer 142. For example, the surface treatment layer can be formed by: electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/replacement Gold electroplating, direct immersion gold (DIG) electroplating, hot air solder leveling (HASL) or the like, but not limited thereto.

通孔143可將形成於不同層上的重佈層142、連接墊122或其類似者彼此電連接，從而在扇出型半導體封裝100A中產生電路徑。通孔143中的每一者的材料可為導電材料，諸如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金。通孔143亦可完全填充有導電材料；或者導電材料亦可沿通孔的壁形成。另外，通孔143可具有在先前技術中已知的所有形狀，諸如錐形形狀、圓柱形形狀以及其類似者。The through hole 143 may electrically connect the redistribution layer 142, the connection pad 122 or the like formed on different layers to each other, thereby generating an electrical path in the fan-out semiconductor package 100A. The material of each of the through holes 143 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Titanium (Ti) or its alloys. The through hole 143 may also be completely filled with conductive material; or the conductive material may be formed along the wall of the through hole. In addition, the through hole 143 may have all shapes known in the prior art, such as a tapered shape, a cylindrical shape, and the like.

鈍化層150可另外經組態以保護第二連接構件140免受外部物理或化學損壞。鈍化層150可具有開口151，開口151暴露第二連接構件140的重佈層142的至少部分。可使用彈性模數大於第二連接構件140的絕緣層141的彈性模數的材料作為鈍化層150的材料。舉例而言，可使用不包含玻璃纖維但包含無機填充劑及絕緣樹脂的ABF作為鈍化層150的材料。當ABF用作鈍化層150的材料時，包含於鈍化層150中的無機填充劑的重量百分比可大於包含於第二連接構件140的絕緣層141中的無機填充劑的重量百分比，以改良可靠性。The passivation layer 150 may be additionally configured to protect the second connection member 140 from external physical or chemical damage. The passivation layer 150 may have an opening 151 that exposes at least a portion of the redistribution layer 142 of the second connection member 140. As the material of the passivation layer 150, a material having an elastic modulus greater than that of the insulating layer 141 of the second connection member 140 may be used. For example, ABF, which does not contain glass fiber but contains inorganic filler and insulating resin, can be used as the material of the passivation layer 150. When ABF is used as the material of the passivation layer 150, the weight percentage of the inorganic filler contained in the passivation layer 150 may be greater than the weight percentage of the inorganic filler contained in the insulating layer 141 of the second connection member 140 to improve reliability .

凸塊下金屬層160可另外經組態以改良連接端子170的連接可靠性且改良扇出型半導體封裝100A的板級可靠性。凸塊下金屬層160可連接至經由鈍化層150的開口151暴露的第二連接構件140的重佈層142。可藉由使用諸如金屬的已知導電金屬的已知金屬化方法來在鈍化層150的開口151中形成凸塊下金屬層160，但不限於此。The under bump metal layer 160 may be additionally configured to improve the connection reliability of the connection terminal 170 and improve the board-level reliability of the fan-out semiconductor package 100A. The under-bump metal layer 160 may be connected to the redistribution layer 142 of the second connection member 140 exposed through the opening 151 of the passivation layer 150. The under bump metal layer 160 may be formed in the opening 151 of the passivation layer 150 by a known metallization method using a known conductive metal such as a metal, but is not limited thereto.

連接端子170可另外經組態以在外部實體連接或電連接扇出型半導體封裝100A。舉例而言，扇出型半導體封裝100A可經由連接端子170安裝於電子裝置的主板上。連接端子170中的每一者可由導電材料（例如焊料或其類似者）形成。然而，此僅為實例，且連接端子170中的每一者的材料不特定限於此。連接端子170中的每一者可為焊盤、球、接腳或其類似者。連接端子170可形成為多層結構或單層結構。當連接端子170形成為多層結構時，連接端子170可包含銅（Cu）柱以及焊料。當連接端子170形成為單層結構時，連接端子170可包含錫-銀焊料或銅（Cu）。然而，此僅為實例，且連接端子170不限於此。The connection terminal 170 may additionally be configured to physically or electrically connect the fan-out semiconductor package 100A. For example, the fan-out semiconductor package 100A can be mounted on the motherboard of the electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material (such as solder or the like). However, this is only an example, and the material of each of the connection terminals 170 is not particularly limited thereto. Each of the connection terminals 170 may be a pad, a ball, a pin, or the like. The connection terminal 170 may be formed in a multi-layer structure or a single-layer structure. When the connection terminal 170 is formed in a multilayer structure, the connection terminal 170 may include copper (Cu) pillars and solder. When the connection terminal 170 is formed in a single-layer structure, the connection terminal 170 may include tin-silver solder or copper (Cu). However, this is only an example, and the connection terminal 170 is not limited to this.

連接端子170的數目、間隔、安置或其類似者不受特定限制，且可由熟習此項技術者取決於設計細節而充分修改。舉例而言，可根據半導體晶片120的連接墊122的數目以數十至數千的量提供連接端子170，但不限於此，且亦可以數十至數千或更多或數十至數千或更少的量提供連接端子170。當連接端子170為焊球時，連接端子170可覆蓋延伸至鈍化層150的一個表面上的凸塊下金屬層160的側表面，且連接可靠性可更佳。The number, spacing, placement, or the like of the connection terminals 170 are not particularly limited, and can be sufficiently modified by those skilled in the art depending on design details. For example, the connection terminals 170 may be provided in an amount of tens to thousands according to the number of connection pads 122 of the semiconductor chip 120, but is not limited thereto, and may also be tens to thousands or more or tens to thousands The connection terminal 170 is provided in a smaller amount. When the connection terminal 170 is a solder ball, the connection terminal 170 may cover the side surface of the under bump metal layer 160 extending to one surface of the passivation layer 150, and the connection reliability may be better.

連接端子170中的至少一者可安置於扇出區中。扇出區為除安置有半導體晶片120的區以外的區。與扇入型封裝相比，扇出型封裝可具有極佳可靠度，可實施多個輸入/輸出（I/O）端子，且可促進3D互連。另外，與球狀柵格陣列（ball grid array；BGA）封裝、焊盤柵格陣列（land grid array；LGA）封裝或其類似者相比，扇出型封裝可製造有小的厚度，且可具有價格競爭力。At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out area is an area other than the area where the semiconductor wafer 120 is placed. Compared with fan-in packages, fan-out packages can have excellent reliability, can implement multiple input/output (I/O) terminals, and can facilitate 3D interconnection. In addition, compared to ball grid array (BGA) packages, land grid array (LGA) packages, or the like, fan-out packages can be manufactured with a small thickness and can Price competitive.

圖11為說明扇出型半導體封裝的另一實例的示意性橫截面圖。11 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

圖12為沿圖11的扇出型半導體封裝的線II-II'截取的示意性平面圖。12 is a schematic plan view taken along line II-II' of the fan-out semiconductor package of FIG.

參看圖式，在根據另一例示性實施例的扇出型半導體封裝100B中，圖案層132可延伸至覆蓋第一連接構件110的囊封體130的區。舉例而言，圖案層132可覆蓋囊封體130的整個表面。其他內容與上文所描述的內容重疊，且因此省略其詳細描述。Referring to the drawings, in the fan-out semiconductor package 100B according to another exemplary embodiment, the pattern layer 132 may extend to an area of the encapsulation body 130 covering the first connection member 110. For example, the pattern layer 132 may cover the entire surface of the encapsulation body 130. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

圖13為說明扇出型半導體封裝的另一實例的示意性橫截面圖。13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

圖14為沿圖13的扇出型半導體封裝的線III-III'截取的示意性平面圖。14 is a schematic plan view taken along line III-III' of the fan-out semiconductor package of FIG. 13.

參看圖式，在根據本發明中的另一例示性實施例的扇出型半導體封裝100C中，第一連接構件110可進一步包含安置於穿孔110H的壁上的金屬層115。金屬層115可延伸至絕緣層111的上部部分及下部部分，但不限於此。由半導體晶片120產生的熱（由箭頭表示）可朝向第一連接構件110移動且接著經由金屬層115朝第一連接構件110之上或下耗散。另外，可更加有效地阻隔電磁波。金屬層115亦可藉由已知的電鍍方法而形成，且可包含已知的導電材料。其他內容與上文所描述的內容重疊，且因此省略其詳細描述。Referring to the drawings, in a fan-out semiconductor package 100C according to another exemplary embodiment of the present invention, the first connection member 110 may further include a metal layer 115 disposed on the wall of the through hole 110H. The metal layer 115 may extend to the upper portion and the lower portion of the insulating layer 111, but is not limited thereto. The heat generated by the semiconductor wafer 120 (indicated by the arrow) may move toward the first connection member 110 and then dissipate above or below the first connection member 110 via the metal layer 115. In addition, electromagnetic waves can be blocked more effectively. The metal layer 115 may also be formed by a known plating method, and may include a known conductive material. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

圖15為說明扇出型半導體封裝的另一實例的示意性橫截面圖。15 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

圖16為沿圖15的扇出型半導體封裝的線IV-IV'截取的示意性平面圖。16 is a schematic plan view taken along line IV-IV' of the fan-out semiconductor package of FIG.

參看圖式，在根據另一例示性實施例的扇出型半導體封裝100D中，金屬層128可安置於半導體晶片120的非主動表面上，且通孔133可連接至金屬層128。另外，圖案層132a及圖案層132b可包含覆蓋鄰近於半導體晶片120的非主動表面的囊封體130的至少部分的散熱圖案132a，且可包含重佈半導體晶片120的連接墊122或其類似者的佈線圖案132b。在此情況下，散熱圖案132a與佈線圖案132b可在囊封體130上彼此斷開連接。另外，第一連接構件110可包含分別安置於待與金屬層115斷開連接的絕緣層111的上部表面及下部表面上的重佈層112a及重佈層112b，且重佈層112a及重佈層112b可藉由穿透絕緣層111的通孔113而彼此電連接。另外，覆蓋圖案層132a及圖案層132b的至少部分的鈍化層180可安置於囊封體130上，且散熱構件190可附接至鈍化層180。同時，散熱構件190可直接附接至鈍化層180或可經由連接構件195附接至鈍化層180，以改良可靠性。Referring to the drawings, in the fan-out semiconductor package 100D according to another exemplary embodiment, the metal layer 128 may be disposed on the inactive surface of the semiconductor wafer 120, and the through hole 133 may be connected to the metal layer 128. In addition, the pattern layer 132a and the pattern layer 132b may include a heat dissipation pattern 132a covering at least a portion of the encapsulation body 130 adjacent to the inactive surface of the semiconductor wafer 120, and may include the connection pad 122 of the semiconductor wafer 120 redistributed or the like的wiring pattern 132b. In this case, the heat dissipation pattern 132a and the wiring pattern 132b may be disconnected from each other on the encapsulation body 130. In addition, the first connection member 110 may include a redistribution layer 112a and a redistribution layer 112b disposed on the upper and lower surfaces of the insulating layer 111 to be disconnected from the metal layer 115, and the redistribution layer 112a and the redistribution The layers 112b may be electrically connected to each other by through holes 113 penetrating the insulating layer 111. In addition, the passivation layer 180 covering at least part of the pattern layer 132a and the pattern layer 132b may be disposed on the encapsulation body 130, and the heat dissipation member 190 may be attached to the passivation layer 180. Meanwhile, the heat dissipation member 190 may be directly attached to the passivation layer 180 or may be attached to the passivation layer 180 via the connection member 195 to improve reliability.

金屬層128可用以更加有效地耗散由半導體晶片120產生的熱或更加有效地阻隔電磁波，且可形成於半導體晶片120的非主動表面上。金屬層128可具有板形狀且可覆蓋半導體晶片120的非主動表面的全部，但並非限於此。金屬層128亦可藉由已知的電鍍方法形成且可包含諸如銅（Cu）或其類似者的導電材料。通孔133可連接至金屬層128，以由此連接至半導體晶片120的非主動表面。The metal layer 128 can be used to more effectively dissipate heat generated by the semiconductor wafer 120 or block electromagnetic waves more effectively, and can be formed on the inactive surface of the semiconductor wafer 120. The metal layer 128 may have a plate shape and may cover the entire inactive surface of the semiconductor wafer 120, but is not limited thereto. The metal layer 128 may also be formed by a known plating method and may include a conductive material such as copper (Cu) or the like. The via 133 may be connected to the metal layer 128 to thereby be connected to the inactive surface of the semiconductor wafer 120.

散熱圖案132a可覆蓋佈線圖案132b並非安置於囊封體130上的區。散熱圖案132a可具有板形狀，但不限於此。散熱圖案132a可連接至經由通孔133形成於第一連接構件110中的金屬層115。散熱圖案132a及金屬層115可視需要執行接地（GND）功能。在此情況下，散熱圖案132a及金屬層115可經由用於形成於第一連接構件110及第二連接構件140中的重佈層的接地的圖案或通孔電連接至半導體晶片120的連接墊122中用於接地的連接墊。亦即，圖案層132a及圖案層132b可包含接地圖案。The heat dissipation pattern 132 a may cover the area where the wiring pattern 132 b is not disposed on the encapsulation body 130. The heat dissipation pattern 132a may have a plate shape, but is not limited thereto. The heat dissipation pattern 132 a may be connected to the metal layer 115 formed in the first connection member 110 via the through hole 133. The heat dissipation pattern 132a and the metal layer 115 may perform a ground (GND) function as needed. In this case, the heat dissipation pattern 132a and the metal layer 115 may be electrically connected to the connection pad of the semiconductor chip 120 via the pattern or via hole for grounding of the redistribution layer formed in the first connection member 110 and the second connection member 140 Connection pad for grounding in 122. That is, the pattern layer 132a and the pattern layer 132b may include ground patterns.

佈線圖案132b可為各種用於重佈半導體晶片120的連接墊122的重佈圖案。在散熱圖案132a執行接地功能的情況下，佈線圖案132b可包含除接地圖案以外的功率圖案及信號圖案。意即，圖案層132a及圖案層132b可包含功率圖案及信號圖案。佈線圖案132b可經由通孔133電連接至第一連接構件110的重佈層112a及重佈層112b以及通孔113。另外，佈線圖案132b亦可經由第一連接構件110電連接至第二連接構件140的重佈層142及通孔143。佈線圖案132b亦可經由上文所描述的路徑電連接至半導體晶片120的連接墊122。佈線圖案132b亦可包含各種墊圖案。The wiring pattern 132b may be various redistribution patterns for redistribution of the connection pads 122 of the semiconductor wafer 120. When the heat dissipation pattern 132a performs a grounding function, the wiring pattern 132b may include a power pattern and a signal pattern other than the ground pattern. That is, the pattern layer 132a and the pattern layer 132b may include power patterns and signal patterns. The wiring pattern 132 b may be electrically connected to the redistribution layer 112 a and the redistribution layer 112 b of the first connection member 110 and the through hole 113 through the via hole 133. In addition, the wiring pattern 132b may also be electrically connected to the redistribution layer 142 and the through hole 143 of the second connection member 140 via the first connection member 110. The wiring pattern 132b may also be electrically connected to the connection pad 122 of the semiconductor wafer 120 via the path described above. The wiring pattern 132b may also include various pad patterns.

重佈層112a及重佈層112b可用以重佈連接墊122。在第一連接構件110包含如上文所描述的重佈層112a及重佈層112b的情況下，可減少第二連接構件140的層的數目，以使得可提高設計自由度且有可能薄化第二連接構件140。重佈層112a及重佈層112b可取決於對應層的設計而執行各種功能。舉例而言，重佈層112a及重佈層112b可包含接地（GND）圖案、功率（PWR）圖案、信號（S）圖案以及其類似者。此處，信號（S）圖案可包含除了接地（GND）圖案、功率（PWR）圖案以及其類似者以外的各種信號圖案，諸如資料信號圖案以及其類似者。另外，重佈層112a及重佈層112b可包含通孔墊、連接端子墊以及其類似者。The redistribution layer 112a and the redistribution layer 112b can be used to redistribute the connection pad 122. In the case where the first connection member 110 includes the redistribution layer 112a and the redistribution layer 112b as described above, the number of layers of the second connection member 140 can be reduced, so that design freedom can be improved and it is possible to thin the first Second connection member 140. The redistribution layer 112a and the redistribution layer 112b may perform various functions depending on the design of the corresponding layer. For example, the redistribution layer 112a and the redistribution layer 112b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, power (PWR) pattern, and the like, such as the data signal pattern and the like. In addition, the redistribution layer 112a and the redistribution layer 112b may include via pads, connection terminal pads, and the like.

通孔113可將形成於不同層上的重佈層112a及重佈層112b彼此電連接。通孔113可完全填充有導電材料；或者導電材料亦可沿通孔113的壁形成。另外，通孔113可具有在先前技術中已知的所有形狀，諸如圓柱形形狀、沙漏形狀以及其類似者。The through hole 113 may electrically connect the redistribution layer 112 a and the redistribution layer 112 b formed on different layers to each other. The through hole 113 may be completely filled with conductive material; or the conductive material may be formed along the wall of the through hole 113. In addition, the through hole 113 may have all shapes known in the prior art, such as a cylindrical shape, an hourglass shape, and the like.

鈍化層180可包含與上文所描述的鈍化層150的材料相同或類似的材料。在此情況下，可經由安置於扇出型半導體封裝100D的兩側上的鈍化層150及鈍化層180的對稱效應來抑制扇出型半導體封裝100D的彎曲。然而，鈍化層180的材料不限於此而可為另一材料。舉例而言，可使用包含核心材料（諸如，玻璃織物）或其類似者的預浸體作為鈍化層180的材料。同時，包含於鈍化層180中的無機填充劑的重量百分比可大於包含於囊封體130中的無機填充劑的重量百分比，以抑制彎曲。鈍化層180在其經硬化前亦可附接至囊封體130。在此情況下，歸因於硬化所產生的無機填充劑的移動而可形成朝向穿孔110H的凹坑。The passivation layer 180 may include the same or similar materials as the passivation layer 150 described above. In this case, the bending of the fan-out semiconductor package 100D can be suppressed through the symmetry effect of the passivation layer 150 and the passivation layer 180 disposed on both sides of the fan-out semiconductor package 100D. However, the material of the passivation layer 180 is not limited thereto and may be another material. For example, a prepreg including a core material (such as glass fabric) or the like may be used as the material of the passivation layer 180. Meanwhile, the weight percentage of the inorganic filler contained in the passivation layer 180 may be greater than the weight percentage of the inorganic filler contained in the encapsulation body 130 to suppress bending. The passivation layer 180 may also be attached to the encapsulation body 130 before it is hardened. In this case, pits toward the through holes 110H may be formed due to the movement of the inorganic filler due to hardening.

散熱構件190可為已知的散熱片。散熱構件190可易於耗散經由圖案層132a及圖案層132b的散熱圖案132a耗散到扇出型半導體封裝100A之外的熱。散熱構件190可具有形成於其上部表面中的多個溝槽，以易於耗散熱。在此情況下，可增加表面積以易於耗散熱。只要散熱構件190的材料具有極佳的熱導率，其就不受特別限制。舉例而言，散熱構件190可包含金屬。連接構件195可使散熱構件190易於附接至鈍化層180，且視需要可防止電短路且有效地傳遞熱。可取決於散熱構件190的材料適當地選擇連接構件195的材料。The heat dissipation member 190 may be a known heat sink. The heat dissipation member 190 can easily dissipate heat dissipated outside the fan-out semiconductor package 100A through the heat dissipation patterns 132a of the pattern layer 132a and the pattern layer 132b. The heat dissipation member 190 may have a plurality of grooves formed in the upper surface thereof to easily dissipate heat. In this case, the surface area can be increased to facilitate heat dissipation. As long as the material of the heat dissipation member 190 has excellent thermal conductivity, it is not particularly limited. For example, the heat dissipation member 190 may include metal. The connection member 195 can easily attach the heat dissipation member 190 to the passivation layer 180, and can prevent an electrical short circuit and efficiently transfer heat as necessary. The material of the connection member 195 may be appropriately selected depending on the material of the heat dissipation member 190.

其他內容與上文所描述的內容重疊，且因此省略其詳細描述。Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

圖17為說明扇出型半導體封裝的另一實例的示意性橫截面圖。17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

圖18為沿圖17的扇出型半導體封裝的線V-V'截取的示意性平面圖。18 is a schematic plan view taken along line VV' of the fan-out semiconductor package of FIG. 17.

參看圖式，根據另一例示性實施例的扇出型半導體封裝100E可包含多個穿孔110Ha、穿孔110Hb以及穿孔110Hc，且可包含分別安置於多個穿孔110Ha、穿孔110Hb以及穿孔110Hc中的多個半導體晶片120、半導體晶片125a以及半導體晶片125b。另外安置的半導體晶片125a及半導體晶片125b可為分別包含本體123a及本體123b以及連接墊124a及連接墊124b的彼此相同或不同的積體電路。半導體晶片125a的連接墊124a及半導體晶片125b的連接墊（圖中未示出）亦可電連接至第二連接構件140。視需要，通孔133僅可選擇性地連接至產生大量熱的某些半導體晶片或僅可集中地形成於在其間產生大量熱的半導體晶片120中。其他內容與上文所描述的內容重疊，且因此省略其詳細描述。Referring to the drawings, a fan-out semiconductor package 100E according to another exemplary embodiment may include a plurality of through-holes 110Ha, 110Hb, and 110Hc, and may include multiple holes disposed in the plurality of through-holes 110Ha, 110Hb, and 110Hc, respectively. Semiconductor wafer 120, semiconductor wafer 125a, and semiconductor wafer 125b. The semiconductor wafer 125a and the semiconductor wafer 125b that are additionally disposed may be integrated circuits that include the body 123a and the body 123b and the connection pad 124a and the connection pad 124b, which are the same or different from each other. The connection pad 124a of the semiconductor wafer 125a and the connection pad (not shown) of the semiconductor wafer 125b may also be electrically connected to the second connection member 140. If necessary, the through hole 133 may be selectively connected only to certain semiconductor wafers that generate a large amount of heat or may be formed intensively in the semiconductor wafer 120 that generates a large amount of heat therebetween. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

圖19為說明扇出型半導體封裝的另一實例的示意性橫截面圖。19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

圖20為沿圖19的扇出型半導體封裝的線VI-VI'截取的示意性平面圖。20 is a schematic plan view taken along line VI-VI' of the fan-out semiconductor package of FIG.

參看圖式，根據另一例示性實施例的扇出型半導體封裝100F可包含多個穿孔110Ha、穿孔110Hb以及穿孔110Hc，且可包含分別安置於多個穿孔110Ha、穿孔110Hb以及穿孔110Hc中的半導體晶片120以及被動組件191及被動組件192。被動組件191及被動組件192可為（例如）彼此相同或不同的電容器、電感器或其類似者，但不限於此。同時，通孔133可選擇性地形成為僅連接至半導體晶片120。表面黏著式被動組件193可視需要進一步安置於鈍化層150上。表面黏著式被動組件193亦可為（例如）電容器、電感器或其類似者，但不限於此。在一些情況下，所有被動組件191、被動組件192以及被動組件193可為電容器，且可連接至同一電力佈線線路。其他內容與上文所描述的內容重疊，且因此省略其詳細描述。Referring to the drawings, a fan-out semiconductor package 100F according to another exemplary embodiment may include a plurality of through-holes 110Ha, 110Hb, and 110Hc, and may include semiconductors disposed in the plurality of through-holes 110Ha, 110Hb, and 110Hc, respectively The chip 120 and the passive device 191 and the passive device 192. The passive component 191 and the passive component 192 may be, for example, capacitors, inductors, or the like that are the same as or different from each other, but are not limited thereto. Meanwhile, the through hole 133 may be selectively formed to be connected only to the semiconductor wafer 120. The surface-mounted passive component 193 may be further disposed on the passivation layer 150 as needed. The surface-mounted passive component 193 may also be, for example, a capacitor, an inductor, or the like, but it is not limited thereto. In some cases, all passive components 191, 192, and 193 may be capacitors and may be connected to the same power wiring line. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

圖21為說明扇出型半導體封裝的另一實例的示意性橫截面圖。21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

圖22為沿圖21的扇出型半導體封裝的線VII-VII'截取的示意性平面圖。22 is a schematic plan view taken along line VII-VII' of the fan-out semiconductor package of FIG. 21.

參看圖式，根據另一例示性實施例的扇出型半導體封裝100G可包含多個穿孔110Ha、穿孔110Hb以及穿孔110Hc，且可包含分別安置於多個穿孔110Ha、穿孔110Hb以及穿孔110Hc中的半導體晶片120、半導體晶片125a以及半導體晶片125b。半導體晶片120、半導體晶片125a以及半導體晶片125b分別可具有安置於其非主動表面上的金屬層128、金屬層128a以及金屬層（圖中未示出），且通孔133可連接至金屬層128、金屬層128a以及金屬層（圖中未示出）。另外，圖案層132a及圖案層132b可包含覆蓋鄰近於半導體晶片120、半導體晶片125a以及半導體晶片125b中的每一者的非主動表面的囊封體130的至少部分的散熱圖案132a，且可包含重佈半導體晶片120、半導體晶片125a以及半導體晶片125b的連接墊122、連接墊124a以及連接墊（圖中未示出）的佈線圖案132b。另外，第一連接構件110可包含分別安置於待與金屬層115斷開連接的絕緣層111的上部表面及下部表面上的重佈層112a及重佈層112b，且重佈層112a及重佈層112b可藉由穿透絕緣層111的通孔113而彼此電連接。另外，覆蓋圖案層132a及圖案層132b的至少部分的鈍化層180可安置於囊封體130上，且散熱構件190可附接至鈍化層180。同時，散熱構件190可直接附接至鈍化層180或可經由連接構件195附接至鈍化層180，以改良可靠性。其他內容與上文所描述的內容重疊，且因此省略其詳細描述。Referring to the drawings, a fan-out semiconductor package 100G according to another exemplary embodiment may include a plurality of through-holes 110Ha, 110Hb, and 110Hc, and may include semiconductors disposed in the plurality of through-holes 110Ha, 110Hb, and 110Hc, respectively Wafer 120, semiconductor wafer 125a, and semiconductor wafer 125b. The semiconductor wafer 120, the semiconductor wafer 125a, and the semiconductor wafer 125b may respectively have a metal layer 128, a metal layer 128a, and a metal layer (not shown) disposed on their inactive surfaces, and the via 133 may be connected to the metal layer 128 , A metal layer 128a and a metal layer (not shown in the figure). In addition, the pattern layer 132a and the pattern layer 132b may include a heat dissipation pattern 132a covering at least a portion of the encapsulation 130 adjacent to the inactive surface of each of the semiconductor wafer 120, the semiconductor wafer 125a, and the semiconductor wafer 125b, and may include The wiring patterns 132b of the connection pad 122, the connection pad 124a, and the connection pad (not shown) of the semiconductor wafer 120, the semiconductor wafer 125a, and the semiconductor wafer 125b are redistributed. In addition, the first connection member 110 may include a redistribution layer 112a and a redistribution layer 112b disposed on the upper and lower surfaces of the insulating layer 111 to be disconnected from the metal layer 115, and the redistribution layer 112a and the redistribution The layers 112b may be electrically connected to each other by through holes 113 penetrating the insulating layer 111. In addition, the passivation layer 180 covering at least part of the pattern layer 132a and the pattern layer 132b may be disposed on the encapsulation body 130, and the heat dissipation member 190 may be attached to the passivation layer 180. Meanwhile, the heat dissipation member 190 may be directly attached to the passivation layer 180 or may be attached to the passivation layer 180 via the connection member 195 to improve reliability. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

圖23為說明扇出型半導體封裝的另一實例的示意性橫截面圖。23 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

參考圖式，在根據本發明中的另一例示性實施例的扇出型半導體封裝100H中，第一連接構件110可包含：第一絕緣層111a，其接觸第二連接構件140；第一重佈層112a，其接觸第二連接構件140且嵌入於第一絕緣層111a中；第二重佈層112b，其安置於與嵌入有第一重佈層112a的第一絕緣層111a的一個表面對置的第一絕緣層111a的另一表面上；第二絕緣層111b，其安置於第一絕緣層111a上且覆蓋第二重佈層112b；以及第三重佈層112c，其安置於第二絕緣層111b上。第一重佈層112a、第二重佈層112b以及第三重佈層112c可電連接至連接墊122。同時，第一重佈層112a及第二重佈層112b可經由穿透第一絕緣層111a的第一通孔113a彼此電連接，且第二重佈層112b及第三重佈層112c可經由穿透第二絕緣層111b的第二通孔113b彼此電連接。Referring to the drawings, in a fan-out semiconductor package 100H according to another exemplary embodiment of the present invention, the first connection member 110 may include: a first insulating layer 111a that contacts the second connection member 140; the first weight The cloth layer 112a, which contacts the second connection member 140 and is embedded in the first insulating layer 111a; the second redistribution layer 112b, which is disposed to face one surface of the first insulating layer 111a in which the first redistribution layer 112a is embedded On the other surface of the first insulating layer 111a; the second insulating layer 111b, which is disposed on the first insulating layer 111a and covers the second redistribution layer 112b; and the third redistribution layer 112c, which is disposed on the second On the insulating layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the connection pad 122. Meanwhile, the first redistribution layer 112a and the second redistribution layer 112b may be electrically connected to each other through the first through hole 113a penetrating the first insulating layer 111a, and the second redistribution layer 112b and the third redistribution layer 112c may be passed through The second through holes 113b penetrating the second insulating layer 111b are electrically connected to each other.

由於第一重佈層112a為嵌入式的，因此第二連接構件140的絕緣層141的絕緣距離可基本上恆定，如上文所描述。由於第一連接構件110可包含大量重佈層112a、重佈層112b以及重佈層112c，因此可簡化第二連接構件140。因此，可取決於第二連接構件140的形成程序中出現的缺陷改良產率降低情況。第一重佈層112a可凹入至第一絕緣層111a中，以使得在第一絕緣層111a的下部表面與第一重佈層112a的下部表面之間具有階梯。因此，當形成囊封體130時，可防止囊封體130的材料滲移而污染第一重佈層112a的現象。Since the first redistribution layer 112a is embedded, the insulation distance of the insulation layer 141 of the second connection member 140 may be substantially constant, as described above. Since the first connection member 110 may include a large number of redistribution layers 112a, 112b, and redistribution layers 112c, the second connection member 140 may be simplified. Therefore, the yield reduction situation can be improved depending on defects occurring in the forming process of the second connection member 140. The first redistribution layer 112a may be recessed into the first insulating layer 111a so that there is a step between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Therefore, when the encapsulation body 130 is formed, the material of the encapsulation body 130 can be prevented from migrating and contaminating the first redistribution layer 112a.

第一連接構件110的第一重佈層112a的下部表面可安置於高於半導體晶片120的連接墊122的下部表面的水平高度上。另外，第二連接構件140的重佈層142與第一連接構件110的第一重佈層112a之間的距離可大於第二連接構件140的重佈層142與半導體晶片120的連接墊122之間的距離。原因為，第一重佈層112a可凹入至絕緣層111中。第一連接構件110的第二重佈層112b可安置於半導體晶片120的主動表面與非主動表面之間的水平高度上。第一連接構件110的厚度可形成對應於半導體晶片120的厚度。因此，形成於第一連接構件110中的第二重佈層112b可安置於半導體晶片120的主動表面與非主動表面之間的水平高度上。The lower surface of the first redistribution layer 112 a of the first connection member 110 may be disposed at a higher level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the first redistribution layer 112a of the first connection member 110 may be greater than the distance between the redistribution layer 142 of the second connection member 140 and the connection pad 122 of the semiconductor chip 120 The distance between. The reason is that the first redistribution layer 112a may be recessed into the insulating layer 111. The second redistribution layer 112b of the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120. The thickness of the first connection member 110 may be formed to correspond to the thickness of the semiconductor wafer 120. Therefore, the second redistribution layer 112b formed in the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120.

第一連接構件110的重佈層112a、重佈層112b以及重佈層112c的厚度可大於第二連接構件140的重佈層142的厚度。由於第一連接構件110的厚度可具有等於或大於半導體晶片120的厚度，因此重佈層112a、重佈層112b以及重佈層112c可形成為取決於第一連接構件110的比例而具有較大的大小。另一方面，第二連接構件140的重佈層142可由於較薄而形成相對較小的大小。The thickness of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may have a thickness equal to or greater than that of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be formed to have a larger value depending on the ratio of the first connection member 110 the size of. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed into a relatively small size due to its thinness.

其他內容與上文所描述的內容重疊，且因此省略其詳細描述。同時，對上文所描述的扇出型半導體封裝100B至100G的描述亦可適用於扇出型半導體封裝100H。Other content overlaps with the content described above, and thus a detailed description thereof is omitted. Meanwhile, the description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100H.

圖24為說明扇出型半導體封裝的另一實例的示意性橫截面圖。24 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

參看圖式，在根據另一例示性實施例的扇出型半導體封裝100I中，圖案層132可延伸至覆蓋第一連接構件110的囊封體130的區的至少部分。另外，圖案層132可藉由穿透囊封體130且連接至第一連接構件110的通孔133連接至第一連接構件110。舉例而言，圖案層132可連接至第一連接構件110的第三重佈層112c。電連接至圖案層132的第一連接構件110的重佈層可為接地圖案。意即，圖案層132可連接至第一連接構件110的接地圖案。在此情況下，熱亦可經由第一連接構件110朝下耗散，以使得散熱效果可更佳。於圖式中僅示出第一連接構件110的第一重佈層112a及第三重佈層112c具有電連接至圖案層132的接地圖案的情況，但在一些情況下，第一連接構件110的第二重佈層112b亦可具有經由第一通孔113a電連接至圖案層132的接地圖案。另外，在一些情況下，僅第三重佈層112c亦可具有電連接至圖案層132的接地圖案。Referring to the drawings, in the fan-out semiconductor package 100I according to another exemplary embodiment, the pattern layer 132 may extend to at least a portion of the area of the encapsulation body 130 covering the first connection member 110. In addition, the pattern layer 132 may be connected to the first connection member 110 through the through hole 133 penetrating the encapsulation body 130 and connected to the first connection member 110. For example, the pattern layer 132 may be connected to the third redistribution layer 112c of the first connection member 110. The redistribution layer of the first connection member 110 electrically connected to the pattern layer 132 may be a ground pattern. That is, the pattern layer 132 may be connected to the ground pattern of the first connection member 110. In this case, the heat can also be dissipated downward through the first connecting member 110, so that the heat dissipation effect can be better. In the drawings, only the first redistribution layer 112a and the third redistribution layer 112c of the first connection member 110 have a ground pattern electrically connected to the pattern layer 132, but in some cases, the first connection member 110 The second redistribution layer 112b may also have a ground pattern electrically connected to the pattern layer 132 through the first through hole 113a. In addition, in some cases, only the third redistribution layer 112c may also have a ground pattern electrically connected to the pattern layer 132.

其他內容與上文所描述的內容重疊，且因此省略其詳細描述。上文所描述的扇出型半導體封裝100B至100G的描述亦可適用於扇出型半導體封裝100I。Other content overlaps with the content described above, and thus a detailed description thereof is omitted. The description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100I.

圖25為說明扇出型半導體封裝的另一實例的示意性橫截面圖。25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

參考圖式，在根據本發明中的另一例示性實施例的扇出型半導體封裝100J中，第一連接構件110可包含：第一絕緣層111a；第一重佈層112a及第二重佈層112b，其分別安置於第一絕緣層111a的兩個表面上；第二絕緣層111b，其安置於第一絕緣層111a上且覆蓋第一重佈層112a；第三重佈層112c，其安置於第二絕緣層111b上；第三絕緣層111c，其安置於第一絕緣層111a上且覆蓋第二重佈層112b；以及第四重佈層112d，其安置於第三絕緣層111c上。第一重佈層112a、第二重佈層112b、第三重佈層112c以及第四重佈層112d可電連接至連接墊122。由於第一連接構件110可包含較大數目個重佈層112a、重佈層112b、重佈層112c以及重佈層112d，因此可進一步簡化第二連接構件140。因此，可取決於第二連接構件140的形成程序中出現的缺陷改良產率降低情況。同時，第一重佈層112a、第二重佈層112b、第三重佈層112c以及第四重佈層112d可經由分別穿透第一絕緣層111a、第二絕緣層111b以及第三絕緣層111c的第一通孔113a、第二通孔113b以及第三通孔113c彼此電連接。Referring to the drawings, in a fan-out semiconductor package 100J according to another exemplary embodiment of the present invention, the first connection member 110 may include: a first insulating layer 111a; a first redistribution layer 112a and a second redistribution A layer 112b, which is disposed on both surfaces of the first insulating layer 111a; a second insulating layer 111b, which is disposed on the first insulating layer 111a and covers the first redistribution layer 112a; a third redistribution layer 112c, which Disposed on the second insulating layer 111b; the third insulating layer 111c, which is disposed on the first insulating layer 111a and covers the second redistribution layer 112b; and the fourth redistribution layer 112d, which is disposed on the third insulating layer 111c . The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pad 122. Since the first connection member 110 may include a larger number of redistribution layers 112a, 112b, redistribution layers 112c, and redistribution layers 112d, the second connection member 140 may be further simplified. Therefore, the yield reduction situation can be improved depending on defects occurring in the forming process of the second connection member 140. Meanwhile, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c and the fourth redistribution layer 112d can penetrate the first insulating layer 111a, the second insulating layer 111b and the third insulating layer respectively The first through hole 113a, the second through hole 113b, and the third through hole 113c of 111c are electrically connected to each other.

第一絕緣層111a的厚度可大於第二絕緣層111b的厚度以及第三絕緣層111c的厚度。第一絕緣層111a可相對較厚以便維持剛度，且可引入第二絕緣層111b以及第三絕緣層111c以便形成較大數目個重佈層112c及重佈層112d。第一絕緣層111a包含的絕緣材料可與第二絕緣層111b及第三絕緣層111c的絕緣材料不同。舉例而言，第一絕緣層111a可為（例如）包含核心材料、無機填充劑以及絕緣樹脂的預浸體，且第二絕緣層111b及第三絕緣層111c可為ABF或包含無機填充劑及絕緣樹脂的感光性絕緣膜。然而，第一絕緣層111a的材料及第二絕緣層111b及第三絕緣層111c的材料不限於此。The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and 112d. The insulating material included in the first insulating layer 111a may be different from the insulating materials of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be ABF or include an inorganic filler and Photosensitive insulating film of insulating resin. However, the materials of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

第一連接構件110的第三重佈層112c的下部表面可安置於半導體晶片120的連接墊122的下部表面之下的水平高度上。另外，第二連接構件140的重佈層142與第一連接構件110的第三重佈層112c之間的距離可小於第二連接構件140的重佈層142與半導體晶片120的連接墊122之間的距離。其原因為第三重佈層112c可以凸起形式安置於第二絕緣層111b上，從而接觸第二連接構件140。第一連接構件110的第一重佈層112a及第二重佈層112b可安置於半導體晶片120的主動表面與非主動表面之間的水平高度上。第一連接構件110的厚度可形成對應於半導體晶片120的厚度。因此，形成於第一連接構件110中的第一重佈層112a及第二重佈層112b可安置於半導體晶片120的主動表面與非主動表面之間的水平高度上。The lower surface of the third redistribution layer 112c of the first connection member 110 may be disposed at a level below the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the third redistribution layer 112c of the first connection member 110 may be smaller than the distance between the redistribution layer 142 of the second connection member 140 and the connection pad 122 of the semiconductor chip 120 The distance between. The reason for this is that the third redistribution layer 112c may be disposed on the second insulating layer 111b in a convex form so as to contact the second connection member 140. The first redistribution layer 112a and the second redistribution layer 112b of the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120. The thickness of the first connection member 110 may be formed to correspond to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112a and the second redistribution layer 112b formed in the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120.

第一連接構件110的重佈層112a、重佈層112b、重佈層112c以及重佈層112d的厚度可大於第二連接構件140的重佈層142的厚度。由於第一連接構件110的厚度可具有等於或大於半導體晶片120的厚度，因此重佈層112a、重佈層112b、重佈層112c以及重佈層112d亦可形成為具有較大的大小。另一方面，第二連接構件140的重佈層142可由於較薄而形成相對較小的大小。The thickness of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also be formed to have larger sizes. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed into a relatively small size due to its thinness.

其他內容與上文所描述的內容重疊，且因此省略其詳細描述。同時，對上文所描述的扇出型半導體封裝100B至100G的描述亦可適用於扇出型半導體封裝100J。Other content overlaps with the content described above, and thus a detailed description thereof is omitted. Meanwhile, the description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100J.

圖26為說明扇出型半導體封裝的另一實例的示意性橫截面圖。26 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

參看圖式，在根據另一例示性實施例的扇出型半導體封裝100K中，圖案層132可延伸至覆蓋第一連接構件110的囊封體130的區的至少部分。另外，圖案層132可藉由穿透囊封體130且連接至第一連接構件110的通孔133連接至第一連接構件110。舉例而言，圖案層132可連接至第一連接構件110的第四重佈層112d。電連接至圖案層132的第一連接構件110的重佈層可為接地圖案。意即，圖案層132可連接至第一連接構件110的接地圖案。在此情況下，熱亦可經由第一連接構件110朝下耗散，以使得散熱效果可更佳。在圖式中僅示出第一連接構件110的第二重佈層112b及第四重佈層112d具有電連接至圖案層132的接地圖案，但在一些情況下，第一連接構件110的第一重佈層112a及/或第三重佈層112c亦可具有經由第一通孔113a及/或第二通孔113b電連接至圖案層132的接地圖案。另外，在一些情況下，僅第四重佈層112d亦可具有電連接至圖案層132的接地圖案。Referring to the drawings, in the fan-out semiconductor package 100K according to another exemplary embodiment, the pattern layer 132 may extend to at least a portion of the area of the encapsulation body 130 covering the first connection member 110. In addition, the pattern layer 132 may be connected to the first connection member 110 through the through hole 133 penetrating the encapsulation body 130 and connected to the first connection member 110. For example, the pattern layer 132 may be connected to the fourth redistribution layer 112d of the first connection member 110. The redistribution layer of the first connection member 110 electrically connected to the pattern layer 132 may be a ground pattern. That is, the pattern layer 132 may be connected to the ground pattern of the first connection member 110. In this case, the heat can also be dissipated downward through the first connecting member 110, so that the heat dissipation effect can be better. In the drawings, only the second redistribution layer 112b and the fourth redistribution layer 112d of the first connection member 110 have a ground pattern electrically connected to the pattern layer 132, but in some cases, the first connection member 110 The first redistribution layer 112a and/or the third redistribution layer 112c may also have a ground pattern electrically connected to the pattern layer 132 through the first through hole 113a and/or the second through hole 113b. In addition, in some cases, only the fourth redistribution layer 112d may also have a ground pattern electrically connected to the pattern layer 132.

其他內容與上文所描述的內容重疊，且因此省略其詳細描述。上文所描述的扇出型半導體封裝100B至100G的描述亦可適用於扇出型半導體封裝100K。Other content overlaps with the content described above, and thus a detailed description thereof is omitted. The description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100K.

如上文所闡述，根據本發明中的例示性實施例，可提供扇出型半導體封裝，其中可藉由簡單程序有效地耗散由半導體晶片產生的熱。As explained above, according to the exemplary embodiments in the present invention, a fan-out type semiconductor package can be provided in which the heat generated by the semiconductor chip can be efficiently dissipated by a simple procedure.

雖然上文已展示並描述了例示性實施例，但對於熟習此項技術者將顯而易見的是，可在不脫離如由所附申請專利範圍定義的本發明的範疇的情況下進行修改及變化。Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the present invention as defined by the scope of the appended patent application.

100‧‧‧半導體封裝100‧‧‧Semiconductor packaging

100A、100B、100C、100D、100E、100F、100G、100H、100I、100J、100K‧‧‧扇出型半導體封裝100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K

110‧‧‧第一連接構件110‧‧‧First connecting member

110H、110Ha、110Hb、110Hc‧‧‧穿孔110H, 110Ha, 110Hb, 110Hc

111‧‧‧絕緣層111‧‧‧Insulation

111a‧‧‧第一絕緣層111a‧‧‧First insulation layer

111b‧‧‧第二絕緣層111b‧‧‧Second insulation layer

111c‧‧‧第三絕緣層111c‧‧‧The third insulating layer

112a‧‧‧第一重佈層112a‧‧‧The first layer of cloth

112b‧‧‧第二重佈層112b‧‧‧The second layer

112c‧‧‧第三重佈層112c‧‧‧The third layer of cloth

112d‧‧‧第四重佈層112d‧‧‧The fourth layer

113‧‧‧通孔113‧‧‧Through hole

113a‧‧‧第一通孔113a‧‧‧First through hole

113b‧‧‧第二通孔113b‧‧‧Second through hole

113c‧‧‧第三通孔113c‧‧‧th through hole

115、128、128a‧‧‧金屬層115, 128, 128a ‧‧‧ metal layer

120、125a、125b‧‧‧半導體晶片120, 125a, 125b ‧‧‧ semiconductor chip

121、123a、123b‧‧‧本體121, 123a, 123b

122、124a、124b‧‧‧連接墊122, 124a, 124b ‧‧‧ connection pad

123‧‧‧鈍化層123‧‧‧passivation layer

130‧‧‧囊封體130‧‧‧Encapsulated body

131、133‧‧‧通孔131, 133‧‧‧through hole

132‧‧‧圖案層132‧‧‧pattern layer

132a‧‧‧圖案層/散熱圖案132a‧‧‧pattern layer/heat dissipation pattern

132b‧‧‧圖案層/佈線圖案132b‧‧‧pattern layer/wiring pattern

140‧‧‧第二連接構件140‧‧‧Second connecting member

141‧‧‧絕緣層141‧‧‧Insulation

142‧‧‧重佈層142‧‧‧ heavy cloth layer

143‧‧‧通孔143‧‧‧Through hole

150、180‧‧‧鈍化層150, 180‧‧‧ Passivation layer

151‧‧‧開口151‧‧‧ opening

160‧‧‧凸塊下金屬層160‧‧‧ under bump metal layer

170‧‧‧連接端子170‧‧‧Connecting terminal

190‧‧‧散熱構件190‧‧‧radiating component

191、192‧‧‧被動組件191,192‧‧‧Passive components

193‧‧‧表面黏著式被動組件193‧‧‧Surface-mounted passive components

195‧‧‧連接構件195‧‧‧Connecting member

1000‧‧‧電子裝置1000‧‧‧Electronic device

1010‧‧‧母板1010‧‧‧Motherboard

1020‧‧‧晶片相關組件1020‧‧‧chip related components

1030‧‧‧網路相關組件1030‧‧‧Network-related components

1040‧‧‧其他組件1040‧‧‧Other components

1050、1130‧‧‧攝影機模組1050、1130‧‧‧Camera module

1060‧‧‧天線1060‧‧‧ Antenna

1070‧‧‧顯示裝置1070‧‧‧Display device

1080‧‧‧電池1080‧‧‧Battery

1090‧‧‧信號線1090‧‧‧Signal cable

1100‧‧‧智慧型電話1100‧‧‧Smartphone

1101‧‧‧本體1101‧‧‧Body

1110‧‧‧主板1110‧‧‧ Motherboard

1120‧‧‧電子組件1120‧‧‧Electronic components

2100‧‧‧扇出型半導體封裝2100‧‧‧Fan-out semiconductor package

2120‧‧‧半導體晶片2120‧‧‧Semiconductor chip

2121‧‧‧本體2121‧‧‧Body

2122‧‧‧連接墊2122‧‧‧ connection pad

2130‧‧‧囊封體2130‧‧‧Encapsulated body

2140‧‧‧連接構件2140‧‧‧Connecting member

2141‧‧‧絕緣層2141‧‧‧Insulation

2142‧‧‧重佈層2142‧‧‧ heavy cloth layer

2143‧‧‧通孔2143‧‧‧Through hole

2150‧‧‧鈍化層2150‧‧‧passivation layer

2160‧‧‧凸塊下金屬層2160‧‧‧ under bump metal layer

2170‧‧‧焊球2170‧‧‧solder ball

2200‧‧‧扇入型半導體封裝2200‧‧‧Fan-in semiconductor package

2220‧‧‧半導體晶片2220‧‧‧Semiconductor chip

2221‧‧‧本體2221‧‧‧Body

2222‧‧‧連接墊2222‧‧‧ connection pad

2223‧‧‧鈍化層2223‧‧‧passivation layer

2240‧‧‧連接構件2240‧‧‧Connecting member

2241‧‧‧絕緣層2241‧‧‧Insulation

2242‧‧‧佈線圖案2242‧‧‧Wiring pattern

2243‧‧‧通孔2243‧‧‧Through hole

2243h‧‧‧通路孔2243h‧‧‧via hole

2250‧‧‧鈍化層2250‧‧‧passivation layer

2251‧‧‧開口2251‧‧‧ opening

2260‧‧‧凸塊下金屬層2260‧‧‧ under bump metal layer

2270‧‧‧焊球2270‧‧‧solder ball

2280‧‧‧底部填充樹脂2280‧‧‧Bottom filling resin

2290‧‧‧模製材料2290‧‧‧Molding material

2301‧‧‧插入式基板2301‧‧‧Plug-in board

2302‧‧‧單獨的插入式基板2302‧‧‧Separate plug-in board

2500‧‧‧主板2500‧‧‧ Motherboard

I-I’、II-II’、III-III’、IV-IV’、V-V’、VI-VI’、VII-VII’‧‧‧線I-I’, II-II’, III-III’, IV-IV’, V-V’, VI-VI’, VII-VII’‧‧‧ line

自以下結合附圖進行的詳細描述，將更清楚地理解本發明的上述及其他態樣、特徵以及優點，其中： 圖1為說明電子裝置系統的實例的示意性方塊圖。 圖2為說明電子裝置的實例的示意性透視圖。 圖3A及圖3B為說明在被封裝之前及被封裝之後的扇入型半導體封裝的狀態的示意性橫截面圖。 圖4為說明扇入型半導體封裝的封裝程序的示意性橫截面圖。 圖5為說明扇入型半導體封裝安裝於插入式基板上且最終安裝於電子裝置的主板上的情況的示意性橫截面圖。 圖6為說明扇入型半導體封裝嵌入於插入式基板中且最終安裝於電子裝置的主板上的情況的示意性橫截面圖。 圖7為說明扇出型半導體封裝的示意性橫截面圖。 圖8為說明扇出型半導體封裝安裝於電子裝置的主板上的情況的示意性橫截面圖。 圖9為說明扇出型半導體封裝的實例的示意性橫截面圖。 圖10為沿圖9的扇出型半導體封裝的線I-I'截取的示意性平面圖。 圖11為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖12為沿圖11的扇出型半導體封裝的線II-II'截取的示意性平面圖。 圖13為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖14為沿圖13的扇出型半導體封裝的線III-III'截取的示意性平面圖。 圖15為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖16為沿圖15的扇出型半導體封裝的線IV-IV'截取的示意性平面圖。 圖17為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖18為沿圖17的扇出型半導體封裝的線V-V'截取的示意性平面圖。 圖19為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖20為沿圖19的扇出型半導體封裝的線VI-VI'截取的示意性平面圖。 圖21為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖22為沿圖21的扇出型半導體封裝的線VII-VII'截取的示意性平面圖。 圖23為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖24為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖25為說明扇出型半導體封裝的另一實例的示意性橫截面圖。 圖26為說明扇出型半導體封裝的另一實例的示意性橫截面圖。The above and other aspects, features, and advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the drawings, wherein: FIG. 1 is a schematic block diagram illustrating an example of an electronic device system. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged. 4 is a schematic cross-sectional view illustrating a packaging procedure of a fan-in semiconductor package. FIG. 5 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device. 6 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. 8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package. FIG. 10 is a schematic plan view taken along line II′ of the fan-out semiconductor package of FIG. 9. 11 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 12 is a schematic plan view taken along line II-II' of the fan-out semiconductor package of FIG. 13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 14 is a schematic plan view taken along line III-III' of the fan-out semiconductor package of FIG. 13. 15 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 16 is a schematic plan view taken along line IV-IV' of the fan-out semiconductor package of FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 18 is a schematic plan view taken along line VV' of the fan-out semiconductor package of FIG. 17. 19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 20 is a schematic plan view taken along line VI-VI' of the fan-out semiconductor package of FIG. 21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 22 is a schematic plan view taken along line VII-VII' of the fan-out semiconductor package of FIG. 21. 23 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 24 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 26 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Claims (11)

一種扇出型半導體封裝，包括： 半導體晶片，具有主動表面及非主動表面，所述主動表面上安置有連接墊且所述非主動表面與所述主動表面對置； 囊封體，具有通孔且囊封所述半導體晶片的所述非主動表面的至少部分，其中所述通孔穿透所述囊封體； 圖案層，其安置於所述囊封體上且覆蓋鄰近於所述半導體晶片的所述非主動表面的所述囊封體的至少部分，其中所述圖案層與所述半導體晶片的所述非主動表面藉由所述通孔彼此連接；以及 連接構件，其安置於所述半導體晶片的所述主動表面上且包含電連接至所述半導體晶片的所述連接墊的重佈層， 其中所述圖案層從所述囊封體的上層凸起。A fan-out semiconductor package includes: a semiconductor chip having an active surface and a non-active surface, a connection pad is disposed on the active surface and the non-active surface is opposed to the active surface; an encapsulation body with a through hole And encapsulating at least part of the inactive surface of the semiconductor wafer, wherein the through hole penetrates the encapsulation body; a pattern layer, which is disposed on the encapsulation body and covers adjacent to the semiconductor wafer At least part of the encapsulated body of the non-active surface, wherein the pattern layer and the non-active surface of the semiconductor wafer are connected to each other through the through hole; and a connecting member, which is disposed on the A redistribution layer electrically connected to the connection pad of the semiconductor wafer on the active surface of the semiconductor wafer, wherein the pattern layer protrudes from an upper layer of the encapsulation body. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述圖案層與所述通孔彼此整合且所述圖案層與所述通孔之間不具有邊界。The fan-out semiconductor package as described in item 1 of the patent application range, wherein the pattern layer and the via are integrated with each other and there is no boundary between the pattern layer and the via. 如申請專利範圍第1項所述的扇出型半導體封裝，其進一步包括金屬層，所述金屬層安置於所述半導體晶片的所述非主動表面上，其中所述通孔與所述金屬層接觸。The fan-out semiconductor package according to item 1 of the patent application scope further includes a metal layer disposed on the inactive surface of the semiconductor wafer, wherein the through hole and the metal layer contact. 如申請專利範圍第1項所述的扇出型半導體封裝，其進一步包括： 鈍化層，其覆蓋所述圖案層的至少部分；以及 散熱構件，其附接至所述鈍化層。The fan-out semiconductor package as described in item 1 of the patent scope, further comprising: a passivation layer that covers at least part of the pattern layer; and a heat dissipation member that is attached to the passivation layer. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述圖案層包含與所述半導體晶片的所述連接墊電絕緣的圖案。The fan-out semiconductor package as described in item 1 of the patent application range, wherein the pattern layer includes a pattern electrically insulated from the connection pad of the semiconductor wafer. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述圖案層包含接地圖案。The fan-out semiconductor package as described in item 1 of the patent application range, wherein the pattern layer includes a ground pattern. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述圖案層進一步包含信號圖案。The fan-out semiconductor package as described in item 6 of the patent application range, wherein the pattern layer further includes a signal pattern. 如申請專利範圍第1項所述的扇出型半導體封裝，其進一步包括具有穿孔的核心構件，其中所述半導體晶片安置於所述核心構件的所述穿孔中，且所述囊封體囊封所述核心構件的至少部分且填充所述穿孔的至少部分。The fan-out semiconductor package according to item 1 of the patent application scope, further comprising a core member having a through hole, wherein the semiconductor wafer is disposed in the through hole of the core member, and the encapsulation body is encapsulated At least part of the core member and fills at least part of the perforation. 如申請專利範圍第8項所述的扇出型半導體封裝，其中所述核心構件包括電連接至所述連接墊的至少一個重佈層。The fan-out semiconductor package as recited in item 8 of the patent application range, wherein the core member includes at least one redistribution layer electrically connected to the connection pad. 如申請專利範圍第8項所述的扇出型半導體封裝，其進一步包括金屬層，所述金屬層安置於所述穿孔的壁上。The fan-out semiconductor package as described in item 8 of the patent application scope further includes a metal layer disposed on the perforated wall. 如申請專利範圍第8項所述的扇出型半導體封裝，其中所述核心構件包含作為所述穿孔的第一穿孔及第二穿孔，所述半導體晶片安置於所述第一穿孔中，被動組件安置於所述第二穿孔中，且所述通孔選擇性地連接至所述半導體晶片的所述非主動表面。The fan-out semiconductor package as recited in item 8 of the patent application range, wherein the core member includes a first through hole and a second through hole as the through hole, the semiconductor chip is disposed in the first through hole, and the passive component It is disposed in the second through hole, and the through hole is selectively connected to the inactive surface of the semiconductor wafer.
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