TW201822200A - Memory apparatus - Google Patents

Abstract

A memory apparatus is provided. A current adjustment circuit controls a reference current generation circuit generating a reference current corresponding to a power voltage according to the power voltage, so as to make a sensing amplifier generate a sensing signal corresponding to the power voltage. A processing circuit determines a state of a memory cell unit according to the sensing signal.

Description

Memory device

The present invention relates to an electronic device, and more particularly to a memory device.

Among various memory products, non-volatile memory (non-volatile memory) allows multiple data programming, reading, and erasing operations, and even in the power supply of the memory The data stored in it can be saved after the interruption. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices. In general, the operation of non-volatile memory requires an external power supply voltage, and corresponding to different power supply voltages, the corresponding memory cell currents for reading operations on memory states such as programming and erasing will also be different. In this way, when the power supply voltage changes, the sensing signal generated by the sense amplifier based on the memory cell current and the reference current also changes with the fluctuation of the power supply voltage. However, the memory cell current and the reference current change with the power supply voltage. The resulting changes are not the same, so there may be cases where the memory state of the memory cell is misjudged.

The invention provides a memory device, which can avoid the situation that the memory state of the memory cell is misjudged due to the change of the power supply voltage.

The memory device of the present invention includes a memory array, a sense amplifier, a reference current generation circuit, a current adjustment circuit, and a processing circuit. The memory array includes at least one memory cell unit, which is coupled to a power voltage and outputs a memory cell current according to a word line selection signal, a bit line selection signal, and a control signal. The reference current generating circuit is coupled to the power supply voltage to generate a reference current. The sense amplifier is coupled to the memory array and the reference current generating circuit, and generates a sensing signal according to the memory cell current and the reference current. The sense amplifier includes a current comparison circuit. The current comparison circuit is coupled to the memory cell unit and the reference current generating circuit, and compares the memory cell current and the reference current to generate a sensing signal. The current adjustment circuit is coupled to the power supply voltage and the reference current generation circuit, and controls the reference current generation circuit to generate a reference current corresponding to the power supply voltage according to the power supply voltage. The processing circuit is coupled to the current comparison circuit, and judges the memory state of the memory cell unit according to the sensing signal.

In an embodiment of the present invention, the current comparison circuit includes a first current mirror circuit and a second current mirror circuit. The input terminal and the output terminal of the first current mirror circuit are respectively coupled to the memory cell unit and the output terminal of the current comparison circuit, and a first current mirror signal is generated at the output terminal of the first current mirror circuit according to the memory cell current. The input terminal and the output terminal of the second current mirror circuit are respectively coupled to the output terminals of the reference current generating circuit and the current comparison circuit, and generate a second current mirror signal according to the reference current, and react to the current according to the first current mirror signal and the second current mirror signal. The bias state of the comparison circuit generates a sensing signal at the output of the current comparison circuit.

In an embodiment of the present invention, the above-mentioned reference current generating circuit includes a plurality of current sources, which are connected in parallel between the input terminal of the second current mirror circuit and the ground, and are respectively controlled by the current adjustment circuit to generate a current. The input terminal of the two current mirror circuit generates a reference current corresponding to the power supply voltage.

In an embodiment of the present invention, each of the current sources includes a resistor and a switch. The resistor is coupled to the input terminal of the second current mirror circuit. The switch is coupled between the resistor and the ground. The switch is controlled by the current adjustment circuit to change its conducting state, so that the input terminal of the second current mirror circuit generates a reference current corresponding to the power supply voltage.

In an embodiment of the present invention, the current adjusting circuit includes a voltage dividing circuit, an analog-to-digital conversion circuit, and a first encoder. The voltage dividing circuit is coupled to the power voltage, and divides the power voltage to generate a divided voltage. The analog digital conversion circuit is coupled to the voltage dividing circuit and converts the divided voltage into a digital control signal. The first encoder is coupled to the analog digital conversion circuit and the plurality of switches, and generates a switch control signal according to the digital control signal to control the conduction states of the plurality of switches, and generates a corresponding power supply voltage at the input end of the second current mirror circuit. Reference current.

In an embodiment of the present invention, the voltage dividing circuit includes a first resistor and a second resistor. The second resistor and the first resistor are connected in series between the power voltage and the ground. The first resistor and the second resistor are in common. The contact generates a divided voltage.

In an embodiment of the present invention, the analog-to-digital conversion circuit includes a plurality of voltage dividing resistors, a plurality of comparators, and a second encoder. A plurality of voltage dividing resistors are connected in series between the reference voltage and the ground to generate a plurality of sub-reference voltages. The first input terminal of each comparator is coupled to the divided voltage, and the second input terminal of each comparator is respectively coupled to the corresponding sub-reference voltage, so as to generate a thermometer code signal at the output terminal of the comparator. The second encoder is coupled to the plurality of comparators, and encodes the hot code signal to generate a digital control signal.

In one embodiment of the present invention, the digital control signal is a binary code signal, and the switch control signal is a one-hot code signal.

In an embodiment of the present invention, the first encoder further stores a lookup table, and converts the hot code signal into a single hot code signal according to the lookup table.

Based on the above, the embodiment of the present invention controls the reference current generating circuit to generate a better reference current corresponding to the power supply voltage according to the power supply voltage, so that the sense amplifier generates a sensing signal corresponding to the power supply voltage, and avoids generating memory due to a change in power supply voltage Misjudgment of the memory state of the cell.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. Please refer to FIG. 1. The memory device includes a memory array 102, a sense amplifier SA1, a reference current generation circuit 104, a current adjustment circuit 108, and a processing circuit 110. The sense amplifier SA1 is coupled to the memory array 102, the reference current generation circuit 104, and the processing circuit 110. The processing circuit 110 may be, for example, a central processing unit, and the memory array 102 may be, for example, a flash memory array, but is not limited thereto. The memory array 102 includes at least one memory cell unit 112, which is coupled to the power supply voltage VDD. And output the memory cell current IC1 according to the word line selection signal SWL, the bit line selection signal SGD, and the control signal FWL. The reference current generation circuit 104 is coupled to the current comparison circuit 106 and the current adjustment circuit 108. The reference current generating circuit 104 can be used to generate a reference current Iref. The sense amplifier SA1 can generate a sensing signal S1 according to the memory cell current IC1 and the reference current Iref. Further, the sense amplifier circuit SA1 can include a current comparison circuit 106, and the current comparison circuit 106 can compare the memory cell current IC1 and the reference current Iref. In order to generate the sensing signal S1, the current adjustment circuit 108 can control the reference current generation circuit to generate the reference current Iref corresponding to the power supply voltage VDD according to the power supply voltage VDD.

In addition, the processing circuit 110 can determine the memory state of the memory cell unit 112 according to the sensing signal S1. Furthermore, the processing circuit 110 can obtain the comparison result between the memory cell current IC1 and the reference current Iref according to the sensing signal S1. Furthermore, the memory state of the memory cell unit 112 can be determined. For example, when the memory cell current IC1 is greater than the reference current Iref, the memory cell unit 112 can be judged to be in an erased state, and when the memory cell current IC1 is not greater than the reference current Iref, the memory can be judged The cell unit 112 is in a stylized state.

Because the current adjustment circuit 108 of this embodiment can control the reference current generation circuit 104 to generate the reference current Iref corresponding to the power supply voltage VDD according to the power supply voltage VDD. For example, when the voltage value of the power supply voltage VDD provided to the memory cell unit 112 decreases, the current adjustment circuit 108 may control the reference current generation circuit 104 to generate a better reference current Iref according to the power supply voltage VDD, so as to prevent the IC1 from being damaged by the power supply. The voltage VDD decreases and becomes smaller. The reference current Iref which becomes smaller and smaller is compared with the memory cell current IC1 which becomes larger and smaller, and the memory cell unit 112 in the erased state is misjudged as the memory cell unit 112 in the stylized state.

FIG. 2 is a schematic diagram of a memory device according to another embodiment of the present invention. Please refer to FIG. 2. In this embodiment, the memory cell unit 112 may include a word line selection transistor M1, a memory transistor M2, and a bit line selection transistor M3. A word line selection transistor M1, a memory transistor M2, and a bit The element line selection transistor M3 is connected in series between the power supply voltage VDD and the current comparison circuit 106. The gates of the word line selection transistor M1, the memory transistor M2, and the bit line selection transistor M3 respectively receive the word line selection. The signal SWL, the control signal FWL, and the bit line selection signal SGD. The memory transistor M2 has a floating gate for storing data charges, and can provide a memory cell current IC1 in response to a control signal.

In addition, the current comparison circuit 106 may include a current mirror circuit 202 and a current mirror circuit 204, and the reference current generation circuit 104 may include a plurality of current sources I1 ~ IN, where N is a positive integer. Multiple current sources I1 ~ IN are connected in parallel between the input terminal of the current mirror circuit 204 and the ground, and are respectively controlled by the current adjustment circuit 108 to generate a current, so that the input terminal of the current mirror circuit 204 generates a reference current Iref corresponding to the power supply voltage VDD. . The input and output of the current mirror circuit 202 are respectively coupled to the memory cell 112 and the output of the current comparison circuit 106. The input and output of the current mirror circuit 204 are respectively coupled to the reference current generation circuit 104 and the current comparison circuit 106. Output. The current mirror circuit 202 generates a current mirror signal IM1 at the output terminal of the current mirror circuit 202 according to the memory cell current IC1. The current mirror circuit 204 generates a current mirror signal IM2 according to the reference current Iref. The current mirror signal IM1 and the current mirror signal IM2 are generated based on the memory cell current IC1 and the reference current Iref, and the sensing signal S1 is the current mirror signal IM1 and the current. The mirror signal IM2 is generated by the bias state of the current comparison circuit 106, so the processing circuit 110 can also learn the comparison result between the memory cell current IC1 and the reference current Iref according to the sensing signal S1, and then judge the memory of the memory cell unit 112. status. Among them, the reference current Iref can make a better change in response to the change in the power supply voltage VDD, so that the situation of misjudgment of the memory state of the memory cell due to the change in the power supply voltage VDD can be avoided.

FIG. 3 is a schematic diagram of a memory device according to another embodiment of the present invention. Please refer to FIG. 3. Further, the current mirror circuit 202 may include, for example, a transistor M4 and a transistor M5, and the current mirror circuit 204 may include a transistor Q1 and a transistor Q2, where the transistor M4 is coupled between the memory cell unit 112 and the ground The drain and the source of the transistor M4 are coupled, and the gate of the transistor M4 is more coupled to the gate of the transistor M5. The drain and source of transistor M5 are respectively coupled to the drain and ground of transistor Q1. The source of the transistor Q1 is coupled to the power supply voltage VDD, the gate of the transistor Q1 is coupled to the gate of the transistor Q2, and the source and the drain of the transistor Q2 are respectively coupled to the power supply voltage VDD and the reference current generating circuit 104. Transistor M4 and transistor M5 can generate a current mirror signal IM1 at the drain of transistor M5 according to the memory cell current IC1, and transistors Q1 and Q2 can generate a current mirror signal at the drain of transistor Q2 according to the reference current Iref IM2, the current mirror signal IM1 and the current mirror signal IM2 can respond to the bias state of the transistor M5 to generate a sensing signal S1 for the processing circuit 110 to determine the memory state of the memory cell unit 112.

In this embodiment, the current sources I1 to IN of FIG. 3 may be implemented by, for example, resistors and switches connected in series between the input terminal 204 and the ground of the current mirror circuit, for example, connected in series with the input terminal 204 of the current mirror circuit and The resistor R1 and the switch SW1, the resistor R2 and the switch SW2, ... the resistor RN and the switch SWN between the grounds, where N is a positive integer. The switches SW1 to SWN can be implemented by, for example, transistor switches, but not limited to this. Each of the switches SW1 to SWN can receive the switching control signal SC1 from the current adjustment circuit 108 to change its conducting state, thereby changing the reference current Iref. The current value. The current adjustment circuit 108 may include, for example, a voltage dividing circuit 302, an analog digital conversion circuit 304, and an encoder 306. The analog digital conversion circuit 304 is coupled to the voltage dividing circuit 302 and the encoder 306. The encoder 306 is further coupled to a reference current generating circuit. 104.

The voltage dividing circuit 302 can divide the power supply voltage VDD to generate a divided voltage VD1. In this embodiment, the voltage dividing circuit 302 can include, for example, a resistor RD1 and a resistor RD2, and a resistor RD1 connected in series between the power voltage VDD and the ground. The common contact with the resistor RD2 is coupled to the analog-to-digital conversion circuit 304 for generating a divided voltage VD1. The analog digital conversion circuit 304 converts the divided voltage VD1 into a digital control signal SD1. The encoder 306 can generate a switching control signal SC1 according to the digital control signal SD1 to control the conduction state of the switches SW1 to SWN. The input terminal generates a reference current Iref corresponding to the power supply voltage VDD.

Further, the analog-to-digital conversion circuit 304 can be implemented, for example, with the implementation shown in FIG. 4. In the embodiment of FIG. 4, the analog-to-digital conversion circuit 304 includes a plurality of voltage dividing resistors RD, a plurality of comparators A1, and an encoder. 402. A plurality of voltage dividing resistors RD are connected in series between the reference voltage Vref and the ground, and a plurality of sub-reference voltages are generated at the contacts between the voltage dividing resistors RD. One input terminal of each comparator A1 is coupled to the divided voltage VD1, and the other input terminal is respectively coupled to the corresponding sub-reference voltage. Each comparator A1 compares its corresponding sub-reference voltage with the divided voltage VD1, and Corresponding bit values are generated according to the comparison results, and then a thermometer code signal is generated at the output ends of these comparators A1. For example, in this embodiment, multiple comparators A1 can generate bit bits in response to the divided voltage VD1 The data is a hot code signal of "0001111". The encoder 402 may encode the hot code signal to generate a digital control signal SC1, where the digital control signal SC1 may be a binary code signal. For example, in this embodiment, a hot code signal whose bit data is "0001111" can be converted into a binary code signal whose bit data is "101". It is worth noting that the hot code signal and the binary code of this embodiment The bit value of the signal is only an exemplary embodiment, and the bit value of the hot code signal and the binary code signal may change with the change of the sub-reference voltage and the divided voltage VD1, which is not used in practice. limit.

The encoder 306 in the embodiment of FIG. 3 can convert a binary code signal output by the analog-to-digital conversion circuit 304 into a one-hot code signal and use it as a switch control signal SC1. For example, the encoder 306 may store a lookup table and convert a binary code signal into a single hot code signal according to the lookup table. The lookup table may be as shown in Table 1: Table 1

As shown in FIG. 3, it is assumed that the reference current generating circuit 104 includes switches SW1 to SW3 (that is, the reference current generating circuit 104 has three current sources), and each bit of a single hot code signal output by the encoder 306 can control one switch respectively. To adjust the reference current Iref. It is worth noting that the binary code signal and the single hot code signal (switch control signal SC1) listed in Table 1 are 3-bit bit signals, but not limited to this. In other embodiments, the binary code The signal and the single hot code signal can also be bit signals with different numbers of bits. In addition, the conversion relationship between the binary code signal and the single hot code signal is not limited to Table 1. It can be based on the user's reference current. The requirements of Iref are adjusted so that the sensing signal S1 can correctly reflect the memory state of the memory cell unit 112 to avoid misjudgment.

In summary, the embodiment of the present invention controls the reference current generating circuit to generate a better reference current corresponding to the power supply voltage according to the power supply voltage, so that the sense amplifier generates a sensing signal corresponding to the power supply voltage, and avoids the processing circuit from being damaged due to the power supply voltage. The situation that the memory state of the memory cell is misjudged by the change.

102‧‧‧Memory Array

104‧‧‧Reference current generating circuit

106‧‧‧Current comparison circuit

108‧‧‧Current adjustment circuit

110‧‧‧Processing circuit

112‧‧‧Memory Cell Unit

202, 204‧‧‧ current mirror circuit

302‧‧‧Divided voltage circuit

304‧‧‧ Analog Digital Conversion Circuit

306‧‧‧ Encoder

402‧‧‧Encoder

SA1‧‧‧Sense Amplifier

VDD‧‧‧ supply voltage

SWL‧‧‧Word line selection signal

SGD‧‧‧Bit line selection signal

FWL‧‧‧Control signal

IC1‧‧‧Memory cell current

S1‧‧‧sensing signal

Iref‧‧‧Reference current

M1‧‧‧Word line selection transistor

M2‧‧‧Memory Transistor

M3‧‧‧bit line selection transistor

I1 ~ IN‧‧‧current source

IM1, IM2‧‧‧ current mirror signal

M4, M5, Q1, Q2 ‧‧‧ Transistors

R1 ~ RN, RD1, RD2‧‧‧ resistance

SW1 ~ SWN‧‧‧Switch

SC1‧‧‧Switch control signal

VD1‧‧‧ divided voltage

SD1‧‧‧Digital control signal

RD‧‧‧Voltage Divider

A1‧‧‧ Comparator

Vref‧‧‧Reference voltage

FIG. 1 is a schematic diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a memory device according to another embodiment of the invention. FIG. 3 is a schematic diagram of a memory device according to another embodiment of the invention. FIG. 4 is a schematic diagram of an analog-to-digital conversion circuit according to an embodiment of the present invention.

Claims (9)

A memory device includes: a memory array including: at least one memory cell unit coupled to a power voltage, and outputting a memory cell current according to a word line selection signal, a bit line selection signal, and a control signal; a reference A current generating circuit is coupled to the power voltage to generate a reference current; a sense amplifier is coupled to the memory array and the reference current generating circuit, and a sensing signal is generated according to the memory cell current and the reference current, and the sensing The sense amplifier includes: a current comparison circuit coupled to the memory cell unit and the reference current generating circuit, comparing the memory cell current and the reference current to generate the sensing signal; a current adjustment circuit, coupled to the power supply voltage and The reference current generation circuit controls the reference current generation circuit to generate the reference current corresponding to the power supply voltage according to the power supply voltage; and a processing circuit coupled to the current comparison circuit to judge the memory of the memory cell unit based on the sensing signal Body status. The memory device according to item 1 of the patent application scope, wherein the current comparison circuit comprises: a first current mirror circuit, the input end and the output end of the current comparison circuit are respectively coupled to the memory cell unit and the output end of the current comparison circuit Generating a first current mirror signal at the output terminal of the first current mirror circuit according to the memory cell current; and a second current mirror circuit whose input terminal and output terminal are respectively coupled to the reference current generating circuit and the current comparison The output end of the circuit generates a second current mirror signal according to the reference current, and the first current mirror signal and the second current mirror signal reflect the bias state of the current comparison circuit and generate the current comparison circuit output. Sense the signal. The memory device according to item 2 of the scope of patent application, wherein the reference current generating circuit includes: a plurality of current sources connected in parallel between an input terminal of the second current mirror circuit and a ground, respectively controlled by the current The adjusting circuit generates a current, so that the input terminal of the second current mirror circuit generates the reference current corresponding to the power supply voltage. According to the memory device in claim 3, each of the current sources includes: a resistor coupled to the input terminal of the second current mirror circuit; and a switch coupled between the resistor and the ground. The switch is controlled by the current adjustment circuit to change its conducting state, so that the input terminal of the second current mirror circuit generates the reference current corresponding to the power supply voltage. The memory device according to item 4 of the scope of patent application, wherein the current adjustment circuit includes: a voltage dividing circuit coupled to the power supply voltage, and dividing the power supply voltage to generate a divided voltage; an analog digital conversion A circuit coupled to the voltage dividing circuit to convert the divided voltage into a digital control signal; and a first encoder coupled to the analog digital conversion circuit and the switches to generate a switch control according to the digital control signal Signals to control the on-states of the switches, and the reference current corresponding to the power supply voltage is generated at the input terminal of the second current mirror circuit. The memory device according to item 5 of the scope of patent application, wherein the voltage dividing circuit includes: a first resistor; and a second resistor connected in series with the first resistor between the power supply voltage and the ground, A common contact point of the first resistor and the second resistor generates the divided voltage. The memory device according to item 5 of the patent application scope, wherein the analog digital conversion circuit includes: a plurality of voltage dividing resistors connected in series between a reference voltage and the ground to generate a plurality of sub-reference voltages; a plurality of comparisons A first input terminal of each of the comparators is coupled to the divided voltage, and a second input terminal of each of the comparators is respectively coupled to the corresponding sub-reference voltages so that a heat is generated at the output terminals of the comparators A thermometer code signal; and a second encoder coupled to the comparators to encode the hot code signal to generate the digital control signal. The memory device according to item 7 of the patent application scope, wherein the digital control signal is a binary code signal, and the switch control signal is a one-hot code signal. According to the memory device described in item 8 of the patent application scope, the first encoder further stores a lookup table, and converts the binary code signal into the single hot code signal according to the lookup table.