TW201541457A - Electrical device and control method - Google Patents

Abstract

A control method is suitable for an electrical device including a flash memory and a controller. The control method includes steps of detecting a temperature of the flash memory; adjusting a reference voltage generated by a reference voltage generation circuit according to the temperature of the flash memory; reading a reading voltage of a memory cell of the flash memory; comparing the reference voltage and the reading voltage by a comparator of the controller. A first level signal is outputted by the comparator when the reading voltage is larger than the reference voltage. A second level signal is outputted by the comparator when the reading voltage is smaller than the reference voltage. The first level signal is larger than the second level signal.

Description

Electronic device and control method

The present invention relates to a flash memory, and more particularly to a flash memory that can adjust a reference voltage according to the temperature of the flash memory.

In recent years, Flash Memory is suitable for use in various electronic devices, especially portable electronic products, because of its non-volatile data, power saving, small size, and no mechanical structure.

Traditionally, flash memory has a memory array for storing data. The memory array has a plurality of storage units, and each storage unit can be used to store one-bit data. With the advancement of process technology, the volume of each storage unit is getting smaller and smaller, but the data stored in the storage unit is more susceptible to temperature, resulting in reliability problems.

Therefore, there is a need to improve the reliability of current flash memory due to temperature variations.

The invention discloses an electronic device. The electronic device includes a flash memory and a controller. The flash memory includes a storage array and a temperature sensor. The storage array has at least one storage unit, the storage unit has a floating gate for storing data, and when the storage unit is read, a read voltage is generated. The temperature sensor is used to detect the temperature of the flash memory. The controller includes a reference A voltage generating circuit, a processing unit, and a comparator. The reference voltage generating circuit is configured to output a reference voltage. The processing unit adjusts the reference voltage of the reference voltage generating circuit according to the temperature of the flash memory. The comparator is configured to compare the read voltage and the reference voltage, and when the read voltage is greater than the reference voltage, output a signal at a first level, and when the read voltage is less than the reference voltage, output a signal at a second level The first level is greater than the second level.

The invention discloses a control method suitable for an electronic device, wherein the electronic device has a flash memory and a controller. The control method includes: detecting a temperature of the flash memory; adjusting a reference voltage generated by a reference voltage generating circuit according to the temperature of the flash memory; and reading a read voltage of the storage unit of the flash memory; Comparing the read voltage and the reference voltage by one of the controllers; and when the read voltage is greater than the reference voltage, the comparator outputs a signal at a first level, and when the read voltage is less than the reference voltage, The comparator outputs a signal at a second level, wherein the first level is greater than the second level.

5‧‧‧Flash memory device

10‧‧‧ Controller

11‧‧‧Processing unit

12‧‧‧Error Correction Decoder

13‧‧‧Reference voltage generating circuit

14‧‧‧ Comparator

15‧‧‧ memory device

20‧‧‧Flash memory

21‧‧‧ Storage Array

22‧‧‧ Temperature Sensor

31‧‧‧Negative feedback operational amplifier

B1‧‧‧ busbar

Vd‧‧‧ reading voltage

Vref‧‧‧reference voltage

Vo‧‧‧ signal

WL1-WLK‧‧‧ word line

BL1-BLN‧‧‧ character line

M ₁₁ -M _KN ‧‧‧ storage unit

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

CO‧‧‧Control oxide layer

TO‧‧‧Through Oxide Layer

FG‧‧‧ floating gate

SR1-SRN‧‧‧Voltage Generating Unit

SW1-SWN‧‧‧ Switching Components

R1-RN‧‧‧ resistance

Iref‧‧‧reference current source

S51-S52‧‧‧Steps

1 is a schematic diagram of a flash memory device provided by the present invention; FIG. 2 is a schematic diagram of a memory array provided by the present invention; and FIG. 3 is a schematic diagram of a memory unit provided by the present invention; FIG. 4A-4B The schematic diagram of the operation of the comparator provided by the present invention; FIG. 5A is a schematic diagram of the reference voltage generating circuit provided by the present invention; FIG. 5B is another schematic diagram of the reference voltage generating circuit provided by the present invention; Figure 6 is a flow chart of the control method provided by the present invention;

The apparatus and method of use of various embodiments of the present invention are discussed in detail below. However, it is to be noted that many of the possible inventive concepts provided by the present invention can be implemented in various specific ranges. These specific examples are only intended to illustrate the apparatus and methods of use of the present disclosure, but are not intended to limit the scope of the invention.

1 is a schematic diagram of a flash memory device in accordance with an embodiment of the present invention. As shown in FIG. 1, the flash memory device 5 includes a controller 10 and a flash memory 20. The flash memory 20 has a storage array 21 and a temperature sensor 22. The controller 10 is used to access the storage array 21 of the flash memory 20. The controller 10 includes a processing unit 10, an Error Correction Code (ECC) decoder 12, a reference voltage generating circuit 13, a comparator 14, and a memory device 15.

The storage array 21 has a plurality of storage units, each storage unit having a corresponding address. In this embodiment, the processing unit 11 of the controller 10 and the flash memory 20 transmit the address and the command via the bus bar B1. Corresponding to the read command from the controller 10, the flash memory 20 supplies data corresponding to the read command to the comparator 14 in accordance with the read address from the controller 10. In one embodiment, the data corresponding to the read command is composed of a plurality of bytes stored in the storage array 21 and corresponding to the read address, but is not limited thereto. For convenience of description, the data corresponding to the read command in this embodiment is represented by only one bit, but is not limited thereto. In this embodiment, a read voltage Vd is generated when the memory cell corresponding to the read address in the flash memory 20 is read, but is not limited thereto.

The comparator 14 generates a signal at a first level or a signal at a second level according to the read voltage Vd and a reference voltage Vref, wherein the first level and the second level are opposite logic levels. However, it is not limited to this. In some embodiments, the first level is a high level and the second level is a low level. In some embodiments, the first level is a low level and the second level is a high level. Next, the error correction code decoder 12 decodes the signal of the first level or the signal of the second level according to an error correction code (ECC_CODE) to provide the decoded signal to the processing unit 11. The processing unit 11 determines whether the signal of the first level or the signal of the second level is valid data according to the received signal.

In this embodiment, the processing unit 11 receives the temperature of the flash memory 20 detected by the temperature sensor 22 of the flash memory 20 via the bus bar B1, and adjusts the reference voltage according to the temperature of the flash memory 20. Vref. In an embodiment, the processing unit 11 can adjust the reference voltage Vref according to a lookup table stored in the memory device 15 and the temperature of the flash memory 20. For example, the temperature and the corresponding reference voltage are recorded in the lookup table, and the processing unit 11 obtains the corresponding reference voltage Vref from the lookup table according to the temperature of the flash memory 20. In another embodiment, the processing unit 11 determines whether the temperature of the flash memory 20 is greater than the first temperature to determine whether to adjust the reference voltage Vref, but is not limited thereto.

Please refer to FIG. 2, which is a schematic diagram of the storage array 21 of FIG. As shown in Fig. 2, the storage array 21 has a plurality of storage units (M ₁₁ , M ₁₂ , ..., M _KN ). Each storage unit is a metal oxide semiconductor and has a floating gate for storing data. In one embodiment, the storage unit is a one-dimensional storage unit for storing digital data representing 0 or 1, but is not limited thereto. In another embodiment, the storage unit may also be a storage unit of a plurality of bits. In the present embodiment, the processing unit 11 of the controller 10 selects a word line and a bit line via the bus bar B1 to read the storage unit. For example, the processing unit 11 selects the word line WL1 and the bit lines BL1 to BLN to generate read voltages corresponding to those stored in the memory cells M ₁₁ , M ₁₂ , . . . , M _1N .

Please refer to FIG. 3, which is a schematic diagram of the storage unit in FIG. As shown in FIG. 3, the memory cell is a Metal-Oxide-Semiconductor Field-Effect Transistor having a floating gate FG. In this embodiment, the gate G of the storage unit is electrically connected to the word line, the drain D is electrically connected to the bit line, and the source S is electrically connected to the ground (ground) ), but not limited to this. For example, the storage unit is the storage unit M _{11 in} FIG. 2 , and the gate G, the drain D and the source S of the storage unit M ₁₁ are electrically connected to the word line WL1 , the bit line BL1 and the ground, respectively.

As shown in FIG. 3, the floating gate FG of the memory cell is isolated from the gate G by a control oxide CO, and by a tunnel oxide TO and a drain D and a source. Extreme S isolation.

In the present embodiment, when the controller 10 to perform writing to the program (program process) on behalf of the data storage unit to store 0 M _11, the processing unit 11 selected by the word line WL1 bus B1 and the bit line BL1, The voltage of the word line WL1 is made a first voltage and the bit line BL1 has a selection voltage. The first voltage applied to the gate G on the word line WL1 will cause an induced channel between the drain D and the source S of the memory cell M ₁₁ and the selection voltage applied to the drain D on the word line BL1. Part of the electrons will pass through the tunneling oxide layer TO and be injected into the floating gate FG. For example, the first voltage may be greater than the threshold voltage of the storage unit M ₁₁ . Conversely, when the controller 10 is to execute erasure of a program (erass process) representing a data storage _11, the controller 10 such that the voltage of the word line WL1 and the second voltage to a second voltage source storage unit is less than M The voltage of S and the drain D causes the negative electrons of the floating gate FG to be removed, and the data stored in the memory unit M ₁₁ is changed from 0 to 1. In this embodiment, the first voltage is greater than the second voltage.

In the present embodiment, when the controller 10 to read data storage means ₁₁ stored in M, 10 the voltage of the word line WL1 is set to a third voltage controller. When the threshold voltage difference between the memory cell M ₁₁ is a source electrode S and the gate G Class M ₁₁ is greater than the storage unit, the channel between the drain D and the source S will be turned on, and having a conduction current. When the present embodiment, the memory cells M ₁₁ source electrode S of the ground, so when a voltage is applied to the gate G of the third storage means is greater than the threshold voltage of M _11, M ₁₁ of the storage unit of the drain D and the source S The channel between them will be turned on. It should be noted that, in this embodiment, the threshold voltage of the storage unit M ₁₁ is determined by the negative electrons stored in the floating gate FG. For example, the greater the number of negative electrons stored by the floating gate FG, the larger the threshold voltage of the storage unit. Thus, when the third voltage is applied to the word line WL1 of the memory cell M ₁₁ is the gate electrode G, will be in accordance with the floating gate electrode FG negative electrons determine whether the channel between the drain D and the source S is turned on. In one embodiment, the controller 10 reads the storage unit to be M _11, the word line WL1 and bit line BL1 are selected simultaneously and respectively the third voltage having a bias voltage, and the floating gate FG of the negative electron storage implementation decisions unit ₁₁ and a threshold voltage M flows through the storage unit ₁₁ conduct current M. The controller 10 can determine the content of the data stored by the storage unit M ₁₁ by turning on the current.

For example, if the floating gate FG has a negative charge (for example, the stored data is 0), the threshold voltage is raised. ₁₁ the controller 10 reads the storage unit M, is generated corresponding to a first conduction current. If the floating gate FG does not have a negative charge (for example, the stored data is 1), the threshold voltage is not raised. When the second conductive current controller 10 reads the storage unit M _11, it will produce the corresponding. In this embodiment, the second on-current corresponding to the stored data being 1 is greater than the first on-current corresponding to the stored data being 0, but is not limited thereto.

In one embodiment, the first on current or the second on current is converted to a read voltage Vd via a current to voltage converter (not shown). For example, the current-voltage converter may be a resistor such that when the first/second conduction current flows through the resistor, the read voltage Vd is generated at one end of the resistor, but is not limited thereto. In this embodiment, the second on-current corresponding to the data stored in the storage unit is greater than the first on-current corresponding to the data stored in the storage unit. Similarly, the data stored in the storage unit is that the corresponding read voltage Vd is greater than the read voltage Vd corresponding to the data stored in the storage unit.

In another embodiment, the storage unit can also be used to store data of a plurality of bits. For example, the storage unit can store data such as 00, 01, 10, and 11, but is not limited thereto. For example, the controller 10 can control the voltage of the word line such that the floating gate FG has a different number of negative electrons. When the floating gate FG of the storage unit has a different number of negative electrons, the storage unit also generates a corresponding threshold voltage. Therefore, when the controller 10 reads the data of the storage unit, since the threshold voltage of the storage unit is different, the generated conduction current is also different, so the controller 10 can determine the stored data according to the magnitude of the conduction current.

The storage unit of the flash memory 20 stores the stored data by the negative electrons of the floating gate FG. However, the negative charge stored by the floating gate FG When a temperature rises, part of the negative electrons are lost through the tunneling oxide layer TO, so that the threshold voltage of the memory cell becomes small. Therefore, the read voltage Vd generated by the same memory cell being read at a high temperature is greater than the read voltage Vd generated by the read at a low temperature.

Please refer to FIG. 4, and FIG. 4A-4B is a diagram for explaining the operation method of the comparator 14. In one embodiment, the comparator 14 is used to compare the read voltage Vd with the reference voltage Vref (as shown in FIG. 4A). When the read voltage Vd is greater than the reference voltage Vref, the signal Vo at a first level is output. When the read voltage Vd is less than the reference voltage Vref, the signal Vo at a second level is output, and the signal of the first level is greater than the signal of the second level (as shown in FIG. 4B). In an embodiment, when the comparator 14 outputs the signal at the first level, the processing unit 11 determines that the data stored in the storage unit is 1; when the comparator 14 outputs the signal at the second level, the processing unit 11 It is judged that the data stored in the storage unit is 0, but not limited thereto.

Referring to FIG. 5A, FIG. 5A is a schematic diagram of a reference voltage generating circuit 13 according to an embodiment of the present invention. As shown in FIG. 5A, the reference voltage generating circuit 13 includes complex voltage generating units (SR1, SR2, ..., SRN) and a reference current source Iref. The voltage generating units (SR1, SR2, ..., SRN) are connected in parallel between the current source Iref and the ground. Each voltage generating unit has a resistor connected in series with a switching element. For example, the voltage generating unit SR1 has a first resistor R1 and a switching element SW1 connected in series, the voltage generating unit SR2 has a second resistor R2 connected in series, and a switching element SW2, and so on.

In this embodiment, the resistance of the first resistor R1 is smaller than the resistance of the second resistor R2, and the resistance of the second resistor R2 is smaller than the resistance of the third resistor R3, and so on, but not limited thereto. . Therefore, when the switching element SW1 is turned on The reference voltage Vref is smaller than the reference voltage Vref generated when the switching element SW2 is turned on, the reference voltage Vref generated when the switching element SW2 is turned on is smaller than the reference voltage Vref generated when the switching element SW3 is turned on, and so on. In this embodiment, the reference current source Iref may be generated by a current source or by a storage unit in the flash memory, but is not limited thereto.

It should be noted that the processing unit 11 of the present invention selects the switching element to be turned on according to the temperature of the flash memory. For example, when the temperature sensor 22 detects that the temperature of the flash memory 20 is 20 degrees, the switching element SW1 is turned on and the other switching elements SW2-SWN are turned off, but not limited thereto. When the temperature of the flash memory detected by the temperature sensor 22 is 30 degrees, the switching element SW2 is turned on and the other switching elements SW1, SW3-SWN are turned off, and so on. In other words, the processing unit 11 increases the reference voltage Vref when the temperature of the flash memory 20 is greater than a first temperature (eg, 20 degrees or 30 degrees). In another embodiment, the processing unit 11 controls the conduction of the switching elements SW1 - SWN according to the lookup table stored in the memory device 15 and the temperature of the flash memory 20, but is not limited thereto.

Referring to Fig. 5B, Fig. 5B is another embodiment of the reference voltage generating circuit of the present invention. The reference voltage generating circuit 131 of FIG. 5B is similar to the reference voltage generating circuit 13 of FIG. 5A except that the reference voltage generating circuit 131 of FIG. 5B further includes a negative feedback operational amplifier 31. The negative feedback operational amplifier 31 is coupled between the reference current source Iref and the voltage generating unit (SR1, SR2, . . . , SRN) and is used to output the reference voltage Vref.

Please refer to FIG. 6, which is a flow chart of the control method according to the present invention. The flow starts in step S51, and the processing unit 11 receives the temperature detected by the temperature sensor 22 from the flash memory 20, and proceeds to step S52. In the steps In S52, the processing unit 11 selects the switching elements in the voltage generating units (SR1, SR2, ..., SRN) to be turned on based on the temperature of the flash memory 20, and returns to step S51. For example, the processing unit 11 can select the switching elements to be turned on in the voltage generating units (SR1, SR2, ..., SRN) according to the temperature and reference voltage recorded by the lookup table and the temperature of the flash memory 20, but Not limited to this.

In summary, the negative electrons stored in the floating gate of the memory cell of the flash memory are negatively electron-induced, and the read voltage is also changed when the memory cell is read. The reference voltage of the comparator of the present invention can be adjusted according to the temperature to avoid erroneous judgment of the comparator. Therefore, the reliability problem caused by the flash memory when the temperature of the memory changes can be overcome.

S51-S52‧‧‧Steps

Claims (10)

An electronic device includes: a flash memory, comprising: a storage array having at least one storage unit, the storage unit having a floating gate for storing data, and the reading unit is read to generate a read And a temperature sensor for detecting the temperature of the flash memory; and a controller comprising: a reference voltage generating circuit for outputting a reference voltage; and a processing unit for a temperature of the flash memory, adjusting the reference voltage of the reference voltage generating circuit; and a comparator for comparing the read voltage and the reference voltage, and when the read voltage is greater than the reference voltage, the output is located at a a signal of a level, and when the read voltage is less than the reference voltage, outputting a signal at a second level, the first level being greater than the second level. The electronic device of claim 1, wherein when the comparator outputs a signal at the first level, the processing unit determines that the data stored in the storage unit is 1, and when the comparator output is located above When the signal of the second level is used, the processing unit determines that the data stored in the storage unit is 0. The electronic device of claim 1, wherein the processing unit increases the reference when the temperature of the flash memory is greater than a first temperature Voltage. The electronic device of claim 1, wherein the processing unit adjusts the reference voltage according to the temperature of the flash memory and a lookup table. The electronic device of claim 1, wherein the reference voltage generating circuit further comprises: a plurality of voltage generating units connected in parallel between a reference current source and a ground, each voltage generating unit having a series connection a resistor and a switching component, wherein the processing unit is configured to generate a control signal according to the temperature of the flash memory to control the switching component to generate the reference voltage. The electronic device of claim 1, wherein the controller further comprises an error correction decoder for outputting the signal at the first level or the output of the comparator according to an error correction code. The signal of the second level described above is decoded. A control method is applicable to an electronic device, wherein the electronic device has a flash memory and a controller, and the control method includes: detecting a temperature of the flash memory; and adjusting a temperature according to the temperature of the flash memory a reference voltage generated by the reference voltage generating circuit; reading a read voltage of one of the memory cells of the flash memory; comparing the read voltage and the reference voltage by one of the controllers; and When the read voltage is greater than the reference voltage, outputting a signal at a first level, and when the read voltage is less than the reference voltage, outputting a signal at a second level, wherein the first level is greater than the second level. The control method of claim 7, wherein when the comparator outputs the signal of the first level, the data stored by the storage unit is 1, and when the comparator output is at the second level When the signal is received, the data stored in the storage unit is 0. The control method of claim 7, wherein the step of adjusting the reference voltage comprises: increasing the reference voltage when the temperature of the flash memory is greater than a first temperature. The control method of claim 7, wherein the step of adjusting the reference voltage comprises adjusting the reference voltage according to the temperature of the flash memory and a lookup table.