JP2006065945A - Nonvolatile semiconductor storage device and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remarkably improve a rewriting resistance of a nonvolatile memory cell. <P>SOLUTION: A power source circuit 9 prepared in a flash memory module of a semiconductor integrated circuit device is comprised of a voltage generation circuit 9a, and a temperature characteristic determining circuit 9b. The voltage generation circuit 9a generates various voltages used in data writing, erasing, verifying, etc. The temperature characteristic determining circuit 9b performs controls so as not to have a temperature gradient at a write verification judgment memory gate voltage in an ordinary temperature range (about 0 to about 35°C) and to have the temperature gradient at the write verification judgment memory gate voltage in the temperature range lower than the lower limit temperature of the ordinary temperature range and in the temperature range higher than the upper limit temperature of the ordinary temperature range. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for improving the number of rewrites in a nonvolatile semiconductor memory device, and more particularly to a technique that is effective when applied to prevention of excessive voltage application of a memory cell in writing and erasing.

  One of nonvolatile semiconductor memory devices that can be electrically rewritten and erased is a flash memory. In this flash memory, writing / erasing is performed to rewrite data.

  The write / erase procedure in the flash memory is shown below.

  First, a high voltage that causes a write / erase operation is applied to a target memory of a memory array for a predetermined time. Next, verification is performed. When the electrical state of the memory cell reaches a predetermined value corresponding to each of the write / erase levels, the write / erase is terminated.

  If the electrical state of the memory cell does not reach a predetermined value, a high voltage that causes a write / erase operation again is applied for a predetermined time and verification, and the electrical state of the memory cell reaches a predetermined write / erase level. Repeat the operation until As described above, the verification is performed in order to confirm whether or not the electrical state of the memory cell has reached a predetermined value.

  When the electrical state of the memory cell is a threshold voltage, in this verification, the verify determination memory gate voltage is set so that the threshold voltage of the memory cell becomes the allowable upper limit value at the time of erasing and the allowable lower limit value at the time of writing. Set.

  In addition, in order to reduce a change in threshold voltage distribution due to a difference in temperature between writing and erasing and reading, some verify determination memory gate voltage has temperature dependency.

As a technology for reducing temperature dependence in this type of nonvolatile semiconductor memory device, for example, a temperature detection circuit is provided for a variable clock generator that generates an internal clock signal, and variable clock generation is performed according to the detection signal of the temperature detection circuit. There is a technique for compensating the temperature dependence of the internal clock signal by changing the oscillation cycle of the device and changing the cycle of the clock signal accordingly (see Patent Document 1).
JP 2002-215258 A

  However, the present inventors have found that the verify technique in the nonvolatile semiconductor memory device as described above has the following problems.

  FIG. 21 is a diagram showing an example of the temperature characteristic of the memory gate voltage at the time of write verification, and FIG. 22 is a diagram showing the memory current characteristic of the memory cell after writing.

  In FIG. 21, the horizontal axis represents temperature and the vertical axis represents memory gate voltage. In FIG. 22, the vertical axis indicates the memory current and the horizontal axis indicates the memory gate voltage, respectively, and indicates the temperature dependence of the I (current) -V (voltage) characteristics of the memory cell. When a constant memory gate voltage is applied, the IV characteristic at high temperature is Tbb, and the IV characteristic at low temperature is Tc.

  In this specification, the written state of a memory cell is a state in which an equivalent memory current can be obtained by applying a higher memory gate voltage compared to the erased state, and the threshold voltage of the memory cell Is a high state. However, the writing state and the erasing state are relative and are not limited to these.

  In the region below the intersection of the IV characteristic Tc at the low temperature and the IV characteristic Tbb at the high temperature, when the voltage Vc ′ is applied to the memory gate, the write verify determination memory current is obtained in the verification at the high temperature. However, the write verify determination memory current cannot be obtained at a low temperature.

  Therefore, as shown in FIG. 21, when verifying is performed by applying a constant write verify determination memory gate voltage to a memory cell regardless of temperature, a write verify determination memory gate voltage equal to or higher than point B when writing at a low temperature (Tc). In the writing at a high temperature Tbb, the IV characteristic of the substantial memory cell becomes a high temperature (Tb).

  As a result, there is a problem that if the write verify is performed at a constant write verify determination memory gate voltage in the guaranteed temperature range, overstress occurs at a high temperature (Tb).

  FIG. 23 is a diagram showing an example of the temperature characteristic of the memory gate voltage at the time of write verification, and FIG. 24 is a diagram showing the memory current characteristic of the memory cell after writing.

  In FIG. 23, the horizontal axis represents temperature and the vertical axis represents memory gate voltage. In FIG. 24, the vertical axis indicates the memory current and the horizontal axis indicates the memory gate voltage, respectively, and indicates the temperature dependence of the IV characteristic of the memory cell.

  In a nonvolatile semiconductor memory device, when rewriting is repeated, memory characteristics deteriorate, and for example, an erasing time and a writing time increase. Since the erase time and the write time have practical upper limits, the number of rewrites that can be guaranteed is less than or equal to these upper limits.

  FIG. 25 is a diagram showing the relationship between the threshold voltage change and the number of rewrites in the memory cell at the time of writing.

  As shown in the figure, when the change of the threshold voltage of the memory cell at the time of erasing / writing is large (FIG. 21), since a large voltage stress is assumed, the change of the threshold voltage is small (FIG. 23). ) Will deteriorate faster than).

  Further, when a certain temperature dependence (FIG. 23) is provided in the write verify determination memory gate voltage, overstress on the memory cell at high temperature (Tb) can be avoided, but I The temperature dependence of the -V characteristic is not constant. For example, the temperature dependence becomes small in a low temperature (Tc) region, and overstressing is applied to the memory cell in the temperature range.

  An object of the present invention is to provide a nonvolatile semiconductor memory device and a semiconductor integrated circuit device capable of greatly improving the rewriting durability of nonvolatile memory cells.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A nonvolatile semiconductor memory device according to the present invention includes a memory array unit having a plurality of nonvolatile memory cells, and a voltage generation unit that supplies a predetermined voltage to be supplied to the nonvolatile memory cells. In the first temperature range, the voltage is generated without depending on the temperature, and in the temperature range other than the first temperature range, the voltage is generated depending on the temperature.

  In the nonvolatile semiconductor memory device according to the present invention, the voltage generation unit generates a predetermined voltage based on the operation control signal, and a voltage having no temperature dependence in the first temperature range. And a temperature characteristic determination circuit that outputs an operation control signal so that a voltage having temperature dependency is generated in a temperature range other than the first temperature range. It is.

  Furthermore, in the nonvolatile semiconductor memory device according to the present invention, the temperature characteristic determining circuit generates an operation control signal for generating a voltage having a first temperature gradient in a second temperature range higher than the upper limit of the first temperature range. And an operation control signal for generating a voltage having a second temperature gradient is output in a third temperature range lower than the lower limit of the first temperature range.

  In the nonvolatile semiconductor memory device according to the present invention, the temperature characteristic determination circuit generates an operation control signal for generating a voltage having a second temperature gradient in a second temperature range higher than the upper limit of the first temperature range. Output.

  Further, in the nonvolatile semiconductor memory device according to the present invention, the voltage generation unit generates any one of a write verify determination memory gate voltage, an erase verify determination memory gate voltage, a write memory voltage, and an erase memory voltage. is there.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  The present invention includes a non-volatile storage unit and a central processing unit, and the central processing unit can execute a predetermined process and give an operation instruction to the non-volatile storage unit. The unit is a semiconductor integrated circuit device having a plurality of nonvolatile memory cells for storing information, and the nonvolatile memory unit supplies a memory array unit having a plurality of nonvolatile memory cells and the nonvolatile memory cells. A voltage generation unit that supplies a predetermined voltage, the voltage generation unit generates a voltage without depending on the temperature in the first temperature range, and depends on the temperature in a temperature range other than the first temperature range. To generate a voltage.

  According to the present invention, the voltage generator generates a voltage generating circuit that generates a predetermined voltage based on the operation control signal, and a voltage that does not have temperature dependency in the first temperature range. And a temperature characteristic determining circuit that outputs an operation control signal and outputs an operation control signal so that a voltage having temperature dependency is generated in a temperature range other than the first temperature range.

  In the present invention, the temperature characteristic determining circuit outputs an operation control signal for generating a voltage having a first temperature gradient in a second temperature range higher than the upper limit of the first temperature range, In the third temperature range lower than the lower limit of the temperature range, an operation control signal for generating a voltage having the second temperature gradient is output.

  In the present invention, the temperature characteristic determination circuit outputs an operation control signal for generating a voltage having a second temperature gradient in a second temperature range higher than the upper limit of the first temperature range.

  Further, according to the present invention, the voltage generation unit generates any one of a write verify determination memory gate voltage, an erase verify determination memory gate voltage, a write memory voltage, and an erase memory voltage.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The characteristic deterioration in the memory cell due to excessive voltage application can be avoided, and the rewrite tolerance of the memory cell can be greatly improved.

  (2) According to the above (1), the reliability of the nonvolatile semiconductor memory device and the semiconductor integrated circuit device configured using the nonvolatile semiconductor memory device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a block diagram of a flash memory module provided in the semiconductor integrated circuit device of FIG. 1, and FIG. 3 is a flash of FIG. 4 is a block diagram showing an example of a power supply circuit provided in the memory module, FIG. 4 is an explanatory diagram showing a circuit configuration example of a temperature characteristic determination circuit provided in the power supply circuit of FIG. 3, and FIG. 5 is a temperature characteristic of FIG. 6 is a circuit diagram showing an example of a temperature characteristic adding circuit provided in the determination circuit, FIG. 6 is an explanatory diagram showing an example of the temperature characteristic of the memory voltage at the time of verification set by the temperature characteristic determination circuit of FIG. 4, and FIG. FIG. 8 is an explanatory diagram of memory current characteristics in an erase state and a write state in a memory cell provided in the flash memory module of FIG. 2, and FIG. FIG. 9 is a flowchart showing an erase operation, FIG. 9 is a flowchart showing a write operation in the flash memory module of FIG. 2, and FIG. It is explanatory drawing shown.

  In the first embodiment, the semiconductor integrated circuit device 1 is composed of, for example, a single chip microcomputer. As shown in FIG. 1, the semiconductor integrated circuit device 1 is exemplified by a peripheral circuit 2, a bus controller 3, a CPU (central processing unit) 4, a RAM 5, an I / O 6, a flash memory controller 7, and a nonvolatile semiconductor memory device. The flash memory module (nonvolatile storage unit) 8 is configured.

Peripheral circuit 2 consists of A / D converter, serial communication interface , A watchdog timer, and various function modules such as a timer pulse unit.

  The A / D converter converts an analog signal input from an external terminal into a digital signal. The serial communication interface is an interface that performs serial data communication with an external device. The watch dog timer monitors the runaway of the semiconductor integrated circuit device 1. The timer pulse unit is a timer that can output a PWM (Pulse Width Modulation) waveform.

  The bus controller 3 controls the address bus and data bus inside and outside the semiconductor integrated circuit device 1. The CPU 4 manages all control in the semiconductor integrated circuit device 1. The RAM 5 is a volatile memory that can be read / written at any time, and temporarily stores input / output data, operation data, and the like.

  The I / O 6 includes, for example, an input / output buffer, and is provided as an interface with an externally connected device. The flash memory controller 7 controls operations such as writing / reading / erasing of the flash memory module 8. The flash memory module 8 performs data writing / reading and erasing in accordance with instructions from the flash memory controller 7.

  The peripheral circuit 2, bus controller 3, CPU 4, RAM 5, I / O 6, flash memory controller 7, and flash memory module 8 are connected to each other via an internal bus B.

  FIG. 2 is a block diagram showing a configuration of the flash memory module 8.

  The flash memory module 8 includes a power supply circuit (voltage generation unit) 9, an oscillation circuit 10, a control circuit 11, an address buffer 12, a row decoder / driver circuit 13, an I / O unit 14, a sense amplifier circuit 15, a column decoder 16, and a write A latch control circuit 17 and a memory mat (memory array section) 18 are included.

  The power supply circuit 9 generates various boosted power supply voltages and step-down power supply voltages from the externally supplied power supply voltages VCC and VDD. The oscillation circuit 10 generates a clock signal and supplies it to each module such as the power supply circuit 9 and the control circuit 11.

  The control circuit 11 temporarily stores the control signal output from the connected flash memory controller 7 and controls the operation logic. The address buffer 12 temporarily stores an address input from the outside. A row decoder / driver circuit 13 and a column decoder 16 are connected to the address buffer 12.

  The row decoder / driver circuit 13 performs decoding based on the column (row) address output from the address buffer 12. Various signals such as data read from the memory mat 18 and program data are input to and output from the I / O unit 14.

  The sense amplifier circuit 15 amplifies and outputs the data output from the memory cell (nonvolatile memory cell) S of the memory mat 18. The column decoder 16 performs decoding based on the row (column) address output from the address buffer 12. The write latch control circuit 17 latches write data and performs latch control thereof.

  In the memory mat 18, the memory cells S, which are the minimum storage units, are regularly arranged in an array. The memory cell S provided in the memory mat 18 is composed of a non-volatile memory cell, can electrically rewrite data, and does not need a power source for storing data.

  FIG. 3 is a block diagram illustrating a configuration example of the power supply circuit 9 provided in the flash memory module 8.

  As shown in the figure, the power supply circuit 9 includes a voltage generation circuit 9a and a temperature characteristic determination circuit 9b.

  The voltage generation circuit 9a generates various voltages used for data writing, erasing, verifying, and the like. The temperature characteristic determination circuit 9b takes into account the retention characteristic depending on the temperature at the time of data writing or the current characteristic of the memory cell S having different temperature dependence depending on the temperature range, and the verify determination memory gate in an arbitrary temperature range. Voltage control is performed so that the voltage has temperature characteristics.

  FIG. 4 is an explanatory diagram showing a circuit configuration example of the temperature characteristic determination circuit 9b.

  The temperature characteristic determination circuit 9b includes comparison circuits 19 to 21, temperature characteristic addition circuits 22 and 23, an OR circuit 24, an AND circuit 25, a resistance unit (comparison voltage generation unit) 26, and a reference power generation circuit 27. ing.

  The resistance unit 26 has a configuration in which a plurality of resistors are connected in series between a boosted voltage generated by the voltage generation circuit 9a and a reference potential (ground potential), and compares any divided voltage as reference voltages VR1 to VR3. These are supplied to the negative (−) side input terminals of the circuits 19 to 21, respectively.

  The reference power generation circuit 27 generates a reference voltage Vref. The reference voltage Vref generated by the reference power generation circuit 27 is connected to be supplied to the positive (+) side input terminal of the comparison circuit 19 and the input portions of the temperature characteristic addition circuits 22 and 23, respectively.

  The positive (+) side input terminals of the comparison circuits 20 and 21 are connected to the output portions of the temperature characteristic addition circuits 22 and 23, respectively. One input part of the OR circuit 24 is connected to the output terminal of the comparison circuit 19, and the other input part of the OR circuit 24 is connected to the output terminal of the comparison circuit 20.

  One input part of the AND circuit 25 is connected to the output part of the OR circuit 24, and the output terminal of the comparison circuit 21 is connected to the other input part of the AND circuit 25. Then, a signal output from the output unit of the AND circuit 25 is output to the voltage generation circuit 9a as a stop signal.

  The voltage generation circuit 9a is composed of, for example, a charge pump. When a stop signal is input, the voltage generation circuit 9a stops the charge pump operation and stops generating the boosted voltage.

  FIG. 5 is a circuit diagram showing an example of the temperature characteristic addition circuit 22 (, 23).

  The temperature characteristic adding circuit 22 (, 23) is composed of P-channel MOS transistors T1 and T2 and N-channel MOS transistors T3 to T5, and is a circuit that outputs a temperature-dependent voltage.

  The power supply voltage VCC is connected to one connection part of the transistors T1 and T2, and one connection part of the transistor T3 and the gates of the transistors T1 and T2 are connected to the other connection part of the transistor T1, respectively. Has been.

  In addition, one connection portion and the gate of the transistor T4 are connected to the other connection portion of the transistor T2. The other connection portion of the transistor T3 is connected to the other connection portion of the transistor T4, one connection portion of the transistor T5, and the gate, and a reference potential is connected to the other connection portion of the transistor T5. Has been.

  The gate of the transistor T3 serves as an input part of the temperature characteristic addition circuit 22 (, 23), and is connected so that the reference voltage Vref output from the reference power generation circuit 27 is input. The gate of the transistor T4 serves as an output section of the temperature characteristic addition circuit 22 (, 23) and is connected to the positive (+) side input terminal of the comparison circuit 20 (, 21).

  When the reference voltage Vref is input to the input part of the temperature characteristic addition circuit 22 (, 23), a voltage with a temperature gradient is output from the output part of the temperature characteristic addition circuit 22 (, 23).

  In this case, the temperature characteristic addition circuit 22 (23) adds a temperature gradient to the output voltage by operating the transistors T3 and T4 having different gate widths in the subthreshold current region.

  FIG. 6 is an explanatory diagram showing an example of the temperature characteristic of the memory voltage at the time of verification set by the temperature characteristic determination circuit 9b. In FIG. 6, the horizontal axis represents the write verify determination memory gate voltage, and the horizontal axis represents the temperature range in the semiconductor integrated circuit device.

  In this case, as shown in the figure, in the normal temperature range (first temperature range) A, the temperature range C lower than the lower limit temperature of the normal temperature range A without causing a temperature gradient in the write verify determination memory gate voltage, and In the temperature range B higher than the upper limit temperature of the normal temperature range A, control is performed so that each write verify determination memory gate voltage has a temperature gradient.

  Here, the normal temperature range A is a partial temperature range of the entire guaranteed temperature range of the semiconductor integrated circuit device 1. For example, the semiconductor integrated circuit device operates in the temperature range of about 0 ° C. to 35 ° C. as the outside air temperature. It is the surface temperature of the semiconductor integrated circuit device in the state of being. This temperature range is a temperature range in which the semiconductor integrated circuit device 1 is most frequently operated, and may vary depending on the environment in which the semiconductor integrated circuit device 1 is installed.

  Further, memory current characteristics in the erased state and the written state in the memory cell S will be described with reference to the explanatory diagram of FIG.

  A state where the threshold voltage of the memory cell S is low is referred to as an erased state, and a state where the threshold voltage is high is referred to as a written state. In this case, the threshold voltage of the memory cell S can be moved from the written state to the erased state by applying the erase voltage, and from the erased state to the written state by applying the write voltage.

  These two states can be determined by applying a read voltage to the memory gate of the memory cell S and detecting the magnitude of the memory current. As described above, the logic values “1” and “0” correspond to the two states, respectively, to function as a memory.

  The larger the threshold voltage difference in the memory cell S between the read voltage and the erased state, the larger the memory current at the time of reading. At the time of erasing, a determination level is provided so that a sufficient memory current can be secured at the time of reading, and the erasing voltage is applied while determining that the threshold voltage is always lower than that level.

  This determination operation is called erase verify, and the determination level can be defined by the voltage applied to the memory gate and the memory current value flowing at that time. On the other hand, the larger the threshold voltage difference between the read voltage and the written state, the smaller the memory current at the time of reading, and the difference from the erased state becomes clear.

  At the time of writing, a reference level is provided and the writing voltage is applied while determining that the threshold voltage is always equal to or higher than that level. This determination operation is called write verify. Similar to the erase verify, the determination level can be defined by the voltage applied to the memory gate and the memory current value flowing at that time.

  Next, the operation of the flash memory module 8 according to this embodiment will be described.

  First, the erase operation in the flash memory module 8 will be described with reference to the flowchart of FIG.

  First, when an erase address is designated (step S101), the erase voltage generated by the power supply circuit 9 is applied to the memory cell S to be erased (step S102). Subsequently, erase verify is performed. If the threshold voltage of the memory cell S is equal to or lower than the determination level, the erase is completed. If the threshold voltage is not lower than the determination level, the erase voltage is applied again to erase verify. Is performed (step S103).

  Next, the writing operation in the flash memory module 8 will be described with reference to the flowchart of FIG.

  First, a write address is designated (step S201), and write data is transferred (step S202). Thereafter, the write voltage generated by the power supply circuit 9 is applied to the memory cell S to be written (step S203).

  Subsequently, write verify is performed. If the threshold voltage of the memory cell S is equal to or higher than the determination level, the write is terminated. If the threshold voltage is lower than the determination level, the write voltage is applied again to perform the write verify (step S204). ).

  Next, the operation of the power supply circuit 9 in write verification will be described.

  In the write verify, the power supply circuit 9 performs the normal temperature range A having no temperature gradient, the temperature range (second temperature range) B having the temperature gradient, and the temperature range (third temperature range) C as described above. A write verify determination memory gate voltage is generated.

  The comparison circuit 19 compares the reference voltage Vref and the reference voltage (first comparison reference voltage) VR1, and when the write verify determination memory gate voltage is a voltage (Va or higher) equal to or higher than the gradient a (FIG. 6), “1” is output, and “0” is output at a voltage lower than that.

  The comparison circuit 20 compares the reference voltage (second comparison reference voltage) VR2 with the reference voltage Vref2 having a temperature gradient added by the temperature characteristic adding circuit 22, and the write verify determination memory gate voltage has a gradient (first voltage). If the voltage is equal to or higher than the temperature gradient b (FIG. 6), “1” is output, and if the voltage is lower than the gradient b, “0” is output.

  Further, the comparison circuit 21 compares the reference voltage (third comparison reference voltage) VR3 with the reference voltage Vref3 having a temperature gradient added by the temperature characteristic adding circuit 23, and the write verify determination memory gate voltage has a gradient (first voltage). 2) If the voltage is equal to or higher than c (FIG. 6), “1” is output, and if the voltage is lower than the gradient c, “0” is output.

  The signals output from the comparison circuits 19 to 21 are input to the logical sum circuit 24 and the logical product circuit 25, respectively. In each of the temperature ranges A to C, a voltage equal to or higher than the solid line of the gradients a to c in FIG. Then, a stop signal of “1” is output, and the charge pump circuit of the voltage generation circuit 9a is stopped.

  Further, in each of the temperature ranges A to C, when the voltage is lower than the solid line of the gradients a to c in FIG. 6, the stop signal becomes '0', and the charge pump circuit of the voltage generation circuit 9a operates. As a result, the write verify determination memory gate voltage is controlled.

  Here, it is assumed that the reference power generation circuit 27 (FIG. 4) that generates the reference voltage Vref generates the reference voltage Vref having no temperature dependency. Therefore, the determination of the comparison circuit 19 does not have temperature dependency.

  Further, by adjusting the reference voltage Vref input to the comparison circuit 19 and the temperature gradients of the temperature characteristic addition circuits 22 and 23, the gradients of the temperature ranges Ta1 to Ta2 and the temperature ranges B and C of the normal temperature range A can be arbitrarily set. Can be set to The reference voltage Vref input to the temperature characteristic addition circuits 22 and 23 may be set to a voltage value individually for each temperature characteristic addition circuit.

  FIG. 10 is an explanatory diagram showing the relationship between the temperature and the threshold voltage of the memory cell S at the time of writing.

  As shown in the figure, when the retention characteristic deteriorates according to the write temperature, the write verify determination memory gate voltage must be set in addition to the temperature characteristic of the memory current.

  For example, if the write verify determination memory gate voltage in accordance with the memory current characteristic is assumed to be a gradient c (FIG. 6), the write verify determination memory gate voltage added with the deterioration of the retention characteristic is a solid line (FIG. 6). However, when a constant temperature gradient is provided for the write verify determination memory gate voltage, it must be set as the gradient b (FIG. 6), resulting in overstress during low temperature writing.

  However, as shown in the present embodiment, when a temperature gradient is provided for each of the temperature ranges A to C, a low temperature region having a low retention characteristic is adjusted to the write verify determination memory gate voltage. It is possible to write with minimal stress.

  By replacing a place where the temperature dependence is extremely small (Ta1 to Ta2) without a temperature gradient as the write verify determination memory gate voltage, the generated voltage is controlled while avoiding the temperature gradient variation of the temperature characteristic addition circuits 22 and 23. Can do.

  Thereby, according to the present embodiment, by adjusting the temperature gradient of the write verify determination memory gate voltage to the temperature characteristic of the memory cell S, the movement of the threshold voltage of the memory cell S is further reduced by writing and erasing. Thus, deterioration of memory characteristics due to excessive voltage application can be avoided, and the number of rewrites in the flash memory module 8 can be greatly improved.

  In the first embodiment, the write verify is described. For example, as shown in FIG. 11, the normal temperature range A having no temperature gradient and the lower limit temperature of the normal temperature range A having the temperature gradient are shown. The erase verify determination memory gate voltage may be generated in each of the lower temperature range C and the temperature range B higher than the upper limit temperature of the normal temperature range A to perform erase verify.

  In this case, in the normal temperature range A, the erase verify determination memory gate voltage is a voltage equal to or higher than the gradient a (voltage Va), the voltage within the temperature range C is equal to or higher than the gradient c, and the voltage within the temperature range B is equal to or higher than the gradient b.

  FIG. 12 is a diagram showing an example of temperature dependence of current characteristics in the memory cell S after erasure.

  As shown in the figure, when the temperature dependence is reversed in the normal temperature range A, when a certain gradient is provided for the erase verify determination memory gate voltage, the setting is not made as shown by the gradient k (FIG. 11). In other words, overstress occurs when erasing is performed at a temperature other than two points of the lowest temperature Tc and the highest temperature Tb.

  However, in the method shown in FIG. 11, erasing can be performed with a minimum amount of stress by matching the current characteristics of the memory cell S in which the temperature dependence reversal exists with the erase verify determination memory gate voltage.

(Embodiment 2)
FIG. 13 is a circuit diagram showing a configuration of the temperature characteristic determining circuit provided in the semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 14 is a memory at the time of verification set by the temperature characteristic determining circuit of FIG. FIG. 15 is an explanatory diagram showing an example of the temperature characteristic of the voltage, and FIG. 15 is an explanatory diagram showing an example of the temperature dependence of the memory current characteristic after writing to the memory cell provided in the flash memory module according to the second embodiment of the present invention. is there.

  In the second embodiment, the semiconductor integrated circuit device 1 includes a peripheral circuit 2, a bus controller 3, a CPU 4, a RAM 5, an I / O 6, a flash memory controller 7, and a nonvolatile memory as in the first embodiment (FIG. 1). The flash memory module 8 is an example of a volatile semiconductor memory device.

Also in the configuration of the flash memory module 8, as in the first embodiment (FIG. 2), the power supply circuit 9, the oscillation circuit 10, the control circuit 11, the address buffer 12, the row decoder / driver circuit 13, the I / O Part 14, sense amplifier circuit 15, column decoder 16, write latch control circuit 17, memory mat 18, and the like. The difference is the configuration of temperature characteristic determination circuit 9 b ₁ provided in power supply circuit 9. .

As shown in FIG. 13, the temperature characteristic determination circuit 9b ₁ includes comparison circuits 28 and 29, a temperature characteristic addition circuit 30, an OR circuit 31, a resistance unit (comparison voltage generation unit) 32, and a reference power generation circuit 33. Has been.

  The resistance unit 32 has a configuration in which a plurality of resistors are connected in series between a boosted voltage generated by the voltage generation circuit 9a and a reference potential (ground potential), and an arbitrary divided voltage is compared as reference voltages VR4 and VR5. The signals are supplied to the negative (−) side input terminals of the circuits 28 and 29, respectively.

  The reference power generation circuit 27 generates a reference voltage Vref. The reference voltage Vref generated by the reference power generation circuit 27 is connected to be supplied to the positive (+) side input terminal of the comparison circuit 28 and the input section of the temperature characteristic addition circuit 30. Here, the temperature characteristic addition circuit 30 has the same configuration as that of FIG.

  The positive (+) side input terminal of the comparison circuit 29 is connected to the output part of the temperature characteristic addition circuit 30. One input section of the OR circuit 31 is connected to the output terminal of the comparison circuit 28, and the other input section of the OR circuit 31 is connected to the output terminal of the comparison circuit 29.

  Then, a signal output from the output unit of the OR circuit 31 is output to the voltage generation circuit 9a as a stop signal. The voltage generation circuit 9a is composed of, for example, a charge pump. When a stop signal is input, the voltage generation circuit 9a stops the charge pump operation and stops generating the boosted voltage.

In this case, as shown in FIG. 14, the temperature characteristic determination circuit 9b ₁ performs the write verification by generating the write verify determination memory gate voltage including the temperature range A having no temperature gradient and the temperature range B having the temperature gradient. .

In the temperature characteristic determining circuit 9b _1, comparator circuit 28 compares the reference voltage (fourth comparison reference voltage) VR4 and the reference voltage Vref, the when the write verify determination memory gate voltage is equal to or higher than the voltage Va (gradient a) “1” is output, and “0” is output when the voltage level is lower than the voltage Va.

  Further, in the comparison circuit 29, the reference voltage (fifth comparison reference voltage) VR5 is compared with the reference voltage Vref5 having a temperature gradient added by the temperature characteristic adding circuit 30, and the write verify determination memory gate voltage becomes the gradient b. When the voltage level is above, “1” is output, and when the voltage level is lower than the gradient b, “0” is output.

  Then, by taking the logical sum of the signals output from the comparison circuits 28 and 29 by the logical sum circuit 31, a stop signal of “1” is output if the voltage is higher than the solid line of the gradients a and b shown in FIG. Thus, the charge pump circuit of the voltage generation circuit 9a is stopped, and if the voltage is lower than the solid lines of the gradients a and b, a stop signal of “0” is output and the charge pump circuit operates. By this operation, the write verify determination memory gate voltage is controlled.

  Thus, by adjusting the determination voltage level of the comparison circuit 28 and the temperature gradient of the temperature characteristic addition circuit 30, the temperature regions Ta1 to Ta2 of the temperature range A and the gradient of the temperature range B can be arbitrarily set. .

  FIG. 15 is an explanatory diagram showing the temperature dependence of memory current characteristics after writing.

  As shown in FIG. 15, by adjusting the memory current characteristic that has almost no temperature dependency in a certain temperature region Ta1 to Ta2 in the temperature range A and has a large or small temperature dependency to the verify determination memory gate voltage, Writing is possible with minimal stress.

  Accordingly, in the second embodiment, the voltage control variation due to the variation of the temperature characteristic addition circuit 30 or the like can be suppressed by not providing the temperature gradient in the region where the temperature gradient is small.

  Also in the second embodiment, for example, as shown in FIG. 16, in the temperature range A having no temperature gradient and in the temperature range C lower than the upper limit temperature of the temperature range A, the erase verify determination memory gate voltage May be generated and erase verification may be performed.

  FIG. 17 is a diagram showing an example of temperature dependence of current characteristics in the memory cell S after erasure.

  As shown in the figure, when there is almost no temperature dependence in the temperature range Ta1 to Ta2 in the temperature range A that is within the guaranteed temperature range, the gradient k (see FIG. 16), and over-stress occurs when erasing is performed at a temperature other than the lowest and highest temperatures.

  However, by providing a temperature gradient as shown in FIG. 16, it is possible to match the memory current characteristic having the temperature dependence with the verify determination memory gate voltage, and erasing can be performed with a minimum stress. .

Further, as shown in FIG. 18, the temperature characteristic determination circuit 9b ₂ may vary the determination level of the write verify determination memory gate voltage according to the number of rewrites.

In this case, the temperature characteristic determination circuit 9b ₂ includes comparison circuits 34, 34a, 35, and 35a, temperature characteristic addition circuits 36 and 36a, an OR circuit 37, a resistance unit 38, a reference power generation circuit 39, a counter 40, and a logic circuit 41. , And selectors 42 and 43.

  The counter 40 counts the number of rewrites. The counter 40 is connected to a logic circuit 41, and the logic circuit 41 outputs a selection signal according to the count number of the counter 40.

  Selectors 42 and 43 are connected to the logic circuit 41, respectively. The selector 42 is connected to the output portions of the comparison circuits 34 and 34a, and the selector 43 is connected to the output portions of the comparison circuits 35 and 35a.

  The selector 42 selects and outputs one of the comparison circuits 34 and 34 a based on the selection signal output from the logic circuit 41. The selector 43 selects and outputs one of the comparison circuits 35 and 35a based on the selection signal output from the logic circuit 41.

  The resistor unit 38 has a configuration in which a plurality of resistors are connected in series between a boosted voltage generated by the voltage generation circuit 9a and a reference potential (ground potential), and compares an arbitrary divided voltage as reference voltages VR6 to VR9. The circuits 34, 34a, 35, and 35a are respectively supplied to the negative (−) side input terminals.

  The reference power generation circuit 39 generates a reference voltage Vref. The reference voltage Vref is connected to be supplied to the positive (+) side input terminals of the comparison circuits 34 and 34a and the input portions of the temperature characteristic addition circuits 36 and 36a, respectively. Here, the temperature characteristic addition circuits 36 and 36a have the same configuration as that of FIG.

  The positive (+) side input terminal of the comparison circuit 35 is connected to the output part of the temperature characteristic addition circuit 36, and the positive (+) side input terminal of the comparison circuit 35a is connected to the output part of the temperature characteristic addition circuit 36a. Is connected.

  The input terminal of the selector 42 is connected to the output terminals of the comparison circuits 34 and 34a, and the input terminal of the selector 43 is connected to the output terminals of the comparison circuits 35 and 35a. One input part of the logical sum circuit 37 is connected to the output part of the selector 42, and the other input part of the logical sum circuit 37 is connected to the output part of the selector 43.

  Then, a signal output from the output unit of the OR circuit 37 is output to the voltage generation circuit 9a as a stop signal. The voltage generation circuit 9a is composed of, for example, a charge pump. When a stop signal is input, the voltage generation circuit 9a stops the charge pump operation and stops generating the boosted voltage.

  In this case, by inputting different reference voltages VR6 to VR9 to the negative (−) side input ends of the comparison circuits 34, 34a, 35, and 35a, the determination level of the temperature range A having no temperature gradient and the temperature gradient are obtained. The temperature range B has a gradient and is selected according to the number of rewrites.

  Thus, even if the temperature characteristics of the memory current change due to repeated rewriting, the verify determination memory gate voltage can be flexibly changed in accordance with the change, so that writing can be performed with minimum stress.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, as shown in FIG. 19, the write voltage may have temperature characteristics. In this case, as shown in the figure, write voltages corresponding to a normal temperature range A having no temperature gradient and a temperature range C having a temperature gradient lower than the lower limit of the normal temperature range A are generated to I do. The generation of the write voltage can be realized by the circuit configuration shown in FIG. 13 of the second embodiment.

  Thereby, the temperature dependence of the writing time can be relaxed. Further, since the breakdown voltage of the element (MOS transistor) required in the row decoder / driver circuit 13 can be reduced, the cost of the semiconductor integrated circuit device 1 can be reduced.

  Furthermore, as shown in FIG. 20, the erase voltage may be erased with a temperature gradient. FIG. 20 is a diagram showing an example of the temperature characteristic of the memory voltage at the time of erasing. In this case, erasing is performed by generating an erasing negative voltage composed of a normal temperature range A having no temperature gradient and a temperature range B having a temperature gradient. The generation of the erase voltage can also be realized by the circuit configuration shown in FIG. 13 of the second embodiment.

  Even in this case, the temperature dependence of the erasing time can be relaxed and the breakdown voltage of the element (MOS transistor) required for the row decoder / driver circuit 13 can be reduced, so that the cost of the semiconductor integrated circuit device 1 can be reduced. Can be reduced.

  The present invention is suitable for a technique for improving the rewrite endurance of a nonvolatile memory cell in a nonvolatile semiconductor memory device.

1 is a block diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 2 is a block diagram of a flash memory module provided in the semiconductor integrated circuit device of FIG. 1. FIG. 3 is a block diagram illustrating an example of a power supply circuit provided in the flash memory module of FIG. 2. It is explanatory drawing which shows the circuit structural example of the temperature characteristic determination circuit provided in the power supply circuit of FIG. FIG. 5 is a circuit diagram illustrating an example of a temperature characteristic addition circuit provided in the temperature characteristic determination circuit of FIG. 4. FIG. 5 is an explanatory diagram illustrating an example of a temperature characteristic of a memory voltage at the time of verification set by the temperature characteristic determination circuit of FIG. 4. FIG. 3 is an explanatory diagram of memory current characteristics in an erased state and a written state in a memory cell provided in the flash memory module of FIG. 2. 3 is a flowchart showing an erase operation in the flash memory module of FIG. 2. 3 is a flowchart showing a write operation in the flash memory module of FIG. 2. FIG. 3 is an explanatory diagram showing a relationship between a temperature and a threshold voltage of a memory cell at the time of writing in the flash memory module of FIG. 2. It is explanatory drawing which shows an example of the temperature characteristic of the memory voltage at the time of the erase verification in the flash memory module by other embodiment of this invention. It is the figure which showed an example of the temperature dependence of the current characteristic in the memory cell after the erase | elimination in the flash memory module by other embodiment of this invention. It is a circuit diagram which shows the structure of the temperature characteristic determination circuit provided in the semiconductor integrated circuit device by Embodiment 2 of this invention. It is explanatory drawing which shows an example of the temperature characteristic of the memory voltage at the time of the verification set by the temperature characteristic determination circuit of FIG. It is explanatory drawing which shows an example of the temperature dependence of the memory current characteristic after writing in the memory cell provided in the flash memory module by Embodiment 2 of this invention. It is explanatory drawing which shows the temperature characteristic of the memory voltage at the time of the erase verification by other embodiment of this invention. It is the figure which showed an example of the temperature dependence of the current characteristic in the memory cell after the erase | elimination by other embodiment of this invention. It is explanatory drawing which shows the other circuit structural example of the temperature characteristic determination circuit by other embodiment of this invention. It is explanatory drawing which shows the other example of the temperature characteristic of the memory voltage at the time of writing by other embodiment of this invention. It is explanatory drawing which showed the other example of the temperature characteristic of the memory voltage at the time of the erase | elimination by other embodiment of this invention. It is explanatory drawing which showed an example of the temperature characteristic of the memory gate voltage at the time of the write verification which this inventor examined. It is explanatory drawing which shows the memory current characteristic of the memory cell after the writing in FIG. It is explanatory drawing which showed the other example of the temperature characteristic of the memory gate voltage at the time of the write verification which this inventor examined. FIG. 24 is a diagram showing memory current characteristics of the memory cell after writing in FIG. FIG. 24 is an explanatory diagram showing the relationship between the memory threshold voltage change and the number of rewrites during writing in FIGS. 21 and 23.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device 2 Peripheral circuit 3 Bus controller 4 CPU (central processing unit)
5 RAM
6 I / O
7 Flash memory controller 8 Flash memory module (nonvolatile memory)
9 Power supply circuit (voltage generator)
9a Voltage generation circuit 9b Temperature characteristic determination circuit 9b ₁ Temperature characteristic determination circuit 10 Oscillation circuit 11 Control circuit 12 Address buffer 13 Row decoder / driver circuit 14 I / O unit 15 Sense amplifier circuit 16 Column decoder 17 Write latch control circuit 18 Memory mat 19 to 21 Comparison circuits 22 and 23 Temperature characteristic addition circuit 24 OR circuit 25 AND circuit 26 Resistance section (comparison voltage generation section)
27 Reference power supply generation circuits 28 and 29 Comparison circuit 30 Temperature characteristic addition circuit 31 OR circuit 32 Resistance section (comparison voltage generation section)
33 Reference power generation circuit 34, 34a Comparison circuit 35, 35a Comparison circuit 36, 36a Temperature characteristic addition circuit 37 OR circuit 38 Resistor 39 Reference power generation circuit 40 Counter 41 Logic circuit 42, 43 Selector B Bus S Memory cell (nonvolatile) Memory cell)
VR1 reference voltage (first comparison reference voltage)
VR2 reference voltage (second comparison reference voltage)
VR3 reference voltage (third comparison reference voltage)
VR4 reference voltage (fourth comparison reference voltage)
VR5 reference voltage (fifth comparison reference voltage)
Vref reference voltage Vref2, Vref3, Vref5 reference voltage T1-T5 transistor

Claims (15)

A memory array section having a plurality of nonvolatile memory cells, and a voltage generation section for supplying a predetermined voltage to be supplied to the nonvolatile memory cells,
The voltage generator is
A nonvolatile semiconductor memory device, wherein a voltage is generated in a first temperature range without depending on temperature, and a voltage is generated in a temperature range other than the first temperature range depending on temperature. The nonvolatile semiconductor memory device according to claim 1,
The voltage generator is
A voltage generation circuit for generating a predetermined voltage based on the operation control signal;
In the first temperature range, an operation control signal is output so that a voltage having no temperature dependency is generated, and in a temperature range other than the first temperature range, a voltage having a temperature dependency is generated. And a temperature characteristic determination circuit for outputting an operation control signal. The nonvolatile semiconductor memory device according to claim 1,
The temperature characteristic determination circuit includes:
In a second temperature range higher than the upper limit of the first temperature range, an operation control signal for generating a voltage having a first temperature gradient is output, and a third lower temperature than the lower limit of the first temperature range is output. A nonvolatile semiconductor memory device that outputs an operation control signal for generating a voltage having a second temperature gradient in a temperature range. The nonvolatile semiconductor memory device according to claim 3.
The temperature characteristic determination circuit includes:
A comparison voltage generation unit that divides the voltage generated by the voltage generation circuit and generates first to third comparison reference voltages;
A first comparison circuit that compares the first comparison reference voltage generated by the comparison voltage generation unit with a reference voltage and outputs a comparison result;
A first temperature characteristic addition circuit that changes the second comparison reference voltage generated by the comparison voltage generation unit depending on temperature;
A second comparison circuit that compares the reference voltage with the voltage to which the temperature dependency is added by the first temperature characteristic addition circuit, and outputs the comparison result;
A second temperature characteristic addition circuit for changing the third comparison reference voltage generated by the comparison voltage generation unit depending on the temperature;
A third comparison circuit that compares the voltage to which the temperature dependency is added by the second temperature characteristic addition circuit with a reference voltage and outputs the comparison result;
The comparison result output from the first to third comparison circuits is logically operated to generate a voltage having no temperature gradient in the first temperature range, and the first temperature gradient is calculated in the second temperature range. And a logic circuit that outputs an operation control signal so as to generate a voltage having a second temperature gradient in the third temperature range. The nonvolatile semiconductor memory device according to claim 1,
The temperature characteristic determination circuit includes:
A nonvolatile semiconductor memory device that outputs an operation control signal for generating a voltage having a second temperature gradient in a second temperature range higher than an upper limit of the first temperature range. The nonvolatile semiconductor memory device according to claim 5,
The temperature characteristic determination circuit includes:
A comparison voltage generation unit that divides the voltage generated by the voltage generation circuit and generates fourth and fifth comparison reference voltages;
A fourth comparison circuit that compares the fourth comparison reference voltage generated by the comparison voltage generation unit with a reference voltage and outputs the comparison result;
A third temperature characteristic addition circuit for changing the fifth comparison reference voltage generated by the comparison voltage generation unit depending on the temperature;
A fifth comparison circuit that compares the voltage to which the temperature dependency is added by the third temperature characteristic addition circuit with a reference voltage and outputs the comparison result;
A logical operation is performed on the comparison results output from the fourth and fifth comparison circuits to generate a voltage having no temperature gradient in the first temperature range, and a first temperature gradient in the second temperature range. A non-volatile semiconductor memory device comprising: a logic circuit that outputs an operation control signal so as to generate a voltage having the same. The nonvolatile semiconductor memory device according to claim 1,
The voltage generated by the voltage generator is
A non-volatile semiconductor memory device characterized by being either a write verify determination memory gate voltage or an erase verify determination memory gate voltage. The nonvolatile semiconductor memory device according to claim 1,
The voltage generated by the voltage generator is
A non-volatile semiconductor memory device, which is either a write memory voltage or an erase memory voltage. A non-volatile storage unit and a central processing unit, the central processing unit can execute a predetermined process, and can instruct the non-volatile storage unit, the non-volatile storage unit, A semiconductor integrated circuit device having a plurality of nonvolatile memory cells for storing information,
The nonvolatile memory unit includes a memory array unit having a plurality of nonvolatile memory cells, and a voltage generation unit that supplies a predetermined voltage to be supplied to the nonvolatile memory cells,
The voltage generator generates a voltage without depending on temperature in the first temperature range, and generates a voltage depending on temperature in a temperature range other than the first temperature range. Semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 9.
The voltage generator is
A voltage generation circuit for generating a predetermined voltage based on the operation control signal;
In the first temperature range, an operation control signal is output so that a voltage having no temperature dependency is generated, and in a temperature range other than the first temperature range, a voltage having a temperature dependency is generated. And a temperature characteristic determining circuit for outputting an operation control signal to the semiconductor integrated circuit device. The semiconductor integrated circuit device according to claim 9 or 10,
The temperature characteristic determination circuit includes:
In a second temperature range higher than the upper limit of the first temperature range, an operation control signal for generating a voltage having a first temperature gradient is output, and a third lower temperature than the lower limit of the first temperature range is output. In the temperature range, an operation control signal for generating a voltage having a second temperature gradient is output. The semiconductor integrated circuit device according to claim 11.
The temperature characteristic determination circuit includes:
A comparison voltage generation unit that divides the voltage generated by the voltage generation circuit and generates first to third comparison reference voltages;
A first comparison circuit that compares the first comparison reference voltage generated by the comparison voltage generation unit with a reference voltage and outputs a comparison result;
A first temperature characteristic addition circuit that changes the second comparison reference voltage generated by the comparison voltage generation unit depending on temperature;
A second comparison circuit that compares the reference voltage with the voltage to which the temperature dependency is added by the first temperature characteristic addition circuit, and outputs the comparison result;
A second temperature characteristic addition circuit for changing the third comparison reference voltage generated by the comparison voltage generation unit depending on the temperature;
A third comparison circuit that compares the voltage to which the temperature dependency is added by the second temperature characteristic addition circuit with a reference voltage and outputs the comparison result;
The comparison result output from the first to third comparison circuits is logically operated to generate a voltage having no temperature gradient in the first temperature range, and the first temperature gradient is calculated in the second temperature range. And a logic circuit that outputs an operation control signal so as to generate a voltage having a second temperature gradient in the third temperature range. The semiconductor integrated circuit device according to claim 9 or 10,
The temperature characteristic determination circuit includes:
The semiconductor integrated circuit device outputs an operation control signal for generating a voltage having a second temperature gradient in a second temperature range higher than the upper limit of the first temperature range. The semiconductor integrated circuit device according to claim 13.
The temperature characteristic determination circuit includes:
A comparison voltage generation unit that divides the voltage generated by the voltage generation circuit and generates fourth and fifth comparison reference voltages;
A fourth comparison circuit that compares the fourth comparison reference voltage generated by the comparison voltage generation unit with a reference voltage and outputs the comparison result;
A third temperature characteristic addition circuit for changing the fifth comparison reference voltage generated by the comparison voltage generation unit depending on the temperature;
A fifth comparison circuit that compares the voltage to which the temperature dependency is added by the third temperature characteristic addition circuit with a reference voltage and outputs the comparison result;
A logical operation is performed on the comparison results output from the fourth and fifth comparison circuits to generate a voltage having no temperature gradient in the first temperature range, and a first temperature gradient in the second temperature range. A semiconductor integrated circuit device comprising: a logic circuit that outputs an operation control signal so as to generate a voltage having the same. The semiconductor integrated circuit device according to any one of claims 9 to 14,
The voltage generated by the voltage generator is
A semiconductor integrated circuit device, which is one of a write verify determination memory gate voltage, an erase verify determination memory gate voltage, a write memory voltage, and an erase memory voltage.

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