TWI518688B - Semiconductor memory system and access method thereof - Google Patents

Description

Semiconductor memory system and access method thereof

The Korean Patent No. 10-2007-0134342 filed on Dec. 20, 2007 is the priority file of the present disclosure, the disclosure of which is incorporated herein by reference.

The present invention relates to a semiconductor and a system for controlling a semiconductor memory, and more particularly to a semiconductor memory system and an access method thereof for improving reliability.

The semiconductor memory device is suitable for storing data. In general, semiconductor memory devices can be classified into volatile and non-volatile categories. Volatile memory devices lose data when the power supply is powered down, but non-volatile memory devices retain their data when the power supply is stopped.

Since non-volatile memory devices can store data at low power, it is a popular portable storage medium. A flash memory device is a non-volatile memory. The following uses flash memory as an example, but the following description is also applicable to other types of non-volatile memory, such as phase change random access memory (PRAM), ferroelectric random memory. Take a memory (Ferroelectric Random Access Memory, FRAM for short) and a magnetic random access memory (Magnetic RAM).

1 is a cross-sectional view of a memory cell of a flash memory device. Referring to FIG. 1, the source S and the drain D of the memory cell are formed on the semiconductor substrate, and the channel region is located between the source S and the drain D. Floating gate A pole is formed over the channel region, and a Thin Dielectric Film is located between the floating gate and the channel region. A source S, a drain D, a floating gate, and a semiconductor substrate are connected to the respective terminals for receiving a voltage for performing stylization (programming), erasing, and reading.

In the flash memory device, the threshold voltage of the memory cell can be discriminated to read the data. The threshold voltage of the memory cell can be determined by the amount of electrons accumulated in the floating gate. When there is enough electrons stored in the floating gate, the threshold voltage becomes high.

For many reasons, the electrons of the floating gate leak in the direction of the arrow in Figure 1. In particular, electrons are subject to external stimuli, such as heat, and leak from the floating gate. In addition, electrons are released from the floating gate due to the tired memory cells. The main reason for causing fatigue in the dielectric film between the channel region and the floating gate is the repeated access operation to the flash memory device. The above access actions include stylization, erasing, and reading.

2 is a schematic diagram of a threshold voltage distribution of a memory cell. Referring to FIG. 2, the vertical axis indicates the number of memory cells, and the horizontal axis indicates the threshold voltage Vth. If the memory cell is a Single Level Cell (SLC), the memory cell can be switched between two states (S0, S1).

When the read voltage Vr is applied to the control gate of the memory cell (please refer to FIG. 1), the memory cell of the state S0 is turned on, and the memory cell of the state S1 is turned off. If the memory cell is turned on, current will flow through the memory cell. If the memory cell is turned off, no current will flow through the memory cell. Therefore, the data can be discriminated by whether the memory cell is turned on or off. In order to be able to accurately measure the state of the data stored in the memory cell, the threshold voltage of the memory cell must be maintained from time to time. However, based on the above, the threshold voltage of the memory cell is lowered due to the external environment and/or fatigue.

3 is a schematic diagram showing an example in which the threshold voltage of the memory cell in FIG. 2 is lowered by an indeterminate level. Referring to FIG. 3, the solid line represents the initial threshold voltage of the memory cell, and the broken line represents that the threshold voltage is lowered due to the external environment and/or fatigue. Even if the threshold voltage of the memory cell has been programmed into state S1, the memory cells belonging to the shaded area are recognized as state S0 due to the reduced threshold voltage when detected. This result can lead to read errors, which in turn reduces the reliability of the semiconductor memory.

Especially for multiple Multi-Level Cell (MLC), the change of threshold voltage will cause many operational errors. The reason is that in order to increase the integrated density of the semiconductor memory device, one unit of the multi-layer memory cell is designed to store a plurality of data bits.

4 is a schematic diagram of a threshold voltage distribution of a 3-bit level memory cell. Referring to FIG. 4, the 3-bit memory cell can operate in one of eight states (S0-S7). S0 is the erase state, and S1~S7 indicate the stylized state. In contrast to single-layer memory cells, the threshold voltages of the multi-layer memory cells are correspondingly arranged in a narrower interval. Therefore, in a multi-layer memory cell, a slight change in threshold voltage can cause a series of problems.

Fig. 5 is a view showing an example in which the threshold voltage of the 3-bit memory cell is lowered in accordance with Fig. 4. Referring to FIG. 5, the solid line represents the initial threshold voltage of the memory cell, and the broken line represents that the threshold voltage is lowered due to the external environment and fatigue, and the reduced threshold voltage corresponds to the shadow area, which may cause a reading error in the memory cell.

The present invention provides a semiconductor memory system capable of improving reliability by performing an access operation in accordance with variations in memory cell characteristics.

Further, the present invention provides an access method of a semiconductor memory system, which can perform memory access by measuring variations in memory cell characteristics.

The concept and spirit of the invention will be apparent to those skilled in the <RTIgt;

In an embodiment and application of the spirit of the present invention, a semiconductor memory system is provided that includes a non-volatile memory and a memory controller. Non-volatile memory stores monitoring data in one or more memory cells. The memory controller controls non-volatile memory. The memory controller can detect the monitoring data and adjust the bias voltage supplied to the memory cells according to the detection result.

The memory controller detects the monitoring data and adjusts the bias voltage at the power-on time of the semiconductor memory system.

The above memory cells can be grouped into a plurality of blocks, and monitoring data is included in the corresponding blocks. When reading data from the above block, the memory controller can detect the monitoring data corresponding to the above block. The memory controller can store the monitoring data in the blank of the above block. The memory controller can store the monitoring data in the blank of the above block with the smallest error rate.

The memory controller can store the detection result of the monitoring data. The bias voltage can be a read voltage. The monitoring data may correspond to one of a plurality of threshold voltage states of the memory cell. The memory controller can detect the threshold voltage state and according to The detection result adjusts the bias voltage.

The monitoring data may be information about the number of erasures of the above memory cells. The memory controller detects the erased quantity and adjusts the bias voltage based on the detection result. If the number of read errors is greater than the reference number of the memory cells, the memory controller can detect the monitoring data and adjust the bias voltage according to the detection result. The memory controller can detect read errors using an error correction code mechanism. The monitoring data corresponds to one of a plurality of threshold voltage states of the memory cell.

In an embodiment and application of the spirit of the present invention, an access method of a semiconductor memory system is provided. The access method includes storing the monitoring data in one or more memory cells, detecting the monitoring data to generate the detection result, and adjusting the bias voltage supplied to the memory cell according to the detection result.

When the data is programmed, the monitoring data can be stored. Detection monitoring data can be executed at the power-on time. The memory cells can be grouped into a plurality of blocks, and the monitoring data can be included in the corresponding blocks described above. When the above block is read, the monitoring data can be detected according to the above block. If the read error generated in the memory cell exceeds the reference number, the monitoring data can be detected.

In the semiconductor memory system of the spirit of the present invention, the access operation can be performed in accordance with the variation of the characteristics of the memory cell.

In an embodiment and application of the spirit of the present invention, an electronic device is further provided, which includes a semiconductor memory system and a processor. The semiconductor memory system includes a non-volatile memory and a memory controller. Non-volatile memory stores monitoring data in one or more memory cells. The memory controller controls non-volatile memory. The memory controller can detect the monitoring data and adjust the bias voltage supplied to the memory cells according to the detection result. processor The data read from the semiconductor memory system can be processed in accordance with the adjusted bias voltage.

The above described features and advantages of the invention will be apparent from the following description.

The features and advantages of the invention will be more apparent from the following description of the embodiments.

Next, the memory system (Figs. 6 to 10) and its access method (Fig. 11 and Fig. 12) will be described simultaneously with the drawing. In embodiments of the invention, the semiconductor memory can include a wide variety of non-volatile memory, such as phase change random access memory, magnetic random access memory, charge trapping flash memory (Charge Trap) Flash, CTF)...etc.

In the spirit of the present invention, the access voltage can be adjusted depending on the characteristic change of the memory cell caused by the external environment and/or fatigue. Here, the access voltage refers to a voltage applied to the memory cell when reading, programming, and erasing operations are performed. The characteristic variation (eg, threshold voltage) of the memory cell can be detected based on a plurality of monitoring memory cells (M/C) of the memory cell array or the number of erasures, which will be described in more detail below.

FIG. 6 is a block diagram of a semiconductor memory system 100 in accordance with an embodiment of the invention. Referring to FIG. 6, the semiconductor memory system includes a non-volatile memory device 110 and a memory controller 120. The non-volatile memory device 110 includes a memory cell array 130, a column selector 140, an input/output (I/O) circuit 150, and a voltage generator 170. And control logic circuit 160. Here, the reading operation of the non-volatile memory device 110 will be described, but the spirit of the present invention is not limited thereto. The spirit of the present invention can also be applied to the stylization and erasing actions of a memory device.

The non-volatile memory device 110 and the memory controller 120 can be connected by one or more wired or wireless external communication lines for receiving or transmitting signals and/or data. The non-volatile memory device 110 and the memory controller 120 can be integrated into a single body. In this example, the wired or wireless external communication line can be a data or signal bus.

The memory cell array 130 includes a plurality of memory blocks BLK1 BLBLKn. Each memory block includes a memory cell (not shown in FIG. 6) that is disposed in an array of multiple columns (or word lines) and multiple rows (or bit lines). The memory cell can be configured in the logic structure of the inverse gate or the inverse gate.

Column selector 140 can drive selected and unselected columns in conjunction with column addresses (not shown). The voltage generator 170 can generate a driving voltage. At the time of the read operation, the column selector 140 applies the read voltage Vr to the selected column while applying the pass voltage Vpass to one or more unselected columns.

The input/output circuit 150 can be used as a sense amplifier during a read operation. In the read operation, the input/output circuit 150 reads data from the memory cells of the memory cell array. The read data is transmitted from the input/output circuit 150 to the adjustment circuit 180.

The adjusting circuit 180 can detect the threshold voltage variation of the plurality of monitoring memory cells M/C of the memory cell array 130 in cooperation with the data provided by the input/output circuit 150. A method of detecting the change in the threshold voltage of the monitor memory cell M/C by the adjustment circuit 180 will be described later in FIG. Adjustment circuit 180 is based on supervision The threshold voltage change of the control memory cell M/C provides an adjustment command Tr_cmd to the control logic circuit 160.

The control logic circuit 160 controls the voltage generator 170 to generate an adjustment level of the driving voltage (rising or falling) in accordance with the variation of the threshold voltage. The driving voltage generated by the voltage generator 170 is maintained at a fixed level until the next adjustment command Tr_cmd or a reset command is supplied to the control logic circuit 160.

In this embodiment, at least one memory cell in the memory cell array 130 can be utilized to monitor memory cell characteristics. For example, a portion of the memory cells of the system data area can be used to monitor the characteristics of the memory cells. The memory controller 120 can utilize the system data area to manage the semiconductor memory system 100.

Here, the memory cell used for monitoring can be defined as a monitoring memory cell. A memory cell other than the memory cell M/C can be defined as a data memory cell. In addition, the threshold voltage of the data memory cell can be determined according to the threshold voltage of the monitoring memory cell. Since the monitoring memory cell is disposed in the adjacent data memory cell, the threshold voltage of the data memory cell can be determined/detected to decrease as the threshold voltage of the monitoring memory cell changes or decreases. All or part of the monitoring memory cell M/C to the page of the memory block can be provided.

Referring to FIG. 6, a partial page of the monitor memory cell M/C in the block BLK1 can be configured. The memory cell characteristics can be detected more efficiently and correctly based on the number of monitored memory cells M/C. However, in this example, the amount of memory device storage can be reduced, for example, the number of data memory cells can be reduced. Therefore, the number of monitored memory cells can be determined according to the correctness of the detected memory cell characteristics and the amount of storage.

Monitoring the restricted area in the memory cell can be improved in the following manner. A unit of memory block can be divided into data and blank spaces. The blanks can retain the Parity Information of the Error Correction Code (ECC) and the necessary information of the system. Since the unused area in the blank can be used as the monitoring memory cell M/C, it is possible to provide space for monitoring the memory cell without reducing the amount of memory.

Still further, paging with a smaller error rate among the plurality of pages of the memory block can reduce the amount of parity information by storing a lower degree of error correction code in the page. In this way, the blanks protected in the memory block can be used to monitor the memory cell M/C. For example, if the error rate of a particular page is lower than the error rate of a normal page, a specific page will be assigned an 8-bit error correction code, and a normal page will be assigned a 16-bit error correction code. Since the demand for co-located information will become smaller, the unused space in the blank space will be expanded. Unused blanks can be used to monitor memory cells to increase the storage of memory cell array 130.

The monitor memory cell M/C can be pre-programmed to have a specific threshold voltage. That is, the monitor memory cell M/C can be programmed to have monitoring data corresponding to the threshold voltage of the normal memory cell. The monitor memory cell M/C can be programmed to have a corresponding threshold voltage state. For example, portions of the plurality of monitor memory cells M/C can be programmed to have a threshold voltage belonging to state S1 (as shown in FIG. 4), and the other portions of the monitor memory cells M/C can be programmed. It is made to have a threshold voltage belonging to state S2 (as shown in Figure 4). Since the memory cell M/C is programmed when the data is programmed, it can be detected by monitoring the memory cell M/C. The characteristics of the data memory cells change.

In accordance with the spirit of the present invention, the memory cells can be sensed at the power-on time of the semiconductor memory system 100. Therefore, the characteristic change of the memory cell can be detected from the period before the monitor memory cell M/C is programmed to the power source of the semiconductor memory system. At the same time, the memory cell M/C is monitored by the block corresponding to the monitoring memory cell M/C. And when the first read action is performed on a particular memory region (eg, a memory block), the memory cell M/C can be sensed. Finally, if the number of read errors is greater than the reference number, the action of monitoring the memory cell M/C can be performed.

When the non-volatile memory device 110 and the memory controller 120 respectively receive power, independently receive power from different voltage sources or selectively turn on or off, at least one non-volatile memory device 110 and memory The power-on time of the controller 120 performs a monitoring action of monitoring the memory cell M/C. Here, the power-on time may represent a period when at least one of the non-volatile memory device 110 and the memory controller 120 receives power or is turned on according to the supplied power.

Accordingly, the semiconductor memory system 100 can further include a power supply 190 to provide power to the non-volatile memory device 110 and the memory controller 120. The power supply 190 can provide power to the memory controller 120, and then the power supply is supplied from the memory controller 120 to the non-volatile memory via the communication line connected to the non-volatile memory device 110 and the memory controller 120. Body device 110. The power supply 190 can be a plurality of independent power sources or selectively provide power to one of the corresponding non-volatile memory device 110 and the memory controller 120. The power supply 190 can be The non-volatile memory device 110 and the memory controller 120 are integrated into a single body. Of course, the power supply 190 can also be a separate unit and it is coupled to the semiconductor memory system 100.

7 is a schematic diagram of a method of detecting a threshold voltage of a memory cell M/C. Referring to Figure 7, the solid line represents the initial threshold voltage and the dashed line represents the threshold voltage being reduced by the external environment and or by fatigue. In the present embodiment, the threshold voltage is reduced as an example, but the invention is not limited thereto. In other embodiments, it can also be applied to threshold voltage rises, changes, or adjustments by external factors or stimuli.

In the read operation of monitoring the memory cell M/C, the read voltage is used. This read voltage can be used to control the gate of the monitored memory cell. During the read operation, the read voltage is maintained. However, the read voltage can be varied at a predetermined threshold. Depending on the change in the read voltage, portions of the plurality of monitor memory cells M/C can be turned off and other portions of the monitor memory cells M/C described above can be turned on.

Depending on the change in read voltage, the number of monitored memory cells M/C startup and shutdown will also change. By monitoring the number of memory cell M/C activation and shutdown by statistical analysis, the threshold voltage change of the monitoring memory cell M/C can be detected. For example, in one example, each of the plurality of monitor memory cells is programmed to be in states S6 and S7, and the read voltage Vrd1 is set at a median value of the change distribution of the threshold voltage, which causes the monitor memory cells to be turned on or off. The quantity has the smallest change. This operation can be performed by the work of the adjustment circuit 180.

FIG. 8 is a block diagram of a semiconductor memory system 800 in accordance with an embodiment of the present invention. Please refer to FIG. 8 , the semiconductor memory system 200 package The memory controller 220 and the non-volatile memory device 210 are included. The memory controller 220 can include an adjustment circuit 280. The non-volatile memory device 210 can include a memory cell array 230, a column selector 240, an input/output circuit 250, a control logic circuit 260, and a voltage generator 270. The components in Fig. 8 are similar to those in Fig. 6, and therefore their operation will not be repeated. 8 is different from FIG. 6 in that each of the memory blocks BLK1 BLBLKn of the memory cell array of FIG. 8 includes monitoring memory cells M/C1 to M/C, respectively. Therefore, the accuracy of detecting changes in the characteristics of the detected memory cells in each block can be improved.

The semiconductor memory system 200 can further include a power supply 290. The power supply 290 of FIG. 8 is similar to the power supply 190 of FIG. 6, and its operation will not be described again.

In addition, at the power-on time of the semiconductor memory system 200, the reliability of the semiconductor memory system 200 can be improved by simplifying the detection of the threshold voltage of the monitor memory cell from the portion of the memory block.

FIG. 9 is a block diagram of a semiconductor memory system 300 in accordance with an embodiment of the present invention. Referring to FIG. 9, the semiconductor memory system 300 can include a non-volatile memory device 310 and a memory controller 320. The non-volatile memory device 310 can include a memory cell array 330, a column selector 340, an input/output circuit 350, a control logic circuit 360, and a voltage generator 370. The components in Fig. 9 are similar to those in Fig. 6, and therefore their operation will not be repeated.

The semiconductor memory system 300 can further include a power supply 390. The power supply 390 of FIG. 9 is similar to the power supply 190 of FIG. 6, and its operation will not be described again.

The semiconductor memory system 300 of FIG. 9 differs slightly from FIG. 6. For example, the memory cell array 330 of FIG. 9 stores information about the number of erases (E/C). The erased quantity (E/C) can be stored anywhere in the memory cell array 330. The erase quantity (E/C) refers to the number of times the memory block is erased. The erased quantity (E/C) is a threshold voltage change that detects the data memory cell. If the erased number (E/C) of the memory block is greater than a reference straight (for example, if the memory block is tired to reduce the necessary or required function), the threshold voltage of the memory cell in the block will be quickly reduced. . The erase quantity (E/C) can be written to a portion of the memory block or to the system data of the memory cell array 330.

When the memory cell array 330 receives an instruction from the memory controller 320 to perform an erase operation, the memory cell array 330 counts the number of instructions to perform an erase operation to generate an erase quantity (E/C) and/or will wipe In addition to the quantity (E/C), a portion of the memory cells stored in the memory cell array 330 are stored.

FIG. 10 is a block diagram of a semiconductor memory system 400 in accordance with an embodiment of the present invention. Referring to FIG. 10, the semiconductor memory system 400 can include a non-volatile memory device 410 and a memory controller 420. The non-volatile memory device 410 can include a memory cell array 430, a column selector 440, an input/output circuit 450, a control logic circuit 460, and a voltage generator 470. The components in Fig. 10 are similar to those in Fig. 6, and therefore their operation will not be repeated.

The semiconductor memory system 400 can further include a power supply 490. The power supply 490 in FIG. 10 is similar to the power supply 190 of FIG. 6, and its operation will not be described again.

The memory blocks BLK1~BLKn of the memory cell array in Fig. 10 respectively It is included in the monitoring memory cells M/C1~M/Cn. Therefore, the change in the characteristics of the memory cells in each block can be correctly detected. In addition, the erase amount (E/C) can be stored in the memory cell array 430. In this way, the threshold voltage of the data memory cell can be stored in the memory cell array 430 according to the monitoring memory cell M/C and the erased quantity E/C.

11 is a flow chart of an access method of a semiconductor memory system according to FIG. 6 , FIG. 8 or FIG. 10 . Referring to FIG. 11, the access method of the semiconductor memory system may include multiple steps, such as a power-on startup step of the semiconductor memory system of step S110, a read monitor memory cell of step S120, and a threshold voltage of step S130. The change and the read voltage of step S140 are adjusted.

The monitor memory cell M/C can be pre-programmed to correspond to a particular state of the threshold voltage. Therefore, the variation characteristics of the data memory cell can be detected by monitoring the memory cell M/C. The memory cells can then be programmed to have threshold voltages that are the same or different from each other.

In step S110, the power of the semiconductor memory system is activated (or turned on). When the semiconductor memory system is powered on, a power-up step is performed. After the stylized monitoring of the memory cell M/C, the semiconductor memory system can be turned on at various points in time. For example, a semiconductor memory system can be powered on with the host. The semiconductor memory system can also be turned on when the host is connected.

In step S120, the threshold voltage of the monitoring memory cell M/C can be detected. According to the threshold voltage of the monitoring memory cell M/C, the potential of the reading voltage given to the data memory cell can be determined. Detecting each of the threshold voltages of the monitored memory cells M/C The steps have been described together with the description of FIG. 7, and will not be described in detail herein. When the threshold voltage of the monitoring memory cell is detected at the power-on time of the semiconductor memory system, its steps can be performed in the block reading step.

In step S130, it can be discriminated whether or not the threshold voltage of the monitor memory cell M/C is changed. Unless the threshold voltage of the monitor memory cell M/C is changed, this process is terminated without changing the potential of the read voltage. If the threshold voltage of the monitor memory cell M/C is changed, step S140 is executed.

In step S140, the potential of the read voltage can be adjusted by monitoring the change in the threshold voltage of the memory cell M/C. If the threshold voltage of the monitoring memory cell M/C becomes low, the reading voltage given to the data memory cell is lowered. In contrast, if the threshold voltage of the monitor memory cell M/C becomes high, the read voltage given to the data memory cell is boosted. Then, the read operation can be performed on the data memory cell according to the read voltage of the potential after adjustment or maintenance.

In summary, the threshold voltage of the memory cell M/C can be detected at the power-on time of the semiconductor memory system. According to the detection result of the threshold voltage, the reading voltage given to the data memory cell can be adjusted to enhance the reliability of the reading operation in the semiconductor memory system. Although this embodiment uses the monitor memory cell M/C as an example to detect the threshold voltage change, in other embodiments, the erase amount (E/C) can also be used to perform detection and/or discriminate the threshold voltage. Change.

FIG. 12 is a flow chart of an access method of a memory system according to FIG. 6, FIG. 9, and FIG. Referring to FIG. 12, the reading method may include multiple steps, such as reading the data memory cell in step S210, searching for the reading error in step S220, and determining the number of reading errors in step S230. Step S240 corrects the error, and step S250 reads the monitor memory cell and the adjusted read voltage of step S260. When the number of errors is greater than the reference number, the threshold voltage of the monitoring memory cell is detected. The reference quantity can be set to be less than the maximum number of read errors, which is within the range that can be corrected. For example, if the number of correctable read errors is 8, the reference number can be set to 6. Therefore, the read voltage can be adjusted before the error correction or adjustment of the threshold voltage.

In step S210, the reading operation of reading the data memory cell can be started. The read voltage given to the data memory cell may be a preset voltage or a potential adjusted as described in FIG.

If a read error is detected in step S220, step S230 is followed. If no error is detected in step S220, the access operation ends. Read errors can be detected in a variety of ways. For example, a read error can be found by an error correction code mechanism. The error correction code can be stored in a memory cell array of the semiconductor memory device. In the read operation, the data error can be detected by comparing the stored error correction code with the newly generated error correction code.

In step S230, it can be determined whether the number of errors is greater than the reference number. For example, an error correction code can be used to detect the number of errors. Unless the number of errors is greater than the reference number, step S240 is continued. If the number of errors is greater than the reference number, step S250 is performed.

In step S240, the read error can be repaired. The read error can be corrected by the error correction code.

In step S250, the threshold voltage of the monitoring memory cell M/C can be detected. The threshold voltage of the data memory cell can be discriminated or detected, wherein the threshold voltage of the data memory cell is related to the threshold voltage of the monitoring memory cell M/C. If the threshold voltage of the monitoring memory cell M/C is sensed to be lower than before, then the threshold voltage of the data memory cell will also decrease.

In step S260, the read voltage given to the data memory cell is adjusted in accordance with the change in the threshold voltage of the monitor memory cell M/C. If the threshold voltage of the monitoring memory cell M/C is lowered, the potential of the reading voltage given to the data memory cell is also lowered. In contrast, if the threshold voltage of the monitoring memory cell M/C is increased, the potential of the reading voltage given to the data memory cell will also become high. Returning to step S210 after step S260. This access method will continue until the data memory cell has no read errors. But this has a problem, because the physical memory of the data memory cannot be repaired by error correction and adjustment of the read voltage, so it will cause the access action to be repeatedly executed repeatedly. Therefore, the number of repetitions of the access action must be limited to a predetermined number.

The embodiment illustrated in Figures 11 and 12 can be performed together. That is, the embodiment of FIG. 11 can be performed at the power-on time of the semiconductor memory system, and the embodiment of FIG. 12 can be performed in the read operation of the semiconductor memory system. With the above-described method, even if the power-on time of the semiconductor memory system is not extended, the reliability of the semiconductor memory system can be improved by changing the potential of the read voltage when the generated read error is larger than the reference number.

Further, the read result of the monitoring memory cell can be stored in a storage unit (for example, a static random access memory), and the storage unit can be included in the memory controller 120. Therefore, the read monitoring memory cell can be reduced The number of repetitions of the action.

The spirit of the invention can also be implemented as a computer readable code on a computer readable medium. Computer readable media can include computer readable recording media and computer readable transmission media. The computer readable recording medium can be any form of data storage device that can store data such as programs and can be thereafter read by a computer system. The computer readable recording medium may include, for example, a read only memory (ROM), a random access memory (RAM), a compact disc, a magnetic tape, a floppy disk, and an optical data storage device. The computer can read the recording medium or be distributed to the network connected to the computer system, so the computer readable code can be stored and executed in a distributed manner. A computer readable transmission medium can carry a carrier or signal (eg, wired or wireless data transmission over a network). Similarly, programmers skilled in the art can apply the spirit of the present invention to functional programs, code and code segments.

Figure 13 is a block diagram of a computer system having a semiconductor memory system, such as an electronic device, in accordance with an embodiment of the present invention.

Referring to FIG. 13, the computer system 500 includes a processor 510, a controller 520, an input unit 530, an output unit 540, a non-volatile memory 550, and a main memory unit 560. In Figure 13, the solid line represents the system bus that can transmit signals, data, or instructions.

Computer system 500 can input data through input unit 530, such as a keyboard or a camera. The input data may be an instruction input by the user or a multimedia material obtained by the input source or the recording source. For example, the multimedia material may be image data, and the input source or the recording source may be a camera. Input data can be stored in non-volatile memory 550 or main memory Yuan 560.

The results processed by processor 510 can be stored in non-volatile memory 550 or main memory unit 560. The output unit 540 can output data from the non-volatile memory 550 or the main memory unit 560. For example, the output unit 540 can output data to the viewer in a visual form. For another example, the output unit 540 can include a display device or a speaker.

The non-volatile memory 550 can be adapted for use in an access method in accordance with the spirit of the present invention. Not only can the reliability of the non-volatile memory 550 be improved, but the reliability of the computer system 500 can be improved accordingly.

Non-volatile memory 550 and/or controller 520 can be mounted on computer system 500 using a variety of packaging configurations. For example, the non-volatile memory 550 and/or the controller 520 can be disposed on any package, such as a package on package (PoP) or a ball grid array (Ball Grid Arrays). BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip-On-Board (COB), Ceramic Double In-Chip (CERamic Dual In-) Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline (SOIC), Ultra Small Package ( Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi-Chip Package (MCP), Wafer-Level Process Package ( Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP) or Wafer-Level Processed Package (WSP).

Although not shown above, those skilled in the art will recognize that a power supply is required to supply power to computer system 500. If computer system 500 is a mobile device, battery power can be used to power computer system 500. The power supply of FIG. 6, FIG. 8 to FIG. 10 can also be used as a power supply to the computer system 500.

The semiconductor memory system according to the inventive concept can also be applied to a solid state hard disk. The solid state hard disk can be used to implement the non-volatile memory 550 or the main memory 560. The solid state drive can be coupled to the computer system 500 in a separate manner. The non-volatile memory 550 or the main memory 560 can also be implemented in combination with a solid state hard disk and a conventional hard disk.

The semiconductor memory system according to the inventive concept can also be applied to a mobile storage device. It can therefore be an MP3 player, a digital camera, a personal digital assistant or a storage device for an e-book. In addition, it can also be used as a storage device for digital TVs or computers.

Output device 540 can perform the output functions or actions of computer system 500. For example, when computer system 500 is an image processing and/or forming device, output device 540 can perform image processing and/or forming operations to process Processing and/or forming of images. If computer system 500 is a data generating device, output device 540 can perform a data generation action to process the required or necessary format data corresponding to the functionality of computer system 500.

The computer system 500 can further include an interface unit 570 for communicating with the external device 600 to receive or transmit data. The interface unit 570 can be connected to the external device 600 through a wired or wireless communication line.

Based on the above, the semiconductor memory system according to the spirit of the invention can detect a change in characteristics (threshold voltage), thereby implementing a monitoring function (such as monitoring the memory cell or erasing the number). Therefore, the access voltage (for example, the read voltage) can be adjusted according to the change of the characteristics of the memory cell to improve the reliability of the access operation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400‧‧‧ semiconductor memory system

110, 210, 310, 410‧‧‧ Non-volatile memory devices

120, 220, 320, 420‧‧‧ memory controller

130, 230, 330, 430‧‧‧ memory cell array

140, 240, 340, 440‧ ‧ column selector

150, 250, 350, 450‧‧‧ input/output circuits

160, 260, 360, 460‧‧‧ control logic

170, 270, 370, 470‧‧‧ voltage generator

180, 280, 380, 480‧‧‧ adjustment circuit

190, 290, 390, 490‧‧‧ power supply

500‧‧‧Computer system

510‧‧‧ processor

520‧‧‧ Controller

530‧‧‧Input unit

540‧‧‧Output unit

550‧‧‧Non-volatile memory

560‧‧‧Main memory unit

570‧‧‧Interface unit

600‧‧‧External devices

Tr_cmd‧‧‧ adjustment instructions

BLK1~BLKn‧‧‧ memory block

M/C, M/C1~M/Cn‧‧‧ monitor memory cells

Vth‧‧‧ threshold voltage

S0~S7‧‧‧ Status

G‧‧‧ gate

S‧‧‧ source

D‧‧‧汲

Vr‧‧‧ reading voltage

E/C‧‧‧ erasing quantity

Steps of the access method of S110, S120, S130, S140, S210, S220, S230, S240, S250, S260‧‧

1 is a cross-sectional view of a memory cell of a flash memory device.

2 is a schematic diagram of a threshold voltage distribution of a memory cell.

3 is a schematic diagram showing an example in which the threshold voltage of the memory cell in FIG. 2 is lowered by an indeterminate level.

4 is a schematic diagram of a threshold voltage distribution of a 3-bit level memory cell.

Fig. 5 is a view showing an example in which the threshold voltage of the 3-bit memory cell is lowered in accordance with Fig. 4.

6 is a semiconductor memory device according to an embodiment of the invention. A block diagram of system 100.

7 is a schematic diagram of a method of detecting a threshold voltage of a memory cell M/C.

FIG. 8 is a block diagram of a semiconductor memory system 800 in accordance with an embodiment of the present invention.

FIG. 9 is a block diagram of a semiconductor memory system 300 in accordance with an embodiment of the present invention.

FIG. 10 is a block diagram of a semiconductor memory system 400 in accordance with an embodiment of the present invention.

11 is a flow chart of an access method of a semiconductor memory system according to FIG. 6 , FIG. 8 or FIG. 10 .

FIG. 12 is a flow chart of an access method of a memory system according to FIG. 6, FIG. 8, and FIG.

Figure 13 is a block diagram of a computer system having a semiconductor memory system, such as an electronic device, in accordance with an embodiment of the present invention.

100‧‧‧Semiconductor memory system

110‧‧‧Non-volatile memory device

120‧‧‧ memory controller

130‧‧‧ memory cell array

140‧‧‧ column selector

150‧‧‧Input/Output Circuit

160‧‧‧Control logic

170‧‧‧Voltage generator

180‧‧‧Adjustment circuit

190‧‧‧Power supply

Tr_cmd‧‧‧ adjustment instructions

BLK1~BLKn‧‧‧ memory block

M/C‧‧‧Monitor memory cells

Claims (20)

A semiconductor memory system comprising: a non-volatile memory comprising a plurality of memory cells connected to a plurality of word lines and one or more memory cells connected to at least one word line, the one or more memory cells And storing a monitoring data; and a memory controller for controlling the non-volatile memory, wherein the memory controller reads the monitoring data, and adjusts a bias voltage supplied to the plurality of memory cells according to the reading result thereof, Wherein, if the number of read errors is greater than a reference quantity, and the reference quantity is set to be less than the maximum number of read errors that can be corrected, the memory controller reads the monitoring data, and adjusts the monitoring data according to the read result. a bias voltage, wherein the monitoring data corresponds to the same single state of the plurality of threshold voltage states of the memory cell, wherein the memory controller detects the change of the threshold voltage of the same single state via the reading, And adjusting the bias voltage according to the detected change of the threshold voltage of the same single state, and wherein the plurality of word lines form a user area of the user data And the at least one word line system forming a storage region of the non-monitoring data of the user data. The semiconductor memory system of claim 1, wherein the memory controller reads the monitoring data and adjusts the bias voltage during a power-on time of the semiconductor memory system. The semiconductor memory system as described in claim 1 The memory cells are grouped into a plurality of blocks, and the monitoring data is included in the corresponding block. The semiconductor memory system of claim 3, wherein the memory controller reads the monitoring data corresponding to the block when reading data from the block. The semiconductor memory system of claim 3, wherein the memory controller stores the monitoring data in a blank of the block. The semiconductor memory system of claim 5, wherein the memory controller stores the monitoring data in a blank of the block having a minimum error rate. The semiconductor memory system of claim 1, wherein the memory controller stores the detection result of the monitoring data. The semiconductor memory system of claim 1, wherein the bias voltage is a read voltage. The semiconductor memory system of claim 1, wherein the monitoring data is data corresponding to an erased quantity of the plurality of memory cells. The semiconductor memory system of claim 9, wherein the memory controller detects the erase amount and adjusts the bias voltage according to the detection result. The semiconductor memory system of claim 1, wherein the memory controller detects a read error using an error correction code mechanism. The semiconductor memory system of claim 1, wherein the non-volatile memory comprises a plurality of pages for storing the user data, and at least one page for storing the monitoring data. A method for accessing a semiconductor memory system, comprising: storing monitoring data in one or more memory cells; reading the monitoring data; and adjusting a bias voltage supplied to the memory cell according to the reading result, wherein The read error generated in the memory cell exceeds a reference quantity, and the reference quantity is set to be less than the maximum number of read errors that can be corrected, and the monitoring data is read, wherein the monitoring data corresponds to the plurality of memory cells The same single state of the threshold voltage state, wherein the change in the threshold voltage of the same single state is obtained via the reading, and the bias voltage is adjusted according to the detected change in the threshold voltage of the same single state, and The multi-semiconductor memory system includes a user area including a memory cell connected to a plurality of word lines, configured to store user data, and a system area including a connection to the system area One or more memory cells of at least one word line configured to store the monitoring data other than the user data. For example, in the access method described in claim 13, when the user data is programmed to the memory cell, the monitoring data is stored. The access method of claim 13, wherein the reading of the monitoring data is performed at a power-on time. The access method of claim 13, wherein the memory cells are grouped into a plurality of blocks, and the monitoring data is included in the corresponding block. The access method of claim 16, wherein when the block is read, the monitoring data is read according to the block. The access method of claim 13, wherein the semiconductor memory system includes a plurality of pages for storing the user data, and at least one page for storing the monitoring data. An electronic device comprising: a semiconductor memory system comprising: a non-volatile memory comprising a plurality of memory cells connected to a plurality of word lines and one or more memory cells connected to at least one word line, One or more memory cells store monitoring data; and a memory controller that controls the non-volatile memory, the memory controller reads the monitoring data, and adjusts a bias supplied to the memory cell according to the reading result thereof And a processor for processing data read from the semiconductor memory system according to the adjusted bias voltage, wherein if the number of read errors is greater than a reference quantity, the reference quantity is set to be less than correctable When the maximum number of errors is read, the memory controller reads the monitoring data and adjusts the bias according to the reading result, wherein the monitoring data corresponds to the same single state of the plurality of threshold voltage states of the memory cell The memory controller detects the same single via the reading a change in the threshold voltage of the state, and adjusting the bias voltage according to the detected change in the threshold voltage of the same single state, and wherein the plurality of word lines form a user area of the user data, and the At least one word line forms a system area for storing the monitoring data other than the user data. The electronic device of claim 19, wherein the non-volatile memory comprises a plurality of pages for storing the user data, and at least one page for storing the monitoring data.