KR101905746B1 - Multi level memory apparatus and its data sensing method - Google Patents

Abstract

The present invention can provide a resistive memory device capable of efficiently and accurately detecting a wide range of current flowing in a memory cell.
The resistive memory device of the present invention comprises at least two current paths for passing current of different magnitudes; A resistive memory cell electrically connected to said at least two current paths; And a cell current replicating unit for replicating a cell current flowing in the resistive memory cell.

Description

[0001] MULTI LEVEL MEMORY APPARATUS AND ITS DATA SENSING METHOD [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a memory device including multi-level memory cells.

A conventional DRAM includes a memory cell composed of a capacitor, and stores data while charging or discharging the memory cell. However, since there is a leakage current due to the characteristics of the capacitor, the DRAM has a disadvantage that it is a volatile memory. In order to improve the disadvantages of the DRAM, memories which are nonvolatile and which do not require retention of data are being developed. In particular, attempts have been made to implement non-volatility by changing the memory cell structure, one of which is a resistive memory device comprising a resistive memory cell.

1 is a schematic view showing a configuration of a conventional resistive memory device. 1, a resistive memory device according to the prior art includes a memory cell 10 and a transistor N1. The memory cell 10 is composed of a resistive material whose resistance value changes according to temperature or current, and has different resistance values depending on stored data.

The transistor N1 provides a sensing current to sense the data stored in the memory cell 10. The transistor N1 controls the bias voltage VB to apply the power supply voltage VPPSA to the sensing node SAI.

A conventional resistive memory device senses data stored in the memory cell 11 by changing the voltage of the sensing node SAI. The transistor N1 is turned on when the bias voltage VB is applied, and is configured to provide a certain amount of current to the sensing node SAI. The current flowing through the sensing node SAI flows through the memory cell 10. [ Therefore, the voltage level of the sensing node SAI depends on the resistance value of the memory cell 10. [ That is, when the resistance value of the memory cell 10 is large, the voltage of the sensing node SAI has a high level, and when the resistance value of the memory cell 10 is small, the voltage of the sensing node SAI is low . As described above, the conventional resistive memory device provides a constant current to the sensing node SAI, and is applied to the memory cell 10 using a change in the voltage level of the sensing node SAI according to the resistance value of the memory cell 10. [ Sensing the stored data.

In addition, the step-up voltage VPPSA is used as the power supply voltage to reliably detect the voltage level change of the sensing node SAI according to the resistance value of the memory cell 10. [ The step-up voltage VPPSA can be generated through a pumping circuit or the like at a voltage generally higher than the external power supply level.

The present invention can provide a multilevel memory device capable of efficiently detecting a wide range of currents flowing through a memory cell and a method of data sensing thereof.

In addition, the present invention can provide a multilevel memory device and a method of sensing the data, which can accurately detect a wide range of current flowing in a memory cell.

In addition, the present invention can provide a multilevel memory device capable of quickly detecting multilevel data stored in a memory cell and a method of sensing the data.

The multilevel memory device of the present invention includes at least two current paths for passing current of different magnitudes; A memory cell electrically connected to the at least two current paths; And a cell current replica unit for replicating a cell current flowing in the memory cell.

In addition, the cell current replica section may be coupled with the current mirror type with the at least two or more current paths.

The at least two current paths may include a first current driver capable of passing a first range of the cell current; And a second current driver capable of passing a second range out of the first range of the cell current.

The cell current replica unit may pass a current having the same magnitude as the first current driver.

Comparison means for comparing a cell replica current flowing through the cell current replica portion with a comparison replica current; A data output unit for converting and outputting a comparison signal output from the comparison unit; A comparison current output unit for outputting a comparison current by using a comparison signal output from the data output unit; And a comparison current replicating unit for replicating the comparison current and outputting the comparison replication current.

The comparison means may be configured to compare the cell replica current and the comparison replica current with each other to amplify a potential difference between a first node on a path through which the cell replica current flows and a second node on a path through which the comparison replication current flows, A comparator; And a second comparator for comparing the first node and the second node as inputs.

Further, the multilevel memory device of the present invention includes: a cell current replicating unit for replicating a cell current flowing in a memory cell; Comparison means for comparing a cell replication current flowing through the cell current duplication section with a comparison replication current; A data output unit for converting and outputting a comparison signal output from the comparison unit; A comparison current output unit for outputting a comparison current by using a comparison signal output from the data output unit; And a comparison current replica unit for replicating the comparison current to output the comparison replica current.

According to another aspect of the present invention, there is provided a method of sensing data in a multi-level memory device, comprising: flowing a cell current through a memory cell connected to the current path by selecting one of at least two current paths for passing a current having a different magnitude; Setting a comparison current for comparing the cell current to a predetermined value; If the cell current is greater than the predetermined value, replicating the same size as the cell current; And amplifying and replicating the cell current by a predetermined multiple if the cell current is less than the predetermined value.

Generating a cell replication current by replicating the cell current; Replicating the comparison current to output a comparison replication current; Comparing the cell replication current with the comparison replication current and outputting a comparison signal; And temporarily storing and digitally outputting the comparison signal.

According to the present invention, it is possible to maximize the amount of data that can be stored in a memory cell by accurately detecting a wide range of current according to the resistance value change of the memory cell, and does not require a high power supply voltage.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 schematically shows the construction of a resistive memory device according to the prior art; FIG.
2 is a main configuration diagram of a multi-level memory device according to an embodiment of the present invention,
3 is a graph of the operation of a multi-level memory device according to an embodiment of the present invention,
4 is a block diagram of a multi-level memory device according to another embodiment of the present invention;
5 is a flowchart illustrating an operation of a multi-level memory device according to an exemplary embodiment of the present invention,
6 is a current DAC configuration diagram of a multi-level memory device according to an embodiment of the present invention, and
7 is a current DAC configuration diagram of a multi-level memory device according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms, and the inventor should appropriately interpret the concepts of the terms appropriately It should be interpreted in accordance with the meaning and concept consistent with the technical idea of the present invention based on the principle that it can be defined. Therefore, the embodiments described in this specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and do not represent all the technical ideas of the present invention. Therefore, It is to be understood that equivalents and modifications are possible.

A multi-level memory, for example, a resistive memory, may have various resistance values depending on device characteristics, so various data can be stored in one memory cell instead of binary data. For example, in the case of PCRAM, current can flow in a memory cell in a range of at least 100 nanoamperes (nA) up to 15 microamperes (uA). That is, since the difference between the minimum current and the maximum current flowing in the memory cell is too large, if the size of the switching element used for detecting the current flowing in the memory cell is designed to be the minimum current, the maximum current is prevented from flowing, By design, the switching element will be in a weak inversion state when the minimum current flows. On the other hand, if the switching element is placed in the wicked version state, the current flowing in the switching element can not be accurately copied.

Therefore, according to the present invention, the current flowing in the memory cell can be accurately copied by diversifying the current path through the memory cell.

FIG. 2 is a main configuration diagram of a multi-level memory device according to an embodiment of the present invention, which includes a memory cell 10, a detection voltage generation unit 20, and a cell current copy unit 31.

The detection voltage generator 20 amplifies the difference between the reference voltage VREF and the sensing node voltage VSAI and provides a voltage of a constant level to the sensing node VSAI. The memory cell 10 is connected to the sensing node VSAI and the amount of current flowing to the sensing node VSAI changes depending on the resistance value of the memory cell 10. [ That is, the amount of current flowing to the sensing node VSAI when the resistance value of the memory cell 10 is small is larger than the amount of current flowing to the sensing node VSAI when the resistance value of the memory cell 10 is large.

A multilevel memory device according to an embodiment of the present invention that senses a change in current has a variety of advantages.

First, since the multilevel memory device according to the present invention senses a change in current, it is not necessary to provide a wide range of voltages to the memory cell 10, so there is no need to provide a high level voltage. A conventional resistive memory device requires a threshold or reference value that can change the voltage of the sensing node SAI according to the resistance value of the memory cell 10 and sense the voltage change. Therefore, it is necessary to provide a wide range of voltages to discriminate between the high resistance state and the low resistance state of the memory cell. Therefore, the conventional resistive memory device needs to supply the boost voltage VPPSA by pumping the power supply voltage as shown in Fig. However, since the multilevel memory device according to the embodiment of the present invention does not require a voltage threshold, there is no need to form a wide range of voltage, and it is sufficient to apply the external voltage VDD at the power source voltage as shown in FIG. 2 . Therefore, the current consumption due to the use of the boosted voltage is reduced, and the circuit for generating a high voltage can be eliminated.

Also, the sensing time of data stored in the memory cell 10 is shortened due to the characteristic of sensing a current change. That is, it enables fast data sensing. Further, an unnecessary element such as a conventional clamping switch can be removed by employing an improved structure that provides a certain level of voltage to the sensing node (VSAI).

The detection voltage generator 20 according to an embodiment of the present invention includes a comparator 21 and a plurality of drivers 23 and 25. The comparator 21 amplifies the difference between the reference voltage VREF and the sensing node voltage VSAI to generate the amplified signal AMP and makes the voltage level of the sensing node VSAI equal to the level of the reference voltage VREF The level of the amplified signal AMP is gradually lowered. Here, the reference voltage VREF may be, for example, half of the power supply voltage VDD.

Thereafter, in response to the amplified signal AMP, the sensing node VSAI is gradually and strongly driven to the power supply voltage VDD level. And increases the magnitude of the voltage supplied to the sensing node VSAI according to the amplified signal AMP descending from the driving units 23 and 25. [ When the levels of the reference voltage VREF and the sensing node voltage VSAI become equal to each other, the driving units 23 and 25 fix the level of the sensing node voltage VSAI. The memory cell 10 receives a voltage of a certain level and changes the magnitude of the current flowing to the sensing node VSAI according to the resistance value.

On the other hand, when the resistance value of the memory cell 10 is small and the current is large, the first switch SW1 of the plurality of drivers 23 and 25 is turned on to operate the strong current driver 23, And the second switch SW2 is turned on to operate the weak current driving part 25. In this case, For example, if the current flowing through the memory cell is 1.2 to 15 microamperes (uA), the strong current driver 23 is operated, and if the current flowing through the memory cell is between 100 nanoamperes (nA) and 1.2 microamperes (uA), the weak current driver 25 is operated.

For this purpose, the strong current driver 23 may have the ability to pass a current of several to several tens of times that of the weak current driver 25. According to an embodiment of the present invention, the weak current driver 25 is implemented by one switching device (e.g., FET), and the strong current driver 23 may be connected in parallel with twelve switching devices of the same size. According to another embodiment of the present invention, the weak current driving unit 25 and the strong current driving unit 23 are implemented as one switching device, while the switching device of the strong current driving unit 23 is implemented by the weak current driving unit 25 Of the switching element of the first embodiment.

The cell current replica unit 31 according to an embodiment of the present invention is constructed and arranged to have the same size as that of the strong current driver 23 and has a cell current Icell ) To flow the cell replication current (Icell_copy).

FIG. 3 is a graph illustrating the operation of a multi-level memory device according to an embodiment of the present invention. When the current flowing in the memory cell 10 is 1.2 to 15 microamperes (uA) A cell replica current (Icell_copy) of 1.2 to 15 microamperes (uA) having the same size as that of the strong current driver 23 is output from the cell current replica 31 as a current mirror. If the current Icell flowing through the memory cell 10 is in the range of 100 nA to 1.2 A, the weak current driving unit 25 is operated. However, the cell current replica unit 31, which is a current mirror, The switching element of the current drive unit 23 has a current amplification capability of 12 times as compared with the weak current driving unit 23 so that the level of the cell replica current Icell_copy is set to 1.2 to 15 microamperes uA, Shift the output. Here, the amplifying operation on the linear scale is the same as the level shifting operation on the log scale.

4 is a block diagram of a multilevel memory device according to another embodiment of the present invention. The memory cell 10, the detection voltage generator 20, the current duplicator 30, the first comparator 40, A comparison unit 50, a data output unit 60, and a comparison current output unit 70.

The memory cell 10 and the detection voltage generation unit 20 are the same as those in Fig. The current duplication unit 30 includes a cell current duplication unit 31 and a comparison current duplication unit 33. [ The cell current replica section 31 replicates the cell current Icell flowing through the driving sections 23 and 25 to flow the cell replica current Icell_copy and the comparison current replica section 33 replaces the cell current Icell with the comparison current output section 70 And the comparative replica current Icomp_copy is passed.

The first comparator 40 is connected between the node 31 (N31) and the node 33 (N33) and is controlled by the reset signal RESET to reset the potential of the node 31 (N31) and the node 33 And a positive feedback section 43 for comparing the difference between the output voltages at both ends of the current replica section 30 in a positive feedback manner. Specifically, when the switching element of the reset section 41 is turned on and reset, the node 31 (N31) and the node 33 (N33) are at the same potential. When the reset section 41 is turned off, And the voltage of the node 33 (N33) are applied to the switching elements 431 and 432 in the positive feedback section 43, respectively.

The positive feedback section 43 includes a switching element 431 connected between the node 31 (N31) and ground and controlled by the voltage of the node 33 (N33), a node 43 connected between the node 33 (N33) And a switching element 432 controlled by the voltage of the node N31. The positive feedback section 43 compares the voltage of the node 31 (N31) with the voltage of the node 33 (N33) by a positive feedback method. For example, the cell replica current Icell_copy flowing from the node 31 (N31) The voltage VN31 of the node 31 (N31) becomes lower than the voltage (VN33) of the node 33 (N33) if the comparison replication current Icomp_copy flowing from the node N33 (N33) to the ground side is larger. The voltage VN31 of the lowered node 31 (N31) is applied to the control voltage of the switching device 432 disposed between the node 33 (N33) and the ground, so that the switching device 432 is close to the turn-off state. On the other hand, the voltage VN33 of the node 33 (N33) increased is applied to the control voltage of the switching device 431 disposed between the node 31 (N31) and the ground, so that the switching device 431 is close to the turn-on state. In this way, the switching elements 431 and 432 in the positive feedback section 43 gradually become open in the positive direction.

The second comparator 50 compares the voltage VN31 of the node 31 (N31) with the voltage VN33 of the node 33 (N33) and outputs "H" or "L".

The data output unit 60 receives the output of the second comparison unit 50 and temporarily stores the digital data and outputs the digital comparison signal output from the digital data output unit 61 and the digital data output unit 61 And a D / A converter 63 for converting the signal into an analog comparison signal.

According to an embodiment of the present invention, the digital data output unit 61 may be implemented as a 5-bit register, and the D / A converter 63 may be implemented by a 4-bit D / A converter. That is, if the digital data output section 61 is an N-bit register, the D / A converter can be implemented as an (N-1) bit D / A converter. Here, the D / A converter 63 may be configured to correspond to the current change characteristic according to the data value of the memory cell 10. [ For example, if the cell current exponentially increases or decreases as the data value of the memory cell sequentially increases or decreases, the output of the D / A converter 63 can also increase or decrease exponentially. According to another embodiment of the present invention, if the cell current linearly increases or decreases as the data value of the memory cell 10 sequentially increases or decreases, the output of the D / A converter 63 also increases or decreases linearly .

The comparison current output section 70 is arranged in the same manner as the switching elements of the same size as the comparison current replicating section 33 and increases or decreases the magnitude of the comparison current Icomp according to the output of the D / A converter 63.

5 is a flowchart illustrating an operation of a multi-level memory device according to an exemplary embodiment of the present invention.

The cell current Icell is supplied to the memory cell 10 by turning on the second switch SW2 of the weak current driving unit and the cell current replica unit 31 replicates the cell current Icell flowing in the memory cell, (Icell_copy) to the cell N31. The 5-bit register outputs "0000" (S510) by turning on the switching element of the reset unit 41 and resetting the voltages of the node 31 and the node 33 to the same potential in accordance with the reset signal RESET.

When the switching element of the reset section 41 is turned off and the D / A converter 63 receives the value "0000" output from the 5-bit register and outputs a comparison current Icomp of 1.2 microamperes (uA) The comparison current replica section 33 outputs a comparison replica current Icomp_copy of 1.2 microamperes (uA) replicating the comparison current Icomp, and the first comparison section 40 and the second comparison section 50 output the comparison current Icomp_copy The first bit (MSB) of the 5-bit register is determined by comparing the copy current Icell_copy with the comparison current Icomp_copy of 1.2 microamperes (uA) (S520).

If the cell replica current Icell_copy is greater than 1.2 microamperes (uA) compare replica current Icomp_copy, the first switching device SW1 of the strong current driver 23 is turned on and the 5 bit register is set to "1000" And outputs a comparison current (Icomp) of 4.3 microamperes (uA). On the other hand, when the cell replica current Icell_copy is smaller than the comparative replica current Icomp_copy, the second switching device SW2 of the weak current driver 25 is turned on, so that the cell current Icell becomes 100 nanoamperes (nA) The cell replica current Icell_copy is from 1.2 microamperes (uA) to 15 microamperes (uA) (S530) even when the cell current is less than the microamperes (uA). Here, if the output of the 5-bit register is "0000", the comparison current Icomp is 1.2 microamperes (uA). If the output of the 5-bit register is "1000", the comparison current Icomp is 4.3 microamperes What is changed is to apply a statistical technique to find the target value in the shortest time. In addition, the 4.3 microampere is a median value between 1.2 and 15 on the logarithmic scale.

The register 61 determines the next bit in step S540 and controls the output of the D / A converter 63 in step S550. If the total number of decision bits is equal to the number of bits in the register in step S560, (S570).

FIG. 6A is a current DAC configuration diagram of a multi-level memory device according to an embodiment of the present invention, and FIG. 6B is a graph of an output current versus an exponentially changing binary code.

The current D / A converter of the multi-level memory device according to an embodiment of the present invention is characterized in that when the cell current of the resistive memory cell changes non-linearly, for example, exponentially, A decoder 631 for decoding the output of the register and a plurality of unit current cells 633 connected in parallel controlled according to the output of the decoder 631.

For example, when the output of the register is "0000 ", the unit current cells in the D / A converter are turned on so that 3 * I flows and when the output of the register is & And the unit output cell in the D / A converter is turned on so that 32 * I flows when the output of the register is "1111 ". Here, the current IDAC means the comparison replica current Icomp_copy.

FIG. 7A is a current DAC configuration diagram of a multi-level memory device according to another embodiment of the present invention, and FIG. 7B is a graph of output current versus a linearly changing binary code.

The current D / A converter of the multilevel memory device according to an embodiment of the present invention is configured to linearly change the comparison current for comparing the cell current of the resistive memory cell when the cell current changes linearly. And a plurality of unit current cells 633 connected in parallel controlled in accordance with the output of the decoder 631. [

For example, when the output of the register is "0000 ", the unit current cell in the D / A converter is turned on so that I flows, and when the output of the register is" 0001 & And when the output of the register is "1111 ", the unit current cell in the D / A converter is turned on so that 16 * I flows.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It is to be understood that various changes and modifications may be made without departing from the scope of the appended claims.

10: memory cell 20: detection voltage generating unit
21: comparator 23:
25: weak current drive unit 30: current replica unit
31: cell current replica unit 33: comparison current replica unit
40: first comparison unit 41: reset unit
43, 45: positive feedback section 50: second comparing section
60: Data output unit 61: Digital data output unit
63: D / A converter 70: comparison current output section
Icell: cell current Icell_copy: cell replication current
Icomp: Comparison current Icomp_copy: Comparison replication current

Claims (29)

At least two current paths for passing currents of different sizes;
A memory cell electrically connected to the at least two current paths; And
A cell current replica unit for replicating a cell current flowing in the memory cell;
Comparison means for comparing a cell replication current flowing through the cell current duplication section with a comparison replication current;
A data output unit for converting and outputting a comparison signal output from the comparison unit;
A comparison current output unit for outputting a comparison current by using a comparison signal output from the data output unit; And
A comparative current replica unit for replicating the comparison current and outputting the comparison replica current,
/ RTI > The method according to claim 1,
Wherein the cell current replica portion is coupled in a current mirror type to the at least two or more current paths. The method of claim 1, wherein the at least two current paths comprise:
A first current driver capable of passing a first range of the cell current; And
And a second current driver capable of passing a second range out of the first range of the cell current,
/ RTI > The method of claim 3,
Wherein the cell current replica unit is capable of passing a current of the same magnitude as that of the first current driver. delete 2. The apparatus according to claim 1,
A first comparator for amplifying a potential difference between a first node on a path through which the cell replication current flows and a second node on a path through which the comparison replication current flows using the cell replication current and the comparison replication current; And
And a second comparison unit for comparing the first node and the second node,
/ RTI > 7. The apparatus of claim 6,
A reset unit coupled between the first node and the second node, the reset unit being controlled by a reset signal to match the potentials of the first and second nodes; And
A positive feedback section for amplifying the potential difference between the first node and the second node by a positive feedback method,
/ RTI > 8. The apparatus of claim 7, wherein the positive feedback section comprises:
A first switching element connected between the first node and ground, the first switching element being controlled by the voltage of the second node; And
A second switching element coupled between the second node and ground, the second switching element being controlled by a voltage at the first node,
/ RTI > The data output apparatus according to claim 1,
A storage unit for temporarily storing a comparison signal output from the comparison unit; And
And a conversion unit for outputting the digital comparison signal output from the storage unit as an analog comparison signal,
/ RTI > 10. The method of claim 9,
Wherein the storage unit is an N-bit register. 11. The method of claim 10,
Wherein the converting unit is a (N-1) bit digital / analog converter. 12. The method of claim 11,
Wherein the conversion unit is configured to correspond to a current change characteristic according to a data value of the memory cell. 12. The method of claim 11,
And the output of the conversion unit can be increased or decreased exponentially. 12. The method of claim 11,
And the output of the conversion unit can be linearly increased or decreased. 12. The image processing apparatus according to claim 11,
A decoder for decoding the output of the storage unit; And
A plurality of unit current cells connected in parallel controlled according to an output of the decoder;
/ RTI > A cell current replicating unit for replicating a cell current flowing in the memory cell;
Comparison means for comparing a cell replication current flowing through the cell current duplication section with a comparison replication current;
A data output unit for converting and outputting a comparison signal output from the comparison unit;
A comparison current output unit for outputting a comparison current by using a comparison signal output from the data output unit; And
A comparative current replica unit for replicating the comparison current and outputting the comparison replica current,
/ RTI > 17. The apparatus according to claim 16,
A first comparator for amplifying a potential difference between a first node on a path through which the cell replication current flows and a second node on a path through which the comparison replication current flows using the cell replication current and the comparison replication current; And
And a second comparison unit for comparing the first node and the second node,
/ RTI > 18. The apparatus of claim 17,
A reset unit coupled between the first node and the second node, the reset unit being controlled by a reset signal to match the potentials of the first and second nodes; And
A positive feedback section for amplifying the potential difference between the first node and the second node by a positive feedback method,
/ RTI > 19. The image pickup apparatus according to claim 18,
A first switching element connected between the first node and ground, the first switching element being controlled by the voltage of the second node; And
A second switching element coupled between the second node and ground, the second switching element being controlled by a voltage at the first node,
/ RTI > The data output apparatus according to claim 16,
A storage unit for temporarily storing a comparison signal output from the comparison unit; And
And a conversion unit for outputting the digital comparison signal output from the storage unit as an analog comparison signal,
/ RTI > 21. The method of claim 20,
Wherein the storage unit is an N-bit register. 22. The method of claim 21,
Wherein the converting unit is a (N-1) bit digital / analog converter. 23. The method of claim 22,
Wherein the conversion unit is configured to correspond to a current change characteristic according to a data value of the memory cell. 23. The method of claim 22,
And the output of the conversion unit can be increased or decreased exponentially. 23. The method of claim 22,
And the output of the conversion unit can be linearly increased or decreased. 23. The apparatus according to claim 22,
A decoder for decoding the output of the storage unit; And
A plurality of unit current cells connected in parallel controlled according to an output of the decoder;
/ RTI > Selecting one of at least two current paths for passing current of different magnitudes and flowing a cell current to a memory cell connected to the current path;
Setting a comparison current for comparing the cell current to a predetermined value;
If the cell current is greater than the predetermined value, replicating the same size as the cell current; And
If the cell current is smaller than the predetermined value, amplifying and replicating the cell current by a predetermined multiple
Wherein the data sensing method comprises the steps of: 28. The method of claim 27,
Replicating the cell current to output a cell replica current;
Replicating the comparison current to output a comparison replication current;
Comparing the cell replication current with the comparison replication current and outputting a comparison signal; And
Temporarily storing the comparison signal and digitally outputting the comparison signal
Further comprising the steps of: 29. The method of claim 28,
Wherein the comparison replica current corresponds to a current change characteristic according to a data value of the memory cell.

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