KR20140080944A - Non-volatile memory apparatus - Google Patents

Non-volatile memory apparatus Download PDF

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Publication number
KR20140080944A
KR20140080944A KR1020120150161A KR20120150161A KR20140080944A KR 20140080944 A KR20140080944 A KR 20140080944A KR 1020120150161 A KR1020120150161 A KR 1020120150161A KR 20120150161 A KR20120150161 A KR 20120150161A KR 20140080944 A KR20140080944 A KR 20140080944A
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South Korea
Prior art keywords
voltage
current
signal
sensing node
memory cell
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KR1020120150161A
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Korean (ko)
Inventor
박철현
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에스케이하이닉스 주식회사
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Priority to KR1020120150161A priority Critical patent/KR20140080944A/en
Priority to US13/921,305 priority patent/US20140177319A1/en
Publication of KR20140080944A publication Critical patent/KR20140080944A/en
Priority to US14/797,247 priority patent/US9583186B2/en
Priority to US15/402,984 priority patent/US20170125094A1/en
Priority to US15/402,565 priority patent/US20170125093A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode

Abstract

The nonvolatile memory device includes a voltage generating section, a memory cell, a current replicating section, and a data output section. The voltage generator receives the read voltage and the voltage of the sensing node and provides a voltage of a certain level to the sensing node. The memory cell receives the constant level voltage from the sensing node. The current replica generates a replica current of substantially the same magnitude as the sensing current flowing through the memory cell. The data output unit senses the replica current to generate a plurality of data output signals.

Description

[0001] NON-VOLATILE MEMORY APPARATUS [0002]

The present invention relates to semiconductor devices, and more particularly, to a memory device including non-volatile memory cells.

A conventional DRAM includes a memory cell composed of a capacitor, and stores data while charging or discharging the memory cell. However, since there is a leakage current due to the characteristics of the capacitor, the DRAM has a disadvantage that it is a volatile memory. In order to improve the disadvantages of the DRAM, memories which are nonvolatile and which do not require retention of data have been developed. In particular, attempts have been made to implement non-volatility by changing the memory cell structure, one of which is a resistive memory device comprising a resistive memory cell. The resistive memory device may store multi-level data according to the resistance distribution of the resistive memory cells.

1 is a schematic view showing a configuration of a nonvolatile memory device 10 according to the prior art. 1, a conventional resistive memory device includes a memory cell 11, first through fourth transistors N1, N2, N3, and N4, and a sense amplifier 12. In FIG. The memory cell 11 is made of a resistive material whose resistance value changes according to a temperature or a current, and has a different resistance value according to stored data. The memory cell 11 stores multi-level data.

The first transistor (N1) provides a sensing current to sense data stored in the memory cell (11). The first transistor N1 receives the bias voltage VB and applies a high voltage VPPSA to the sensing node SAI. The second transistor N2 is turned on in response to the bit line select signal BLS to select a bit line for data access. The third transistor N3 is turned on in response to the clamping signal VCLAMP and controls the voltage applied to the memory cell 11 so as not to exceed the threshold value. The fourth transistor N4 is turned on in response to the word line select signal WLS, and selects a word line to which data access is to be performed.

The sense amplifier 12 is connected to the sensing node SAI and receives a sensing voltage VSEN from the sensing node SAI. The sense amplifier 12 compares the sensing voltage VSEN with the first to third reference voltages REF1, REF2 and REF3 to generate a data output signal DOUT.

A conventional non-volatile memory device 10 senses data stored in the memory cell 11 by changing the voltage level of the sensing node SAI. The first transistor N1 is turned on when a bias voltage VB is applied, and is configured to provide a predetermined amount of current to the sensing node SAI. The current flows through the memory cell (11). Therefore, the voltage level of the sensing node SAI depends on the resistance value of the memory cell 11. That is, when the resistance value of the memory cell 11 is large, the voltage of the sensing node SAI is at a high level. When the resistance value of the memory cell 11 is small, the voltage of the sensing node SAI is low Level. As described above, the conventional nonvolatile memory device provides a constant current to the sensing node SAI, detects a change in the voltage level of the sensing node SAI according to the resistance value of the memory cell 11, ). ≪ / RTI >

Also, a high voltage (VPPSA) is used as a power supply voltage to accurately detect the voltage level change of the sensing node SAI according to the resistance value of the memory cell 11. [ The high voltage VPPSA may be generated through a pumping circuit or the like at a voltage generally higher than the external power supply level.

Since the data stored in the memory cell 11 is multilevel data, the sense amplifier 12 essentially requires a plurality of reference voltages to sense the data stored in the memory cell 11. [ That is, when the memory cell stores 2-bit data, a total of three reference voltages are required to divide the data into 00, 01, 10, and 11.

Embodiments of the present invention provide a nonvolatile memory device capable of efficiently performing data sensing by sensing a current that varies according to data stored in a memory cell.

Embodiments of the present invention also provide a non-volatile memory device capable of receiving a sensing current from a memory cell storing multi-level data and outputting data stored in the memory cell as a digital signal.

A nonvolatile memory device according to an embodiment of the present invention includes a voltage generator receiving a read voltage and a voltage of a sensing node and providing a voltage of a predetermined level to the sensing node; A memory cell receiving the constant level voltage from the sensing node; A current replica unit for generating a replica current of substantially the same magnitude as the sensing current flowing through the memory cell; And a data output unit for generating a plurality of data output signals by sensing the replica current.

According to another aspect of the present invention, there is provided a nonvolatile memory device including: a voltage generator receiving a read voltage and a voltage of a sensing node to provide a predetermined level of voltage to the sensing node; A memory cell having one end connected to the sensing node; And a data output unit coupled to the other end of the memory cell and receiving a sensing current flowing through the memory cell to generate a plurality of data output signals.

Embodiments of the present invention detect currents that vary in accordance with data stored in memory cells, thus increasing the sensing speed and eliminating the need for high level voltages for data read operations. Also, it does not require a large number of reference voltages to sense multilevel data. Thus, the operating speed of the memory device can be increased, the current consumption can be reduced, and the circuit area can be improved.

1 is a view showing a configuration of a nonvolatile memory device according to the related art,
2 is a diagram illustrating a configuration of a nonvolatile memory device according to an embodiment of the present invention;
FIG. 3 is a block diagram schematically showing a configuration of an embodiment of the digital signal generator of FIG. 2;
FIG. 4 is a diagram illustrating the configuration of an embodiment of the 1-bit ADC of FIG. 3;
5 is a diagram illustrating a configuration of a nonvolatile memory device according to another embodiment of the present invention.

2 is a diagram showing a configuration of a nonvolatile memory device 1 according to an embodiment of the present invention. 2, the nonvolatile memory device 1 includes a voltage generating unit 110, a memory cell 120, a current replicating unit 130, and a data output unit 140. The voltage generator 110 provides a voltage VC of a predetermined level to the sensing node SAI in response to the read voltage VRD and the voltage of the sensing node SAI.

The memory cell 120 is connected to the sensing node SAI. The memory cell 120 receives a certain level of voltage VC from the sensing node SAI. When the memory cell 120 receives the voltage VC of a certain level, a sensing current ISEN flows according to the resistance value of the memory cell 120. That is, the amount of the sensing current ISEN changes according to the resistance value of the memory cell 120. The amount of the sensing current ISEN when the resistance value of the memory cell 120 is small is greater than the amount of the sensing current ISEN when the resistance value of the memory cell 120 is large. The memory cell 120 may store a plurality of bits of data, i.e., multi-level data.

The current replica 130 generates a replica current ICOPY having substantially the same magnitude as the sensing current ISEN. The data output unit 140 senses the copy current ICOPY and generates a data output signal DOUT of a plurality of bits. The data output unit 140 senses the copy current ICOPY and provides a digital signal of a plurality of bits to the data output signal DOUT. Therefore, the data output unit 140 may output the sensing current ISEN flowing through the memory cell 120 and the multi-level data having a plurality of bits from the replica current ICOPY.

The nonvolatile memory device 10 according to the prior art shown in FIG. 1 fixes a current flowing to the sensing node SAI and controls the voltage level of the sensing node SAI according to the resistance value of the memory cell 11. [ And sensing a change in the voltage level to sense data. 2, the nonvolatile memory device 1 maintains the sensing node SAI at a constant voltage level, and the sensing node SAI is maintained at a constant voltage level, And has a structure that changes the amount of current flowing in the node SAI and senses the change of the current to sense data.

The nonvolatile memory device 1 according to an embodiment of the present invention for sensing a change in current has various advantages. First, the nonvolatile memory device 1 does not need to provide a wide voltage range to the memory cell 120 because it senses a change in current, and thus does not need to provide a high level voltage. The conventional nonvolatile memory device 10 needs a threshold or reference value capable of changing the voltage of the sensing node SAI according to the resistance value of the memory cell 11 and sensing the voltage change. Therefore, it is necessary to provide a wide range of voltages so as to discriminate between the high resistance state and the low resistance state of the memory cell. Therefore, it can be seen that the conventional nonvolatile memory device 10 pumped the power supply voltage as shown in FIG. 1 to provide a high voltage VPPSA. However, since the non-volatile memory device 1 according to the embodiment of the present invention does not require the voltage threshold value as described above, there is no need to form a wide range of voltages, Is sufficient. Therefore, current consumption due to use of a high voltage is reduced, and a circuit for generating a high voltage can be eliminated.

Also, the sensing time of data stored in the memory cell 120 is shortened due to the characteristic of sensing a current change. That is, it enables fast data sensing. In addition, an unnecessary element such as a conventional clamping switch can be removed by employing an improved structure that provides a certain level of voltage (VC) to the sensing node (SAI).

In the embodiment of the present invention, the data output unit 140 can generate the data output signal DOUT of a plurality of bits by sensing the copy current ICOPY, And does not require a reference voltage for sensing data.

2, the voltage generating unit 110 includes a comparator 111 and a driver unit 112. [ The comparator 111 compares the level of the read voltage VRD with the voltage level of the sensing node SAI to generate a comparison signal COM. The read voltage VRD is a voltage that can be biased for data sensing. Meanwhile, the voltage generator 110 may be enabled in response to a sensing enable signal SEN. The sensing enable signal SEN may be generated from a read command. The read command includes all read commands for data output such as a normal read command, a verify read command, and the like. The driver unit 112 provides the voltage having the predetermined level to the sensing node SAI in response to the comparison signal COM. The driver unit 112 includes a first transistor M1. In FIG. 2, the first transistor M1 is exemplified as a PMOS transistor, but the present invention is not limited thereto. The first transistor M1 receives the comparison signal COM as a gate and receives the power supply voltage VDD as a source and a drain thereof is connected to the sensing node SAI.

The comparator 111 gradually decreases the level of the comparison signal COM until the voltage level of the sensing node SAI becomes equal to the level of the read voltage VRD. The driver unit 112 gradually drives the sensing node SAI to the power supply voltage VDD level in response to the comparison signal COM. The driver unit 112 increases the voltage supplied to the sensing node SAI according to the falling comparison signal COM. When the level of the read voltage VRD becomes equal to the voltage level of the sensing node SAI, the driver unit 112 maintains the voltage level of the sensing node SAI. The memory cell 120 receives the voltage VC at a predetermined level and changes the amount of the sensing current ISEN according to the resistance value of the memory cell 120. [

The change of the sensing current ISEN changes the gate voltage level of the first transistor M1, that is, the level of the comparison signal COM. Therefore, the sensing voltage generator 110 provides a voltage VC of a predetermined level to the sensing node SAI, and the magnitude of the sensing current ISEN varies depending on the resistance value of the memory cell 120. For example, .

In FIG. 2, the current replica 130 may generate the replica current ICOPY in response to the comparison signal COM. The current replica 130 includes a second transistor M2. The second transistor M2 is preferably a transistor of the same type and size as the first transistor M1 constituting the driver unit 112. [ The second transistor M2 receives the comparison signal COM as a gate, receives the power supply voltage VDD as a source, and outputs the replica current ICOPY as a drain.

The data output unit 140 includes a linear conversion unit 141 and a digital signal generation unit 142. The linear converter 141 receives the replica current ICOPY to generate a current amplified signal IAMP. Since the sensing current ISEN and the replica current ICOPY are inversely proportional to the resistance value of the memory cell 120, the magnitude of the sensing current ISEN and the replica current ICOPY change to a log scale . Therefore, the linear converter 141 converts the replica current ICOPY having the logarithmic scale into the current amplified signal IAMP having a linear scale to accurately detect the change in the replica current ICOPY, . The linear converter 141 may be implemented as a log-linear converter.

The digital signal generation unit 142 receives the current amplified signal IAMP and generates a data output signal DOUT of a plurality of bits. The digital signal generation unit 142 may convert the current amplified signal IAMP into a digital code signal having a plurality of bits and generate a plurality of data output signals DOUT based on the digital code signal.

In FIG. 2, the nonvolatile memory device 1 may further include a column switch 150 and / or a row switch 160. The column switch 150 connects the memory cell 120 and the sensing node SAI in response to a bit line selection signal BLS. The row switch 160 is connected to a word line and forms a current path through the memory cell 120. That is, the row switch 160 connects the memory cell 120 to the ground voltage VSS in response to the word line select signal WLS.

In FIG. 2, the nonvolatile memory device may further include a precharge section 170. The precharge section 170 provides a precharge voltage VPCG to the sensing node SAI in response to a precharge signal PCG. The precharge voltage VPCG may be any voltage that is equal to or less than the level of the read voltage VRD. The precharge section 170 provides the precharge voltage VPCG to the sensing node SAI when the precharge signal PCG is enabled to raise the voltage level of the sensing node SAI. When the sensing node VSAI receives the precharge voltage VPCG by the precharge section 213 before the comparator 111 compares the reference voltage VREF with the voltage level of the sensing node VSAI, Level, a faster sensing operation can be supported. That is, the comparator 111 compares the voltage of the sensing node SAI raised by the precharge voltage VPCG with the read voltage VRD, so that the voltage of the sensing node SAI is lower than the voltage The time required for the driver unit 112 to be equal to the level of the voltage VRD is shortened and the point at which the driver unit 112 supplies the voltage VC having a constant level to the sensing node SAI is accelerated.

FIG. 3 is a block diagram schematically showing the configuration of an embodiment of the digital signal generating unit 142 of FIG. 3, the digital signal generation unit 142 includes a plurality of 1-bit analog-to-digital converters (hereinafter, referred to as 1-bit ADCs 311-316) and an output unit 320. In FIG. 3, six 1-bit ADCs 311-316 are illustrated to produce a 6-bit digital code signal (DC <0: 5>). The first to sixth 1-bit ADCs 311 to 316 are serially connected in series, and the first 1-bit ADC 311 receives the current amplification signal IAMP. The first 1-bit ADC 311 generates a first digital output DC <0> and a first analog output Aout1 from the current amplified signal IAMP, 2 1-bit ADC 312, and the first digital output DC <0> is input to the output unit 320. The second to sixth 1-bit ADCs 312-316 also output the respective analog outputs Aout2-Aout5 to the next stage 1-bit ADC, and each of the digital outputs DC <2: 5> (320). Thus, the first to sixth 1-bit ADCs 311-316 form a digital output with six bits (DC <0: 5>) of the digital code signal.

The output unit 320 encodes the digital code signal DC <0: 5> to generate the data output signal DOUT of the plurality of bits. The output unit 320 may encode the digital code signal DC <0: 5> in various manners. For example, when the data stored in the memory cell 120 is 2-bit multi-level data, the output unit 320 decodes the digital code signal DC <0: 5> And the output unit 320 encodes the digital code signal DC <0: 5> when the data stored in the memory cell 120 is 3-bit multilevel data, Bit data output signal DOUT.

4 is a diagram showing the configuration of an embodiment of the 1-bit ADC of FIG. The first through sixth 1-bit ADCs 311-316 in FIG. 3 may all have the same configuration. The 1-bit ADC receives the preset reference current Iref and the reference voltage Vcom. The 1-bit ADC includes a first comparison voltage generation unit 410, a second comparison voltage generation unit 420, and a determination unit 430. The first comparison voltage generator 410 generates a first comparison voltage Vin corresponding to twice the magnitude of the input current Ain input to the 1-bit ADC. The second comparison voltage generator 420 receives the reference current Iref and generates a second comparison voltage Vref corresponding to the magnitude of the reference current Iref. The determining unit 430 compares the first comparison current Icom1 and the second comparison current Icom2 corresponding to the first and second comparison voltages Vin and Vref and outputs the digital output DC n &Gt;) and an analog output Aout.

The first comparison voltage generator 410 includes first and second comparators 411 and 412 and first to fourth transistors 413, 414, 415, and 416. The first comparator 411 receives the input current Ain and the reference voltage Vcom. The first transistor 413 receives an output of the first comparator 411 as a gate, a source thereof is connected to a ground voltage VSS, and receives the input current Ain as a drain. The output terminal of the first comparator 411 becomes a voltage level corresponding to the magnitude of the input current Ain. The second and third transistors 414 and 415 are in the form of a current mirror and receive the output of the first comparator 411 as a gate, respectively, and the source is connected to the ground voltage VSS. Therefore, the current flowing to the first node NA by the second and third transistors 414 and 415 may be twice the input current Ain. The fourth transistor 416 receives the power supply voltage VDD as a source and the drain thereof is connected to the drains of the second and third transistors 414 and 415. The second comparator 412 is commonly connected to the drains of the second to fourth transistors 414 and 415 and receives the reference voltage Vcom and has an output terminal connected to the gate of the fourth transistor 416 Thereby generating the first comparison voltage Vin. The first comparison voltage Vin has a voltage level corresponding to twice the magnitude of the input current Ain.

The second comparison voltage generator 420 includes a third comparator 421 and a fifth transistor 422. The third comparator 421 receives the reference current Iref and the reference voltage Vcom. The fifth transistor 422 receives the output of the third comparator 421 as a gate, receives the reference current Iref as a drain, and the source is connected to the ground voltage VSS. The second comparison voltage Vref is generated at the output terminal of the third comparator 421. Therefore, the second comparison voltage Vref has a voltage level corresponding to the magnitude of the reference current Iref.

The determination unit 430 includes sixth to tenth transistors 431 to 435 and a fourth comparator 436. The sixth transistor 431 receives the first comparison voltage Vin as a gate and receives the power supply voltage VDD as a source. The sixth transistor 431 may receive the first comparison voltage Vin to generate the first comparison current Icom1 having a magnitude substantially equal to the magnitude of the current flowing through the first node NA have. The seventh transistor 432 receives the second comparison voltage Vref as its gate and its source is connected to the ground voltage VSS. The seventh transistor 432 may receive the second comparison voltage Vref and may generate a second comparison current Icom2 having substantially the same magnitude as the reference current Iref.

The fourth comparator 436 is coupled to the drains of the sixth and seventh transistors 431 and 432, respectively, and generates the digital output DC < n >. The fourth comparator 436 compares the first and second comparison currents Icom1 and Icom2 to generate the digital output DC <n>. The digital output DC <n> may be varied according to the relative magnitudes of the first and second comparison currents Icom1 and Icom2. If the magnitude of the first comparison current Icom1 is greater than the magnitude of the second comparison current Icom2, the fourth comparator 436 may generate a high level digital output DC <n>. Conversely, when the magnitude of the second comparison current Icom2 is greater than the magnitude of the first comparison current Icom1, the fourth comparator 436 may generate a low level digital output DC <n> . The digital output DC <n> is output to the output unit 320.

The eighth transistor 433 receives the first comparison voltage Vin as a gate, the power supply voltage VDD as a source, and the drain thereof is connected to a second node NB. The eighth transistor 433 receives the first comparison voltage Vin and outputs a current having substantially the same magnitude as the current flowing through the first node NA to the second node NB have. The ninth transistor 434 receives the second comparison voltage Vref as a gate, the source thereof is connected to the ground voltage VSS, and the drain thereof is connected to one end of the tenth transistor 435. The ninth transistor 434 receives the second comparison voltage Vref so that a current having substantially the same magnitude as the reference current Iref can flow. The tenth transistor 435 receives the digital output DC <n> as a gate and has one end connected to the second node NB and the other end connected to the drain of the ninth transistor 434 . The analog output Aout is output from the second node NB.

The tenth transistor 435 is turned on according to the digital output DC < n >. The tenth transistor 435 is turned on and the ninth transistor 434 is connected to the second node NB when the digital output DC is high. Therefore, at the second node NB, a current having a magnitude obtained by subtracting the current generated by the ninth transistor 434 from the current generated by the eighth transistor 433 is output. That is, the analog output Aout has a magnitude twice the magnitude of the input current Ain minus the magnitude of the reference current Iref. The tenth transistor 435 is turned off when the digital output DC <n> is at a low level and the magnitude of the second input current Ain is substantially equal to the magnitude of the input current Ain at the second node NB, Is output as it is. The analog output is input to the next stage 1-bit ADC.

5 is a diagram showing the configuration of a nonvolatile memory device 2 according to another embodiment of the present invention. 5, the nonvolatile memory device 2 includes a voltage generation unit 510, a memory cell 520, and a data output unit 540. [ The voltage generator 510 has the same configuration as the voltage generator 110 of FIG. One end of the memory cell 520 is connected to the sensing node SAI and receives a constant level voltage VC generated by the voltage generation unit 510 from the sensing node SAI.

The data output unit 540 receives the sensing current ISEN flowing through the memory cell 520 from the other end of the memory cell 520. The data output unit 540 receives the sensing current ISEN and generates a data output signal DOUT of a plurality of bits.

The non-volatile memory device 2 may further include a column switch 550, a row switch 560 and a precharge section 570, which are the same as the nonvolatile memory device 1 of FIG. 2 . In the nonvolatile memory device 1 of FIG. 2, the data output unit 140 is connected to the sensing node SAI. In the nonvolatile memory device 2 of FIG. 5, And is connected to the other end of the memory cell 520. That is, the data output unit 540 receives the sensing current ISEN on the word line side. As described above, the volatile memory device 2 according to the embodiment of the present invention provides a voltage VC having a constant level to the memory cell 520, And sensing the current (ISEN). 1, the conventional nonvolatile memory device 10 detects a change in the voltage level in accordance with the resistance value of the memory cell 11, so that the sense amplifier 12 that generates the data output signal DOUDT must It must be located at the sensing node SAI. However, since the nonvolatile memory device 2 senses the sensing current ISEN flowing through the memory cell 520, the data output unit 540 outputs the sensing current ISEN to the memory cell 520, That is, on the word line side.

When the data output unit 540 is connected to the word line side, the data output unit 540 may be disposed in the memory core, not in the peripheral circuit unit, or may be disposed under the memory. Therefore, it is possible to secure the area of the peripheral circuit portion in which many control circuits are dense, and the degree of freedom of design of the memory device can be improved. In addition, since the distance from the memory cell to the data output unit is short, data can be accurately and quickly sensed.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

1/2/10: nonvolatile memory device 11/120/520: memory cell
12: sense amplifier 110/510: voltage generator
111/511: Comparison unit 112/512: Driver unit
130: current replica unit 140/540: data output unit
141/541: linear conversion unit 142/542: digital signal generation unit
150/550: Column switch 160/560: Low switch
170/570:

Claims (17)

A voltage generator receiving the read voltage and the voltage of the sensing node and providing a voltage of a certain level to the sensing node;
A memory cell receiving the constant level voltage from the sensing node;
A current replica unit for generating a replica current of substantially the same magnitude as the sensing current flowing through the memory cell; And
And a data output unit for generating a plurality of data output signals by sensing the copy current. The method according to claim 1,
The voltage generator may include a comparator that compares the read voltage and the voltage of the sensing node to generate a comparison signal; And
And a driver for supplying a power supply voltage to the sensing node in response to the comparison signal. 3. The method of claim 2,
Wherein the driver section receives the comparison signal at a gate and receives the power supply voltage at either the drain or the source and the other of the drain and the source is connected to the sensing node. 3. The method of claim 2,
Wherein the current replica receives the comparison signal to generate the replica current having a magnitude substantially equal to the sensing current. The method of claim 3,
Wherein the current replica includes a second transistor that receives the comparison signal to a gate and receives the supply voltage to either the drain or the source and generates the replica current to the other of the drain and the source. The method according to claim 1,
Wherein the data output unit comprises: a linear transformer for receiving the replica current and generating a current amplified signal; And
And a digital signal generator for receiving the current amplified signal and generating the data output signal. The method according to claim 6,
Wherein the linear converter is a logarithmic linear converter that converts the replica current having a logarithmic scale to the current amplified signal having a linear scale. The method according to claim 6,
Wherein the digital signal generator comprises: a digital-to-analog converter for generating a plurality of digital signals from the current amplified signal; And
And an output unit for encoding the plurality of bits of the digital signal to generate the data output signal of the plurality of bits. A voltage generator receiving the read voltage and the voltage of the sensing node and providing a voltage of a certain level to the sensing node;
A memory cell having one end connected to the sensing node; And
And a data output unit connected to the other end of the memory cell and receiving a sensing current flowing through the memory cell to generate a plurality of data output signals. 10. The method of claim 9,
The voltage generator may include: a comparator that compares the read voltage and the voltage of the sensing node to generate a comparison signal; And
And a driver for supplying a power supply voltage to the sensing node in response to the comparison signal. 11. The method of claim 10,
Wherein the driver section receives the comparison signal at a gate and receives the power supply voltage at either the drain or the source and the other of the drain and the source is connected to the sensing node. 10. The method of claim 9,
Wherein the data output unit comprises: a linear transformer for receiving the replica current and generating a current amplified signal; And
And a digital signal generator for receiving the current amplified signal and generating the data output signal. 13. The method of claim 12,
Wherein the linear converter is a logarithmic linear converter that converts the replica current having a logarithmic scale to the current amplified signal having a linear scale. 13. The method of claim 12,
Wherein the digital signal generator comprises: a digital-to-analog converter for generating a plurality of digital signals from the current amplified signal; And
And an output unit for encoding the plurality of bits of the digital signal to generate the data output signal of the plurality of bits. 10. The method of claim 9,
A column switch for connecting the sensing node and one end of the memory cell in response to a bit line selection signal; And
And a row switch for connecting a ground voltage to the other end of the memory cell in response to a word line select signal. 16. The method of claim 15,
And the data output unit is connected between the other end of the memory cell and the row switch to receive the sensing current. 10. The method of claim 9,
And a precharge section for driving the sensing node to a precharge voltage level equal to or lower than the reference voltage level in response to the precharge signal.
KR1020120150161A 2012-12-21 2012-12-21 Non-volatile memory apparatus KR20140080944A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020120150161A KR20140080944A (en) 2012-12-21 2012-12-21 Non-volatile memory apparatus
US13/921,305 US20140177319A1 (en) 2012-12-21 2013-06-19 Nonvolatile memory apparatus
US14/797,247 US9583186B2 (en) 2012-12-21 2015-07-13 Non-volatile memory apparatus sensing current changing according to data stored in memory cell
US15/402,984 US20170125094A1 (en) 2012-12-21 2017-01-10 Nonvolatile memory apparatus
US15/402,565 US20170125093A1 (en) 2012-12-21 2017-01-10 Nonvolatile memory apparatus

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KR20180045680A (en) * 2016-10-26 2018-05-04 에스케이하이닉스 주식회사 Sense amplifier, non-volatile memory apparatus and system including the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180045680A (en) * 2016-10-26 2018-05-04 에스케이하이닉스 주식회사 Sense amplifier, non-volatile memory apparatus and system including the same

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