KR20140006544A - Multi level memory apparatus and its data sensing method - Google Patents

Abstract

The present invention can provide a resistance memory apparatus capable of effectively detecting a wide-range current flow in a memory cell. The resistance memory apparatus of the present invention comprises two or more current paths which pass differently-sized current; a resistance memory cell selectively connected to the current paths; and a cell current copy unit for copying the cell current flow in the resistance memory cell.

Description

MULTI LEVEL MEMORY APPARATUS AND ITS DATA SENSING METHOD}

The present invention relates to a semiconductor device, and more particularly to a memory device including a multi-level memory cell.

A conventional DRAM includes a memory cell composed of a capacitor, and stores data while charging or discharging the memory cell. However, because of the leakage current due to the characteristics of the capacitor, DRAM has the disadvantage of being a volatile memory. To alleviate the shortcomings of DRAMs, memories are being developed that are nonvolatile and do not require data retention. In particular, attempts have been made to implement non-volatility by changing the memory cell structure, one of which is a resistive memory device comprising a resistive memory cell.

1 is a diagram schematically illustrating a configuration of a resistive memory device according to the related art. In FIG. 1, a resistive memory device according to the prior art includes a memory cell 10 and a transistor N1. The memory cell 10 is composed of a resistive material whose resistance value changes according to temperature or current, and has different resistance values depending on stored data.

The transistor N1 provides a sensing current to sense the data stored in the memory cell 10. The transistor N1 controls the bias voltage VB to apply the power supply voltage VPPSA to the sensing node SAI.

The conventional resistive memory device senses data stored in the memory cell 11 by changing the voltage of the sensing node SAI. The transistor N1 is turned on when the bias voltage VB is applied, and is configured to provide a certain amount of current to the sensing node SAI. The current flowing through the sensing node SAI flows through the memory cell 10. [ Therefore, the voltage level of the sensing node SAI depends on the resistance value of the memory cell 10. [ That is, when the resistance value of the memory cell 10 is large, the voltage of the sensing node SAI has a high level, and when the resistance value of the memory cell 10 is small, the voltage of the sensing node SAI is low . As described above, the conventional resistive memory device provides a constant current to the sensing node SAI, and changes the voltage level of the sensing node SAI according to the resistance value of the memory cell 10 to the memory cell 10. Sensing the stored data.

In addition, the step-up voltage VPPSA is used as the power supply voltage to reliably detect the voltage level change of the sensing node SAI according to the resistance value of the memory cell 10. [ The boosted voltage VPPSA may be generated through a pumping circuit at a voltage higher than an external power supply level.

The present invention can provide a multi-level memory device capable of efficiently detecting a wide range of currents flowing through a memory cell and a data sensing method thereof.

In addition, the present invention can provide a multi-level memory device and a data sensing method thereof capable of accurately detecting a wide range of currents flowing in a memory cell.

In addition, the present invention can provide a multi-level memory device and a data sensing method thereof capable of quickly detecting multi-level data stored in a memory cell.

The multi-level memory device of the present invention includes at least two current paths for passing different magnitudes of current; A memory cell electrically connected to the at least two current paths; And a cell current replicating unit configured to copy a cell current flowing through the memory cell.

In addition, the cell current replication unit may be coupled to the at least two current paths and the current mirror type.

The at least two current paths may include: a first current driver configured to pass a first range of the cell current; And a second current driver capable of passing a second range outside the first range of the cell current.

In addition, the cell current replica may pass a current having the same magnitude as that of the first current driver.

In addition, comparing means for comparing the cell replication current and the comparison replication current flowing through the cell current replication unit; A data output unit for converting and outputting a comparison signal output from the comparison means; A comparison current output unit which outputs a comparison current by using the comparison signal output from the data output unit; And a comparison current replication unit configured to copy the comparison current to output the comparison replication current.

The comparison means may further include: a first step of amplifying a potential difference between a first node on a path through which the cell replication current flows and a second node on a path through which the comparative replication current flows using the cell replication current and the comparative replication current; Comparator; And a second comparison unit configured to compare the first node and the second node as inputs.

In addition, the multi-level memory device of the present invention, the cell current replica unit for replicating the cell current flowing through the memory cell; Comparison means for comparing a cell replication current flowing through the cell current replication unit with a comparison replication current; A data output unit for converting and outputting a comparison signal output from the comparison means; A comparison current output unit which outputs a comparison current by using the comparison signal output from the data output unit; And a comparison current replication unit configured to copy the comparison current to output the comparison replication current.

In addition, the data sensing method of the multi-level memory device of the present invention comprises the steps of flowing a cell current to the memory cell connected to the current path by selecting any one of at least two or more current paths for passing a current of different magnitude; Setting a comparison current for comparing the cell currents to a predetermined value; If the cell current is greater than the predetermined value, replicating the cell current with the same magnitude; And if the cell current is smaller than the predetermined value, replicating the cell current by a predetermined multiple.

The method may further include replicating the cell current to output a cell replication current; Copying the comparison current to output a comparison replication current; Outputting a comparison signal by comparing the cell replication current with the comparison replication current; And temporarily storing the comparison signal and digitally outputting the comparison signal.

According to the present invention, by accurately detecting a wide range of currents caused by a change in the resistance value of the memory cell, the amount of data that can be stored in the memory cell can be maximized, and a high power supply voltage is not required.

1 is a view schematically showing a configuration of a resistive memory device according to the prior art;
2 is a main configuration diagram of a multi-level memory device according to an embodiment of the present invention;
3 is a graph of the operation of a multi-level memory device according to an embodiment of the present invention,
4 is a configuration diagram of a multi-level memory device according to another embodiment of the present invention;
5 is an operation flowchart of a multi-level memory device according to an embodiment of the present invention;
6 is a configuration diagram of a current DAC of a multi-level memory device according to an embodiment of the present invention;
7 is a configuration diagram of a current DAC of a multi-level memory device according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms, and the inventor should appropriately interpret the concepts of the terms appropriately It should be interpreted in accordance with the meaning and concept consistent with the technical idea of the present invention based on the principle that it can be defined. Therefore, the embodiments described in this specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and do not represent all the technical ideas of the present invention. Therefore, It is to be understood that equivalents and modifications are possible.

A multi-level memory, for example, a resistive memory, may have various resistance values depending on device characteristics, so various data can be stored in one memory cell instead of binary data. For example, in the case of PCRAM, current may flow in a memory cell in a range of at least 100 nanoamps (nA) to at most 15 microamps (uA). That is, since the difference between the minimum current and the maximum current flowing in the memory cell is too large, if the size of the switching element used for detecting the current flowing in the memory cell is designed to be the minimum current, the maximum current is prevented from flowing, By design, the switching element will be in a weak inversion state when the minimum current flows. On the other hand, if the switching element is placed in the wicked version state, the current flowing in the switching element can not be accurately copied.

Therefore, according to the present invention, the current flowing in the memory cell can be accurately copied by diversifying the current path through the memory cell.

2 is a main block diagram of a multi-level memory device according to an embodiment of the present invention, and includes a memory cell 10, a detection voltage generation unit 20, and a cell current replication unit 31.

The detection voltage generator 20 amplifies a difference between the reference voltage VREF and the sensing node voltage VSAI to provide a voltage of a predetermined level to the sensing node VSAI. The memory cell 10 is connected to the sensing node VSAI, and the amount of current flowing through the sensing node VSAI varies according to the resistance of the memory cell 10. That is, the amount of current flowing through the sensing node VSAI when the resistance value of the memory cell 10 is small is greater than the amount of current flowing through the sensing node VSAI when the resistance value of the memory cell 10 is large.

The multi level memory device according to an embodiment of the present invention for detecting a change in current has various advantages.

First, since the multi-level memory device according to the present invention senses a change in current, it is not necessary to provide a wide range of voltages to the memory cell 10, and thus does not need to provide a high level of voltage. In the conventional resistive memory device, a threshold or a reference value for changing the voltage of the sensing node SAI and sensing a voltage change is required according to the resistance value of the memory cell 10. Therefore, it is necessary to provide a wide range of voltages to discriminate between the high resistance state and the low resistance state of the memory cell. Therefore, the conventional resistive memory device needs to supply the boost voltage VPPSA by pumping the power supply voltage as shown in Fig. However, since the multi-level memory device according to the embodiment of the present invention does not need a voltage threshold, it is not necessary to form a wide range of voltage, and it is sufficient to apply the external voltage VDD as the power supply voltage as shown in FIG. 2. . Therefore, the current consumption due to the use of the boosted voltage is reduced, and the circuit for generating a high voltage can be eliminated.

In addition, the sensing time of data stored in the memory cell 10 is shortened due to the characteristic of detecting a change in current. That is, it enables fast data sensing. In addition, an unnecessary element such as a conventional clamping switch can be removed by employing an improved structure that provides a certain level of voltage to the sensing node (VSAI).

The detection voltage generation unit 20 according to an embodiment of the present invention includes a comparator 21 and a plurality of driving units 23 and 25. The comparator 21 amplifies the difference between the reference voltage VREF and the sensing node voltage VSAI to generate an amplified signal AMP, and the voltage level of the sensing node VSAI becomes equal to the level of the reference voltage VREF. Gradually decrease the level of the amplified signal (AMP) until Here, the reference voltage VREF may be, for example, half of the power supply voltage VDD.

Thereafter, in response to the amplified signal AMP, the sensing node VSAI is gradually driven to the power supply voltage VDD level. The driving units 23 and 25 decrease the magnitude of the voltage provided to the sensing node VSAI according to the amplified signal AMP. When the levels of the reference voltage VREF and the sensing node voltage VSAI become the same, the driving units 23 and 25 fix the level of the sensing node voltage VSAI. The memory cell 10 receives a voltage of a predetermined level and changes the magnitude of the current flowing through the sensing node VSAI according to the resistance value.

On the other hand, when the resistance value of the memory cell 10 is small and the current is large, the first switch SW1 of the plurality of driving units 23 and 25 is turned on to operate the strong current driver 23 to operate the memory cell 10. When the resistance is large and the current is small, the weak current driver 25 is operated by turning on the second switch SW2. For example, when the current flowing in the memory cell is 1.2 to 15 microamps (uA), the strong current driver 23 is operated, and when the current is 100 nanoamps (nA) to 1.2 microamps (uA), the weak current driver 25 is operated.

To this end, the strong current driver 23 may have a capability of passing a current several times to several tens of times of the weak current driver 25. According to an embodiment of the present invention, the weak current driver 25 may be implemented with one switching element (eg, FET), and the strong current driver 23 may have 12 switching elements of the same size connected in parallel. Further, according to another embodiment of the present invention, the weak current driver 25 and the strong current driver 23 are each implemented as one switching device, while the switching device of the strong current driver 23 is the weak current driver 25. It can have the ability to pass 12 times the current compared to the switching element of).

The cell current replication unit 31 according to an embodiment of the present invention is configured and disposed with the same size as the strong current driver 23, and the cell current Icell flowing through the drivers 23 and 25 to the memory cell 10. ) Is replicated to flow a cell replication current (Icell_copy).

3 is an operation graph of a multi-level memory device according to an embodiment of the present invention. When the current flowing in the memory cell 10 is 1.2 to 15 microamps (uA), the strong current driver 23 is operated. The cell copy current Icell_copy of 1.2 to 15 microamps (uA) having the same magnitude as that of the strong current driver 23 is output from the cell current replica 31 which is a current mirror. On the other hand, when the current Icell flowing through the memory cell 10 is 100 nanoamps (nA) to 1.2 microamps (uA), the weak current driving unit 25 is operated, but the cell current replicating unit 31 which is a current mirror. Has a current amplification capacity of 12 times that of the weak current driver 23, and as shown in the dotted line of FIG. 3, the level of the cell replication current (Icell_copy) is 1.2 to 15 microamps (uA). Shift output. Here, the amplification operation on the linear scale is the same as the level shift operation on the log scale.

4 is a block diagram illustrating a multilevel memory device according to another exemplary embodiment of the present invention. The comparison unit 50 includes a data output unit 60 and a comparison current output unit 70.

The memory cell 10 and the detection voltage generator 20 are the same as those in FIG. The current replication unit 30 includes a cell current replication unit 31 and a comparison current replication unit 33. The cell current replication unit 31 replicates the cell current Icell flowing through the driving units 23 and 25 and flows the cell replication current Icell_copy, and the comparison current replication unit 33 describes the comparison current output unit 70 described later. The comparative current (Icomp) flowing through is replicated to flow a comparative replication current (Icomp_copy).

The first comparator 40 is connected between the nodes 31 (N31) and the nodes 33 (N33), and is controlled by the reset signal RESET to reset the potentials of the nodes 31 (N31) and the nodes 33 (N33). (41) and a positive feedback unit 43 for comparing the difference between the output voltages of the current replication unit 30 in a positive feedback manner. Specifically, when the switching element of the reset unit 41 is turned on and reset, the node 31 (N31) and the node 33 (N33) are at the same potential, and when the reset unit 41 is turned off, the node 31 (N31) And the voltage of the node 33 (N33) are applied to the switching elements 431 and 432 in the positive feedback unit 43, respectively.

The positive feedback unit 43 is connected between the node 31 (N31) and the ground, the switching element 431 controlled to the voltage of the node 33 (N33), and connected between the node 33 (N33) and the ground, node 31 And a switching element 432 controlled to the voltage of N31. The positive feedback unit 43 compares the voltage of the node 31 (N31) with the voltage of the node 33 (N33) in a positive feedback manner. For example, the cell replication current Icell_copy flowing from the node 31 (N31) to the ground side is a node. If it is greater than the comparative replication current Icomp_copy flowing from 33 to 33, the voltage VN31 of the node 31 N31 is lower than the voltage VN33 of the node 33 N33. The lowered voltage VN31 of the node 31 (N31) is applied to the control voltage of the switching element 432 disposed between the node 33 (N33) and ground, so that the switching element 432 is close to the turn-off state. On the other hand, the increased voltage VN33 of the node 33 (N33) is applied as a control voltage of the switching element 431 disposed between the node 31 (N31) and the ground so that the switching element 431 is close to the turn-on state. In this manner, the switching elements 431 and 432 in the positive feedback unit 43 gradually open up in the positive direction.

The second comparator 50 compares the voltage VN31 of the node 31 (N31) with the voltage VN33 of the node 33 (N33) and outputs "H" or "L".

The data output unit 60 receives the output of the second comparator 50 to temporarily store digital data, and outputs the digital comparison signal output from the digital data output unit 61 and the digital data output unit 61. And a D / A converter 63 for converting to an analog comparison signal.

According to an embodiment of the present invention, the digital data output unit 61 may be implemented as a 5-bit register, and the D / A converter 63 may be implemented as a 4-bit D / A converter. That is, if the digital data output unit 61 is an N bit register, the D / A converter may be implemented as an (N-1) bit D / A converter. Here, the D / A converter 63 may be configured to correspond to a current change characteristic according to the data value of the memory cell 10. For example, if the cell current increases or decreases exponentially as the data value of the memory cell 10 sequentially increases or decreases, the output of the D / A converter 63 may also increase or decrease exponentially. Further, according to another embodiment of the present invention, if the cell current linearly increases or decreases as the data value of the memory cell 10 sequentially increases or decreases, the output of the D / A converter 63 may also increase or decrease linearly. Can be.

In the comparison current output unit 70, switching elements having the same size as the comparison current replication unit 33 are arranged in the same manner, and increase or decrease the magnitude of the comparison current Icomp according to the output of the D / A converter 63.

5 is an operation flowchart of a multi-level memory device according to an embodiment of the present invention.

First, the second switch SW2 of the weak current driving unit is turned on to flow the cell current Icell to the memory cell 10, and the cell current replicating unit 31 duplicates the cell current Icell flowing through the memory cell to the node 31. The cell copy current Icell_copy flows to N31. Then, the 5-bit register outputs "0000" by turning on the switching elements of the reset unit 41 in accordance with the reset signal RESET to reset the voltages of the nodes 31 and 33 to the same potential (S510).

When the switching element of the reset unit 41 is turned off and the D / A converter 63 receives the value " 0000 " output from the 5-bit register and outputs a comparative current Icomp of 1.2 microamps (uA), The comparison current replica unit 33 outputs a comparison replication current Icomp_copy of 1.2 microamperes (uA) that duplicates the comparison current Icomp, and the first comparator 40 and the second comparator 50 are cells. The first bit MSB of the 5-bit register is determined by comparing the copy current Icell_copy and the comparison copy current Icomp_copy of 1.2 microamps uA (S520).

When the cell replication current Icell_copy is greater than the comparative replication current Icomp_copy of 1.2 microamps (uA), the 5-bit register turns on "1000" while turning on the first switching element SW1 of the strong current driver 23. Outputs a comparator current Icomp of 4.3 microamps (uA). On the other hand, when the cell replication current Icell_copy is smaller than the comparative replication current Icomp_copy, the second switching element SW2 of the weak current driver 25 is turned on so that the cell current Icell is 100 nanoamps nA to 1.2. Even if it is less than microamperes (uA), the cell replication current (Icell_copy) is set to 1.2 microamps (uA) to 15 microamps (uA) (S530). Here, if the output of the 5-bit register is "0000", the comparison current Icomp is 1.2 microamps (uA). If the output of the 5-bit register is "1000", the comparison current Icomp is 4.3 microamps (uA). What is changed is the application of statistical techniques to find the target value in the shortest time. In addition, the 4.3 microamp is a median between 1.2 and 15 on the logarithmic scale.

After that, the next bit is determined (S540), and accordingly, the output of the D / A converter 63 is controlled (S550). If the total number of bits determined is equal to the number of bits of the register (S560), the register 61 is a code value. It outputs (S570).

6A is a configuration diagram of a current DAC of a multi-level memory device according to an embodiment of the present invention, and FIG. 6B is a graph of an output current versus a binary code that changes exponentially.

In the current D / A converter of the multi-level memory device according to an embodiment of the present invention, when the cell current of the resistive memory cell changes nonlinearly, for example, exponentially, the comparative current comparing the same may also be exponentially. The configuration for changing includes a decoder 631 for decoding the output of the register and a plurality of unit current cells 633 connected in parallel controlled according to the output of the decoder 631.

For example, if the output of the resistor is "0000", the unit current cell in the D / A converter is turned on so that 3 * I flows, and if the output of the register is "0001", the unit current cell in the D / A converter flows 3.5 * I. Turn on and turn on the unit current cell in the D / A converter so that 32 * I flows if the output of the resistor is " 1111 ". Here, the current IDAC means a comparative replication current Icomp_copy.

FIG. 7A is a configuration diagram of a current DAC of a multi-level memory device according to another exemplary embodiment of the present invention, and FIG. 7B is a graph of an output current versus a binary code that varies linearly.

The current D / A converter of a multi-level memory device according to an embodiment of the present invention is configured to linearly change a comparison current comparing a current when a cell current of a resistive memory cell changes linearly. A decoder 631 for decoding the output and a plurality of unit current cells 633 connected in parallel controlled according to the output of the decoder 631.

For example, if the output of the register is "0000", the unit current cell in the D / A converter is turned on so that I flows. If the output of the register is "0001", the unit current cell in the D / A converter is turned on so that 2 * I flows. If the output of the register is " 1111 ", the unit current cell in the D / A converter is turned on so that 16 * I flows.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It is to be understood that various changes and modifications may be made without departing from the scope of the appended claims.

10: memory cell 20: detection voltage generation unit
21: comparator 23: strong current drive unit
25: weak current drive unit 30: current replication unit
31: cell current replication unit 33: comparison current replication unit
40: first comparison unit 41: reset unit
43, 45: positive feedback section 50: second comparison section
60: data output unit 61: digital data output unit
63: D / A converter 70: comparison current output unit
Icell: cell current Icell_copy: cell replication current
Icomp: Comparative Current Icomp_copy: Comparative Replication Current

Claims (29)

At least two current paths for passing currents of different sizes;
A memory cell electrically connected to the at least two current paths; And
A cell current replica unit for replicating the cell current flowing through the memory cell
/ RTI > The method of claim 1,
The cell current replica unit is coupled to the at least two current paths and the current mirror type multi-level memory device. The method of claim 1, wherein the at least two current paths comprise:
A first current driver capable of passing the first range of cell currents; And
A second current driver capable of passing a second range outside the first range of the cell current
/ RTI > The method of claim 3,
The cell current replica unit may pass a current having the same magnitude as the first current driver. The method of claim 1,
Comparison means for comparing a cell replication current flowing through the cell current replication unit with a comparison replication current;
A data output unit for converting and outputting a comparison signal output from the comparison means;
A comparison current output unit which outputs a comparison current by using the comparison signal output from the data output unit; And
Comparative current replica unit for copying the comparison current to output the comparison replication current
Level memory device. The method of claim 5, wherein the comparison means,
A first comparison unit amplifying a potential difference between a first node on a path through which the cell replication current flows and a second node on a path through which the comparative replication current flows using the cell replication current and the comparative replication current; And
A second comparing unit comparing the first node and the second node as inputs;
/ RTI > The method of claim 6, wherein the first comparison unit,
A reset unit connected between the first node and the second node and controlled by a reset signal to match potentials of the first and second nodes; And
Positive feedback unit for amplifying the potential difference between the first node and the second node in a positive feedback method
/ RTI > The method of claim 7, wherein the positive feedback unit,
A first switching element connected between the first node and ground and controlled to a voltage of the second node; And
A second switching element connected between the second node and ground and controlled to the voltage of the first node
/ RTI > The method of claim 5, wherein the data output unit,
A storage unit for temporarily storing a comparison signal output from the comparison unit; And
Converter for outputting the digital comparison signal output from the storage as an analog comparison signal
/ RTI > 10. The method of claim 9,
And the storage unit is an N bit register. The method of claim 10,
And the converting portion is a (N-1) bit digital / analog converter. 12. The method of claim 11,
And the converter is configured to correspond to a current change characteristic according to a data value of the memory cell. 12. The method of claim 11,
And the output of the converter can be exponentially increased or decreased. 12. The method of claim 11,
The multi-level memory device capable of linearly increasing or decreasing the output of the converter. The method of claim 11, wherein the conversion unit,
A decoder for decoding the output of the storage unit; And
A plurality of unit current cells connected in parallel controlled according to the output of the decoder
Multi-level memory device comprising a. A cell current replica unit which replicates a cell current flowing in the memory cell;
Comparison means for comparing a cell replication current flowing through the cell current replication unit with a comparison replication current;
A data output unit for converting and outputting a comparison signal output from the comparison means;
A comparison current output unit which outputs a comparison current by using the comparison signal output from the data output unit; And
Comparative current replica unit for copying the comparison current to output the comparison replication current
/ RTI > The method of claim 16, wherein the comparison means,
A first comparison unit amplifying a potential difference between a first node on a path through which the cell replication current flows and a second node on a path through which the comparative replication current flows using the cell replication current and the comparative replication current; And
A second comparing unit comparing the first node and the second node as inputs;
/ RTI > The method of claim 17, wherein the first comparison unit,
A reset unit connected between the first node and the second node and controlled by a reset signal to match potentials of the first and second nodes; And
Positive feedback unit for amplifying the potential difference between the first node and the second node in a positive feedback method
/ RTI > The method of claim 18, wherein the positive feedback unit,
A first switching element connected between the first node and ground and controlled to a voltage of the second node; And
A second switching element connected between the second node and ground and controlled to the voltage of the first node
/ RTI > The method of claim 16, wherein the data output unit,
A storage unit for temporarily storing a comparison signal output from the comparison unit; And
Converter for outputting the digital comparison signal output from the storage as an analog comparison signal
/ RTI > 21. The method of claim 20,
And the storage unit is an N bit register. The method of claim 21,
And the converting portion is a (N-1) bit digital / analog converter. The method of claim 22,
And the converter is configured to correspond to a current change characteristic according to a data value of the memory cell. The method of claim 22,
And the output of the converter can be exponentially increased or decreased. The method of claim 22,
The multi-level memory device capable of linearly increasing or decreasing the output of the converter. The method of claim 22, wherein the conversion unit,
A decoder for decoding the output of the storage unit; And
A plurality of unit current cells connected in parallel controlled according to the output of the decoder
Multi-level memory device comprising a. Selecting one of at least two current paths through which currents of different magnitudes pass, and flowing a cell current to a memory cell connected to the current path;
Setting a comparison current for comparing the cell currents to a predetermined value;
If the cell current is greater than the predetermined value, replicating the cell current with the same magnitude; And
If the cell current is smaller than the predetermined value, replicating the cell current by a predetermined multiple
Data sensing method of a multi-level memory device comprising a. 28. The method of claim 27,
Outputting a cell replication current by copying the cell current;
Copying the comparison current to output a comparison replication current;
Outputting a comparison signal by comparing the cell replication current with the comparison replication current; And
Temporarily storing the comparison signal and digitally outputting the comparison signal
The data sensing method of the multi-level memory device further comprising. 29. The method of claim 28,
And the comparative replica current corresponds to a current change characteristic according to a data value of the memory cell.

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