TWI732572B - Memory device and operation method thereof - Google Patents

Memory device and operation method thereof Download PDF

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TWI732572B
TWI732572B TW109117967A TW109117967A TWI732572B TW I732572 B TWI732572 B TW I732572B TW 109117967 A TW109117967 A TW 109117967A TW 109117967 A TW109117967 A TW 109117967A TW I732572 B TWI732572 B TW I732572B
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current
source
coupled
memory
memory device
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TW202145207A (en
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劉逸青
羅棋
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旺宏電子股份有限公司
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Abstract

A memory device includes: a memory array including a plurality of memory cells and a plurality of bit lines; and a current converting circuit, coupled to the memory array. In executing a calculation operation, the memory cells of the memory array generate a source current corresponding to a calculation operation result. The source current is converted by the current converting circuit into an output value for being an input signal provided to a next calculation operation.

Description

記憶體裝置及其操作方法 Memory device and its operation method

本發明是有關於一種記憶體裝置及其操作方法。 The invention relates to a memory device and an operation method thereof.

大數據(big data)、人工智慧(AI)和機器學習為目前市場焦點。AI運算上需要大量乘積累加運算(MAC,Multiply Accumulate)。近來,AI硬體需要高性能且低功率的MAC解決方案。記憶體內運算(in-memory computation)已為廣泛提出,因為可直接在記憶體陣列內執行MAC,減少資料搬移,以節省功率與延遲。 Big data, artificial intelligence (AI) and machine learning are the current market focus. AI operations require a large number of multiply accumulate operations (MAC, Multiply Accumulate). Recently, AI hardware requires high-performance and low-power MAC solutions. In-memory computation (in-memory computation) has been widely proposed, because MAC can be executed directly in the memory array, reducing data movement and saving power and delay.

故而,如何實施記憶體內大量資料運算,對於大數據、AI、機器學習等領域亦為重要關鍵。 Therefore, how to implement a large number of data operations in the memory is also an important key to the fields of big data, AI, and machine learning.

根據本案一實例,提出一種記憶體裝置,包括:一記憶體陣列,包括複數個記憶體單元與複數條位元線;以及一電流轉換電路,耦接至該記憶體陣列。其中,於執行一運算操作時,該記憶體陣列的該些記憶體單元產生相關於一運算操作結果的一源極電流。該源極電流由該電流轉換電路轉換成一輸出數值,用以提供一下一運算操作的一輸入訊號。 According to an example of this case, a memory device is provided, including: a memory array including a plurality of memory cells and a plurality of bit lines; and a current conversion circuit coupled to the memory array. Wherein, when an arithmetic operation is performed, the memory cells of the memory array generate a source current related to a result of the arithmetic operation. The source current is converted into an output value by the current conversion circuit to provide an input signal for the next arithmetic operation.

根據本案更一實例,提出一種記憶體裝置的操作方法,該記憶體裝置包括一記憶體陣列,該記憶體陣列包括複數個記憶體單元與複數條位元線,該操作方法包括:於執行一運算操作時,該記憶體陣列的該些記憶體單元產生相關於一運算操作結果的一源極電流;以及將該源極電流轉換成一輸出數值,用以提供一下一運算操作的一輸入訊號。 According to a further example of the present case, an operating method of a memory device is provided. The memory device includes a memory array, the memory array includes a plurality of memory cells and a plurality of bit lines, and the operation method includes: During arithmetic operations, the memory cells of the memory array generate a source current related to a result of arithmetic operation; and convert the source current into an output value to provide an input signal for the next arithmetic operation.

為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下: In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

100:記憶體裝置 100: Memory device

110:記憶體陣列 110: memory array

130:電流轉換電路 130: current conversion circuit

ISL、ISL1、ISL2:源極電流 ISL, ISL1, ISL2: source current

OUT_DC:輸出數值 OUT_DC: output value

WL0~WLN:字元線 WL0~WLN: character line

BL1~BL2:位元線 BL1~BL2: bit line

SSL1~SSL2:串選擇線 SSL1~SSL2: string selection line

SL1~SL2:源極線 SL1~SL2: source line

T:記憶體單元 T: memory unit

BK1~BK2:區塊 BK1~BK2: block

130A、130B、130C:電流轉換電路 130A, 130B, 130C: current conversion circuit

A1~A3:操作放大器 A1~A3: Operational amplifier

MP11~MP13、MN11~MN12、MP21~MP23、MN21~MN28_P、MP31、MN31~MN33:電晶體 MP11~MP13, MN11~MN12, MP21~MP23, MN21~MN28_P, MP31, MN31~MN33: Transistor

IREF1、IREF2:參考電流源 IREF1, IREF2: Reference current source

VREF:參考電壓 VREF: Reference voltage

N11~N12、N3:節點 N11~N12, N3: Node

OUT1~OUT2:輸出端 OUT1~OUT2: output terminal

VDD:操作電壓 VDD: operating voltage

I11~I12、I21~I22、I3:電流 I11~I12, I21~I22, I3: current

410:控制邏輯電路 410: Control logic circuit

OUT_DC:輸出數值 OUT_DC: output value

EN0~ENP:致能信號 EN0~ENP: enable signal

VB1:偏壓電壓 VB1: Bias voltage

RL:電阻 RL: resistance

510:類比數位轉換器 510: Analog to Digital Converter

VB2:偏壓電壓 VB2: Bias voltage

305、405、505:電壓調整電路 305, 405, 505: voltage adjustment circuit

第1圖繪示依照本案一實施例的記憶體裝置之功能方塊圖。 FIG. 1 is a functional block diagram of a memory device according to an embodiment of the present invention.

第2圖繪示依照本發明一實施例的記憶體陣列之源端感應示意圖。 FIG. 2 is a schematic diagram of source sensing of a memory array according to an embodiment of the invention.

第3圖繪示依照本發明一實施例的電流轉換電路示意圖。 FIG. 3 is a schematic diagram of a current conversion circuit according to an embodiment of the invention.

第4圖繪示依照本發明另一實施例的電流轉換電路示意圖。 FIG. 4 is a schematic diagram of a current conversion circuit according to another embodiment of the invention.

第5圖繪示依照本發明又一實施例的電流轉換電路示意圖。 FIG. 5 is a schematic diagram of a current conversion circuit according to another embodiment of the invention.

本說明書的技術用語係參照本技術領域之習慣用語,如本說明書對部分用語有加以說明或定義,該部分用語之解釋係以本說明書之說明或定義為準。本揭露之各個實施例分別具有一或多個技術特徵。在可能實施的前提下,本技術領域具有通常知識者可選擇性地實施任一實施例中部分 或全部的技術特徵,或者選擇性地將這些實施例中部分或全部的技術特徵加以組合。 The technical terms in this specification refer to the customary terms in the technical field. If there are descriptions or definitions for some terms in this specification, the explanation of the part of the terms is based on the description or definitions in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those with ordinary knowledge in the technical field can selectively implement part of any of the embodiments. Or all the technical features, or selectively combine some or all of the technical features in these embodiments.

第1圖繪示依照本案一實施例的記憶體裝置之功能方塊圖。如第1圖所示,依照本案一實施例的記憶體裝置100包括:記憶體陣列110與電流轉換電路130。 FIG. 1 is a functional block diagram of a memory device according to an embodiment of the present invention. As shown in FIG. 1, the memory device 100 according to an embodiment of the present application includes: a memory array 110 and a current conversion circuit 130.

記憶體陣列110耦接至電流轉換電路130。當於人工智慧運算中執行乘積累加運算(MAC,Multiply Accumulate)時,記憶體陣列110會產生相關於乘積累加運算結果的一源極電流ISL。電流轉換電路130會將源極電流ISL轉換成輸出數值OUT_DC,該輸出數值OUT_DC代表乘積累加運算結果。輸出數值OUT_DC可以當成下一運算操作的輸入訊號。例如,以單個記憶體裝置100當成一級運算單元的話,則該記憶體裝置100執行乘積累加運算所得的輸出數值OUT_DC可以輸入至下一級運算單元(亦即另一個記憶體裝置100),以繼續進行AI運算。 The memory array 110 is coupled to the current conversion circuit 130. When a Multiply Accumulate (MAC) operation is performed in an artificial intelligence operation, the memory array 110 generates a source current ISL related to the result of the multiply-accumulate operation. The current conversion circuit 130 converts the source current ISL into an output value OUT_DC, and the output value OUT_DC represents the result of the multiplication and accumulation operation. The output value OUT_DC can be used as the input signal for the next operation. For example, if a single memory device 100 is used as the first-level arithmetic unit, the output value OUT_DC obtained by the multiplication-accumulation-add operation of the memory device 100 can be input to the next-level arithmetic unit (that is, another memory device 100) to continue. AI operation.

第2圖繪示依照本發明一實施例的記憶體陣列之源極端感應示意圖。第2圖以記憶體陣列為三維(3D)記憶體陣列為例做說明,但當知本案並不受限於此。 FIG. 2 is a schematic diagram of the source terminal sensing of the memory array according to an embodiment of the invention. Fig. 2 takes the memory array as a three-dimensional (3D) memory array as an example for illustration, but it should be understood that this case is not limited to this.

如第2圖所示,記憶體陣列110包括:複數個字元線WL0~WLN(N為正整數),複數條位元線(以BL1~BL2為例),複數條串選擇線(以SSL1~SSL2為例),複數條源極線SL1~SL2,以及複數個記憶體單元T。該些記憶體單元T形成 於字元線與位元線之交叉處。記憶體陣列110包括複數個區塊(BK1,BK2,...)。 As shown in Figure 2, the memory array 110 includes: a plurality of word lines WL0~WLN (N is a positive integer), a plurality of bit lines (taking BL1~BL2 as an example), a plurality of string selection lines (using SSL1 ~SSL2 as an example), a plurality of source lines SL1~SL2, and a plurality of memory cells T. These memory cells T form At the intersection of the character line and the bit line. The memory array 110 includes a plurality of blocks (BK1, BK2,...).

底下說明以位元線電壓當成輸入,而將與字元線耦接的記憶體單元T的電導(cell conductance,GCELL)當成權重,來進行乘積累加運算的例子。其中,記憶體單元T所產生的電流ICELL可為位元線電壓VBL與記憶體單元的權重(例如但不受限於為電導GCELL)的乘積(ICELL=VBL * GCELL)。但當知本案並不受限於此。 The following describes an example in which the bit line voltage is used as the input, and the cell conductance (GCELL) of the memory cell T coupled to the word line is used as the weight to perform the multiplying, accumulating and adding operation. Wherein, the current ICELL generated by the memory cell T can be the product of the bit line voltage VBL and the weight of the memory cell (for example, but not limited to, the conductance GCELL) (ICELL=VBL * GCELL). But Dangzhi this case is not limited to this.

當具有複數個記憶體單元T時,源極線SL1或SL2耦接至該些記憶體單元T的源極,該些記憶體單元T所產生的電流會經由該些條源極線SL1~SL2輸出加總成為源極電流ISL。 When there are a plurality of memory cells T, the source line SL1 or SL2 is coupled to the sources of the memory cells T, and the current generated by the memory cells T passes through the source lines SL1~SL2 The sum of the outputs becomes the source current ISL.

更進一步說明,以第2圖為例,區塊BK1可包含耦接至字元線WL1的至少一組記憶體單元串,以及串選擇線SSL1。該記憶體單元串具有複數個相互耦接的記憶體單元T。於進行乘積累加運算時,在區塊BK1內的串選擇線SSL1被開啟。當字元線WL1被選擇時,與字元線WL1耦接的該些記憶體單元T將被導通,其中,字元線WL1上的該些記憶體單元T的權重可分別為W1與W2,而位元線BL1具有位元線電壓VBL1,位元線BL2具有位元線電壓VBL2,當進行乘積累加運算時,與字元線WL1耦接的該些記憶體單元T所產生的源極電流ISL1便可如下表示: ISL1=VBL1*W1+VBL2*W2。如果輸入與權重皆以邏輯位準表示,邏輯1為高位準,邏輯0為低位準,舉例而言,當VBL1=1,VBL2=0,W1=1,W2=1,則ISL1=1*1+0*1=1。 To further illustrate, taking FIG. 2 as an example, the block BK1 may include at least one memory cell string coupled to the word line WL1, and a string selection line SSL1. The memory cell string has a plurality of memory cells T coupled to each other. During the multiply-accumulate-add operation, the string selection line SSL1 in the block BK1 is turned on. When the word line WL1 is selected, the memory cells T coupled to the word line WL1 will be turned on, wherein the weights of the memory cells T on the word line WL1 can be W1 and W2, respectively. The bit line BL1 has a bit line voltage VBL1, and the bit line BL2 has a bit line voltage VBL2. When the multiply-accumulate operation is performed, the source current generated by the memory cells T coupled to the word line WL1 ISL1 can be expressed as follows: ISL1=VBL1*W1+VBL2*W2. If the input and weight are both expressed in logic level, logic 1 is high level and logic 0 is low level. For example, when VBL1=1, VBL2=0, W1=1, W2=1, then ISL1=1*1 +0*1=1.

再更進一步說明,仍以第2圖為例,區塊BK1具有複數組記憶體單元串,該些記憶體單元串相互耦接在一起,並且分別與對應的字元線(WL1~WLN)耦接。於進行乘積累加運算時,在區塊BK1內的串選擇線SSL1被選擇開啟。當有字元線WL1~WLN被選擇時,該些記憶體單元T將被導通,當進行乘積累加運算時,位元線電壓VBL1與VBL2與該些記憶體單元T的個別權重相乘加總,因而產生對應於區塊BK1的源極電流ISL1。同樣的,區塊BK2也具有複數組記憶體單元串,該些記憶體單元串相互耦接在一起,並且也分別與對應的字元線(WL1~WLN)耦接。於進行乘積累加運算時,在區塊BK2內的串選擇線SSL2被開啟時,同樣可產生對應於區塊BK2的源極電流ISL2。此時記憶體陣列110所輸出的源極電流ISL=ISL1+ISL2。 To further illustrate, still taking Fig. 2 as an example, the block BK1 has a complex array of memory cell strings, which are coupled to each other and are respectively coupled to the corresponding word lines (WL1~WLN) Pick up. During the multiply-accumulate-add operation, the string selection line SSL1 in the block BK1 is selectively turned on. When word lines WL1~WLN are selected, the memory cells T will be turned on. When multiplying and accumulating, the bit line voltages VBL1 and VBL2 are multiplied by the individual weights of the memory cells T and summed up. Therefore, the source current ISL1 corresponding to the block BK1 is generated. Similarly, the block BK2 also has a plurality of memory cell strings, which are coupled to each other and are also respectively coupled to the corresponding word lines (WL1~WLN). In the multiplication, accumulation and addition operation, when the string selection line SSL2 in the block BK2 is turned on, the source current ISL2 corresponding to the block BK2 can also be generated. At this time, the source current output by the memory array 110 is ISL=ISL1+ISL2.

因此,該些記憶體單元可經由前述方式被感應以產生源極電流ISL。亦即,記憶體陣列110所輸出的源極電流ISL為複數個區塊內的該些記憶體單元所產生的源極電流之總和。 Therefore, the memory cells can be induced to generate the source current ISL through the aforementioned method. That is, the source current ISL output by the memory array 110 is the sum of the source currents generated by the memory cells in a plurality of blocks.

第3圖繪示依照本發明一實施例的電流轉換電路 示意圖。電流轉換電路130A包括:電壓調整電路305、電晶體MP12~MP13、MN11~MN12,以及參考電流源IREF1。其中,電壓調整電路305可以是操作放大器A1與電晶體MP11所組成。 Figure 3 shows a current conversion circuit according to an embodiment of the present invention Schematic. The current conversion circuit 130A includes: a voltage adjustment circuit 305, transistors MP12~MP13, MN11~MN12, and a reference current source IREF1. Wherein, the voltage adjustment circuit 305 may be composed of an operational amplifier A1 and a transistor MP11.

操作放大器A1的兩輸入端分別耦接至參考電壓VREF與電晶體MP11的源極。操作放大器A1的輸出端則耦接至電晶體MP11的閘極。操作放大器A1與電晶體MP11用以提供穩定的電壓。詳言之,透過操作放大器A1的負回授機制,可使得電晶體MP11的源極電壓接近參考電壓VREF。由於電晶體MP11為導通,故而,使得電晶體MP11的汲極電壓也接近參考電壓VREF,亦即,節點N11的電壓可接近於參考電壓VREF,如此可使得源極電流ISL能穩定。 The two input terminals of the operational amplifier A1 are respectively coupled to the reference voltage VREF and the source of the transistor MP11. The output terminal of the operational amplifier A1 is coupled to the gate of the transistor MP11. The operational amplifier A1 and the transistor MP11 are used to provide a stable voltage. In detail, through the negative feedback mechanism of the operational amplifier A1, the source voltage of the transistor MP11 can be made close to the reference voltage VREF. Since the transistor MP11 is turned on, the drain voltage of the transistor MP11 is also close to the reference voltage VREF, that is, the voltage of the node N11 can be close to the reference voltage VREF, so that the source current ISL can be stabilized.

電晶體MP11具有一源極接收源極電流ISL;一閘極,耦接至操作放大器A1的輸出端;以及一汲極,耦接至節點N11。 The transistor MP11 has a source to receive the source current ISL; a gate coupled to the output terminal of the operational amplifier A1; and a drain coupled to the node N11.

電晶體MN11具有一源極與一閘極,耦接至節點N11;以及一汲極,耦接至參考電壓VSS,該參考電壓可以是一接地電壓。 The transistor MN11 has a source and a gate, which are coupled to the node N11, and a drain, which is coupled to the reference voltage VSS, which may be a ground voltage.

電晶體MN12具有一源極,耦接至一輸出端OUT1;一閘極,耦接至電晶體MN11的閘極;以及一汲極,耦接至參考電壓VSS。電晶體MN11與MN12形成一第一電流鏡,以鏡射源極電流ISL以產生電流I11。 The transistor MN12 has a source coupled to an output terminal OUT1; a gate coupled to the gate of the transistor MN11; and a drain coupled to the reference voltage VSS. The transistors MN11 and MN12 form a first current mirror to mirror the source current ISL to generate a current I11.

電晶體MP12具有一源極,耦接至一操作電壓VDD;一閘極,耦接至電晶體MP13的閘極(亦即,節點N12);以及一汲極,耦接至輸出端OUT1。 The transistor MP12 has a source coupled to an operating voltage VDD; a gate coupled to the gate of the transistor MP13 (ie, node N12); and a drain coupled to the output terminal OUT1.

電晶體MP13具有一源極,耦接至一操作電壓VDD;一閘極,耦接至電晶體MP12的閘極(亦即,節點N12)與參考電流源IREF1;以及一汲極,耦接至參考電流源IREF1。 Transistor MP13 has a source coupled to an operating voltage VDD; a gate coupled to the gate of transistor MP12 (ie, node N12) and the reference current source IREF1; and a drain coupled to Reference current source IREF1.

電晶體MP12與MP13形成一第二電流鏡,以鏡射參考電流IREF1以產生電流I12。 Transistors MP12 and MP13 form a second current mirror to mirror the reference current IREF1 to generate a current I12.

以下將說明電流轉換電路130A的操作。 The operation of the current conversion circuit 130A will be described below.

透過電晶體MP11與操作放大器A1,可使得節點N11的節點電壓約等於參考電壓VREF。透過由電晶體MN11與MN12所形成的第一電流鏡,可以在電晶體MN12的電流路徑上形成電流I11,其中,I11=ISL。 Through the transistor MP11 and the operational amplifier A1, the node voltage of the node N11 can be approximately equal to the reference voltage VREF. Through the first current mirror formed by the transistors MN11 and MN12, a current I11 can be formed on the current path of the transistor MN12, where I11=ISL.

相似地,透過由電晶體MP12與MP13所形成的第二電流鏡,可以在電晶體MP12的電流路徑上形成電流I12,其中,I12=IREF1。 Similarly, through the second current mirror formed by the transistors MP12 and MP13, a current I12 can be formed on the current path of the transistor MP12, where I12=IREF1.

因此,輸出端OUT1的電位可由電晶體MP12的上拉強度(pull up strength)與電晶體MN12的下拉強度(pull down strength)來決定。故而,如果電流I11(=源極電流ISL)大於電流I12(=參考電流IREF1),則OUT1所輸出的數值可為高位準,例如邏輯1;反之,如果電流I11(=源極電流ISL)小 於電流I12(=參考電流IREF1),則OUT1所輸出的數值可為低位準,例如邏輯0。在本案實施例中,參考電流IREF1的值是可以視需要而進行調整。例如,在一例中,參考電流IREF1的值可設定為數值M,而在另一例中,參考電流IREF1的值可設定數值M的倍數,例如但不限於2*M。 Therefore, the potential of the output terminal OUT1 can be determined by the pull up strength of the transistor MP12 and the pull down strength of the transistor MN12. Therefore, if the current I11 (=source current ISL) is greater than the current I12 (=reference current IREF1), the value output by OUT1 can be a high level, such as logic 1. On the contrary, if the current I11 (=source current ISL) is small At the current I12 (=reference current IREF1), the value output by OUT1 can be a low level, such as logic 0. In the embodiment of this case, the value of the reference current IREF1 can be adjusted as needed. For example, in one example, the value of the reference current IREF1 may be set to a value M, and in another example, the value of the reference current IREF1 may be set to a multiple of the value M, such as but not limited to 2*M.

亦即,透過第3圖的電流轉換電路130A可以得到乘積累加運算結果(OUT1),在第3圖中,OUT1即為輸出數值OUT_DC。 That is, through the current conversion circuit 130A in FIG. 3, the multiplying-accumulating-adding operation result (OUT1) can be obtained. In FIG. 3, OUT1 is the output value OUT_DC.

第4圖繪示依照本發明另一實施例的電流轉換電路示意圖。電流轉換電路130B包括:電壓調整電壓405、電晶體MP22~MP23、MN21~MN28_P(P為正整數),參考電流源IREF2,以及控制邏輯電路410。其中,電壓調整電路405可以是操作放大器A2與電晶體MP21所組成。 FIG. 4 is a schematic diagram of a current conversion circuit according to another embodiment of the invention. The current conversion circuit 130B includes: a voltage adjustment voltage 405, transistors MP22~MP23, MN21~MN28_P (P is a positive integer), a reference current source IREF2, and a control logic circuit 410. Wherein, the voltage adjustment circuit 405 may be composed of an operational amplifier A2 and a transistor MP21.

操作放大器A2、電晶體MP21~MP23、MN21與MN22的操作相同或相似於第3圖的操作放大器A1、電晶體MP11~MP13、MN11與MN12,故其操作細節在此省略。 The operation of the operational amplifier A2, the transistors MP21~MP23, MN21 and MN22 are the same or similar to the operation amplifier A1, the transistors MP11~MP13, MN11 and MN12 in Figure 3, so the operation details are omitted here.

控制邏輯電路410,在本實施例中,舉例而言,可以是逐次逼近型暫存器邏輯(SAR,Successive Approximation Register Logic)電路,控制邏輯電路410可以輸出致能信號(或稱為控制信號)EN0~ENP給電晶體MN26_0~MN26_P。電晶體MN25與MN26_0~MN26_P當成開關電晶體(亦可稱為開關電晶體群組),用以控制參考電流 IREF1的數值。其中,I22=IREF1。另,電晶體MN25的閘極接收偏壓電壓VB1,而偏壓電壓VB1使得電晶體MN25正常下為導通。致能信號EN0~ENP則控制電晶體MN26_0~MN26_P為導通或關閉。控制邏輯電路410根據電流I22與I21(亦即源極電流ISL,I21=ISL)而逐回合地產生該些致能信號EN0~ENP,該些致能信號EN0~ENP用以控制該開關電晶體群組,以決定參考電流IREF1的數值。 The control logic circuit 410, in this embodiment, for example, may be a Successive Approximation Register Logic (SAR, Successive Approximation Register Logic) circuit, and the control logic circuit 410 may output an enable signal (or called a control signal) EN0~ENP feed the transistors MN26_0~MN26_P. Transistors MN25 and MN26_0~MN26_P are used as switching transistors (also called switching transistor groups) to control the reference current The value of IREF1. Among them, I22=IREF1. In addition, the gate of the transistor MN25 receives the bias voltage VB1, and the bias voltage VB1 makes the transistor MN25 normally conductive. The enable signals EN0~ENP control the transistors MN26_0~MN26_P to be on or off. The control logic circuit 410 generates the enabling signals EN0~ENP one by one according to the currents I22 and I21 (ie, the source current ISL, I21=ISL), and the enabling signals EN0~ENP are used to control the switching transistors. Group to determine the value of the reference current IREF1.

參考電流源IREF2會流經電晶體MN24。電晶體MN24、MN27與MN28_0~MN28_P形成複數個電流鏡(亦可稱為電流鏡群組)。舉例而言,若電晶體MN24尺寸的寬長比為1,電晶體MN27尺寸的寬長比可為0.5,而電晶體MN28_0~MN28_P尺寸的寬長比可分別為20、21、...、2P。也就是說,流經電晶體MN27的電流為0.5*IREF2;如果電晶體MN26_0為導通,則流經電晶體MN28_0的電流為20*IREF2;如果電晶體MN26_1為導通,則流經電晶體MN28_1的電流為21*IREF2;其餘可依此類推。 The reference current source IREF2 will flow through the transistor MN24. Transistors MN24, MN27 and MN28_0~MN28_P form a plurality of current mirrors (also called current mirror groups). For example, if the aspect ratio of the size of transistor MN24 is 1, the aspect ratio of the size of transistor MN27 may be 0.5, and the aspect ratio of the size of transistors MN28_0~MN28_P may be 2 0 , 2 1 , .. ., 2 P. In other words, the current flowing through the transistor MN27 is 0.5*IREF2; if the transistor MN26_0 is on, the current flowing through the transistor MN28_0 is 2 0 *IREF2; if the transistor MN26_1 is on, it flows through the transistor MN28_1 The current is 2 1 *IREF2; the rest can be deduced by analogy.

以下將說明電流轉換電路130B的操作。 The operation of the current conversion circuit 130B will be explained below.

透過電晶體MP21、操作放大器A2、電晶體MN21與MN22,可以在電晶體MN22的電流路徑上形成電流I21,其中,I21=ISL。亦即,透過由電晶體MN21與MN22所形成的第三電流鏡來鏡射源極電流ISL以產生電流I21。 Through the transistor MP21, the operational amplifier A2, the transistors MN21 and MN22, a current I21 can be formed on the current path of the transistor MN22, where I21=ISL. That is, the source current ISL is mirrored through the third current mirror formed by the transistors MN21 and MN22 to generate the current I21.

相似地,透過由電晶體MP22與MP23所形成的 電流鏡,可以在電晶體MP22的電流路徑上形成電流I22,其中,電流I22可為電晶體MN27與MN28_0~MN28_P的電流總和。亦即,透過由MP22與MP23所形成的第四電流鏡來鏡射參考電流IREF1以產生電流I22。 Similarly, through the transistors MP22 and MP23 formed The current mirror can form a current I22 on the current path of the transistor MP22, where the current I22 can be the sum of the currents of the transistors MN27 and MN28_0~MN28_P. That is, the reference current IREF1 is mirrored through the fourth current mirror formed by MP22 and MP23 to generate the current I22.

如果電流I21(=源極電流ISL)大於電流I22,則OUT2所輸出的數值可為高位準,例如邏輯1;反之,如果電流I21(=源極電流ISL)小於電流I22,則OUT2所輸出的數值可為低位準,例如邏輯0。 If the current I21 (=source current ISL) is greater than the current I22, the value output by OUT2 can be a high level, such as logic 1. On the contrary, if the current I21 (=source current ISL) is less than the current I22, the output value of OUT2 The value can be a low level, such as logic 0.

透過逐回合地控制致能信號EN0~ENP,控制邏輯電路410可使得電流I22逐漸逼近源極電流ISL。當電流I22最逼近源極電流ISL時,控制邏輯電路410可以輸出該些致能信號EN0~ENP。 By controlling the enable signals EN0˜ENP round by round, the control logic circuit 410 can make the current I22 gradually approach the source current ISL. When the current I22 is closest to the source current ISL, the control logic circuit 410 can output the enabling signals EN0~ENP.

亦即,透過第4圖的電流轉換電路130B可以在電晶體MP23的電流路徑上產生參考電流IREF1。亦即,第4圖的電晶體MN24、參考電流源IREF2、控制邏輯電路410、電晶體MN25、電晶體MN26_0~MN26_P、電晶體MN27、電晶體MN28_0~MN28_P可用以產生第3圖的參考電流IREF1。 That is, the current conversion circuit 130B in FIG. 4 can generate the reference current IREF1 on the current path of the transistor MP23. That is, the transistor MN24, the reference current source IREF2, the control logic circuit 410, the transistor MN25, the transistor MN26_0~MN26_P, the transistor MN27, and the transistor MN28_0~MN28_P in Figure 4 can be used to generate the reference current IREF1 in Figure 3. .

第5圖繪示依照本發明又一實施例的電流轉換電路示意圖。電流轉換電路130C包括:電壓調整電路505、電晶體MN31~MN33、電阻RL與類比數位轉換器(ADC)510。其中,電壓調整電路505可以是操作放大器A3與電晶體MP31所組成。第5圖的電流轉換電路130C可以得到Q位元解析度 的乘積累加運算結果OUT_DC,其中,Q為正整數,其代表類比數位轉換器(ADC)510的解析度。 FIG. 5 is a schematic diagram of a current conversion circuit according to another embodiment of the invention. The current conversion circuit 130C includes: a voltage adjustment circuit 505, transistors MN31-MN33, a resistor RL, and an analog-to-digital converter (ADC) 510. Among them, the voltage adjustment circuit 505 may be composed of an operational amplifier A3 and a transistor MP31. The current conversion circuit 130C in Figure 5 can obtain Q-bit resolution The multiplying and accumulating operation result of OUT_DC, where Q is a positive integer, which represents the resolution of the analog-to-digital converter (ADC) 510.

操作放大器A3、電晶體MP31、MN31與MN32的操作相同或相似於第3圖的操作放大器A1、電晶體MP11、MN11與MN12,故其操作細節在此省略。 The operations of the operational amplifier A3, the transistors MP31, MN31, and MN32 are the same or similar to the operational amplifier A1, the transistors MP11, MN11, and MN12 in FIG. 3, so the operation details are omitted here.

電晶體MN33具有一源極,耦接電阻RL;一閘極,接收偏壓電壓VB2;以及一汲極,耦接至電晶體MN32的汲極。偏壓電壓VB2使得電晶體MN33在正常狀態下為導通。 The transistor MN33 has a source, which is coupled to the resistor RL; a gate, which receives the bias voltage VB2; and a drain, which is coupled to the drain of the transistor MN32. The bias voltage VB2 makes the transistor MN33 conductive in a normal state.

以下將說明電流轉換電路130C的操作。 The operation of the current conversion circuit 130C will be explained below.

透過電晶體MP31、操作放大器A3、電晶體MN31與MN32,可以在電晶體MN32的電流路徑上形成電流I3,其中,I3=ISL。亦即,透過由電晶體MN31與MN32所形成的第五電流鏡來鏡射源極電流ISL以產生電流I3。 Through the transistor MP31, the operational amplifier A3, the transistors MN31 and MN32, a current I3 can be formed on the current path of the transistor MN32, where I3=ISL. That is, the source current ISL is mirrored through the fifth current mirror formed by the transistors MN31 and MN32 to generate the current I3.

由於電流I3亦流經電阻RL,故而,節點N3的節點電壓為VDD-RL*I3,並將節點N3電壓傳送到ADC510電路。節點N3的電壓相關於源極電流ISL的電流值,ADC 510可將節點N3的電壓,轉換成乘積累加運算結果OUT_DC。 Since the current I3 also flows through the resistor RL, the node voltage of the node N3 is VDD-RL*I3, and the voltage of the node N3 is transmitted to the ADC510 circuit. The voltage of the node N3 is related to the current value of the source current ISL, and the ADC 510 can convert the voltage of the node N3 into a multiplication and accumulation operation result OUT_DC.

本案實施例應用源極端感應(source side sensing)來執行乘積累加運算。記憶體單元電流代表輸入(例如但不受限於,位元線電壓)與權重(例如但不受限於,記憶體單元電導)的乘積。多個記憶體單元的個別源極耦接至共同節點,則該 些記憶體單元的個別記憶體單元源極電流可被加總,以達成乘積累加運算的目的。所得到的乘積累加運算結果可以輸入給其他級的乘積累加運算,或是輸入到控制器(未示出)以當成特定資訊或特定圖樣(pattern)辨識,進而可以應用於AI、大數據、機器學習等需要大量資訊運算的領域。 In the embodiment of this case, source side sensing is used to perform multiplication, accumulation and addition operations. The memory cell current represents the product of the input (for example, but not limited to, the bit line voltage) and the weight (for example, but not limited to, the conductance of the memory cell). The individual sources of multiple memory cells are coupled to a common node, then the The source currents of individual memory cells of these memory cells can be summed to achieve the purpose of multiplying and accumulating. The result of the multiply accumulation and addition operation can be input to other stages of multiply accumulation and addition operations, or input to a controller (not shown) for identification of specific information or specific patterns, which can then be applied to AI, big data, and machines. Learning and other fields that require a lot of information computing.

在本案實施例中,記憶體裝置例如為3D NAND快閃記憶體裝置,但本案並不受限於此,本案亦可應用至其他類型的記憶體,此皆在本案精神範圍內。 In the embodiment of the present case, the memory device is, for example, a 3D NAND flash memory device, but the present case is not limited to this, and the present case can also be applied to other types of memory, which are all within the spirit of the present case.

在上例中,以位元線電壓當成輸入而記憶體單元電導當成權重,輸入乘上權重得到記憶體單元電流為例做說明,但當知本案並不受限於此。在本案其他可能實施例中,可以控制記憶體單元電流的任意參數組合也可以當成輸入或權重,例加,輸入可以是字元線電壓,而權重可以是記憶體單元的臨界電壓等,此皆在本案精神範圍內。 In the above example, the bit line voltage is used as the input and the memory cell conductance is used as the weight, and the input is multiplied by the weight to obtain the memory cell current as an example, but it should be understood that this case is not limited to this. In other possible embodiments of this case, any combination of parameters that can control the current of the memory cell can also be used as input or weight. For example, the input can be the word line voltage, and the weight can be the threshold voltage of the memory cell, etc. Within the spirit of this case.

綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100:記憶體裝置 100: Memory device

110:記憶體陣列 110: memory array

130:電流轉換電路 130: current conversion circuit

ISL:源極電流 ISL: Source current

OUT_DC:輸出數值 OUT_DC: output value

Claims (10)

一種記憶體裝置,包括:一記憶體陣列,包括複數個記憶體單元與複數條位元線;以及一電流轉換電路,耦接至該記憶體陣列,其中,於執行一乘積累加運算操作時,該記憶體陣列的該些記憶體單元產生相關於一乘積累加運算操作結果的一源極電流,以及該源極電流由該電流轉換電路轉換成一輸出數值,用以提供一下一運算操作的一輸入訊號;以及其中,該電流轉換電路包括:一電壓調整電路,耦接至該記憶體陣列,用以接收該源極電流。 A memory device includes: a memory array including a plurality of memory cells and a plurality of bit lines; and a current conversion circuit coupled to the memory array, wherein, when performing a multiply-accumulate-add operation, The memory cells of the memory array generate a source current related to the result of a multiply-accumulate-add operation, and the source current is converted into an output value by the current conversion circuit to provide an input for the next arithmetic operation Signal; and wherein, the current conversion circuit includes: a voltage adjustment circuit coupled to the memory array for receiving the source current. 如請求項1所述之記憶體裝置,其中,該電流轉換電路更包括:一第一電流鏡,耦接至該電壓調整電路,鏡射該源極電流以產生一第一電流;一第一參考電流源,產生一第一參考電流;以及一第二電流鏡,耦接至該第一電流鏡與該第一參考電流源,鏡射該第一參考電流以產生一第二電流;其中,依據該第一電流與該第二電流以產生該輸出數值。 The memory device according to claim 1, wherein the current conversion circuit further comprises: a first current mirror, coupled to the voltage adjustment circuit, and mirrors the source current to generate a first current; A reference current source generates a first reference current; and a second current mirror, coupled to the first current mirror and the first reference current source, mirrors the first reference current to generate a second current; wherein, The output value is generated according to the first current and the second current. 如請求項1所述之記憶體裝置,其中,該電流轉換電路更包括:一第三電流鏡,耦接至該電壓調整電路,鏡射該源極電流以產生一第三電流;一第二參考電流源,產生一第二參考電流;一第四電流鏡,耦接至該第三電流鏡;一開關電晶體群組,耦接至該第四電流鏡;以及一電流鏡群組,耦接至該開關電晶體群組與該第二參考電流源,用以鏡射該第二參考電流以產生一第四電流;其中,該開關電晶體群組用以決定該第四電流;以及依據該第三電流與該第四電流以決定該輸出數值。 The memory device according to claim 1, wherein the current conversion circuit further comprises: a third current mirror, coupled to the voltage adjustment circuit, and mirrors the source current to generate a third current; and a second The reference current source generates a second reference current; a fourth current mirror coupled to the third current mirror; a switching transistor group coupled to the fourth current mirror; and a current mirror group coupled Connected to the switching transistor group and the second reference current source for mirroring the second reference current to generate a fourth current; wherein, the switching transistor group is used for determining the fourth current; and according to The third current and the fourth current are used to determine the output value. 如請求項3所述之記憶體裝置,其中,該電流轉換電路更包括一控制邏輯電路,耦接至該開關電晶體群組,該控制邏輯電路根據該第四電流與該源極電流而逐回合地產生複數個致能信號,該些致能信號用以控制該開關電晶體群組。 The memory device according to claim 3, wherein the current conversion circuit further includes a control logic circuit coupled to the switching transistor group, and the control logic circuit sequentially changes according to the fourth current and the source current A plurality of enabling signals are generated in rounds, and the enabling signals are used to control the switching transistor group. 如請求項4所述之記憶體裝置,其中,該控制邏輯電路為一逐次逼近型暫存器邏輯電路。 The memory device according to claim 4, wherein the control logic circuit is a successive approximation type register logic circuit. 如請求項1所述之記憶體裝置,其中,該電流轉換電路更包括:一第五電流鏡,耦接至該電壓調整電路,鏡射該源極電流以產生一第五電流;以及 一類比數位轉換器,將相關於該第五電流的一節點電壓轉換成該輸出數值。 The memory device of claim 1, wherein the current conversion circuit further comprises: a fifth current mirror, coupled to the voltage adjustment circuit, and mirrors the source current to generate a fifth current; and An analog-to-digital converter converts a node voltage related to the fifth current into the output value. 如請求項1所述之記憶體裝置,其中,該源極電流為複數個權重與複數個輸入的乘積之和。 The memory device according to claim 1, wherein the source current is a sum of products of a plurality of weights and a plurality of inputs. 如請求項7所述之記憶體裝置,其中,該權重包括:一記憶體單元電導或一記憶體單元臨界電壓,而該些輸入包括一位元線電壓或一字元線電壓。 The memory device according to claim 7, wherein the weight includes a memory cell conductance or a memory cell threshold voltage, and the inputs include a bit line voltage or a word line voltage. 一種記憶體裝置的操作方法,該記憶體裝置包括一記憶體陣列與一電流轉換電路,該記憶體陣列包括複數個記憶體單元與複數條位元線,該操作方法包括:於執行一乘積累加運算操作時,該記憶體陣列的該些記憶體單元產生相關於一乘積累加運算操作結果的一源極電流;以及將該源極電流轉換成一輸出數值,用以提供一下一運算操作的一輸入訊號;其中,該電流轉換電路包括:一電壓調整電路,耦接至該記憶體陣列,用以接收該源極電流。 An operation method of a memory device, the memory device includes a memory array and a current conversion circuit, the memory array includes a plurality of memory cells and a plurality of bit lines, the operation method includes: performing a multiplication accumulation addition During an operation, the memory cells of the memory array generate a source current related to the result of a multiply-accumulate-add operation; and convert the source current into an output value to provide an input for the next operation Signal; wherein, the current conversion circuit includes: a voltage adjustment circuit coupled to the memory array for receiving the source current. 如請求項9所述之記憶體裝置的操作方法,其中,該源極電流為複數個權重與複數個輸入的乘積之和;該權重包括:一記憶體單元電導或一記憶體單元臨界電壓;以及 該些輸入包括一位元線電壓或一字元線電壓。 The operating method of a memory device according to claim 9, wherein the source current is the sum of the product of a plurality of weights and a plurality of inputs; the weight includes: a memory cell conductance or a memory cell threshold voltage; as well as The inputs include one-bit line voltage or one-word line voltage.
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