CN115796252A - Weight writing method and device, electronic equipment and storage medium - Google Patents
Weight writing method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
A weight writing method and device applied to a neural network of a memristor array, electronic equipment and a storage medium. The weight writing method comprises the following steps: acquiring a target weight value written into a target memristor unit in a memristor array and an error amplitude used for writing the target weight value, wherein the error amplitude is determined based on probability distribution corresponding to the target weight value; acquiring a current weight value of a target memristor unit; judging whether the absolute value of the difference between the current weight value and the target weight value is within the error range; in response to an absolute value of a difference between the current weight value and the target weight value being within a margin of error, determining that the target weight value has been written to the target memristor cell. The weight writing method can improve the efficiency of writing the weights of the neural network into the memristor array.
Description
Technical Field
Embodiments of the present disclosure relate to a weight writing method and apparatus, an electronic device, and a storage medium applied to a neural network of a memristor array.
Background
A memristor is a non-volatile device whose conduction state can be adjusted by applying an external stimulus. According to kirchhoff's current law and ohm's law, an array formed by memristors can complete multiplication and accumulation calculation in parallel, and storage and calculation both occur in each device of the array. Based on the computing architecture, the storage and computation integrated computing without a large amount of data movement can be realized. Meanwhile, multiply-accumulate is the core computational task required to run neural networks. Thus, using the conductances of the memristors in the array to represent the weight values, energy-efficient neural network operations may be implemented based on such computational-integrated calculations. In neural network operations, the conductance values of memristors on a memristor array represent synaptic weights in the neural network.
Disclosure of Invention
At least one embodiment of the present disclosure provides a weight writing method applied to a neural network of a memristor array, including: acquiring a target weight value to be written into a target memristor unit in the memristor array and an error amplitude for writing the target weight value, wherein the error amplitude is determined based on a probability distribution corresponding to the target weight value; obtaining a current weight value of the target memristor unit; judging whether the absolute value of the difference between the current weight value and the target weight value is within the error amplitude; determining that the target weight value has been written to the target memristor cell in response to an absolute value of a difference between the current weight value and the target weight value being within the margin of error.
For example, in a weight writing method provided in at least one embodiment of the present disclosure, the probability distribution is a gaussian distribution, the target weight value is a mean value of the gaussian distribution, and the error magnitude is determined based on a standard deviation of the gaussian distribution.
For example, in a weight writing method provided in at least one embodiment of the present disclosure, the error magnitude is positively correlated with the standard deviation.
For example, in the weight writing method provided in at least one embodiment of the present disclosure, the error magnitude is a product of the standard deviation and a scaling factor, and the scaling factor is greater than 1.
For example, in a weight writing method provided by at least one embodiment of the present disclosure, a target memristor cell includes a first memristor and a second memristor, and obtaining the current weight value of the target memristor cell includes: obtaining a conductance value of the first memristor and a conductance value of the second memristor; calculating a difference between the conductance value of the first memristor and the conductance value of the second memristor, the difference being the current weight value.
For example, in a weight writing method provided in at least one embodiment of the present disclosure, the method further includes: in response to an absolute value of a difference between the current weight value and the target weight value not being within the margin of error, programming the target memristor cell until the absolute value of the difference between the current weight value and the target weight value is within the margin of error.
For example, in a weight writing method provided in at least one embodiment of the present disclosure, the neural network is a bayesian neural network, and the weight writing method further includes: training the Bayesian neural network to obtain a training result, wherein the training result includes a plurality of weights in the Bayesian neural network, the weights are mapped to conductance values of a plurality of memristor units included in a memristor array, the memristor units include the target memristor unit, and acquiring the target weight values written into the target memristor units in the memristor array includes: determining a target weight value written to the target memristor cell from the plurality of weights.
For example, in a weight writing method provided in at least one embodiment of the present disclosure, training the bayesian neural network to obtain a training result includes: acquiring a prior standard deviation applied to the Bayesian neural network; and training the Bayesian neural network based on the prior standard deviation to obtain the training result.
For example, in a weight writing method provided by at least one embodiment of the present disclosure, the a priori standard deviation includes a weight fluctuation standard deviation of the memristor array based on the conductance values of the memristors.
For example, in a weight writing method provided in at least one embodiment of the present disclosure, training the bayesian neural network based on the prior standard deviation to obtain the training result includes: calculating a total loss function of the Bayesian neural network based on the weight fluctuation standard deviation; performing back propagation on the total loss function so as to update the current weight value in the Bayesian neural network to obtain an object weight value; obtaining a constraint condition of the object weight value; and constraining the object weight values based on the constraint conditions to obtain training results of the multiple weights of the Bayesian neural network.
For example, in the weight writing method provided in at least one embodiment of the present disclosure, the prior standard deviation is determined based on prior knowledge of a learning task for which the bayesian neural network is intended.
For example, in a weight writing method provided in at least one embodiment of the present disclosure, the method further includes: acquiring a deep neural network operated by the memristor array; in response to the deep neural network not being the Bayesian neural network, converting the deep neural network into the Bayesian neural network, the Bayesian neural network having the same network structure as the deep neural network.
At least one embodiment of the present disclosure also provides a weight writing apparatus applied to a neural network of a memristor array, including: a first obtaining unit configured to obtain a target weight value written to a target memristor cell in the memristor array and an error magnitude for writing the target weight value, the error magnitude being determined based on a probability distribution corresponding to the target weight value; a second obtaining unit configured to obtain a current weight value of the target memristor cell; a judging unit configured to judge whether an absolute value of a difference between the current weight value and the target weight value is within the error margin; a determination unit configured to determine that the target weight value has been written to the target memristor cell in response to an absolute value of a difference between the current weight value and the target weight value being within the margin of error.
At least one embodiment of the present disclosure also provides an electronic device including: a processor; a memory storing one or more computer program instructions; the one or more computer program instructions, when executed by the processor, are for implementing the weight writing method provided by any embodiment of the present disclosure.
At least one embodiment of the present disclosure also provides a computer-readable storage medium, which non-transitory stores computer-readable instructions for implementing the weight writing method provided by any one of the embodiments of the present disclosure when the computer-readable instructions are executed by a processor.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
FIG. 1A shows a schematic structure of a memristor array;
FIG. 1B is a schematic diagram of a memristor device;
FIG. 1C is a schematic diagram of another memristor device;
FIG. 1D illustrates a schematic diagram of mapping a weight matrix of a Bayesian neural network to a memristor array;
fig. 2 illustrates a schematic flow chart of a weight writing method applied to a neural network of a memristor array provided by at least one embodiment of the present disclosure;
fig. 3A is a flowchart of a method of step S20 in fig. 2 according to at least one embodiment of the present disclosure;
fig. 3B is a schematic block diagram of a memristor array provided by at least one embodiment of the present disclosure;
FIG. 3C is a schematic diagram of another memristor array provided by at least one embodiment of the present disclosure;
fig. 4 illustrates a flowchart of a method for training a bayesian neural network to obtain a training result according to at least one embodiment of the present disclosure;
fig. 5 illustrates a flowchart of a method of step S402 in fig. 4 according to at least one embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating another weight writing method provided by at least one embodiment of the present disclosure;
fig. 7 illustrates a flow chart of another weight writing method provided by at least one embodiment of the present disclosure;
fig. 8 illustrates a schematic block diagram of a weight writing apparatus applied to a neural network of a memristor array, provided by at least one embodiment of the present disclosure;
fig. 9 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;
fig. 10 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure;
fig. 11 is a schematic diagram of a storage medium according to some embodiments of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
To write an external offline trained neural network model onto the memristor array, the memristor cells are programmed to the target conductance state within an acceptable error range using a write-verify operation. The write-verify operation can greatly reduce the deviation between the weights in the neural network and the conductance values written into the memristors, and the network performance is almost unchanged. For example, the write-verify operation includes programming the memristor (i.e., writing a required conductance value into the memristor), reading a conductance value of the memristor, comparing whether an absolute value of a difference between the read conductance value and a weight value of the memristor is within an error range, if the absolute value of the difference between the read conductance value and the weight value of the memristor is within the error range, passing the write-verify, and if the absolute value of the difference between the read conductance value and the weight value of the memristor is not within the error range, continuing to perform the write-verify operation again until the absolute value of the difference between the read conductance value and the weight value of the memristor is within the error range. Thus, the write verification process is very energy and time consuming because it requires a large number of on-chip read and program operations. In large scale memristor array applications that require reprogramming for different tasks, large time consuming and power consuming is unacceptable. Applications such as moving edge computing place high demands on high speed and efficient write verification schemes. However, there is still a lack of a high speed and efficient solution for weight-writing memristor arrays.
To this end, at least one embodiment of the present disclosure provides a weight writing method applied to a neural network of a memristor array. The weight writing method comprises the following steps: acquiring a target weight value written into a target memristor unit in the memristor array and an error magnitude used for writing the target weight value, wherein the error magnitude is determined based on a probability distribution corresponding to the target weight value; obtaining a current weight value of the target memristor unit; judging whether the absolute value of the difference between the current weight value and the target weight value is within the error amplitude; determining that the target weight value has been written to the target memristor cell in response to an absolute value of a difference between the current weight value and the target weight value being within the margin of error.
The weight writing method can set a proper error amplitude according to the probability distribution corresponding to the target weight values, so that the error amplitudes of some target weight values can be properly relaxed, reading and programming operations are reduced, and the efficiency of writing the weights into the memristor array is improved.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.
Fig. 1A shows a schematic structure of a memristor array, e.g., made up of a plurality of memristor cells making up an array of M rows and N columns, both M and N being positive integers. Each memristor cell includes one or more switching elements and one or more memristors, and in different examples, the memristor cell may be a 1T1R structure (i.e., one transistor and one memristor) or a 2T2R structure (i.e., two transistors and two memristors). In fig. 1A, WL <1>, WL <2>... WL < M > denote word lines of the first and second rows, respectively, and the control electrodes (e.g., gates of transistors) of the switching elements in the memristor cell circuits of each row are connected to the corresponding word line of the row; BL <1>, BL <2>. The.. Gth BL < N > respectively represent bit lines of a first column and a second column, the memristor in the memristor unit circuit of each column is connected with the corresponding bit line of the column; SL <1>, SL <2>. The.. SL < M > respectively represent the source lines of the first and second rows, the source of the transistor in the memristor unit circuit of each row is connected with the source line corresponding to the row. According to kirchhoff's law, the memristor array may perform multiply-accumulate calculations in parallel by setting the state (e.g., resistance) of the memristor cell and applying corresponding word line and bit line signals on the word line and bit line.
FIG. 1B is a schematic diagram of a memristor device including a memristor array and its peripheral drive circuitry. For example, as shown in fig. 1B, the memristor device includes a signal acquisition device, a word line driver circuit, a bit line driver circuit, a source line driver circuit, a memristor array, and a data output circuit.
For example, the signal obtaining device is configured to convert the Digital signal into a plurality of Analog signals through a Digital-to-Analog converter (DAC) to be input to a plurality of column signal input terminals of the memristor array.
For example, a memristor array includes M source lines, M word lines, and N bit lines, and a plurality of memristor cells arranged in an array of M rows and N columns.
For example, operation of the memristor array is accomplished by word line driver circuits, bit line driver circuits, and source line driver circuits.
For example, the wordline driver circuit includes a plurality of multiplexers (Mux) for switching the wordline input voltages; the bit line driving circuit includes a plurality of multiplexers for switching bit line input voltages; the source line driving circuit also includes a plurality of multiplexers (Mux) for switching source line input voltages. For example, the source line driving circuit further includes a plurality of ADCs for converting analog signals into digital signals. In addition, a Trans-Impedance Amplifier (TIA) (not shown in the figure) may be further disposed between the Mux and the ADC in the source line driving circuit to complete the current-to-voltage conversion for the ADC processing.
For example, a memristor array includes an operational mode and a computational mode. When the memristor array is in an operational mode, the memristor cells are in an initialized state, and values of parameter elements in the parameter matrix may be written into the memristor array. For example, a source line input voltage, a bit line input voltage, and a word line input voltage of the memristor are switched to corresponding preset voltage intervals by the multiplexer.
For example, the word line input voltage is switched to the corresponding voltage interval by the control signal WL _ sw [1 m ] of the multiplexer in the word line driving circuit in fig. 1B. For example, the word line input voltage is set to 2V (volts) when a set operation is performed on the memristor, and is set to 5V when a reset operation is performed on the memristor, for example, the word line input voltage may be obtained by the voltage signal V _ WL [1 m ] in fig. 1B.
For example, the source line input voltage is switched to the corresponding voltage section by the control signal SL _ sw [1 m ] of the multiplexer in the source line driving circuit in fig. 1B. For example, the source line input voltage is set to 0V when a set operation is performed on the memristor, and is set to 2V when a reset operation is performed on the memristor, for example, the source line input voltage can be obtained by the voltage signal V _ SL [1 m ] in fig. 1B.
For example, the bit line input voltage is switched to the corresponding voltage interval by the control signal BL _ sw [ 1. The bit line input voltage is set to 2V, for example, when a set operation is performed on the memristor, and is set to 0V, for example, when a reset operation is performed on the memristor, for example, the bit line input voltage may be obtained by the DAC in fig. 1B.
For example, when the memristor array is in a compute mode, the memristors in the memristor array are in a conductive state available for computation, and the bit line input voltage input by the column signal input does not change the conductance values of the memristors, e.g., the computation may be completed by the memristor array performing a multiply-add operation. For example, the word line input voltage is switched to the corresponding voltage interval by the control signal WL _ sw [1 m ] of the multiplexer in the word line driving circuit in fig. 1B, for example, when the on signal is applied, the word line input voltage of the corresponding row is set to 5V, for example, when the on signal is not applied, the word line input voltage of the corresponding row is set to 0V, for example, the GND signal is turned on; the source line input voltage is switched to a corresponding voltage interval by a control signal SL _ sw [ 1.
For example, the data output circuit may include a plurality of trans-impedance amplifiers (TIAs), ADCs, and may convert current signals of the plurality of row signal output terminals into voltage signals and then into digital signals for subsequent processing.
FIG. 1C is a schematic diagram of another memristor device. The memristor device shown in fig. 1C has substantially the same structure as the memristor device shown in fig. 1B, and also includes a memristor array and its peripheral driver circuit. For example, as shown in fig. 1C, the memristor device includes a signal acquisition device, a word line drive circuit, a bit line drive circuit, a source line drive circuit, a memristor array, and a data output circuit.
For example, a memristor array includes M source lines, 2M word lines, and 2N bit lines, and a plurality of memristor cells arranged in an array of M rows and N columns. For example, each memristor cell is a 2T2R structure, by which a mapping for positive values as well as negative values may be achieved. The operation of mapping the parameter matrix for the transformation process to a plurality of different memristor cells in the memristor array is not described herein. It should be noted that the memristor array may also include M source lines, M word lines, and 2N bit lines, and a plurality of memristor units arranged in an array of M rows and N columns.
The description of the signal acquisition device, the control driving circuit and the data output circuit can refer to the previous description, and is not repeated here.
For example, in some embodiments of the present disclosure, memristor arrays are used for weight writing of bayesian neural networks. The Bayes neural network is a probability model which puts the neural network into a Bayes framework and can describe complex random patterns. To account for uncertainty in the weights, a Bayesian model can preferably be constructed. Under the bayesian model, the weights are not represented by a single value, but by a probability distribution. Given the observed data, the distribution weighted by the bayesian model is called the posterior distribution. As an analog to deriving the best certainty model by gradient-based updating, bayesian machine learning aims at learning approximations of the posterior distribution.
Given a data set D, the training goal of the bayesian neural network is to optimize the posterior distribution of weights p (w | D) using bayes' theorem:
where p (w) is the prior weight distribution, p (D | w) = p (y | x, w) is the likelihood corresponding to the bayesian neural network output, and p (D) is the edge likelihood, i.e., evidence. Since the true posterior distribution p (w | D) is difficult to achieve, the true posterior is not directly calculated, but is usually approximated using an inference method. For example, a posterior distribution of weights of a bayesian neural network is approximated by a variation learning method.
Variational learning is to find the parameter θ of the distribution q (w | θ) of weights of the bayesian neural network so that the KL (Kullback-Leibler) divergence between this distribution and the true posterior distribution is minimized. The KL divergence is used to measure the degree of closeness between the distribution q (w | θ) and the true posterior distribution. The KL divergence, also known as relative entropy or information divergence, is a measure of asymmetry in the difference between two probability distributions. By mathematical transformation, the goal of minimizing the KL divergence between q (w | θ) and p (w | D) can be expressed as:
the first two terms can be optimized by a back propagation algorithm during optimization: KL (q (w | θ) | p (w)) and E q(w|θ) [ logp (D | w). Where KL (q (w | θ) | p (w)) is referred to as the complexity cost term, E q(e|θ) [ logp (D | w) is called likelihood cost term. For a gaussian distributed weight, θ is equivalent to the mean μ and standard deviation σ, then the a posteriori (w | θ) can be expressed as:
BNN derives the a posteriori weight distributions from a priori p (w) and likelihood probabilities p (D | w). This main feature introduces the weight uncertainty of the network into the learning process. Thus, the learned weight parameters and calculations are robust under weight perturbation.
FIG. 1D illustrates a process of mapping a weight matrix of a neural network to a memristor array. A weight matrix between layers in a Bayesian neural network is realized by utilizing a memristor array, distribution corresponding to each weight is realized by using N memristors, N is an integer larger than or equal to 1, and the N memristors can be used as a memristor unit. And calculating N conductance values according to the random probability distribution corresponding to the weight, and mapping the N conductance values to the N memristors. In this manner, the weight matrix in the bayesian neural network is converted into target conductance values that are mapped into a cross sequence of memristor arrays.
As shown in fig. 1D, the left side of the diagram is a three-layer bayesian neural network that includes 3 layers of neuron layers connected one by one. For example, the input layer includes a layer 1 neuron layer, the hidden layer includes a layer 2 neuron layer, and the output layer includes a layer 3 neuron layer. For example, the input layer passes the received input data to the hidden layer, the hidden layer performs computational transformation on the input data and sends the transformed input data to the output layer, and the output layer outputs the output structure of the bayesian neural network.
As shown in fig. 1D, the input layer, the hidden layer and the output layer each include a plurality of neuron nodes, and the number of neuron nodes in each layer may be determined according toDifferent application settings. For example, the number of neurons in the input layer is 2 (including N) 1 And N 2 ) The number of neurons in the intermediate hidden layer is 3 (including N) 3 、N 4 And N 5 ) The number of neurons in the output layer is 1 (including N) 6 )。
As shown in fig. 1D, two adjacent neuron layers of the bayesian neural network are connected through a weight matrix. For example, the weight matrix is implemented by the memristor array as shown on the right side of FIG. 1D.
The structure of the memristor array on the right in fig. 1D is, for example, as shown in fig. 1A, and the memristor array may include a plurality of memristors arranged in an array. In the example shown in FIG. 1D, the weights are mapped to the conductances of the memristor array according to some rule, and the weight between the connecting input N1 and the output N3 is made up of 3 memristors (G) 11 、G 12 、G 13 ) Implementation, other weights in the weight matrix may be implemented identically. More specifically, the source line SL 1 Corresponding neuron N 3 Source line SL 2 Corresponding neuron N 4 Source line SL 5 Corresponding neuron N 5 Bit line BL 1 、BL 2 And BL 3 Corresponding to neuron N1, a weight between the input layer and the hidden layer (neuron N) 1 And neuron N 3 Weight therebetween) are converted into three target conductance values according to distribution, and the three target conductance values are distributed and mapped into a cross sequence of the memristor array, wherein the target conductance values are respectively G 11 、G 12 And G 13 Boxed with dashed lines in the memristor array.
In other embodiments of the present disclosure, the weights in the weight matrix are programmed directly to the conductance of the memristor array, i.e., the weights in the weight matrix correspond one-to-one with the memristors in the memristor array. Each weight is implemented using 1 memristor to correspond to that weight.
In other embodiments of the present disclosure, a difference in conductance of two memristors may also be utilized to represent a weight. For example, the difference in conductance of two memristors of the same column and adjacent rows represents one weight. That is, each weight is implemented using 2 memristors to correspond to that weight.
Fig. 1D describes an embodiment in which a weight matrix of a bayesian neural network is mapped to a memristor array, but is merely exemplary and not limiting of the present disclosure.
Fig. 2 illustrates a schematic flow chart of a weight writing method applied to a neural network of a memristor array, provided by at least one embodiment of the present disclosure.
As shown in fig. 2, the weight writing method includes the following steps S10 to S40.
Step S10: and acquiring a target weight value written into a target memristor unit in the memristor array and an error amplitude used for writing the target weight value, wherein the error amplitude is determined based on probability distribution corresponding to the target weight value.
Step S20: and acquiring a current weight value of the target memristor unit.
Step S30: and judging whether the absolute value of the difference between the current weight value and the target weight value is within the error range.
Step S40: in response to an absolute value of a difference between the current weight value and the target weight value being within a margin of error, determining that the target weight value has been written to the target memristor cell.
According to the weight writing method provided by the embodiment of the disclosure, the error amplitudes are set according to the probability distribution of the target weight values, and compared with a scheme that the error amplitudes of all the target weight values are the same, the error amplitudes of some weights can be properly relaxed, so that the time and energy consumed by the writing and verifying operation are reduced, and the writing efficiency of the weight writing memristor array of the neural network is improved.
It should be noted that, although the foregoing describes mapping of weights of the bayesian neural network to the memristor array as an example, this does not mean that the weight writing method provided by the embodiment of the present disclosure is only applicable to the bayesian neural network. In fact, the weight writing method provided by the embodiment of the present disclosure is applicable to any neural network capable of performing neural network computation by using a memristor array, such as a convolutional neural network, a recurrent neural network, a generation countermeasure neural network, and the like.
For example, the neural network includes a weight matrix, and weights in the weight matrix need to be deployed into the memristor array to perform a fast multiply-add operation with the memristor array. For example, the weights of the weight matrix correspond to memristor cells in a memristor array, each memristor cell including N memristors, N being greater than or equal to 1. The target weight may be any parameter value in the weight matrix.
For step S10, the target memristor cell may be a memristor cell corresponding to the target weight value among a plurality of memristor cells included in the memristor array.
In some embodiments of the present disclosure, the target weight values to be written to the target memristor cells may be considered samples resulting from a certain distribution. For example, consider the weight of a memristor cell representation as following a Gaussian distribution N (μ, σ) in BNN 2 ) Is not determined. The average value μ is the target weight value of the memristor cell to be written onto the memristor array.
For example, the probability density at 0 is determined according to the probability distribution to which the target weight value obeys. If the probability density of the probability distribution of the obedience of the target weight value at 0 is large, the influence of the target weight value on the performance of the neural network is small, and a large error amplitude can be set.
For example, the probability distribution in the embodiment of the present disclosure is a gaussian distribution, that is, the target weight value follows the gaussian distribution, the target weight value is a mean value of the gaussian distribution, and the error magnitude is determined based on a standard deviation of the gaussian distribution. The larger the standard deviation sigma is, the larger the acceptable deviation of the weight is, and the larger the error amplitude of the write verification can be, so that the error amplitude of the weight with the larger acceptable deviation is properly relaxed, the read and program (i.e. write) operations of the weight with the larger acceptable deviation are reduced, and the efficiency of writing the weight into the memristor is improved on the basis of ensuring the performance of the neural network.
For example, the magnitude of the error is positively correlated with the standard deviation. For example, the error amplitude EM i,j Is standard deviation σ i,j Multiplication by a scaling factor k, the scaling factor k being greater than 1, i.e. EM i,j ＝k·σ i,j . For example, the scaling factor k is the same for each weight. Those skilled in the art can learn from neural networksAnd the task determines the value of k. For example, for a neural network with higher identification accuracy, the value of the scaling factor k may be larger, and for a neural network with higher identification accuracy, the value of the scaling factor k may be smaller. The performance of the neural network is insensitive to some degree of bias (related to σ) of the memristor weights, which is guaranteed by the training method of the neural network. In other words, it is not necessary to use a small same error range for verification during the write verification process, and therefore the proportionality coefficient k is larger than 1, so that the error amplitude is properly relaxed and the write efficiency is improved.
In the embodiment of the present disclosure, the probability distribution is not limited to the gaussian distribution, and may be a Weibull (Weibull) distribution or the like, for example.
For step S20, the current weight value of the target memristor cell is read, for example. For example, a voltage signal is applied to the target memristor unit, and a current signal output by the target memristor unit is read, so that a current conductance value, that is, a current weight value of the target memristor unit is obtained by using ohm's law.
For step S30 and step S40, for example, the current weight value W is calculated i,j And target weight value
Absolute value of the difference of (2)
Judgment of
Whether is less than EM i,j . If it is
Less than EM i,j Determining a target weight value
The target memristor cell has been written.
As shown in fig. 2, the weight writing method includes step S50 in addition to steps S10 to S40.
Step S50: in response to an absolute value of a difference between the current weight value and the target weight value not being within a margin of error, programming the target memristor cell until the absolute value of the difference between the current weight value and the target weight value is within the margin of error.
For example,
greater than or equal to EM i,j Then according to
And EM i,j Until the absolute value of the difference between the current weight and the target weight is within the margin of error. For example, if the current weight value W i,j Less than target weight value
And applying voltage to the target memristor unit to increase the conductance value of the target memristor unit, so as to increase the current weight value and reduce the absolute value of the difference between the current weight value and the target weight value.
Fig. 3A is a flowchart of a method in step S20 in fig. 2 according to at least one embodiment of the present disclosure. In this embodiment, the target memristor cell includes a first memristor and a second memristor.
Fig. 3B is a schematic block diagram of a memristor array provided in at least one embodiment of the present disclosure.
As shown in FIG. 3B, the memristor 301 and the memristor 302 may form a memristor pair, the conductance value of the memristor 301 being represented as G 11 The conductance value of the memristor 302 is denoted as G 12 . Since the memristor 302 is connected to an inverter, when the memristor 301 receives an input voltage signal of positive polarity, the inverter may invert the polarity of the input voltage signal, thereby causing the memristor 302 to receive an input voltage signal of negative polarity. For example, the input voltage signal received by the memristor 301 is denoted by v (t), and the input voltage signal received by the memristor 302 is denoted by-v (t). Memristors 301 and 302 are connected to two different SLs, with an input voltage signal passing through the memristorsThe resistor generates an output current. The output current through the memristor 301 and the output current through the memristor 302 are superimposed at the SL termination. Thus, the result of the multiply-accumulate computation of memristors 301 and 302 is v (t) G 11 +(-v(t))G 12 I.e. v (t) (G) 11 -G 12 ). Thus, a memristor pair consisting of memristor 301 and memristor 302 may correspond to a weight, and the weight value is G 11 -G 12 By configuration G 11 -G 12 The numerical relationship of (c) can implement positive, zero, negative values of the element.
Fig. 3C is a schematic diagram of another memristor array provided by at least one embodiment of the present disclosure.
As shown in FIG. 3C, for example, memristor 301 and memristor 302 may constitute a memristor pair, with the conductance value of memristor 301 being represented as G 11 The conductance value of the memristor 302 is denoted as G 12 . Unlike FIG. 3A, the memristor 302 is not connected to an inverter, so when the memristor 301 receives a positive polarity input voltage signal, the memristor 302 also receives a positive polarity input voltage signal. For example, the input voltage signal received by the memristor 301 is denoted by v (t), and the input voltage signal received by the memristor 302 is also denoted by v (t). Memristors 301 and 302 are connected to two different SLs, and the output current through memristor 301 and the output current through memristor 302 are subtracted at the ends of the SLs. Therefore, the result of the multiply-accumulate calculation for memristors 301 and 302 is v (t) G 11 -v(t)G 12 I.e. v 0 (t)(G 11 -G 12 ). Thus, the memristor pair of memristors 301 and 302 may have a weight, and the weight value is G 11 -G 12 By configuration G 11 -G 12 The numerical relationship of (c) can implement positive, zero, negative values of the element.
As shown in fig. 3A, step S20 includes step S21 and step S22.
Step S21: a conductance value of the first memristor and a conductance value of the second memristor are obtained.
Step S22: and calculating a difference value between the conductance value of the first memristor and the conductance value of the second memristor, wherein the difference value is the current weight value.
For example, the memristor cells corresponding to the target weight values include first and second memristors, which are the memristors 601 and 602, respectively. For example, the conductance values of the read memristor 601 and the memristor 602 are G respectively 11 And G 12 If the current weight value is G 11 -G 12 。
In some embodiments of the present disclosure, the neural network is a bayesian neural network. The weight writing method shown in fig. 2 may further include training the bayesian neural network to obtain a training result, where the training result includes a plurality of weights in the bayesian neural network. The plurality of weights may be, for example, a weight matrix forming a bayesian neural network.
The plurality of weights are mapped to conductance values of a plurality of memristor cells included by the memristor array, the plurality of memristor cells including a target memristor cell. In this embodiment, step S10 in fig. 2 includes determining a target weight value written to the target memristor cell from the plurality of weights. For example, the plurality of weights are sequentially taken as target weight values, and thus are sequentially written into target memristor cells in one-to-one correspondence with the plurality of weights.
For example, the structure of the bayesian neural network includes a fully connected structure or a convolutional neural network structure, etc. Each weight of the bayesian neural network is a random variable. For example, after the bayesian neural network is trained, each weight is a distribution, such as a gaussian distribution or a laplacian distribution.
For example, offline (offline) training may be performed on the bayesian neural network to obtain a weight matrix, and a conventional method may be referred to for the method for training the bayesian neural network, for example, a Central Processing Unit (CPU), an image processing unit (GPU), a neural Network Processing Unit (NPU), a neural network accelerator, and the like may be used for training, which is not described herein again.
For example, the weights in a bayesian neural network obey a probability distribution, and the target weight is the mean of the probability distribution. For example, the weights in a bayesian neural network follow a gaussian distribution or normal distribution, and the target weight is the mean of the gaussian distribution.
Fig. 4 shows a flowchart of a method for training a bayesian neural network to obtain a training result according to at least one embodiment of the present disclosure.
As shown in fig. 4, the method may include steps S401 to S402.
Step S401: and acquiring a prior standard deviation applied to the Bayesian neural network.
Step S402: and training the Bayesian neural network based on the prior standard deviation to obtain a training result.
For step S401, the a priori standard deviations include weighted fluctuating standard deviations of the memristor array based on the conductance values of the memristors. Memristors have inherent non-ideal characteristics, including, for example, inter-device fluctuations, device conductance sticking, conductance state drift, etc., that cause, for example, the conductance values written to the memristors to drift. The training method provided by the embodiment of the disclosure integrates the influence of memristor conductance value fluctuation into the training of the Bayesian neural network, so that the output of the memristor neural network is ensured to be robust and reliable even under the disturbance of memristor weight.
For example, a plurality of electrical tests are performed on the memristor in the memristor array to obtain a plurality of test results of the plurality of electrical tests, each test result includes a weight fluctuation value of the memristor, and a standard deviation of the plurality of test results is calculated to be a weight fluctuation standard deviation.
Fig. 5 illustrates a flowchart of a method in step S402 in fig. 4 according to at least one embodiment of the present disclosure.
As shown in fig. 5, step S402 includes steps S412 to S442.
Step S412: and calculating the total loss function of the Bayesian neural network based on the weight fluctuation standard deviation.
Step S422: and performing back propagation on the total loss function so as to update the current weight value in the Bayesian neural network to obtain the object weight value.
Step S432: and obtaining the constraint condition of the object weight value.
Step S442: and constraining the object weight values based on the constraint conditions to obtain a training result of a plurality of weights of the Bayesian neural network.
For step S412, for example, as described above, the total loss function obtained by the variation learning includes KL loss terms and likelihood loss terms. For example, the total loss function is expressed as:
F(D,θ)＝KL[q(w|θ)||P(w)]-E q(w|θ) [logP(D|w)]，
wherein KL [ q (w | theta) | P (w)]A KL loss term, E q(w|θ) [logP(D|w)]Is a likelihood loss term.
In this example, the weight fluctuation standard deviation is taken as the prior standard deviation P (w), and the total loss function is calculated by substituting the weight fluctuation standard deviation into the expression of the loss function.
For step S422, for example, when training parameters such as weights of the neural network by using a gradient descent method, it is necessary to calculate partial derivatives of the loss function to the weights by using back propagation so as to obtain gradients of electrical conduction states of the memristors for each weight of the weight matrix of the bayesian neural network. Geometrically, where the direction along the gradient is where the function increases the fastest and the opposite direction along the gradient is where the function decreases the fastest, it is easier to find the minimum.
For example, for each parameter μ of a Bayesian neural network i ,σ i Each weight w i Obeying Gaussian distribution N (mu) i ,σ i 2 ) (ii) a The total loss function calculated in step S412 is used for back propagation to calculate each current parameter mu i ，σ i And updating each parameter according to the update amount delta. For example, the parameter μ i Is updated to mu i + Δ, i.e. the current weight value μ i Update to object weight value mu i + Δ, parameter σ i Is updated to sigma i +Δ。
For steps S432 and S442, the constraints on the object weight values include, for example, a weight window range of memristor cells. For example, the weight window range is [ -w max ,w max ]Of the object parameters i + Δ constrained to [ -w max ,w max ]And (4) the following steps. E.g. mu i +Δ<-w max Then will μ i + Delta constraint of-w max 。
In this embodiment, since the memristor's conductance window is finite, the weights will be truncated to a symmetrical range, i.e., the weight window range [ -w ] max ,w max ]And the Bayesian neural network is ensured to be more compatible with the memristor array, and the condition that the mean value of Gaussian distribution is out of the weight window range and is difficult to map into the memristor unit is avoided.
The constraint of the object weight values includes, for example, the standard deviation of the gaussian distribution. For example, the standard deviation of the gaussian distribution in the object parameter is constrained such that the standard deviation of the gaussian distribution is greater than or equal to the read fluctuation standard deviation. For example, the standard deviation of the Gaussian distribution is σ i Equal to 0.1, standard deviation of read fluctuation σ read Is equal to 0.15, σ i <σ read Then the standard deviation σ of the Gaussian distribution is calculated i Constraint of 0.15, i.e. σ i The value of (d) is updated to 0.15.
Returning to fig. 4, for step S401, the a priori standard deviation is determined based on a priori knowledge of the learning task for which the bayesian neural network is intended.
The a priori knowledge may for example comprise a probability distribution, or some data information, to which the learning task is obeyed. For example, the learning task is tested multiple times to obtain the probability distribution obeyed by the learning task, so as to determine the prior standard deviation of the learning task. The learning tasks are not limited by the present disclosure, for example, the learning tasks may include speech recognition, text recognition, image recognition, and the like. The a priori standard deviation of the learning task may be determined empirically or by related techniques by one skilled in the art.
Fig. 6 illustrates a schematic diagram of another weight writing method provided by at least one embodiment of the present disclosure.
As shown in fig. 6, the weight writing method is applied to map a weight matrix of a conventional deep neural network 601 into a memristor array 603 to operate the deep neural network 601 with the memristor array 603. First, a deep neural network 601 that operates with a memristor array 603 is obtained. After the deep neural network 601 is obtained, steps S61 to S63 are performed. The conventional deep neural network 601 may be, for example, any neural network other than a bayesian neural network, such as a Convolutional Neural Network (CNN), a Recurrent Neural Network (RNN), a Deep Belief Network (DBN), a deep automatic encoder (AutoEncoder), a generate-confrontation network (GAN), and the like.
Step S61: in response to the deep neural network 601 not being a bayesian neural network, the deep neural network 601 is converted into a bayesian neural network 603, and the network structure of the bayesian neural network 603 is the same as that of the deep neural network 601.
For example, if the deep neural network 601 is a 3-layer convolutional neural network, the three-layer convolutional neural network is converted into a 3-layer bayesian neural network 603. The network structure of the bayesian neural network 603 is the same as that of the deep neural network 601, which means that the neural network includes the same number of layers, and each layer has the same function. For example, a 3-layer convolutional neural network includes an input layer, a hidden layer, and an output layer, and then a 3-layer bayesian neural network also includes an input layer, a hidden layer, and an output layer.
The conventional neural network can be converted into a bayesian neural network by using a calculation method (e.g., probability weighting) of the related data, which is not described herein again.
Step S62: and obtaining the error amplitude of each weight in the Bayesian neural network 603.
For example, the error magnitudes of the weights in the bayesian neural network can be obtained by using the method of step S10 in fig. 2.
Step S63: the individual weights are mapped into the memristor array 803 in terms of the error magnitudes of the individual weights.
For example, a write-verify operation is performed for each weight until a difference between a conductance value read from the memristor corresponding to the weight and the weight is within an error margin of the weight.
Fig. 7 shows a flowchart of another weight writing method according to at least one embodiment of the present disclosure.
As shown in fig. 7, the weight writing method includes steps S701 to S705.
Step S701: obtaining targets in a neural networkWeight of
And the target weight
Error amplitude EM of i,j 。
Step S702: and acquiring the conductance values of the memristors of the memristor units. The memristor unit comprises a first memristor and a second memristor, and the conductance value G of the first memristor is acquired + ij And conductance value G of the second memristor - ij 。
Step S703: calculating a current weight value W of a memristor cell i,j . For example, a difference G between a conductance value of a first memristor and a conductance value of a second memristor is calculated + ij -G - ij As the current weight value W i,j 。
Step S704:
whether or not it is less than a preset threshold EM i,j . If it is
Then for acquiring the next target weight, the next target weight is mapped into the memristor array according to the weight writing method. If it is
The process returns to step S705.
Step S705: continuing to perform the programming operation on the memristor unit corresponding to the current target weight, and after performing the programming operation, returning to perform step S702.
Fig. 8 illustrates a schematic block diagram of a weight writing apparatus 800 applied to a neural network of a memristor array, provided by at least one embodiment of the present disclosure. The weight writing apparatus 800 may be used to perform the weight writing method shown in fig. 2.
As shown in fig. 8, the weight writing apparatus 800 includes a first acquisition unit 801, a second acquisition unit 802, a judgment unit 803, and a determination unit 803.
The first obtaining unit 801 is configured to obtain a target weight value written to a target memristor cell in the memristor array and an error magnitude for writing the target weight value, the error magnitude being determined based on a probability distribution corresponding to the target weight value. The first acquisition unit 801 executes, for example, step S10 in fig. 2.
The second obtaining unit 802 is configured to obtain a current weight value of the target memristor cell. The second acquisition unit 802 performs, for example, step S20 in fig. 2.
The judging unit 803 is configured to judge whether an absolute value of a difference between the current weight value and the target weight value is within an error margin. The determination unit 803 executes, for example, step S30 in fig. 2.
The determining unit 804 is configured to determine that the target weight value has been written to the target memristor cell in response to an absolute value of a difference between the current weight value and the target weight value being within a margin of error. The determination unit 804 performs, for example, step S40 in fig. 2.
The technical effect of the weight writing device is the same as that of the weight writing method shown in fig. 2, and is not repeated herein.
For example, the first acquiring unit 801, the second acquiring unit 802, the determining unit 803, and the determining unit 803 may be hardware, software, firmware, and any feasible combination thereof. For example, the first acquiring unit 801, the second acquiring unit 802, the determining unit 803, and the determining unit 803 may be dedicated or general circuits, chips, devices, or the like, or may be a combination of a processor and a memory. The embodiments of the present disclosure are not limited in this regard to the specific implementation forms of the above units.
It should be noted that, in the embodiment of the present disclosure, each unit of the weight writing apparatus 800 corresponds to each step of the weight writing method, and for the specific function of the weight writing apparatus 800, reference may be made to the description related to the weight writing method, which is not described herein again. The components and structure of the weight writing apparatus 800 shown in fig. 8 are exemplary only, and not limiting, and the weight writing apparatus 800 may further include other components and structures as needed.
At least one embodiment of the present disclosure also provides an electronic device that includes a processor and a memory, the memory storing one or more computer program instructions. One or more computer program instructions, when executed by the processor, are for implementing the weight writing method described above. The electronic device can improve the efficiency of weight writing.
Fig. 9 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 9, the electronic device 900 includes a processor 910 and a memory 920. The memory 920 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 910 is configured to execute non-transitory computer readable instructions, which when executed by the processor 910 may perform one or more of the steps of the weight writing method described above. The memory 920 and the processor 910 may be interconnected by a bus system and/or other form of connection mechanism (not shown).
For example, the processor 910 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X106 or ARM architecture or the like. The processor 910 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 900 to perform desired functions.
For example, memory 920 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by processor 910 to implement various functions of electronic device 900. Various applications and various data, as well as various data used and/or generated by the applications, etc., may also be stored in the computer-readable storage medium.
It should be noted that, in the embodiment of the present disclosure, reference may be made to the description about the weight writing method in the foregoing for specific functions and technical effects of the electronic device 900, and details are not described here again.
Fig. 10 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 1000 is, for example, suitable for implementing the weight writing method provided by the embodiments of the present disclosure. For example, the electronic device 1000 may be a terminal device or the like. It should be noted that the electronic device 1000 shown in fig. 10 is only one example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.
As shown in fig. 10, electronic device 1000 may include a processing means (e.g., central processing unit, graphics processor, etc.) 1010 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM) 1020 or a program loaded from storage device 1080 into a Random Access Memory (RAM) 1030. In the RAM1030, various programs and data necessary for the operation of the electronic apparatus 1000 are also stored. The processing device 1010, the ROM 1020, and the RAM1030 are connected to each other by a bus 1040. An input/output (I/O) interface 1050 is also connected to bus 1040.
Generally, the following devices may be connected to the I/O interface 1050: input devices 1060 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, or the like; an output device 1070 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, or the like; storage 1080 including, for example, tape, hard disk, etc.; and a communication device 1090. The communication means 1090 may allow the electronic device 1000 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 10 illustrates an electronic device 1000 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 1000 may alternatively be implemented or provided with more or less means.
For example, according to an embodiment of the present disclosure, the weight writing method described above may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the weight-writing method described above. In such embodiments, the computer program may be downloaded and installed from a network through communication device 1090, or from storage device 1080, or from ROM 1020. When executed by the processing device 1010, the computer program may implement the functions defined in the weight writing method provided by the embodiments of the present disclosure.
At least one embodiment of the present disclosure also provides a computer-readable storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, may implement the weight writing method described above. With the computer-readable storage medium, the efficiency of weight writing can be improved.
Fig. 11 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. As shown in fig. 11, storage medium 1100 is used to store non-transitory computer readable instructions 1110. For example, the non-transitory computer readable instructions 1110, when executed by a computer, may perform one or more steps in accordance with the weight writing methods described above.
For example, the storage medium 1100 may be applied to the electronic device 1000 described above. For example, the storage medium 1100 may be the memory 920 in the electronic device 900 shown in fig. 9. For example, the related description about the storage medium 1100 may refer to the corresponding description of the memory 920 in the electronic device 900 shown in fig. 9, and is not repeated here.
The following points need to be explained:
(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.
(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.
The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.
Claims (15)
1. A weight writing method applied to a neural network of a memristor array, comprising:
acquiring a target weight value to be written into a target memristor unit in the memristor array and an error amplitude for writing the target weight value, wherein the error amplitude is determined based on probability distribution corresponding to the target weight value;
obtaining a current weight value of the target memristor unit;
judging whether the absolute value of the difference between the current weight value and the target weight value is within the error amplitude; and
determining that the target weight value has been written to the target memristor cell in response to an absolute value of a difference between the current weight value and the target weight value being within the margin of error.
2. The weight writing method according to claim 1, wherein the probability distribution is a gaussian distribution, the target weight value is a mean value of the gaussian distribution, and the error magnitude is determined based on a standard deviation of the gaussian distribution.
3. The weight writing method according to claim 2, wherein the error magnitude is positively correlated with the standard deviation.
4. The weight writing method according to claim 3, wherein the error magnitude is a product of the standard deviation and a scaling factor, the scaling factor being greater than 1.
5. The weight writing method of claim 1, wherein the target memristor cell includes a first memristor and a second memristor,
obtaining the current weight value of the target memristor cell, including:
obtaining a conductance value of the first memristor and a conductance value of the second memristor;
calculating a difference between the conductance value of the first memristor and the conductance value of the second memristor, the difference being the current weight value.
6. The weight writing method according to claim 1, further comprising:
in response to an absolute value of a difference between the current weight value and the target weight value not being within the margin of error, programming the target memristor cell until the absolute value of the difference between the current weight value and the target weight value is within the margin of error.
7. The weight writing method according to claim 1, wherein the neural network is a bayesian neural network, the weight writing method further comprising:
training the Bayesian neural network to obtain a training result, wherein the training result comprises a plurality of weights in the Bayesian neural network,
wherein the plurality of weights are mapped to conductance values of a plurality of memristor cells included by a memristor array, the plurality of memristor cells including the target memristor cell,
obtaining the target weight value written to the target memristor cell in the memristor array, including:
determining a target weight value written to the target memristor cell from the plurality of weights.
8. The weight writing method according to claim 7, wherein training the bayesian neural network to obtain a training result comprises:
acquiring a prior standard deviation applied to the Bayesian neural network; and
and training the Bayesian neural network based on the prior standard deviation to obtain the training result.
9. The weight writing method of claim 8, in which the a priori standard deviation comprises a weight fluctuation standard deviation of the memristor array based on conductance values of the memristors.
10. The weight writing method according to claim 9, wherein training the bayesian neural network to obtain the training result based on the prior standard deviation comprises:
calculating a total loss function of the Bayesian neural network based on the weight fluctuation standard deviation;
performing back propagation on the total loss function so as to update the current weight value in the Bayesian neural network to obtain an object weight value;
acquiring a constraint condition of the object weight value; and
and constraining the object weight values based on the constraint conditions to obtain a training result of the plurality of weights of the Bayesian neural network.
11. The weight writing method according to claim 8, wherein the a priori standard deviation is determined based on a priori knowledge of a learning task for which the bayesian neural network is intended.
12. The weight writing method according to claim 7, further comprising:
acquiring a deep neural network operated by the memristor array;
in response to the deep neural network not being the Bayesian neural network, converting the deep neural network into the Bayesian neural network, wherein a network structure of the Bayesian neural network is the same as the deep neural network.
13. A weight writing apparatus applied to a neural network of a memristor array, comprising:
a first obtaining unit configured to obtain a target weight value written to a target memristor cell in the memristor array and an error magnitude for writing the target weight value, wherein the error magnitude is determined based on a probability distribution corresponding to the target weight value;
a second obtaining unit configured to obtain a current weight value of the target memristor cell;
a judging unit configured to judge whether an absolute value of a difference between the current weight value and the target weight value is within the error margin;
a determination unit configured to determine that the target weight value has been written to the target memristor cell in response to an absolute value of a difference between the current weight value and the target weight value being within the margin of error.
14. An electronic device, comprising:
a processor;
a memory including one or more computer program instructions;
wherein the one or more computer program instructions are stored in the memory and when executed by the processor implement the weight writing method of any of claims 1-12.
15. A computer-readable storage medium storing non-transitory computer-readable instructions, wherein the computer-readable instructions, when executed by a processor, implement the weight writing method of any one of claims 1-12.
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