TW201818506A - Semiconductor device, and manufacturing method of the same - Google Patents
Semiconductor device, and manufacturing method of the same Download PDFInfo
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- TW201818506A TW201818506A TW106142399A TW106142399A TW201818506A TW 201818506 A TW201818506 A TW 201818506A TW 106142399 A TW106142399 A TW 106142399A TW 106142399 A TW106142399 A TW 106142399A TW 201818506 A TW201818506 A TW 201818506A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Abstract
Description
本發明係關於半導體裝置及其製造技術，特別是關於適用於具備LCD (Liquid Crystal Display：液晶顯示器)驅動器等較高耐壓之MISFET之半導體裝置、及其製造技術之有效技術。The present invention relates to a semiconductor device and a manufacturing technology thereof, and more particularly, to a semiconductor device provided with a high-withstand voltage MISFET such as an LCD (Liquid Crystal Display) driver, and an effective technology for a manufacturing technology thereof.
於日本特開2005-116744號公報(專利文獻1)中，記載一種於同一基板上形成高耐壓電晶體及低耐壓電晶體之技術。於該專利文獻1，高耐壓電晶體係具有電場緩和用之偏移絕緣層。且，形成於高耐壓電晶體形成區域之保護環，係與形成於第一層的層間絕緣膜上之布線(最下層之布線)連接。相對於此，高耐壓電晶體之源極區域或汲極區域，係與形成於第一層的層間絕緣膜上之第二層層間絕緣膜上所形成的布線(非最下層之布線)連接。即，高耐壓電晶體之源極區域或汲極區域，係藉由一次貫通第一層層間絕緣膜及第二層層間絕緣膜之插塞，來與配置於第二層層間絕緣膜上之布線連接。 於日本特開平4-171938號公報(專利文獻2)中，記載一種於同一基板上形成高耐壓n通道FET及低耐壓n通道FET之技術。此時，低耐壓n通道FET，係形成於第一層層間絕緣膜上之最下層的布線，與源極區域或汲極區域連接。相對於此，於高耐壓n通道FET中，源極區域或汲極區域，係構成如與形成於第二層層間絕緣膜上之布線連接，而不與最下層之布線連接。 [專利文獻1]日本特開2005-116744號公報 [專利文獻2]日本特開平4-171938號公報Japanese Patent Application Laid-Open No. 2005-116744 (Patent Document 1) describes a technique for forming a high piezoelectric crystal and a low piezoelectric crystal on the same substrate. In this patent document 1, a highly resistant piezoelectric crystal system has an offset insulating layer for electric field relaxation. In addition, the guard ring formed in the region where the high-withstand piezoelectric crystal is formed is connected to the wiring (the wiring on the lowermost layer) formed on the interlayer insulating film of the first layer. In contrast, the source region or the drain region of the high-withstand voltage crystal is a wiring formed on the second interlayer insulating film formed on the first interlayer insulating film (not the lowermost wiring). )connection. That is, the source region or the drain region of the high-withstand voltage crystal is connected to the second-layer interlayer insulating film by a plug that penetrates the first-layer interlayer insulating film and the second-layer interlayer insulating film at one time. Wiring connections. Japanese Patent Application Laid-Open No. 4-171938 (Patent Document 2) describes a technique for forming a high withstand voltage n-channel FET and a low withstand voltage n-channel FET on the same substrate. At this time, the low withstand voltage n-channel FET is a wiring formed at the lowermost layer on the first interlayer insulating film, and is connected to the source region or the drain region. In contrast, in a high withstand voltage n-channel FET, the source region or the drain region is configured to be connected to a wiring formed on a second interlayer insulating film, but not to a wiring on the lowermost layer. [Patent Document 1] Japanese Patent Laid-Open No. 2005-116744 [Patent Document 2] Japanese Patent Laid-Open No. 4-171938
[發明所欲解決之問題] 近年來，將液晶使用於顯示元件之LCD急速普及。該LCD係藉由用以驅動LCD之驅動器來控制。LCD驅動器係由半導體晶片構成，安裝於例如玻璃基板上。構成LCD驅動器之半導體晶片，係於半導體基板上形成有複數電晶體及多層布線之構造，且於表面上形成有凸塊電極。又，經由形成於表面上之凸塊電極而安裝於玻璃基板。 形成於LCD驅動器之複數電晶體(MISFET)中，係存在有低耐壓MISFET及高耐壓MISFET。亦即，LCD驅動器通常除了以5 V程度之電壓加以驅動的低耐壓MISFET所組成之邏輯電路外，還存在有於LCD之電極施加20 V~30 V程度之電壓之電路。為了於LCD之電極施加20 V~30 V程度之電壓，係藉由在以5 V程度驅動之邏輯電路上連接位準偏移電路，並經由位準偏移電路來連接切換元件而構成。該切換元件係以20 V~30 V之電壓加以驅動之MISFET，且由所謂高耐壓MISFET構成。 如此，於LCD驅動器係於同一半導體基板具備低耐壓MISFET及高耐壓MISFET。於形成於同一半導體基板之低耐壓MISFET及高耐壓MISFET上，形成有層間絕緣膜，於該層間絕緣膜上形成有布線。布線及MISFET係藉由貫通層間絕緣膜之插塞來連接。通常，與高耐壓MISFET之源極區域或汲極區域連接之布線並非形成於第一層層間絕緣膜上，而是於第一層層間絕緣膜上進一步形成第二層層間絕緣膜，於該第二層層間絕緣膜上形成。總言之，高耐壓MISFET由於使用20 V~30 V程度之較高電壓，因此為了確保布線與高耐壓MISFET(閘極電極)之耐壓，藉由於第二層層間絕緣膜上配置布線，不於第一層層間絕緣膜上配置布線，來確保高耐壓MISFET之耐壓。因此，高耐壓MISFET與布線係經由貫通第一層層間絕緣膜之插塞、及接著貫通第二層層間絕緣膜之插塞來連接。 近年來，要求LCD驅動器之小型化。因此，進行縮小連接LCD驅動器之MISFET與布線之插塞(接觸插塞)之直徑。例如具體而言，將插塞之直徑從0.24 mm大幅縮小為0.14 mm。然而，若縮小插塞之直徑，則會凸顯插塞所造成之電阻變大之問題。特別是高耐壓MISFET係由於以貫通第一層層間絕緣膜與第二層層間絕緣膜之插塞，來連接高耐壓MISFET與布線，因此藉由縮小插塞之直徑，插塞之高寬比變大，電阻增加。因此，於LCD驅動器，藉由於第一層層間絕緣膜上形成布線，且增大形成於第一層層間絕緣膜上之布線之布線寬，增加連接第一層層間絕緣膜與第二層層間絕緣膜之插塞之數目，來謀求插塞之低電阻化。於第一層層間絕緣膜亦形成布線，藉此無須直接連接貫通第一層層間絕緣膜之插塞與貫通第二層層間絕緣膜之插塞，可減低插塞之高寬比。因此，可抑制插塞徑縮小所造成之高電阻化。 進一步藉由使第一層層間絕緣膜之膜厚變薄，來縮小形成於第一層層間絕緣膜之插塞之高寬比。如此，於LCD驅動器之晶片縮放中，使第一層層間絕緣膜之膜厚變薄，且於第一層層間絕緣膜上進行布線形成。然後，增大形成於第一層層間絕緣膜上之布線之布線寬，增加連接第一層層間絕緣膜與第二層層間絕緣膜之插塞之數目。於此，為了增大形成於第一層層間絕緣膜上之布線之布線寬，與高耐壓MISFET之源極區域連接之源極布線或與高耐壓MISFET之汲極區域連接之汲極布線係以與高耐壓MISFET之閘極電極具有在俯視時重疊之區域之方式形成。 如此，可抑制伴隨於LCD驅動器之小型化之插塞之高電阻化，但會發生新問題。總言之，由於以使第一層層間絕緣膜之膜厚變薄，且源極布線或汲極布線與高耐壓MISFET之閘極電極在俯視時重疊之方式，來構成LCD驅動器，因此發生高耐壓MISFET之閘極電極與源極布線間、或高耐壓MISFET之閘極電極與汲極區域間之耐壓不良。作為該耐壓不良發生之原因，第一可舉出由於第一層層間絕緣膜之成膜步驟或CMP(Chemical Mechanical Polishing：化學機械研磨)等造成之研磨步驟之偏差，形成於高耐壓MISFET之閘極電極上之第一層層間絕緣膜容易變得很薄。因此，據判發生閘極電極與形成於第一層層間絕緣膜上之源極布線或汲極布線之耐壓不良。 第二可舉出於高耐壓MISFET，閘極絕緣膜之膜厚甚厚。然後，於高耐壓MISFET，於源極區域或汲極區域內，形成從半導體基板稍微突出之電場緩和用絕緣區域，由於閘極電極之端部擱置於該電場緩和用絕緣區域上，因此原因之一可舉出閘極電極之高度比低耐壓MISFET高之觀點。 進一步而言，作為第三原因可舉出高耐壓MISFET之驅動電壓為20 V~30 V程度，比低耐壓MISFET高。由以上可知，以現狀之LCD驅動器之結構，難以使抑制插塞伴隨於尺寸縮小之高電阻化，且改善高耐壓MISFET之閘極電極與布線間之耐壓不良同時成立。 本發明之目的在於提供一種在如LCD驅動器等具備高耐壓MISFET及低耐壓MISFET之半導體裝置，抑制由小型化所造成之插塞之高電阻化，且可改善高耐壓MISFET之閘極電極與布線間之耐壓不良之技術。 本發明之前述及其他目的與新特徵可從本說明書之記述及附圖來闡明。 [解決問題之技術手段] 簡單說明本申請案所揭示之發明中之代表者之概要如下。 根據本發明之半導體裝置之特徵為具備：(a1)閘極絕緣膜，其係形成於半導體基板上；(a2)閘極電極，其係形成於前述閘極絕緣膜上；及(a3)MISFET，其係包含於前述閘極電極整合形成之源極區域及汲極區域。然後，具備：(b)絕緣膜，其係形成於前述MISFET上；(c)第一插塞，其係貫通前述絕緣膜並與前述源極區域電性連接；及(d)第二插塞，其係貫通前述絕緣膜並與前述汲極區域電性連接。進一步具備：(e)源極布線，其係形成於前述絕緣膜上，與前述第一插塞電性連接；及(f)汲極布線，其係形成於前述絕緣膜上，與前述第二插塞電性連接。於此，從前述半導體基板與前述閘極絕緣膜之界面至前述閘極電極之上表面之距離設為a，從前述閘極電極之上表面至形成有前述源極布線及前述汲極布線之前述絕緣膜之上表面之距離設為b之情況下，a＞b。此時，前述閘極電極與前述源極布線配置為在俯視時不重疊，且前述閘極電極與前述汲極布線配置為在俯視時不重疊。 而且，根據本發明之半導體裝置之製造方法之特徵為具備以下步驟：(a)於半導體基板形成元件分離區域及電場緩和用絕緣區域之步驟；(b)於前述半導體基板上形成閘極絕緣膜之步驟；及(c)以分別內包前述電場緩和用絕緣區域之方式，形成1對低濃度雜質擴散區域之步驟。然後，具備：(d)於前述閘極絕緣膜上形成閘極電極之步驟；及(e)於前述閘極電極兩側之側壁形成邊牆之步驟。進一步包含(f)於分別由前述1對低濃度雜質擴散區域所內包且為前述電場緩和用絕緣區域之外側之區域，形成1對高濃度雜質擴散區域，並形成由前述1對低濃度雜質擴散區域之1個、及包含於其之前述1對高濃度雜質擴散區域之1個所組成之源極區域，及由前述1對低濃度雜質擴散區域之另1個、及包含於其之前述1對高濃度雜質擴散區域之另1個所組成之汲極區域之步驟。然後，具備：(g)以覆蓋前述閘極電極之方式形成絕緣膜之步驟；及(h)形成貫通前述絕緣膜而到達前述源極區域之第一插塞，並形成貫通前述絕緣膜而到達前述汲極區域之第二插塞之步驟。進一步具備(i)於前述絕緣膜上形成與前述第一插塞連接之源極布線，於前述絕緣膜上形成與前述第二插塞連接之汲極布線之步驟。於此，從前述半導體基板與前述閘極絕緣膜之界面至前述閘極電極之上部之距離設為a，從前述閘極電極之上部至形成有前述源極布線及前述汲極布線之前述絕緣膜之上表面之距離設為b之情況下，a＞b。於該狀況下，以前述閘極電極與前述源極布線在俯視時不重疊之方式形成，且以前述閘極電極與前述汲極布線在俯視時不重疊之方式形成。 [發明之效果] 若簡單說明本申請案所揭示之發明中，藉由代表態樣所獲得之功效時，係如下所述。 在如LCD驅動器此種具備高耐壓MISFET及低耐壓MISFET之半導體裝置中，係可抑制由於半導體裝置之小型化而造成之插塞的高電阻化，且可改善高耐壓MISFET之閘極電極與布線間之耐壓不良。[Problems to be Solved by the Invention] In recent years, LCDs using liquid crystals as display elements have rapidly spread. The LCD is controlled by a driver for driving the LCD. The LCD driver is composed of a semiconductor wafer and is mounted on, for example, a glass substrate. The semiconductor wafer constituting the LCD driver has a structure in which a plurality of transistors and multilayer wirings are formed on a semiconductor substrate, and bump electrodes are formed on the surface. Furthermore, it is mounted on a glass substrate via a bump electrode formed on the surface. A plurality of transistors (MISFETs) formed in the LCD driver include a low withstand voltage MISFET and a high withstand voltage MISFET. That is, in addition to a logic circuit composed of a low-withstand voltage MISFET driven by a voltage of about 5 V, an LCD driver also has a circuit that applies a voltage of about 20 V to 30 V to an electrode of the LCD. In order to apply a voltage of approximately 20 V to 30 V to the electrodes of the LCD, a level shift circuit is connected to a logic circuit driven at a level of 5 V, and a switching element is connected via the level shift circuit. This switching element is a MISFET driven at a voltage of 20 V to 30 V, and is composed of a so-called high-withstand voltage MISFET. In this way, the LCD driver is provided with the low-withstand voltage MISFET and the high-withstand voltage MISFET on the same semiconductor substrate. An interlayer insulating film is formed on the low withstand voltage MISFET and the high withstand voltage MISFET formed on the same semiconductor substrate, and wiring is formed on the interlayer insulating film. The wiring and the MISFET are connected by a plug penetrating through the interlayer insulating film. Generally, the wiring connected to the source region or the drain region of the high-withstand voltage MISFET is not formed on the first interlayer insulating film, but a second interlayer insulating film is further formed on the first interlayer insulating film. The second interlayer insulating film is formed. In short, the high withstand voltage MISFET uses a relatively high voltage of about 20 V to 30 V. Therefore, in order to ensure the withstand voltage of the wiring and the high withstand voltage MISFET (gate electrode), the second interlayer insulating film For wiring, do not arrange wiring on the first interlayer insulating film to ensure the withstand voltage of the high withstand voltage MISFET. Therefore, the high-withstand voltage MISFET and the wiring are connected via a plug penetrating through the first interlayer insulating film and then a plug penetrating through the second interlayer insulating film. In recent years, miniaturization of LCD drivers is required. Therefore, the diameter of the plug (contact plug) connecting the MISFET of the LCD driver and the wiring is reduced. For example, specifically, the diameter of the plug is greatly reduced from 0.24 mm to 0.14 mm. However, if the diameter of the plug is reduced, the problem of increased resistance caused by the plug will be highlighted. In particular, high-withstand voltage MISFETs are connected to the high-withstand voltage MISFET and wiring by plugs that penetrate the first interlayer insulating film and the second interlayer insulating film. Therefore, by reducing the diameter of the plug, the height of the plug is high. As the aspect ratio becomes larger, the resistance increases. Therefore, in the LCD driver, since the wiring is formed on the first interlayer insulating film, and the wiring width of the wiring formed on the first interlayer insulating film is increased, the connection between the first interlayer insulating film and the second layer is increased. The number of plugs of the interlayer insulating film is to reduce the resistance of the plugs. Wiring is also formed on the first interlayer insulating film, thereby eliminating the need to directly connect the plug penetrating the first interlayer insulating film and the plug penetrating the second interlayer insulating film, which can reduce the aspect ratio of the plug. Therefore, it is possible to suppress an increase in resistance due to a reduction in the plug diameter. Further, by reducing the film thickness of the first interlayer insulating film, the aspect ratio of the plug formed in the first interlayer insulating film is reduced. In this way, in the scaling of the wafer of the LCD driver, the film thickness of the first interlayer insulating film is reduced, and wiring is formed on the first interlayer insulating film. Then, the wiring width of the wiring formed on the first interlayer insulating film is increased, and the number of plugs connecting the first interlayer insulating film and the second interlayer insulating film is increased. Here, in order to increase the wiring width of the wiring formed on the first interlayer insulating film, the source wiring connected to the source region of the high withstand voltage MISFET or the drain wiring connected to the source region of the high withstand voltage MISFET The drain wiring is formed so as to have a region overlapping the gate electrode of the high-withstand voltage MISFET in a plan view. In this way, the increase in resistance of the plug accompanying miniaturization of the LCD driver can be suppressed, but a new problem occurs. In short, since the thickness of the first interlayer insulating film is reduced, and the source wiring or the drain wiring and the gate electrode of the high-withstand voltage MISFET are overlapped in a plan view, the LCD driver is configured. Therefore, a breakdown voltage between the gate electrode and the source wiring of the high withstand voltage MISFET, or between the gate electrode and the drain region of the high withstand voltage MISFET occurs. As a cause of the occurrence of this withstand voltage failure, the first reason is that the deviation of the polishing step due to the film-forming step of the first interlayer insulating film or the CMP (Chemical Mechanical Polishing) is formed in the high-withstand voltage MISFET. The first interlayer insulating film on the gate electrode easily becomes very thin. Therefore, it is judged that the breakdown voltage of the gate electrode and the source wiring or the drain wiring formed on the first interlayer insulating film is poor. The second is the high-withstand voltage MISFET, which has a very thick gate insulating film. Then, in the high-withstand voltage MISFET, an insulation region for electric field mitigation that slightly protrudes from the semiconductor substrate is formed in the source region or the drain region. The end of the gate electrode is placed on the insulation region for electric field mitigation. One example is the viewpoint that the height of the gate electrode is higher than that of the low-withstand voltage MISFET. Furthermore, as a third reason, the driving voltage of the high withstand voltage MISFET is about 20 V to 30 V, which is higher than the low withstand voltage MISFET. From the above, it can be known that with the current structure of the LCD driver, it is difficult to suppress the plug to increase the resistance due to the reduction in size, and to improve the breakdown voltage between the gate electrode and the wiring of the high breakdown voltage MISFET simultaneously. An object of the present invention is to provide a semiconductor device having a high withstand voltage MISFET and a low withstand voltage MISFET, such as an LCD driver, to suppress the increase in resistance of a plug caused by miniaturization, and to improve the gate of the high withstand voltage MISFET. Technology for poor voltage resistance between electrodes and wiring. The foregoing and other objects and new features of the present invention can be clarified from the description of the present specification and the accompanying drawings. [Technical means to solve the problem] A brief description of the representative of the invention disclosed in this application is as follows. The semiconductor device according to the present invention includes: (a1) a gate insulating film formed on a semiconductor substrate; (a2) a gate electrode formed on the foregoing gate insulating film; and (a3) a MISFET It is included in the source region and the drain region formed by integrating the foregoing gate electrodes. (B) an insulating film formed on the MISFET; (c) a first plug that penetrates the insulating film and is electrically connected to the source region; and (d) a second plug It penetrates the insulating film and is electrically connected to the drain region. It further includes: (e) a source wiring formed on the insulating film and electrically connected to the first plug; and (f) a drain wiring formed on the insulating film and connected to the foregoing The second plug is electrically connected. Here, the distance from the interface between the semiconductor substrate and the gate insulating film to the upper surface of the gate electrode is set to a, and from the upper surface of the gate electrode to the source wiring and the drain cloth are formed. When the distance between the upper surfaces of the aforementioned insulating films of the wires is set to b, a> b. At this time, the gate electrode and the source wiring are arranged so as not to overlap in a plan view, and the gate electrode and the drain wiring are arranged not to overlap in a plan view. Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized by having the following steps: (a) forming a device separation region and an electric field relaxation insulating region on a semiconductor substrate; (b) forming a gate insulating film on the semiconductor substrate And (c) a step of forming a pair of low-concentration impurity diffusion regions by including the aforementioned electric field mitigation insulating regions, respectively. Then, it is provided with: (d) a step of forming a gate electrode on the foregoing gate insulating film; and (e) a step of forming side walls on both side walls of the foregoing gate electrode. And further including (f) forming a pair of high-concentration impurity diffusion regions in the regions enclosed by the aforementioned one pair of low-concentration impurity diffusion regions and outside the insulation region for electric field relaxation, and forming one pair of low-concentration impurity diffusion regions. A source region composed of one diffusion region and one of the above-mentioned one pair of high-concentration impurity diffusion regions, and another one of the aforementioned pair of low-concentration impurity diffusion regions, and the aforementioned one included therein A step for a drain region composed of another high-concentration impurity diffusion region. Then, (g) forming an insulating film so as to cover the gate electrode; and (h) forming a first plug penetrating the insulating film to reach the source region, and forming a first plug penetrating the insulating film to reach The step of the second plug in the aforementioned drain region. It further includes (i) forming a source wiring connected to the first plug on the insulating film, and forming a drain wiring connected to the second plug on the insulating film. Here, the distance from the interface between the semiconductor substrate and the gate insulating film to the upper portion of the gate electrode is set to a, and from the upper portion of the gate electrode to the portion where the source wiring and the drain wiring are formed. When the distance between the upper surfaces of the insulating films is set to b, a> b. In this case, the gate electrode and the source wiring are formed so as not to overlap in a plan view, and the gate electrode and the drain wiring are not formed to overlap in a plan view. [Effects of the Invention] The effects obtained by the representative aspects in the invention disclosed in this application will be briefly described as follows. In a semiconductor device having a high withstand voltage MISFET and a low withstand voltage MISFET, such as an LCD driver, it is possible to suppress the increase in resistance of the plug due to the miniaturization of the semiconductor device and improve the gate of the high withstand voltage MISFET Poor withstand voltage between electrodes and wiring.
以下實施型態中，為便宜起見，於有其必要時，係分割為複數區段或實施型態來說明，但除特別明示之情況外，其等並非互無關係，一方係屬於另一方之一部分或全部之變形例、詳細、補充說明等關係。 而且，於以下實施型態中，提及要素之數字等(包含個數、數值、量、範圍等)之情況時，除了特別明示之情況，及原理上明顯限定於特定數之情況等外，並不限定於該特定數，特定數以上或以下均可。 進而，於以下實施型態中，其構成要素(亦包含要素步驟等)除了特別明示之情況，及原理上據判明顯必需者之情況等以外，無須贅言，當然未必為必需者。 同樣地，於以下實施型態中，提及構成要素等之形狀、位置關係等時，除了特別明示之情況，及原理上據判明顯否定之情況等以外，實質上係包含與該形狀等近似或類似者等。此時，關於上述數值及範圍，亦如上所述。 又，用以說明本實施型態之所有圖式中，對於同一構件原則上係附以同一標號，並省略其重複說明。此外，為了使圖式易於理解，即使為俯視圖，仍有附上影線之情況。 (實施型態1) 首先，說明有關本實施型態中之LCD驅動器用之半導體晶片。圖1係表示本實施型態中之半導體晶片CHP(半導體裝置)之結構的俯視圖。本實施型態中之半導體晶片CHP為LCD驅動器。於圖1，半導體晶片CHP係具有形成為例如細長之長方形狀的半導體基板1S，且於其主面上，形成有可驅動例如液晶顯示裝置之LCD驅動器。該LCD驅動器，係具有對於構成LCD之胞陣列(cell array)之各像素供給電壓，且控制液晶分子之方向之功能，並具有閘極驅動電路C1、源極驅動電路C2、液晶驅動電路C3、圖形RAM (Random Access Memory：隨機存取記憶體)C4及周邊電路C5。 於半導體晶片CHP之外周附近，複數凸塊電極BMP沿著半導體晶片CHP之外周，於每特定間隔配置。該等複數凸塊電極BMP配置於配置有半導體晶片CHP之元件或布線之有效區域上。於複數凸塊電極BMP中，存在有積體電路之結構上必要之積體電路用之凸塊電極、或積體電路之結構上非必要之虛設凸塊電極。於半導體晶片CHP之1個長邊及2個短邊附近，凸塊電極BMP配置為格子交叉狀。該配置為格子交叉狀之複數凸塊電極BMP主要為閘極輸出信號用或源極輸出信號用之凸塊電極。於半導體晶片CHP之長邊中央呈格子交叉配置之凸塊電極BMP為源極輸出信號用之凸塊電極，於半導體晶片CHP之長邊之兩角附近及半導體晶片CHP之兩短邊呈格子交叉配置之凸塊電極BMP為閘極輸出信號用之凸塊電極。藉由採用該類格子交叉配置，可抑制半導體晶片CHP之尺寸增大，同時可配置數目需要許多之閘極輸出信號用之凸塊電極BMP或源極輸出信號用之凸塊電極BMP。亦即，可縮小晶片尺寸，同時增加凸塊電極之數目。 而且，於半導體晶片CHP之另一長邊附近，並非以格子交叉配置而以排列為一直線狀之方式配置有凸塊電極BMP。以排列為一直線狀之方式配置之凸塊電極BMP為數位輸入信號用或類比輸入信號用之凸塊電極。進一步於半導體晶片CHP之四角附近，形成有虛設凸塊電極。此外，於圖1係說明有關將閘極輸出信號用或源極輸出信號用之凸塊電極BMP予以格子交叉配置，將數位輸入信號用或類比輸入信號用之凸塊電極BMP配置為一直線狀之例。然而，亦可能為將閘極輸出信號用或源極輸出信號用之凸塊電極BMP配置為一直線狀，將數位輸入信號用或類比輸入信號用之凸塊電極BMP予以格子交叉配置之結構。 半導體晶片CHP之外形尺寸例如為短邊方向長度1.0 mm、長邊方向長度12.0 mm，或為短邊方向長度1.0 mm、長邊方向長度10.0 mm。進一步而言，亦有例如短邊方向長度2.0 mm、長邊方向長度20.0 mm者。如此，使用於LCD驅動器之半導體晶片CHP係呈長方形之形狀。具體而言，短邊長度與長邊長度之比為1：8~1：12者甚多。進一步亦有長邊方向長度為5 mm以上者。 於圖1所示而構成之LCD驅動器之半導體晶片CHP之內部，存在有使用於邏輯電路等之低耐壓MISFET及使用於液晶驅動電路等之高耐壓MISFET。例如於本申請說明書中，以5 V~6 V程度之驅動電壓動作之MISFET稱為低耐壓MISFET，以20 V~30 V程度之驅動電壓動作之MISFET稱為高耐壓MISFET。 圖2係存在於圖1所示之半導體晶片CHP之內部之MISFET之剖面圖。於圖2圖示有低耐壓MISFET及高耐壓MISFET。 首先，說明有關高耐壓MISFET之結構。於圖2，於高耐壓MISFET形成區域，於半導體基板1S上形成有元件分離區域2。亦即，在由元件分離區域2分離之活性區域，形成有高耐壓MISFET。在由複數元件分離區域2夾著之半導體基板1S內，形成有p型井4。該p型井4係為了高耐壓MISFET用所形成之井。進一步於高耐壓MISFET形成區域，在由複數元件分離區域2夾著之區域，形成有電場緩和用絕緣區域3。該電場緩和用絕緣區域3係例如與元件分離區域2為同樣結構，以STI(Shallow Trench Isolation：淺溝槽隔離)法形成。 於p型井4內，形成有1對高耐壓用低濃度雜質擴散區域(n型半導體區域)6，各個高耐壓用低濃度雜質擴散區域係以內包電場緩和用絕緣區域3之方式形成。在位於1對高耐壓用低濃度雜質擴散區域6間之半導體基板1S之表面，形成有閘極絕緣膜8，於該閘極絕緣膜8上形成有閘極電極10b。閘極絕緣膜8係由例如氧化矽膜形成，閘極電極10b係由例如多晶矽膜與鈷矽化物膜之疊層膜形成。作為閘極電極10b，藉由於多晶矽膜上形成鈷矽化物膜，可謀求閘極電極10b之低電阻化。 閘極絕緣膜8係其端部擱置於電場緩和用絕緣區域3上而形成。總言之，於高耐壓MISFET形成區域，因元件分離區域2及電場緩和用絕緣區域3之佔有率變高之關係，元件分離區域2及電場緩和用絕緣區域3容易從半導體基板1S之表面突出。因此，閘極絕緣膜8之端部成為擱置於電場緩和用絕緣區域3之形狀。因此，形成於閘極絕緣膜8上之閘極電極10b亦以其端部隆起之方式形成。 接著，於閘極電極10b兩側之側壁形成有邊牆(sidewall)12，該邊牆12亦形成於電場緩和用絕緣區域3上。然後，於電場緩和用絕緣區域3之外側且高耐壓用低濃度雜質擴散區域6內，形成有高耐壓用高濃度雜質擴散區域(n型半導體區域)14。於該高耐壓用高濃度雜質擴散區域14之表面，形成有鈷矽化物膜15。如此，藉由1對高耐壓用低濃度雜質擴散區域6之1個、形成於該高耐壓用低濃度雜質擴散區域6之內部之高耐壓用高濃度雜質擴散區域14及鈷矽化物膜15，形成高耐壓MISFET之源極區域。同樣地藉由1對高耐壓用低濃度雜質擴散區域6之其他1個、形成於該高耐壓用低濃度雜質擴散區域6之內部之高耐壓用高濃度雜質擴散區域14及鈷矽化物膜15，形成高耐壓MISFET之汲極區域。 於本實施型態，由於在閘極電極10b之端部形成有電場緩和用絕緣區域3，因此可緩和形成於閘極電極10b之端部下之電場。因此，可確保閘極電極10b與源極區域間或閘極電極10b與汲極區域間之耐壓。亦即，於高耐壓MISFET構成如藉由形成電場緩和用絕緣區域3，即使驅動電壓成為20 V~30 V，仍可確保耐壓。 本實施型態中之高耐壓MISFET係如上述構成，於以下說明有關本實施型態之低耐壓MISFET之結構。 於圖2，低耐壓MISFET形成區域中，在半導體基板1S上係形成有元件分離區域2。亦即，在元件分離區域2加以分離之活性區域，係形成有低耐壓MISFET。在複數元件分離區域2所挾夾之半導體基板1S內，係形成有p型井4。且，於p型井4內，係形成有低耐壓MISFET用之井，即p型井5。再者，低耐壓MISFET形成區域中，並未形成有電場緩和用絕緣區域3。 於p型井5上形成有閘極絕緣膜7，而該閘極絕緣膜7上係形成有閘極電極10a。閘極絕緣膜7係例如由氧化矽膜所形成，閘極電極10a係例如由多晶矽膜與鈷矽化物膜之疊層膜所形成。作為閘極電極10a，可藉由於多晶矽膜上形成鈷矽化物膜，而謀求閘極電極10a之低電阻化。低耐壓MISFET中，由於驅動電壓比高耐壓MISFET低，因此低耐壓MISFET之閘極絕緣膜7之膜厚，係比高耐壓MISFET之閘極絕緣膜8之膜厚薄。 於閘極電極10a兩側之側壁形成有邊牆12，於該邊牆12正下方之p型井5內，係形成有一對低耐壓用低濃度雜質擴散區域(n型半導體區域)11。且，於一對低耐壓用低濃度雜質擴散區域11之外側，形成有低耐壓用高濃度雜質擴散區域(n型半導體區域)13。於該低耐壓用高濃度雜質擴散區域13之表面，係形成有鈷矽化物膜15。如此，藉由1個低耐壓用低濃度雜質擴散區域11、形成於該低耐壓用低濃度雜質擴散區域11之外側之低耐壓用高濃度雜質擴散區域13、及形成於低耐壓用高濃度雜質擴散區域13之表面之鈷矽化物膜15，來形成低耐壓MISFET之源極區域。同樣地，藉由其他1個低耐壓用低濃度雜質擴散區域11、形成於該低耐壓用低濃度雜質擴散區域11之外側之低耐壓用高濃度雜質擴散區域13、及形成於低耐壓用高濃度雜質擴散區域13之表面上的鈷矽化物膜15，而形成低耐壓MISFET之汲極區域。如以上構成低耐壓MISFET。 接著，說明關於形成於高耐壓MISFET上及低耐壓MISFET上之布線構造。於本實施型態，形成於高耐壓MISFET上之布線構造具有1個特徵。首先，說明有關本實施型態之特徵之高耐壓MISFET上之布線構造。 如圖2所示，於高耐壓MISFET上形成有第一層層間絕緣膜。具體而言，第一層層間絕緣膜係由氮化矽膜16與氧化矽膜17之疊層膜形成。然後，於氮化矽膜16及氧化矽膜17所組成之第一層層間絕緣膜形成有：貫通該層間絕緣膜並到達高耐壓MISFET之源極區域之插塞(第一插塞)PLG1；及貫通該層間絕緣膜並到達高耐壓MISFET之汲極區域之插塞(第二插塞)PLG1。然後，於形成有插塞PLG1之第一層層間絕緣膜上，形成有布線(源極布線、汲極布線)HL1。此外，於第一層層間絕緣膜上形成有布線HL1，進一步於包含該布線HL1之第一層層間絕緣膜上，形成有第二層層間絕緣膜或第三層層間絕緣膜，於各個層間絕緣膜上形成有布線。亦即，於高耐壓MISFET上形成有多層布線，但於圖2僅圖示本發明之特徵之第一層布線HL1。 本實施型態之特徵之一係在於，於第一層層間絕緣膜上，形成作為源極布線或汲極布線之布線HL1，且以布線HL1與高耐壓MISFET之閘極電極10b在俯視時不重疊之方式，配置布線HL1之點。 於以往之LCD驅動器，於高耐壓MISFET形成區域，於第一層層間絕緣膜上不形成布線，於第二層層間絕緣膜上首次形成布線。此係從確保高耐壓MISFET之閘極電極與源極布線之耐壓或高耐壓MISFET之閘極電極與汲極布線之耐壓之觀點實施。該情況下，藉由貫通第一層層間絕緣膜與第二層層間絕緣膜之2種層間絕緣膜之插塞，來連接源極布線與高耐壓MISFET之源極區域或汲極布線與高耐壓MISFET之汲極區域。因此，雖憂慮在貫通第一層層間絕緣膜與第二層層間絕緣膜之插塞，電阻會變高，但由於以往較為確保插塞之直徑(例如0.24 mm)，因此插塞之電阻並未作為問題而凸顯。 然而，由於LCD驅動器之小型化，插塞之直徑大幅縮小。例如0.24 mm之插塞徑被縮小化至0.14 mm之插塞徑。該情況下，於一次貫通第一層層間絕緣膜與第二層層間絕緣膜之插塞，高寬比變大，插塞之高電阻化係作為問題而凸顯。 因此，一同進行插塞徑縮小，以及於第一層層間絕緣膜上，形成作為源極布線或汲極布線之布線HL1。藉此，即使縮小插塞徑，由於在第一層層間絕緣膜上形成有布線HL1，因此可縮小插塞PLG1之高寬比，抑制插塞PLG1之高電阻化。總言之，不形成一次貫通第一層層間絕緣膜與第二層層間絕緣膜之插塞，藉由使布線HL1介在第一層層間絕緣膜上，可形成僅貫通第一層層間絕緣膜之插塞PLG1。然後，為了縮小插塞PLG1之高寬比，實施第一層層間絕緣膜之薄膜化。進一步加寬形成於第一層層間絕緣膜上之布線HL1之布線寬，以複數排插塞連接形成於第一層層間絕緣膜上之布線HL1與形成於第二層層間絕緣膜上之布線而構成，來實施插塞及布線之低電阻化。亦即，由於高耐壓MISFET之閘極電極10b之閘極長(閘極寬)較大，為2 mm~3 mm程度，因此以與高耐壓MISFET之閘極電極10b在俯視時具有重疊之方式，於第一層層間絕緣膜上形成布線HL1。 然而，以與高耐壓MISFET之閘極電極10b在俯視時具有重疊之方式，於第一層層間絕緣膜上形成布線HL1之情況時，於高耐壓MISFET之閘極電極10b與構成源極布線或汲極布線之布線HL1間，會發生耐壓不良。作為產生該耐壓不良之原因，除了將第一層層間絕緣膜之膜厚予以薄膜化以外，可舉出於高耐壓MISFET，如上述，閘極電極10b擱置於從半導體基板1S突出之電場緩和用絕緣區域3，進而閘極絕緣膜8之膜厚變厚。藉此，據判在俯視時具有重疊之布線HL1與高耐壓MISFET之閘極電極之距離接近而引起耐壓不良。進一步據判於高耐壓MISFET，驅動電壓較高而為20 V~30 V亦為原因之一。 因此，本實施型態係於第一層層間絕緣膜上，形成作為源極布線或汲極布線之布線HL1，且以布線HL1與高耐壓MISFET之閘極電極10b在俯視時不重疊之方式配置布線HL1。藉此，首先即使將作為LCD驅動器之半導體晶片予以小型化，仍可縮小連接高耐壓MISFET之源極區域或汲極區域與布線HL1之插塞PLG1之高寬比。總言之，由於在第一層層間絕緣膜上形成布線HL1，因此不形成一次貫通第一層層間絕緣膜與第二層層間絕緣膜之插塞，可形成僅貫通第一層層間絕緣膜之插塞PLG1。因此，即使縮小插塞PLG1之直徑，仍可抑制插塞PLG1之高寬比變大。 進一步而言，如圖2所示，形成於第一層層間絕緣膜上之布線HL1係配置為，與高耐壓MISFET之閘極電極10b不具有俯視重疊。藉此，由於在高耐壓MISFET之閘極電極10b之正上方未形成布線HL1，因此即使將第一層層間絕緣膜予以薄膜化，仍可拉開布線HL1與閘極電極10b之距離。因此，可確保高耐壓MISFET之閘極電極10b與作為源極布線或汲極布線之布線HL1之耐壓。亦即，若根據本實施型態，可抑制半導體裝置之小型化所造成之插塞之高電阻化，且可獲得能改善高耐壓MISFET之閘極電極與布線間之耐壓不良之顯著效果。 例如高耐壓MISFET係呈由於第一層層間絕緣膜之薄膜化或閘極絕緣膜之厚膜化、電場緩和用絕緣區域之存在或驅動電壓之高電壓化，容易引起形成於第一層層間絕緣膜之布線(源極布線或汲極布線)HL1與閘極電極10b間之耐壓不良之構造。然而，藉由配置為形成於第一層層間絕緣膜之布線HL1與閘極電極10b在俯視時不重疊，可一面於第一層層間絕緣膜形成布線HL1，且一面拉開布線HL1與閘極電極10b之距離。因此，即使將LCD驅動器予以小型化，仍可抑制插塞之高電阻化，且可獲得能改善高耐壓MISFET之閘極電極與布線間之耐壓不良之顯著效果。 而且，藉由將形成於第一層層間絕緣膜之布線HL1與閘極電極10b配置為在俯視時不重疊，亦可獲得以下所示之效果。亦即，由於配置有布線HL1之第一層層間絕緣膜薄膜化，因此接近布線HL1、高耐壓MISFET之閘極絕緣膜與半導體基板1S之界面即通道區域。於配置為布線HL1與閘極電極10b在俯視時重疊之情況時，布線HL1係與高耐壓MISFET之通道區域在俯視時重疊。此時，若於布線HL1施加高電壓，則由於第一層層間絕緣膜薄膜化，因此唯恐布線HL1作為閘極電極發揮功能。總言之，布線HL1具有與通道區域在俯視時重疊之區域，且若布線HL1與通道區域之距離變近，藉由施加於布線HL1之電壓，與布線HL1在俯視時重疊之通道區域會反轉。亦即，通道區域全體中與布線HL1在俯視時重疊之區域成為反轉狀態。因此，即使於高耐壓MISFET關閉時，布線HL1與通道區域中在俯視時重疊之區域反轉，實質上未反轉之通道區域之距離變窄。如此一來，發生源極區域與汲極區域間之耐壓降低之問題。 然而，於本實施型態，將布線HL1配置為與閘極電極10b在俯視時不重疊。因此，布線HL1係配置為亦與形成於閘極電極10b正下方之通道區域，在俯視時不重疊。因此，可抑制布線HL1作為閘極電極發揮功能。總言之，若根據本實施型態，可防止布線HL1所造成之寄生MISFET發生，可獲得能抑制源極區域與汲極區域間之耐壓降低之效果。 圖3係從上部觀看圖2所示之高耐壓MISFET形成區域之俯視圖。於圖3以A-A線切斷之剖面係對應於圖2之高耐壓MISFET形成區域。如圖3所示，於閘極電極10b之兩側，形成有作為源極區域或汲極區域之高耐壓用高濃度雜質擴散區域14，於高耐壓用高濃度雜質擴散區域14與閘極電極10b間形成有電場緩和用絕緣區域3。於如此構成之高耐壓MISFET上，中介第一層層間絕緣膜(未圖示)來形成布線。具體而言，於作為源極區域或汲極區域之高耐壓用高濃度雜質擴散區域14上，中介插塞(第一插塞或第二插塞)PLG1來形成布線HL1。如觀看圖3可知，該布線HL1係配置為與閘極電極10b不具有俯視重疊，閘極電極10b與布線HL1之距離分開。因此，可知確保閘極電極10b與布線HL1間之耐壓。 另一方面，於閘極電極10b，經由插塞(第三插塞)PLG1而連接有閘極布線GL。該閘極布線GL係由與構成源極布線或汲極布線之布線HL1同層之布線形成。亦即，閘極布線GL形成於第一層層間絕緣膜上。如圖3所示，該閘極布線GL係配置為與閘極電極10b具有在俯視時重疊之區域。總言之，閘極布線GL係與閘極電極10b經由插塞(第三插塞)PLG1電性連接，不會產生閘極電極10b與閘極布線GL間之耐壓之問題。如此，於本實施型態，其目的為確保形成於第一層層間絕緣膜之布線與閘極電極10b之耐壓。然後，與閘極電極10b之耐壓構成問題者，係形成於第一層層間絕緣膜之布線中，與高耐壓MISFET之源極區域電性連接之源極布線或與高耐壓MISFET之汲極區域電性連接之汲極布線等。總言之，特徵點在於配置為閘極電極10b與作為源極布線或汲極布線之布線HL1在俯視時不重疊，與閘極電極10b電性連接之閘極布線GL與閘極電極10b在俯視時重疊亦可。 於此，本實施型態之特徵在於配置為，形成於第一層層間絕緣膜之布線HL1與高耐壓MISFET之閘極電極10b在俯視時不重疊。此時，形成於第一層層間絕緣膜之布線HL1換言之可稱為最下層布線。然而，於第一層層間絕緣膜不形成布線，於第二層層間絕緣膜形成布線之情況，該形成於第二層層間絕緣膜之布線亦可稱為最下層布線。進一步而言，即使是第二層層間絕緣膜，由於在第一層層間絕緣膜上未形成布線，因此亦可合併第一層層間絕緣膜及第二層層間絕緣膜而稱為1個層間絕緣膜。因此，為了特定本實施型態中作為對象之布線HL1，需要某種定義。 說明有關該定義。本實施型態係由於將第一層層間絕緣膜予以薄膜化而產生問題，由於將該第一層層間絕緣膜予以薄膜化，形成於第一層層間絕緣膜之布線HL1與閘極電極10b之耐壓成為問題。因此，將形成於第一層層間絕緣膜之布線HL1定義如下。 如圖2所示，若從半導體基板1S與閘極絕緣膜8之界面至閘極電極10b之上部之距離設為a，從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離設為b，則將a＞b之布線HL1定義為本實施型態中作為對象之布線。總言之，前提為布線HL1與閘極電極10b間之耐壓不良構成問題，著眼於第一層層間絕緣膜被薄膜化之點，及高耐壓MISFET之閘極絕緣膜8厚，且閘極電極10b擱置於電場緩和用絕緣區域3之點。藉此，可明確定義與閘極電極10b間，耐壓不良成為問題者為配置於a＞b之位置之布線HL1。 具體而言，於高耐壓MISFET，以數值例來說明a＞b之關係成立。首先，層間絕緣膜中，氮化矽膜16之膜厚約50 nm，氧化矽膜17之膜厚約500 nm。然後，高耐壓MISFET之閘極絕緣膜8之膜厚約80 nm，閘極電極10b之膜厚約250 nm。因此，從半導體基板1S與閘極絕緣膜8之界面至閘極電極10b之上部之距離a約為330 nm(80 nm+250 nm)。另一方面，從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離b約為220 nm(550 nm-330 nm)。因此，可知a＞b之關係成立。進一步而言，由於電場緩和用絕緣區域3係從半導體基板1S突出約10 nm~20 nm，因此進一步可知符合a＞b之關係。如此，於本實施型態，閘極電極10b與布線HL1間之耐壓雖構成問題，但該耐壓構成問題者係明確化，其係布線HL1與高耐壓MISFET之位置關係成為a＞b之布線。因此，於圖2雖未圖示，但關於形成於第二層以上之層間絕緣膜上之布線，由於a＞b之關係不成立，因此非本實施型態之對象。亦即，關於形成於第二層以上之層間絕緣膜上之布線，由於與高耐壓MISFET之閘極電極10b之距離充分分開，因此耐壓不良不會構成問題。因此，關於形成於第二層以上之層間絕緣膜上之布線(源極布線或汲極布線)，即使配置為與閘極電極10b在俯視時重疊，亦不構成問題。藉由將形成於第二層以上之層間絕緣膜上之布線，配置為與閘極電極10b在俯視時重疊，可效率良好地配置布線。特別是於高耐壓MISFET，由於閘極電極10b之閘極長廣至2 mm~3 mm，因此將形成於第二層以上之層間絕緣膜上之布線，配置為與閘極電極10b在俯視時重疊甚為有用。 接著，說明有關低耐壓MISFET之布線構造。如圖2所示，於低耐壓MISFET上形成有第一層層間絕緣膜。具體而言，第一層層間絕緣膜係由氮化矽膜16及氧化矽膜17之疊層膜形成。然後，於氮化矽膜16及氧化矽膜17所組成之第一層層間絕緣膜，形成貫通該層間絕緣膜並到達低耐壓MISFET之源極區域之插塞PLG1、及貫通該層間絕緣膜並到達低耐壓MISFET之汲極區域之插塞PLG1。然後，於形成有插塞PLG1之第一層層間絕緣膜上，形成有布線(源極布線、汲極布線)LL1。此外，於第一層層間絕緣膜上雖形成有布線LL1，但進一步於包含該布線LL1之第一層層間絕緣膜上，形成有第二層層間絕緣膜或第三層層間絕緣膜，於各個層間絕緣膜上形成有布線。亦即，於低耐壓MISFET上形成有多層布線，但於圖2僅圖示第一層之布線LL1。 於此，低耐壓MISFET係與高耐壓MISFET不同，第一層之布線LL1係配置為與低耐壓MISFET之閘極電極10a在俯視時具有重疊。亦即，於低耐壓MISFET，第一層之布線LL1與閘極電極10a間之耐壓係與高耐壓MISFET不同，不會構成問題。 作為其理由可舉出，於低耐壓MISFET首先由於閘極絕緣膜7之膜厚較薄及未形成電場緩和用絕緣區域3，因此閘極電極10a未擱置於該電場緩和用絕緣區域3。進一步而言，有低耐壓MISFET之驅動電極為5 V~6 V程度，比驅動電壓為20 V~30 V之高耐壓MISFET容易確保耐壓之點。因此，形成於第一層層間絕緣膜上之布線(源極布線或汲極布線)LL1與閘極電極10a具有俯視重疊亦可。藉此，由於低耐壓MISFET之閘極電極10a之閘極長約160 nm，因此可有效地活用該閘極電極10a上之空間。 進一步而言，作為於低耐壓MISFET可確保耐壓之要因，若從半導體基板1S與閘極絕緣膜7之界面至閘極電極10a之上部之距離設為c，從閘極電極10a之上部至形成有布線LL1之層間絕緣膜之上部之距離設為d，則可舉出c＜d。亦即，於高耐壓MISFET成立之關係(a＞b)在低耐壓MISFET不成立，可確保閘極電極10a與布線LL1之距離，結果於低耐壓MISFET，閘極電極10a與布線LL1之耐壓不良不會構成問題。 具體而言，以數值例來說明。例如層間絕緣膜中，氮化矽膜16之膜厚約50 nm，氧化矽膜17之膜厚約500 nm。然後，低耐壓MISFET之閘極絕緣膜7之膜厚約13 nm，閘極電極10a之膜厚約250 nm。因此，從半導體基板1S與閘極絕緣膜7之界面至閘極電極10a之上部之距離c約為263 nm(13 nm+250 nm)。另一方面，從閘極電極10a之上部至形成有布線LL1之層間絕緣膜之上部之距離d約為287 nm(550 nm-263 nm)。因此，可知c＜d之關係成立。亦即，低耐壓MISFET係與高耐壓MISFET不同，由於從閘極電極10a之上部至布線LL1之距離d比從閘極絕緣膜7之下部至閘極電極10a之上部之距離c大，且驅動電壓低，因此即使閘極電極10a與布線LL1具有在俯視時重疊之區域，仍不會產生耐壓不良。 如以上，本實施型態之特徵在於，於高耐壓MISFET形成區域，於第一層層間絕緣膜上形成作為源極布線或汲極布線之布線HL1，且以布線HL1與高耐壓MISFET之閘極電極10b在俯視時不重疊之方式，配置布線HL1。藉此，，可抑制LCD驅動器之小型化所造成之插塞之高電阻化，且可獲得改善高耐壓MISFET之閘極電極與布線間之耐壓不良之顯著效果。 本實施型態之LCD驅動器(半導體裝置)係如上述構成，於以下，參考圖式來說明有關其製造方法。 首先，準備導入有硼(B)等p型雜質之矽單結晶所組成之半導體基板1S。此時，半導體基板1S成為約略呈圓盤形狀之半導體晶圓之狀態。然後，如圖4所示，形成分離半導體基板1S之低耐壓MISFET形成區域與高耐壓MISFET形成區域之元件分離區域2。元件分離區域2係用以使元件不會互相干擾而設置。該元件分離區域2可利用例如LOCOS (local Oxidation of silicon：矽局部氧化)法或STI(shallow trench isolation：淺溝槽隔離)法來形成。例如於STI法，如以下形成元件分離區域2。亦即，於半導體基板1S，使用光微影技術及蝕刻技術來形成元件分離溝槽。然後，以填埋元件分離溝槽之方式，於半導體基板1S上形成氧化矽膜，其後藉由化學機械研磨法(CMP；chemical mechanical polishing)，去除形成於半導體基板1S上之不要之氧化矽膜。藉此，可僅於元件分離溝槽內，形成埋入有氧化矽膜之元件分離區域2。 於本實施型態，於形成元件分離區域2之步驟亦形成電場緩和用絕緣區域3。該電場緩和用絕緣區域3係以與元件分離區域2同樣之方法形成，例如使用STI法或選擇氧化法(LOCOS法)形成。該電場緩和用絕緣區域3形成於高耐壓MISFET形成區域。特別是於高耐壓MISFET形成區域，由於形成電場緩和用絕緣區域3，因此元件分離區域2及電場緩和用絕緣區域3之佔有率變大。因此，例如若以STI法形成元件分離區域2及電場緩和用絕緣區域3，則於高耐壓MISFET形成區域，元件分離區域2及電場緩和用絕緣區域3容易從半導體基板1S之表面突出。總言之，元件分離區域2及電場緩和用絕緣區域3係構成如從半導體基板1S之表面，突出例如10 nm~20 nm。如後述，於高耐壓MISFET，由於閘極電極之端部形成於電場緩和用絕緣區域3上，因此以閘極電極之端部擱置於突出之電場緩和用絕緣區域3之方式形成。特別於LOCOS法(選擇氧化法)，由於選擇氧化膜係以從半導體基板1S之表面隆起之方式形成，因此閘極電極之擱置量亦變大。 接著，如圖5所示，在由元件分離區域2分離之活性區域導入雜質，形成p型井4。p型井4係藉由離子植入法，將例如硼等p型雜質導入於半導體基板1S而形成。該p型井4雖為高耐壓MISFET用之井，但形成於高耐壓MISFET形成區域及低耐壓MISFET形成區域。然後，於p型井4之表面區域形成通道形成用之半導體區域(未圖示)。該通道形成用之半導體區域係用以調整形成通道之臨限值電壓而形成。此外，於本實施型態，雖以同一步驟形成高耐壓MISFET形成區域及低耐壓MISFET形成區域之p型井4，但以個別之步驟形成亦可。該情況下，可分別以最佳條件，來形成導入於高耐壓MISFET形成區域之雜質濃度及導入於低耐壓MISFET形成區域之雜質濃度。 接著，如圖6所示，於低耐壓MISFET形成區域形成p型井5。p型井5係藉由離子植入法，將例如硼等p型雜質導入於半導體基板1S而形成。該p型井5為低耐壓MISFET用之井。其後，於高耐壓MISFET形成區域形成1對高耐壓用低濃度雜質擴散區域6。該高耐壓用低濃度雜質擴散區域6為n型半導體區域，藉由以離子植入法，將磷(P)或砷(As)等n型雜質導入於半導體基板1S而形成。高耐壓用低濃度雜質擴散區域6係以內包電場緩和用絕緣區域3之方式形成。 接下來，如圖7所示，於半導體基板1S上形成閘極絕緣膜。此時，於低耐壓MISFET形成區域形成薄層之閘極絕緣膜7，於高耐壓MISFET形成區域形成厚層之閘極絕緣膜8。例如形成於低耐壓MISFET形成區域之閘極絕緣膜7之膜厚約13 nm程度，形成於高耐壓MISFET形成區域之閘極絕緣膜8之膜厚約80 nm程度。為了形成如此依區域而不同之膜厚之閘極絕緣膜，例如於半導體基板1S上形成厚層之閘極絕緣膜8後，以抗蝕劑膜將高耐壓MISFET形成區域予以遮罩。然後，藉由以該抗蝕劑膜作為掩模之蝕刻，來減少露出之低耐壓MISFET形成區域之閘極絕緣膜8之膜厚，可形成薄層之閘極絕緣膜7。而且，最初於半導體基板1S全體形成薄層之閘極絕緣膜7，於低耐壓MISFET形成區域形成抗蝕劑膜。然後，藉由於露出之高耐壓MISFET形成區域形成厚層之閘極絕緣膜8，可於低耐壓MISFET形成區域形成薄層之閘極絕緣膜7，於高耐壓MISFET形成區域形成厚層之閘極絕緣膜8。形成於高耐壓MISFET形成區域之閘極絕緣膜8之端部係以擱置於電場緩和用絕緣區域3之方式形成。 閘極絕緣膜7，8係由例如氧化矽膜形成，可使用例如熱氧化法形成。但閘極絕緣膜7，8不限定於氧化矽膜，可予以各種變更，例如閘極絕緣膜7，8為氮氧化矽膜(SiON)亦可。亦即，作為使氮偏析於閘極絕緣膜7，8與半導體基板1S之界面之構造亦可。氮氧化矽膜係相較於氧化矽膜，抑制膜中之界面態之發生或減低電子陷阱之效果甚高。因此，可提升閘極絕緣膜7，8之熱載體耐受性，使絕緣耐受性提升。而且，氮氧化矽膜係相較於氧化矽膜，雜質難以貫通。因此，藉由於閘極絕緣膜7，8使用氮氧化矽膜，可抑制起因於閘極電極中之雜質往半導體基板1S側擴散之臨限值電壓之變動。氮氧化矽膜之形成係例如於含NO、NO2 或NH3 該類氮之氣氛中，將半導體基板1S予以熱處理即可。而且，於半導體基板1S之表面，形成由氧化矽膜所組成之閘極絕緣膜7，8後，於含氮之氣氛中，將半導體基板1S予以熱處理，使氮偏析於閘極絕緣膜7，8與半導體基板1S之界面，藉此亦可獲得同樣效果。 而且，閘極絕緣膜7，8亦可由例如介電率高於氧化矽膜之高介電率膜來形成。以往，從絕緣耐受性高、矽-氧化矽界面之電性‧物性安定性等良好之觀點考量，作為閘極絕緣膜7，8係使用氧化矽膜。然而，伴隨於元件之微細化，關於閘極絕緣膜7，8之膜厚亦要求極薄化。若將如此極薄化之氧化矽膜作為閘極絕緣膜7，8使用，則會發生所謂通道電流，其係流於MISFET之通道之電子，將藉由氧化矽膜所形成之障壁作為通道而流至閘極電極。 因此，藉由使用介電率高於氧化矽膜之材料，來使用電容相同仍可增加物理膜厚之高介電體膜。若藉由高介電體膜，由於即使電容相同仍可增加物理膜厚，因此可減低漏洩電流。 例如作為高介電體膜係使用鉿氧化物之一之氧化鉿膜(HfO2 膜)，但取代氧化鉿膜亦可使用如鉿鋁氧化膜、HfON膜(氮氧化鉿膜)、HfSiO膜(鉿矽化物膜)、HfSiON膜(氮氧矽鉿膜)、HfAlO膜之其他鉿系絕緣膜。進一步而言，於該等鉿系絕緣膜，亦可使用導入有氧化鉭、氧化鈮、氧化鈦、氧化鋯、氧化鑭、氧化釔等氧化物之鉿系絕緣膜。鉿系絕緣膜係與氧化鉿膜相同，由於介電率高於氧化矽膜或氮氧化矽膜，因此可獲得與使用氧化鉿膜之情況相同之效果。 接下來，如圖8所示，於閘極絕緣膜7，8上形成多晶矽膜。多晶矽膜9可使用例如CVD法來形成。然後，使用光微影技術及離子植入法，於多晶矽膜9導入磷或砷等n型雜質。 接著，藉由以經圖案化之抗蝕劑膜作為掩模之蝕刻，來加工多晶矽膜9，於低耐壓MISFET形成區域形成閘極電極10a，於高耐壓MISFET形成區域形成閘極電極10b。閘極電極10a之閘極長約為例如160 nm，閘極電極10b之閘極長約為例如2 mm~3 mm程度。形成於高耐壓MISFET形成區域之閘極電極10b之端部係中介閘極絕緣膜8來擱置於電場緩和用絕緣區域3而形成。 於此，於閘極電極10a，10b，在多晶矽膜9中導入有n型雜質。因此，由於可使閘極電極10a，10b之工作函數值成為矽之傳導帶附近(4.15 eV)之值，因此可減低n通道型MISFET之低耐壓MISFET及高耐壓MISFET之臨限值電壓。 接下來，如圖9所示，藉由使用光微影技術及離子植入法，形成於低耐壓MISFET之閘極電極10a整合之淺層之低耐壓用低濃度雜質擴散區域11。淺層之低耐壓用低濃度雜質擴散區域11為n型半導體區域。 然後，如圖10所示，於半導體基板1S上形成氧化矽膜。氧化矽膜可使用例如CVD法來形成。然後，藉由將氧化矽膜予以各向異性蝕刻，可於閘極電極10a，10b之側壁形成邊牆(sidewall)12。邊牆12係由氧化矽膜之單層膜形成，但不限於此，例如形成由氮化矽膜及氧化矽膜之疊層膜所組成之邊牆12亦可。 接著，如圖11所示，藉由使用光微影技術及離子植入法，於低耐壓MISFET形成區域形成整合於邊牆12之深層之低耐壓用高濃度雜質擴散區域13。深層之低耐壓用高濃度雜質擴散區域13為n型半導體區域。藉由該深層之低耐壓用高濃度雜質擴散區域13及淺層之低耐壓用低濃度雜質擴散區域11，形成低耐壓MISFET之源極區域或汲極區域。如此，藉由以淺層之低耐壓用低濃度雜質擴散區域11及深層之低耐壓用高濃度雜質擴散區域13來形成源極區域及汲極區域，可將源極區域及汲極區域製成LDD(Lightly Doped Drain：輕微摻雜汲極)構造。 藉由對於高耐壓MISFET形成區域，亦同時實施形成低耐壓用高濃度雜質擴散區域13之n型雜質之離子植入，亦形成高耐壓用高濃度雜質擴散區域14。該高耐壓用高濃度雜質擴散區域14亦為n型半導體區域，以成為電場緩和用絕緣區域3之外側並內包於高耐壓用低濃度雜質擴散區域6之方式形成。於高耐壓MISFET，亦藉由高耐壓用高濃度雜質擴散區域14及高耐壓用低濃度雜質擴散區域6來形成源極區域或汲極區域。 如此，於形成低耐壓用高濃度雜質擴散區域13及高耐壓用高濃度雜質擴散區域14後，進行1000℃程度之熱處理。藉此進行已導入之雜質之活性化。 其後，如圖12所示，於半導體基板1S上形成鈷膜。此時，以直接相接於閘極電極10a，10b之方式形成鈷膜。同樣地，鈷膜亦直接相接於深層之低耐壓用高濃度雜質擴散區域13及高耐壓用高濃度雜質擴散區域14。 鈷膜可例如使用濺鍍法來形成。然後，形成鈷膜後，施以熱處理，藉此使構成閘極電極10a，10b之多晶矽膜9與鈷膜反應，形成鈷矽化物膜15。藉此，閘極電極10a，10b成為多晶矽膜9與鈷矽化物膜15之疊層構造。鈷矽化物膜15係為了閘極電極10a，10b之低電阻化而形成。同樣地，藉由上述熱處理，於低耐壓用高濃度雜質擴散區域13及高耐壓用高濃度雜質擴散區域14之表面，矽與鈷膜亦反應，形成鈷矽化物膜15。因此，於低耐壓用高濃度雜質擴散區域13及高耐壓用高濃度雜質擴散區域14，亦可謀求低電阻化。 然後，未反應之鈷膜係從半導體基板1S上去除。此外，本實施型態係構成如形成鈷矽化物膜15，但例如取代鈷矽化物膜15，形成鎳矽化物膜或鈦矽化物膜亦可。如此，可於半導體基板1S上，形成低耐壓MISFET及高耐壓MISFET。 接著，說明有關布線步驟。首先，如圖13所示，於半導體基板1S之主面上，形成作為層間絕緣膜之氮化矽膜16，於該氮化矽膜16上形成氧化矽膜17。藉此，第一層層間絕緣膜成為氮化矽膜16與氧化矽膜17之疊層膜。氮化矽膜16可使用例如CVD法來形成，氧化矽膜17可使用以例如TEOS(tetra ethyl ortho silicate：四乙基矽烷)作為原料之CVD法來形成。此時，氮化矽膜16之膜厚約50 nm，氧化矽膜17之膜厚約1100 nm。 其後，如圖14所示，使用例如CMP(Chemical Mechanical Polishing：化學機械研磨)法來將氧化矽膜17之表面予以平坦化。於該步驟，氧化矽膜17之膜厚減少，成為例如約550 nm程度。如此，氧化矽膜17之膜厚被薄膜化。 接下來，如圖15所示，使用光微影技術及蝕刻技術，於氧化矽膜17形成接觸孔CNT1。接觸孔CNT1係貫通由氧化矽膜17及氮化矽膜16所組成之第一層層間絕緣膜，並到達半導體基板1S。具體而言，接觸孔CNT1形成於高耐壓MISFET形成區域及低耐壓MISFET形成區域。於高耐壓MISFET形成區域，形成到達源極區域(鈷矽化物膜15)之接觸孔(第一接觸孔)CNT1，並且形成到達汲極區域(鈷矽化物膜15)之接觸孔(第二接觸孔)CNT1。此外，於圖15雖未圖示，亦形成到達閘極電極10b之接觸孔。同樣地，於低耐壓MISFET形成區域，亦形成到達源極區域(鈷矽化物膜15)之接觸孔CNT1，並且形成到達汲極區域(鈷矽化物膜15)之接觸孔CNT1。此外，雖未圖示，但亦形成到達閘極電極10a之接觸孔。 接著，如圖16所示，於包含接觸孔CNT1之底面及內壁之氧化矽膜17上，形成鈦/氮化鈦膜18a。鈦/氮化鈦膜18a係由鈦膜及氮化鈦膜之疊層膜構成，可藉由使用例如濺鍍法來形成。該鈦/氮化鈦膜18a具有所謂障壁性，其係防止例如於後續步驟填埋之膜材料之鎢往矽中擴散。其後，以填埋接觸孔CNT1之方式，於半導體基板1S之主面整面形成鎢膜18b。該鎢膜18b可使用例如CVD法來形成。 接著，如圖17所示，藉由例如CMP法來去除形成於氧化矽膜17上之不要之鈦/氮化鈦膜18a及鎢膜18b，僅於接觸孔CNT1內殘留鈦/氮化鈦膜18a及鎢膜18b，藉此可形成插塞PLG1。藉由此時之CMP研磨削切氧化矽膜17。具體而言，相對於CMP研磨前，氧化矽膜17之膜厚約550 nm，CMP研磨後，氧化矽膜17之膜厚約500 nm。 於高耐壓MISFET形成區域，形成與高耐壓MISFET之源極區域電性連接之插塞(第一插塞)PLG1或與高耐壓MISFET之汲極區域電性連接之插塞(第二插塞)PLG1。雖未圖示，但亦形成與閘極電極10b電性連接之插塞(第三插塞)。同樣地，於低耐壓MISFET形成區域，形成與低耐壓MISFET之源極區域電性連接之插塞PLG1或與低耐壓MISFET之汲極區域電性連接之插塞PLG1。此外，雖未圖示，但亦形成與閘極電極10a電性連接之插塞。 接著，如圖18所示，於氧化矽膜17及插塞PLG1上，依序形成鈦/氮化鈦膜19a、含有銅之鋁膜19b及鈦/氮化鈦膜19c。該等膜可藉由使用例如濺鍍法來形成。接下來，藉由使用光微影技術及蝕刻技術，進行該等膜之圖案化，形成布線HL1及布線LL1。如此，可於第一層層間絕緣膜上形成布線HL1及布線LL1。 由於在第一層層間絕緣膜上形成布線HL1及布線LL1，因此可縮小與該布線HL1及布線LL1連接之插塞PLG1之高寬比。因此，即使縮小插塞PLG1之直徑來推展晶片區域之小型化，仍可抑制插塞PLG1之高電阻化。進一步於本實施型態，如以下配置經由插塞PLG1而連接於高耐壓MISFET之源極區域之布線(源極布線)HL1，及經由插塞PLG1而連接於高耐壓MISFET之汲極區域之布線(汲極布線)HL1。總言之，配置於第一層層間絕緣膜上之布線HL1與閘極電極10b配置為在俯視時不具有重疊。藉此，由於在高耐壓MISFET之閘極電極10b正上方未形成布線HL1，因此即使將第一層層間絕緣膜予以薄膜化，仍可拉開布線HL1與閘極電極10b之距離。因此，可確保高耐壓MISFET之閘極電極10b與作為源極布線或汲極布線之布線HL1之耐壓。亦即，若根據本實施型態，可抑制半導體裝置之小型化所造成之插塞之高電阻化，且可獲得改善高耐壓MISFET之閘極電極與布線間之耐壓不良之顯著效果。 此外，雖未圖示，但與閘極電極10b電性連接之閘極布線亦形成於第一層層間絕緣膜上。換言之，由於閘極布線亦與構成源極布線或汲極布線之布線HL1以同層形成。由於閘極布線與閘極電極10b電性連接，因此閘極布線與閘極電極10b間之耐壓不會構成問題。因此，閘極布線係配置為與閘極電極10b具有俯視重疊。 另一方面，於低耐壓MISFET形成區域，於第一層層間絕緣膜上形成有布線LL1。於低耐壓MISFET，由於布線LL1與閘極電極10a間之耐壓不構成問題，因此布線LL1係以與閘極電極10a在俯視時具有重疊之方式，寬廣地形成布線寬。藉此，可有效地活用閘極電極10a上之空間，謀求布線LL1之低電阻化。 接著，如圖19所示，於形成有布線HL1及布線LL1之第一層層間絕緣膜上，形成第二層層間絕緣膜之氧化矽膜20。然後，與上述步驟相同，於氧化矽膜20形成插塞PLG2。該插塞PLG2係與布線HL1及布線LL1連接。然後，於形成有插塞PLG2之氧化矽膜20上，形成布線HL2及布線LL2。於此，由於布線HL1及布線HL2係以複數排之插塞PLG2連接，因此可減低布線電阻及插塞電阻。同樣地，由於布線LL1及布線LL2係以複數排之插塞PLG2連接，因此可減低布線電阻及插塞電阻。 於高耐壓MISFET形成區域，形成於第二層層間絕緣膜之氧化矽膜20上之布線HL2亦可配置為與閘極電極10b具有俯視重疊。此係由於配置於第二層層間絕緣膜上之布線HL2與閘極電極10b係比配置於第一層層間絕緣膜上之布線HL1與閘極電極10b之距離充分分開，因此布線HL2與閘極電極10b間之耐壓不會構成問題。因此，作為閘極長可有效地活用約有2 mm~3 mm之閘極電極10b上之空間，擴大布線HL2之布線寬，藉此可謀求布線HL2之低電阻化。而且，於第二層層間絕緣膜上，在與閘極電極10b在俯視時重疊之區域配置複數布線亦可。 進一步藉由於布線HL2及布線LL2之上層形成布線，以形成多層布線。然後，於多層布線之最上層形成凸塊電極。說明關於形成該凸塊電極之步驟。 圖20係表示形成於多層布線上之氧化矽膜21，於氧化矽膜21上形成墊PAD。雖省略氧化矽膜21之下層構造，但於氧化矽膜21之下層，形成有如圖19所示之低耐壓MISFET、高耐壓MISFET及多層布線。 如圖20所示，形成例如氧化矽膜21。氧化矽膜21可使用例如CVD法來形成。然後，於氧化矽膜21上，疊層鈦/氮化鈦膜、鋁膜及鈦/氮化鈦膜而形成。其後，使用光微影技術及蝕刻技術來將疊層膜予以圖案化。藉由該圖案化，可於氧化矽膜21上形成墊PAD。 接下來，如圖21所示，於形成有墊PAD之氧化矽膜21上，形成表面保護膜22。表面保護膜22係藉由例如氮化矽膜形成，可藉由例如CVD法來形成。接著，使用光微影技術及蝕刻技術，於表面保護膜22形成開口部。該開口部形成於墊PAD上，並露出墊PAD之表面。 接著，如圖22所示，於包含開口部內之表面保護膜22上，形成UBM(Under Bump Metal：凸塊下金屬)膜23。UBM膜23可使用例如濺鍍法來形成，藉由例如鈦膜、鎳膜、鈀膜、鈦‧鎢合金膜、氮化鈦膜或金膜等單層膜或疊層膜來形成。於此，UBM膜23除了發揮提升凸塊電極與墊PAD或表面保護膜22之黏著性之功能、或作為電極發揮功能以外，還具有障壁功能，其係抑制或防止於此後之步驟所形成之導體膜之金屬元素往多層布線側移動，或相反地構成多層布線之金屬元素往導體膜側移動。 接著，如圖23所示，於UBM膜23上塗布抗蝕劑膜RES後，藉由對於該抗蝕劑膜RES施以曝光‧顯影處理來進行圖案化。圖案化係以於凸塊電極形成區域不殘留抗蝕劑膜RES之方式進行。然後，如圖24所示，作為導體膜24係例如使用電鍍法來形成金膜。其後，如圖25所示，藉由去除經圖案化之抗蝕劑膜RES及覆蓋抗蝕劑膜RES之UBM膜23，來形成由導體膜24及UBM膜23所組成之凸塊電極BMP。 接著，藉由切割處於半導體晶圓狀態之半導體基板，可獲得經個片化之半導體晶片CHP。個片化所獲得之半導體晶片CHP係如圖1所示。其後，於玻璃基板實裝藉由將半導體基板予以個片化所獲得之半導體晶片CHP。 接著，表示於實裝基板黏著並實裝LCD驅動器之半導體晶片CHP之狀況。圖26係表示於玻璃基板30a實裝半導體晶片CHP之情況(COG：Chip On Glass(覆晶玻璃))。如圖26所示，於玻璃基板30a搭載有玻璃基板30b，藉此形成LCD之顯示部。然後，於LCD之顯示部附近之玻璃基板30a上，搭載有LCD驅動器之半導體晶片CHP。於半導體晶片CHP形成有凸塊電極BMP，形成於凸塊電極BMP及玻璃基板30a上之端子係經由各向異性導電膜(Anisotropic Conductive Film)32連接。而且，玻璃基板30a與可撓性印刷基板(Flexible Printed Circuit：可撓性印刷電路)31亦藉由各向異性導電膜連接。如此，於搭載於玻璃基板30a上之半導體晶片CHP，輸出用之凸塊電極BMP電性連接於LCD之顯示部，輸入用之凸塊電極BMP連接於可撓性印刷基板31。 圖27係表示LCD之全體結構之圖。如圖27所示，於玻璃基板上形成有LCD之顯示部33，於該顯示部33顯示有圖像。於顯示部33附近之玻璃基板上，搭載有LCD驅動器之半導體晶片CHP。於半導體晶片CHP附近搭載有可撓性印刷基板31，於可撓性印刷基板31與LCD之顯示部33間，搭載有LCD驅動器之半導體晶片CHP。如此，可將半導體晶片CHP搭載於玻璃基板上。藉由經過以上步驟，可將LCD驅動器實裝於玻璃基板上以製造LCD。 (實施型態2) 前述實施型態1之特徵之一，如圖28所示，係於第一層層間絕緣膜(氧化矽膜17)上形成作為源極布線或汲極布線之布線HL1，且以布線HL1與高耐壓MISFET之閘極電極10b在俯視時不重疊之方式配置布線HL1之點。於圖28，表示有高耐壓MISFET之閘極電極10b與布線HL1間在俯視時不重疊之距離e，於本實施型態2，說明關於該距離e之具體數值例。 圖28係表示高耐壓MISFET及低耐壓MISFET之剖面圖，且係與圖2相同之圖。惟，於圖28中，表示有高耐壓MISFET之閘極電極10b與布線HL1間在俯視時不重疊之距離e、及插塞PLG1之直徑z。 如圖28所示，高耐壓MISFET之閘極電極10b與布線HL1僅分開俯視之距離e，但該距離e必須考慮以光微影步驟所形成之圖案之尺寸誤差或圖案之對齊偏離來決定。此係由於例如即使設計上為了確保閘極電極10b與布線HL1之耐壓而設定有充分之距離e，但據判亦可能有由於閘極電極10b或布線HL1之加工之尺寸誤差、或者閘極電極10b與插塞PLG1之對齊偏離、或插塞PLG1與布線HL1之對齊偏離等，而使得閘極電極10b與布線HL1加工在俯視時為重疊之情況。該情況下，無法確保閘極電極10b與布線HL1間之耐壓。 因此，必須以即使產生上述光微影步驟中之圖案之尺寸誤差或圖案之對齊偏離，仍可確保閘極電極10b與布線HL1間在俯視時不重疊之距離e之方式，來設定距離e。 圖29係具體表示光微影步驟之圖案之尺寸誤差或圖案間之對齊偏離之圖。例如於圖29，可知以光微影步驟來形成閘極電極10b時，閘極電極10b之尺寸誤差(偏差)最大為40 nm。進一步而言，插塞PLG1對於閘極電極10b之對齊偏離(重疊偏離、偏差)最大為40 nm。同樣地，布線HL1之尺寸誤差最大為40 nm，布線HL1對於插塞PLG1之重疊偏離最大為70 nm。因此，該等尺寸誤差及重疊偏離全都往縮窄閘極電極10b與布線HL1間在俯視時不重疊之距離e之方向作用之情況時，會成為最縮窄距離e之誤差。 總言之，距離e為190 nm(40 nm+40 nm+40 nm+70 nm)以下之情況時，依光微影步驟之圖案之尺寸誤差及圖案間之重疊偏離之大小，會形成為閘極電極10b與布線HL1在俯視時具有重疊區域。其結果，產生無法確保閘極電極10b與布線HL1間之耐壓之事態。換言之，於距離e分開190 nm以上之情況時，無論如何引起光微影步驟之圖案之尺寸誤差或圖案之重疊偏離，均可防止閘極電極10b與布線HL1具有在俯視時重疊之區域。由此，藉由將距離e取定190 nm以上，即使產生光微影步驟之圖案之尺寸誤差或圖案間之重疊偏離，仍可確實地使閘極電極10b與布線HL1在俯視時不重疊。其結果，可確實提升閘極電極10b與布線HL1間之耐壓，可謀求半導體裝置之可靠性提升。 此外，於上述記載中，表示使閘極電極10b與布線HL1在俯視時不重疊之距離e，大於單純地加上光微影步驟之圖案之尺寸誤差或圖案間之重疊偏離之值(190 nm)之例。其中，由於據判所有圖案之尺寸誤差或圖案間之重疊偏離均產生於縮窄距離e之方向之確率甚少，因此作為評估距離e之方法，亦可考慮取定2次方和之其他方法。亦即，以2次方和來評估光微影步驟之圖案之尺寸誤差或圖案間之重疊偏離。該情況下，距離e成為√(40×40+40×40+40× 40+70×70)=98 nm，藉由使距離e分開98 nm(約100 nm)以上，可充分防止閘極電極10b與布線HL1在俯視時重疊。 (實施型態3) 前述實施型態1之特徵之一係在於配置為，形成於圖28所示之第一層層間絕緣膜(氧化矽膜17)之布線HL1與高耐壓MISFET之閘極電極10b在俯視時不重疊。總言之，於前述實施型態1著眼於由於將第一層層間絕緣膜予以薄膜化所產生之問題，即著眼於由於將該第一層層間絕緣膜予以薄膜化，形成於第一層層間絕緣膜之布線HL1與閘極電極10b之耐壓會構成問題之點。此時，於前述實施型態1係定量地定義第一層層間絕緣膜被薄膜化。 具體而言，如圖28所示，若從半導體基板1S與閘極絕緣膜8之界面至閘極電極10b之上部之距離設為a，從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離設為b，則將a＞b之布線HL1定義為前述實施型態1中作為對象之布線。總言之，前提為布線HL1與閘極電極10b間之耐壓不良構成問題，著眼於第一層層間絕緣膜被薄膜化之點，及高耐壓MISFET之閘極絕緣膜8厚，且閘極電極10b擱置於電場緩和用絕緣區域3之點。藉此，可明確定義與閘極電極10b間，耐壓不良成為問題者為配置於a＞b之位置之布線HL1。 於本實施型態3係說明關於以其他條件來改述上述a＞b之條件。首先，如上述，若從半導體基板1S與閘極絕緣膜8之界面至閘極電極10b之上部之距離設為a，從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離設為b，則本發明之前提條件為a＞b之條件。於此，作為其他條件，可舉出插塞PLG1之直徑z與層間絕緣膜(氧化矽膜17+氮化矽膜16)之厚度f(未圖示)(f=a+b)之關係。亦即，插塞PLG1係貫通層間絕緣膜而形成，但從使插塞PLG1之填埋特性良好之觀點考量，高寬比須為特定值以下。於此，高寬比係指藉由層間絕緣膜之厚度f與插塞PLG1之直徑z，表示作f/z之量。該高寬比變大，對應於例如於厚層之層間絕緣膜形成直徑小之插塞PLG1，填埋特性惡化。總言之，從使插塞PLG1之填埋特性良好之觀點考量，須使高寬比為特定值以下。具體而言，例如該條件能以f/z＜5之條件來表示。總言之，若決定層間絕緣膜之厚度f及插塞PLG1之直徑z，以使高寬比f/z成為5以下，則可抑制插塞PLG1之填埋特性惡化。 於此，層間絕緣膜之厚度f=a+b，從該式會成為a=f-b。將此代入a＞b，則成為f＞2b。另一方面，從高寬比之關係式f/z＜5，則成為f＜5z。因此，從f＜5z及f＞2b之2個關係式，可獲得2b＜5z。若針對b來解開該2b＜5z，則成為b＜2.5z。從以上可知，a＞b之條件係利用層間絕緣膜之厚度f=a+b及高寬比之關係式f/z＜5來置換為b＜2.5z之條件。以文句來說明的話，可知若從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離設為b，插塞PLG1之直徑設為z，則b＜2.5z之條件係置換為從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離b，小於插塞PLG1之直徑z之2.5倍之條件。總言之，本發明之特徵在本實施型態3，係於從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離b，小於插塞PLG1之直徑z之2.5倍之情況時，可將閘極電極10b與配線HL1配置為在俯視時不重疊。 此外，插塞PLG1之直徑雖設為z，於插塞PLG1之直徑遍及插塞PLG1之全體為同一時，不會構成問題，但實際上在層間絕緣膜(氧化矽膜17)之表面之直徑最大，隨著往插塞PLG1之底部前進，直徑變小而形成。該情況下，問題在於插塞PLG1之直徑z為何種深度之直徑，於本實施型態3係將插塞PLG1之底部之直徑稱為z。 (實施型態4) 於前述實施型態1係說明關於將本發明適用於高耐壓MISFET之情況，但於本實施型態4，說明關於將本發明適用於電阻元件之情況。亦即，於LCD驅動器，除了低耐壓MISFET或高耐壓MISFET以外，亦形成構成電路之複數電阻元件。該電阻元件中，亦有與高耐壓MISFET同樣被施加高電壓者。因此，在與高耐壓MISFET同樣使用高電壓之電阻元件，耐壓係構成問題。 圖30係表示本實施型態4之電阻元件之俯視圖。於圖30，於半導體基板1S上形成有閘極絕緣膜8，於該閘極絕緣膜8上形成有作為電阻元件之多晶矽膜(導體膜)40。該作為電阻元件之多晶矽膜40係藉由插塞(第四插塞)42來與布線43連接。另一方面，亦形成未與電阻元件連接之布線44。 本實施型態4之特徵在於，將形成於作為電阻元件之多晶矽膜40上之布線43及布線44中被施加與多晶矽膜40不同電位之布線44，配置為與多晶矽膜40在俯視時不重疊。總言之，由於經由多晶矽膜40及插塞42而直接電性連接之布線43導通，因此與多晶矽膜40間不會產生耐壓問題。由此，如圖30所示，多晶矽膜40與布線43配置為在俯視時具有重疊。相對於此，未經由多晶矽膜40及插塞42直接電性連接且被施加與多晶矽膜40不同電位之布線44，係有與多晶矽膜40間產生高電位差之情況，該情況下，於多晶矽膜40與布線44間，耐壓會構成問題。因此，於未經由多晶矽膜40及插塞42直接電性連接之布線44，配置為與作為電阻元件之多晶矽膜40在俯視時不具有重疊。藉由如此地構成，即使於作為電阻元件之多晶矽膜40與布線44間施加有高電壓，仍可確保耐壓。 圖31係以圖30之B-B線切斷之剖面圖。於圖31，以鄰接於高耐壓MISFET形成區域之方式形成電阻元件形成區域。於以下，說明關於形成於電阻元件形成區域之電阻元件之結構。於圖31，於半導體基板1S上，形成有元件分離區域2，於該元件分離區域2上，形成與使用於高耐壓MISFET之閘極絕緣膜8相同膜厚之膜(稱為閘極絕緣膜8)。然後，於該閘極絕緣膜8上形成有多晶矽膜40，多晶矽膜40係使用與構成高耐壓MISFET之閘極電極10b之多晶矽膜同一之膜來形成。該多晶矽膜40係作為電阻元件來發揮功能。於該多晶矽膜40之側壁，經過形成MISFET之邊牆12之步驟，來形成與邊牆12同等之邊牆41。進一步於多晶矽膜40之表面之一部分，形成鈷矽化物膜15。 然後，以覆蓋多晶矽膜40之方式形成層間絕緣膜。該層間絕緣膜係由氮化矽膜16及氧化矽膜17形成。於層間絕緣膜，形成貫通層間絕緣膜並到達形成於多晶矽膜40之表面之鈷矽化物膜15之插塞42，與該插塞42直接電性連接之布線43形成於層間絕緣膜上。由於圖31係表示以圖30之B-B線切斷之剖面圖，因此圖示有經由插塞42而與多晶矽膜40直接電性連接之布線43。此外，於圖30圖示本實施型態4之特徵，即布線44與多晶矽膜40在俯視時不具有重疊。 於此，電阻元件係使用形成高耐壓MISFET之步驟來形成。亦即，形成於元件分離區域2上之閘極絕緣膜8亦使用與高耐壓MISFET之閘極絕緣膜8同一之膜，且形成於閘極絕緣膜8上之多晶矽膜40亦使用與構成高耐壓MISFET之閘極電極10b之多晶矽膜同一之膜。因此，電阻元件之高度係成為與高耐壓MISFET之高度相同之高度。 另一方面，層間絕緣膜之厚度係於高耐壓MISFET形成區域及電阻元件形成區域相同，且從儘可能縮小於高耐壓MISFET之插塞PLG1之高寬比之觀點考量，進行層間絕緣膜之薄膜化。 由此，於高耐壓MISFET形成區域，若從半導體基板1S與閘極絕緣膜8之界面至閘極電極10b之上部之距離設為a，從閘極電極10b之上部至形成有布線HL1之層間絕緣膜之上部之距離設為b，則成為a＞b之條件。 然後，多晶矽膜40(電阻元件)形成於閘極絕緣膜8上，且多晶矽膜40(電阻元件)係以與構成高耐壓MISFET之閘極電極10b之多晶矽膜同一膜形成。因此，於電阻元件形成區域，從半導體基板1S與閘極絕緣膜8之界面至多晶矽膜40之上部之距離亦與a相同，從多晶矽膜40之上部至形成有布線43或布線44(參考圖30)之層間絕緣膜之上部之距離亦與b相同。因此，於電阻元件形成區域，a＞b之條件亦成立。 從以上，於電阻元件，介在於多晶矽膜40與布線44(於圖31未圖示)間之層間絕緣膜之膜厚變薄，與高耐壓MISFET相同，中介有層間絕緣膜之多晶矽膜40與布線44間之耐壓構成問題。因此，如圖30所示，於電阻元件，亦將形成於作為電阻元件之多晶矽膜40上之布線43及布線44中被施加與多晶矽膜40不同電位之布線44，配置為與多晶矽膜40在俯視時不重疊。藉由如此地構成，即使層間絕緣膜變薄，仍可確保多晶矽膜40與布線44間之耐壓。 於此，作為降低電阻元件之高度之方法，可考慮不於厚層之閘極絕緣膜8上形成構成電阻元件之多晶矽膜40，而於元件分離區域2上直接形成之情況，或於低耐壓MISFET之薄層之閘極絕緣膜上形成。該情況下，因構成電阻元件之多晶矽膜40之高度變低之部分，可增厚介在多晶矽膜40與布線44間之層間絕緣膜之厚度，因此據判可提升多晶矽膜40與布線44之耐壓。 然而，本實施型態4係根據以下所示之理由，在與高耐壓MISFET之閘極絕緣膜8同一之膜上，形成作為電阻元件之多晶矽膜40。參考圖式來說明關於該理由。圖32及圖33係表示形成一般之元件分離區域之步驟之剖面圖。例如圖32所示，藉由使用光微影技術及蝕刻技術，於半導體基板1S形成元件分離溝槽2a。然後，如圖33所示，以於該元件分離溝槽2a埋入氧化矽膜之方式形成後，以化學機械研磨法(CMP：Chemical Mechanical Polishing)去除形成於半導體基板1S之表面之氧化矽膜。藉此，可僅於元件分離溝槽2a內殘留氧化矽膜，因此可於元件分離溝槽2a，形成僅埋入有氧化矽膜之元件分離區域2。圖32及圖33為正常之元件分離區域2之形成步驟。 然而，例如圖34所示，於半導體基板1S形成元件分離溝槽2a時，於半導體基板1S之蝕刻區域附著有異物45a。如此一來，該異物45a成為掩模，形成於異物下層之矽未被蝕刻而殘留。亦即，如圖34所示，於異物45a之下層形成蝕刻殘留物45。其後，如圖35所示，形成以氧化矽膜填埋元件分離溝槽2a之元件分離區域2之情況時，亦維持形成有蝕刻殘留物45。 因此，若於形成有蝕刻殘留物45之元件分離區域2上形成作為電阻元件之多晶矽膜40，則由於蝕刻殘留物45係由矽形成，因此發生多晶矽膜40及半導體基板1S經由蝕刻殘留物45而短路之不便。該不便係於元件分離區域2上直接形成有多晶矽膜40之情況下變得顯著，但如圖36所示，中介薄層之閘極絕緣膜7而形成有多晶矽膜40之情況時，由於對於多晶矽膜40施加有高電壓，因此亦容易發生短路不良。 由此，如圖37所示，於元件分離區域2上形成厚層之閘極絕緣膜8後，於該厚層之閘極絕緣膜8上形成多晶矽膜40。藉由於作為電阻元件之多晶矽膜40與元件分離區域2間形成厚層之閘極絕緣膜8，例如圖37所示，即使於元件分離區域2發生蝕刻殘留物45，仍可大幅減低多晶矽膜40及半導體基板1S經由蝕刻殘留物45而短路。 從以上理由，將構成電阻元件之多晶矽膜40，形成在與高耐壓MISFET之閘極絕緣膜8同一厚度之閘極絕緣膜8上。因此，多晶矽膜40(電阻元件)形成於閘極絕緣膜8上，且多晶矽膜40(電阻元件)係以與構成高耐壓MISFET之閘極電極10b之多晶矽膜同一膜來形成。因此，於電阻元件形成區域，從半導體基板1S與閘極絕緣膜8之界面至多晶矽膜40之上部之距離亦與a相同，從多晶矽膜40之上部至形成有布線43或布線44(參考圖30)之層間絕緣膜之上部之距離亦與b相同。因此，於電阻元件形成區域，a＞b之條件亦成立。 然而，於本實施型態4，由於將形成於作為電阻元件之多晶矽膜40上之布線43及布線44中被施加與多晶矽膜40不同電位之布線44，配置為與多晶矽膜40在俯視時不重疊，因此即使層間絕緣膜變薄，仍發揮可確保多晶矽膜40與布線44間之耐壓之顯著效果。 (實施型態5) 於前述實施型態1中，係說明有關在形成低耐壓MISFET及高耐壓MISFET後，以覆蓋低耐壓MISFET及高耐壓MISFET之方式而形成層間絕緣膜，其後於層間絕緣膜上形成布線之步驟。於本實施型態5，係進一步詳細說明層間絕緣膜之形成步驟。 圖38係表示於半導體基板1S上形成有低耐壓MISFET、高耐壓MISFET及電阻元件之狀況之剖面圖。亦即，於圖38，除了低耐壓MISFET及高耐壓MISFET以外，亦形成有電阻元件。該電阻元件係利用形成高耐壓MISFET之步驟而形成。然後，如圖38所示，以覆蓋低耐壓MISFET、高耐壓MISFET及電阻元件之方式，形成氮化矽膜16。氮化矽膜16可使用例如CVD法來形成。 接下來，如圖39所示，於形成在半導體基板1S上之氮化矽膜16上，形成氧化矽膜50。該氧化矽膜50能以利用例如高密度電漿(high density plasma)之高密度電漿CVD法形成。高密度電漿係指利用高頻電場‧磁場，來將氣體予以高密度地化為電漿，高密度電漿CVD法係指使導入於處理室內之氣體化為高密度電漿，使高密度電漿進行化學反應，於半導體基板1S上堆積膜之方法。作為高密度電漿之發生方法，有例如誘導結合電漿(ICP：induction coupled plasma)或電子迴旋共鳴(ECR：electron cyclotron resonance)法等。 誘導結合電漿係於化學汽相成長法所使用之高密度電漿之一種，以經誘導結合之高頻線圈來激發導入於處理室內之氣體以使其發生之電漿。另一方面，電子迴旋共鳴為以下所示之現象。亦即，若電子於磁場中受到勞侖茲力，則會進行環繞與磁場呈垂直之平面內之迴旋運動。此時，若於電子之運動平面內，賦予環繞頻率一致之電場，則引起迴旋運動與電場之能量共鳴，電場能量會由電子吸收，對於電子供給甚大之能量。利用該現象，可將各種氣體化為高密度電漿。 如以上以高密度電漿CVD法所形成之氧化矽膜50係具有填埋特性良好之優點。因此，藉由於氮化矽膜16上，形成以高密度電漿CVD法所形成氧化矽膜50，即使於SRAM(Static Random Access Memory：靜態隨機存取記憶體)之記憶胞等微細化進展，閘極電極間之間隔變小之元件，仍可使氧化矽膜對於閘極電極間之填埋特性良好。總言之，於作為LCD驅動器之半導體裝置亦搭載有SRAM。該SRAM由於微細化進展，因此閘極電極間之距離變得非常窄。因此，以使用通常密度之電漿之CVD法，於該閘極電極間埋入氧化矽膜之情況時，無法充分地填埋閘極電極間之空間，於閘極電極間之空間發生「孔隙」。若於閘極電極間發生「孔隙」，則於後述步驟中形成插塞時所使用之導體膜會侵入「孔隙」內部，中介侵入「孔隙」內部之導體膜而鄰接之插塞會短路而發生不良。因此，本實施型態5係使用填埋特性佳之高密度電漿CVD法，於氮化矽膜16上形成氧化矽膜50。如此藉由使用高密度電漿CVD法堆積氧化矽膜50，於SRAM等經微細化之元件，可提升對於閘極電極間之空間之填埋特性。其結果，可抑制發生「孔隙」，可防止鄰接插塞之短路不良。 接著，如圖40所示，於氧化矽膜50上形成氧化矽膜51。氧化矽膜51能以例如原料使用TEOS(tetra ethyl ortho silicate：四乙基矽烷)之電漿CVD法來形成。該原料使用TEOS之電漿CVD法係使用通常密度低於上述高密度電漿CVD法之電漿。原料使用TEOS之通常之電漿CVD法係具有氧化矽膜51之膜厚控制性良好之特徵，氧化矽膜51係用以爭取層間絕緣膜之膜厚而形成。 接下來，如圖41所示，將氧化矽膜51之表面予以平坦化。氧化矽膜51表面之平坦化係藉由例如以化學機械研磨法(CMP)，研磨氧化矽膜51之表面來進行。於該步驟中，由於CMP所造成之研磨量之偏差等，氧化矽膜51之膜厚變薄，唯恐高耐壓MISFET之上部或電阻元件之上部露出。 因此，接著如圖42所示，於經平坦化之氧化矽膜51上，形成氧化矽膜(間隙絕緣膜)52。該氧化矽膜52係與氧化矽膜51相同，能以原料使用TEOS之通常之電漿CVD法來形成。 接下來，如圖43所示，使用光微影技術及蝕刻技術，於層間絕緣膜(氧化矽膜52、氧化矽膜51、氧化矽膜50及氮化矽膜16)形成接觸孔。接觸孔係貫通層間絕緣膜並到達半導體基板1S。 然後，於包含接觸孔之底面及內壁之層間絕緣膜上，形成鈦/氮化鈦膜。鈦/氮化鈦膜係由鈦膜及氮化鈦膜之疊層膜構成，可藉由例如使用濺鍍法來形成。其後，以填埋接觸孔之方式，於半導體基板1S之主面整面形成鎢膜。該鎢膜可使用例如CVD法來形成。 接著，藉由以例如CMP法來去除形成於層間絕緣膜上之不要之鈦/氮化鈦膜及鎢膜，僅於接觸孔內殘留鈦/氮化鈦膜及鎢膜，可形成插塞PLG1及插塞42。 接著，如圖44所示，於氧化矽膜52及插塞PLG1上，依序形成鈦/氮化鈦膜、含有銅之鋁膜及鈦/氮化鈦膜。該等膜可藉由使用例如濺鍍法來形成。接下來，藉由使用光微影技術及蝕刻技術，進行該等膜之圖案化，形成布線HL1、布線LL1、布線43及布線53。如此，可於第一層層間絕緣膜上，形成布線HL1、布線LL1、布線43及布線53。 本實施型態5亦與前述實施型態1相同，以配置於第一層層間絕緣膜上之布線HL1與閘極電極10b在俯視時不具有重疊之方式配置。藉此，由於高耐壓MISFET之閘極電極10b正上方未形成有布線HL1，因此即使將第一層層間絕緣膜予以薄膜化，仍可拉開布線HL1與閘極電極10b之距離。因此，可確保高耐壓MISFET之閘極電極10b與作為源極布線或汲極布線之布線HL1之耐壓。 另一方面，於電阻元件形成區域，經由插塞42而直接電性連接於作為電阻元件之多晶矽膜40之布線43，係以與多晶矽膜40在俯視時具有重疊之方式形成。但由於將形成於作為電阻元件之多晶矽膜40上之布線43及布線53中未與插塞42來直接與多晶矽膜40連接，且被施加與多晶矽膜40不同電位之布線53，配置為與多晶矽膜40在俯視時不重疊，因此即使層間絕緣膜變薄，仍可確保多晶矽膜40與布線53間之耐壓。 以上，根據實施型態來具體說明由本發明者所實現之發明，但本發明不限定於前述實施型態，當然可於不脫離其要旨之範圍內予以各種變更。 於前述實施型態，說明關於使用n通道型MISFET來作為形成於LCD驅動器之低耐壓MISFET及高耐壓MISFET之例，但使用p通道型MISFET來作為低耐壓MISFET及高耐壓MISFET之情況，亦可適用本實施型態之技術思想。 (產業上之可利用性) 本發明可廣泛利用於製造半導體裝置之製造業。In the following implementation forms, for the sake of cheapness, when necessary, they are divided into plural sections or implementation forms to explain, but unless specifically stated otherwise, they are not mutually exclusive, and one side belongs to the other Part of or all of the modifications, details, supplementary explanations, etc. Moreover, in the following implementation types, when referring to the number of elements (including the number, value, amount, range, etc.), except for the case where it is specifically stated, and the case where it is clearly limited to a specific number in principle, etc., It is not limited to this specific number, and may be more than or less than a specific number. Furthermore, in the following implementation forms, the constituent elements (including element steps, etc.) need not be redundant, except for the case where it is specifically stated, and the case where it is judged to be obviously necessary in principle, and of course, it is not necessarily necessary. Similarly, in the following implementation forms, when referring to the shape and positional relationship of the constituent elements, etc., except for the case where it is specifically stated, and the case where it is clearly judged to be negative in principle, it basically includes an approximation to the shape, etc. Or similar. At this time, the above numerical values and ranges are also as described above. In addition, in all the drawings for explaining the embodiment, the same components are attached with the same reference numerals in principle, and repeated descriptions thereof are omitted. In addition, in order to make the drawings easy to understand, hatching may be attached even in a top view. (Embodiment Mode 1) First, a semiconductor wafer for an LCD driver in this embodiment mode will be described. FIG. 1 is a plan view showing the structure of a semiconductor wafer CHP (semiconductor device) in this embodiment. The semiconductor chip CHP in this embodiment is an LCD driver. As shown in FIG. 1, the semiconductor wafer CHP has a semiconductor substrate 1S formed in, for example, an elongated rectangular shape, and an LCD driver capable of driving, for example, a liquid crystal display device is formed on a main surface thereof. The LCD driver has a function of supplying voltage to each pixel constituting a cell array of the LCD and controlling the direction of liquid crystal molecules, and has a gate driving circuit C1, a source driving circuit C2, a liquid crystal driving circuit C3, Graphics RAM (Random Access Memory) C4 and peripheral circuit C5. Near the outer periphery of the semiconductor wafer CHP, a plurality of bump electrodes BMP are arranged at specific intervals along the outer periphery of the semiconductor wafer CHP. The plurality of bump electrodes BMP are disposed on an effective area of a device or a wiring on which a semiconductor wafer CHP is disposed. In the plurality of bump electrodes BMP, there are bump electrodes for integrated circuits that are structurally necessary for the integrated circuit, or dummy bump electrodes that are not structurally necessary for the integrated circuit. Near the one long side and the two short sides of the semiconductor wafer CHP, the bump electrodes BMP are arranged in a lattice cross shape. The plurality of bump electrodes BMP arranged in a lattice cross shape are mainly bump electrodes for a gate output signal or a source output signal. The bump electrode BMP arranged in a lattice cross at the center of the long side of the semiconductor wafer CHP is a bump electrode for the source output signal, and is near the two corners of the long side of the semiconductor wafer CHP and the two short sides of the semiconductor wafer CHP. The configured bump electrode BMP is a bump electrode for the gate output signal. By adopting such a lattice cross configuration, it is possible to suppress the increase in the size of the semiconductor chip CHP, and at the same time, it is possible to arrange a number of bump electrodes BMP for gate output signals or bump electrodes BMP for source output signals. That is, the wafer size can be reduced while increasing the number of bump electrodes. Further, the bump electrodes BMP are arranged near the other long side of the semiconductor wafer CHP so as not to be arranged in a grid, but to be arranged in a straight line. The bump electrodes BMP arranged in a linear manner are bump electrodes for digital input signals or analog input signals. Further, dummy bump electrodes are formed near the four corners of the semiconductor wafer CHP. In addition, FIG. 1 illustrates that the bump electrodes BMP for gate output signals or source output signals are arranged in a lattice cross configuration, and the bump electrodes BMP for digital input signals or analog input signals are arranged in a straight line. example. However, it is also possible to configure the bump electrodes BMP for gate output signals or source output signals to be linear, and the bump electrodes BMP for digital input signals or analog input signals to be arranged in a lattice cross configuration. The outer dimension of the semiconductor wafer CHP is, for example, the length in the short-side direction 1. 0 mm, long side length 12. 0 mm, or the short side length 1. 0 mm, length in the long side direction 10. 0 mm. Furthermore, there are, for example, the length in the short side direction of 2. 0 mm, long side length 20. 0 mm. As such, the semiconductor wafer CHP used in the LCD driver has a rectangular shape. Specifically, there are many cases where the ratio of the length of the short side to the length of the long side is 1: 8 to 1:12. Further, there is a length of 5 mm or more in the long side direction. Inside the semiconductor chip CHP of the LCD driver configured as shown in FIG. 1, there are a low withstand voltage MISFET used in logic circuits and the like and a high withstand voltage MISFET used in liquid crystal drive circuits and the like. For example, in this specification, a MISFET operating with a driving voltage of about 5 V to 6 V is called a low withstand voltage MISFET, and a MISFET operating with a driving voltage of about 20 V to 30 V is called a high withstand voltage MISFET. FIG. 2 is a cross-sectional view of a MISFET existing inside the semiconductor wafer CHP shown in FIG. 1. FIG. FIG. 2 illustrates a low breakdown voltage MISFET and a high breakdown voltage MISFET. First, the structure of a high-withstand voltage MISFET will be described. As shown in FIG. 2, an element isolation region 2 is formed on a semiconductor substrate 1S in a region with a high breakdown voltage MISFET. That is, a high breakdown voltage MISFET is formed in the active region separated by the element isolation region 2. A p-type well 4 is formed in the semiconductor substrate 1S sandwiched between the plurality of element isolation regions 2. This p-type well 4 is a well formed for high withstand voltage MISFET. Further, a region is formed in the high-withstand voltage MISFET, and an insulating region 3 for electric field relaxation is formed in a region sandwiched by the plurality of element isolation regions 2. The insulating region 3 for electric field relaxation has a structure similar to that of the element isolation region 2 and is formed by a shallow trench isolation (STI) method. A pair of low-concentration impurity diffusion regions for high withstand voltage (n-type semiconductor region) 6 are formed in the p-type well 4. Each low-concentration impurity diffusion region for high withstand voltage is formed by including an electric field relaxation insulation region 3. . A gate insulating film 8 is formed on the surface of the semiconductor substrate 1S located between a pair of low-concentration impurity diffusion regions 6 for high withstand voltage, and a gate electrode 10 b is formed on the gate insulating film 8. The gate insulating film 8 is formed of, for example, a silicon oxide film, and the gate electrode 10b is formed of, for example, a laminated film of a polycrystalline silicon film and a cobalt silicide film. As the gate electrode 10b, a cobalt silicide film is formed on the polycrystalline silicon film, thereby reducing the resistance of the gate electrode 10b. The gate insulating film 8 is formed by resting its ends on the electric field relaxation insulating region 3. In short, in the region where the high-withstand voltage MISFET is formed, the element isolation region 2 and the electric field mitigation insulating region 3 have a higher occupation ratio, and the element isolation region 2 and the electric field mitigation insulating region 3 are easily removed from the surface of the semiconductor substrate 1S protruding. Therefore, the end portion of the gate insulating film 8 has a shape resting on the insulating region 3 for electric field relaxation. Therefore, the gate electrode 10b formed on the gate insulating film 8 is also formed in such a manner that its ends are raised. Next, side walls 12 are formed on the side walls on both sides of the gate electrode 10b, and the side walls 12 are also formed on the insulation region 3 for electric field mitigation. A high-concentration impurity diffusion region (n-type semiconductor region) 14 for high withstand voltage is formed outside the electric field relaxation insulating region 3 and inside the low-concentration impurity diffusion region 6 for high withstand voltage. A cobalt silicide film 15 is formed on the surface of the high-concentration impurity diffusion region 14 for high withstand voltage. In this way, one pair of low-concentration impurity diffusion regions 6 for high withstand voltage, one high-concentration impurity diffusion region 14 for high withstand voltage, and cobalt silicide formed inside the low-concentration impurity diffusion region 6 for high withstand voltage. The film 15 forms a source region of the high-withstand voltage MISFET. Similarly, a pair of the other one of the low-concentration impurity diffusion region 6 for high withstand voltage is formed inside the high-concentration impurity diffusion region 14 for high withstand voltage and cobalt silicide formed inside the low-concentration impurity diffusion region 6 for high withstand voltage. The object film 15 forms a drain region of a high-withstand voltage MISFET. In this embodiment, since the electric field mitigation insulating region 3 is formed at the end portion of the gate electrode 10b, the electric field formed under the end portion of the gate electrode 10b can be relaxed. Therefore, the withstand voltage between the gate electrode 10b and the source region or between the gate electrode 10b and the drain region can be ensured. That is, in the high-withstand voltage MISFET structure, if the insulation region 3 for electric field relaxation is formed, the withstand voltage can be ensured even if the driving voltage becomes 20 V to 30 V. The high-withstand voltage MISFET in this embodiment is configured as described above, and the structure of the low-withstand voltage MISFET in this embodiment is described below. In FIG. 2, in the low-withstand voltage MISFET formation region, an element isolation region 2 is formed on the semiconductor substrate 1S. That is, the active region separated in the element isolation region 2 is formed with a low breakdown voltage MISFET. A p-type well 4 is formed in the semiconductor substrate 1S sandwiched between the plurality of device isolation regions 2. In addition, a well for low-withstand voltage MISFET, that is, a p-well 5 is formed in the p-well 4. In addition, in the low-withstand voltage MISFET formation region, the electric field relaxation insulating region 3 is not formed. A gate insulating film 7 is formed on the p-type well 5, and a gate electrode 10a is formed on the gate insulating film 7. The gate insulating film 7 is formed of, for example, a silicon oxide film, and the gate electrode 10a is formed of, for example, a laminated film of a polycrystalline silicon film and a cobalt silicide film. As the gate electrode 10a, the resistance of the gate electrode 10a can be reduced by forming a cobalt silicide film on the polycrystalline silicon film. In the low-withstand voltage MISFET, since the driving voltage is lower than that of the high-withstand voltage MISFET, the film thickness of the gate insulating film 7 of the low-withstand voltage MISFET is thinner than that of the high-withstand voltage MISFET. Side walls 12 are formed on the side walls on both sides of the gate electrode 10a. A pair of low-concentration low-concentration impurity diffusion regions (n-type semiconductor regions) 11 are formed in the p-type well 5 directly below the side walls 12. Further, outside the pair of low-withstand-voltage low-concentration impurity diffusion regions 11, a low-withstand-voltage high-concentration impurity diffusion region (n-type semiconductor region) 13 is formed. A cobalt silicide film 15 is formed on the surface of the high-concentration impurity diffusion region 13 for low withstand voltage. In this way, a low-concentration impurity diffusion region 11 for low withstand voltage, a high-concentration impurity diffusion region 13 for low withstand voltage formed outside the low-concentration impurity diffusion region 11 for low withstand voltage, and a low withstand voltage are formed. The cobalt silicide film 15 on the surface of the high-concentration impurity diffusion region 13 is used to form the source region of the low-withstand voltage MISFET. Similarly, another low-concentration impurity diffusion region 11 for low withstand voltage, a high-concentration impurity diffusion region 13 for low withstand voltage formed outside the low-concentration impurity diffusion region 11 for low withstand voltage, and a low-concentration impurity diffusion region 13 formed at low The cobalt silicide film 15 on the surface of the withstand voltage high-concentration impurity diffusion region 13 forms a drain region of the low withstand voltage MISFET. A low-withstand voltage MISFET is configured as described above. Next, a wiring structure formed on a high-withstand voltage MISFET and a low-withstand voltage MISFET will be described. In this embodiment, the wiring structure formed on the high-withstand voltage MISFET has one characteristic. First, a wiring structure on a high withstand voltage MISFET, which is characteristic of this embodiment mode, will be described. As shown in FIG. 2, a first interlayer insulating film is formed on the high-withstand voltage MISFET. Specifically, the first interlayer insulating film is formed of a laminated film of a silicon nitride film 16 and a silicon oxide film 17. Then, a first interlayer insulating film composed of the silicon nitride film 16 and the silicon oxide film 17 is formed with a plug (first plug) PLG1 penetrating the interlayer insulating film and reaching the source region of the high-withstand voltage MISFET. ; And a plug (second plug) PLG1 that penetrates the interlayer insulating film and reaches the drain region of the high-withstand voltage MISFET. Then, wiring (source wiring, drain wiring) HL1 is formed on the first interlayer insulating film on which the plug PLG1 is formed. In addition, a wiring HL1 is formed on the first interlayer insulating film. Further, a second interlayer insulating film or a third interlayer insulating film is formed on the first interlayer insulating film including the wiring HL1. Wiring is formed on the interlayer insulating film. That is, a multilayer wiring is formed on the high-withstand voltage MISFET, but FIG. 2 illustrates only the first-layer wiring HL1 which is a feature of the present invention. One of the characteristics of this embodiment is that a wiring HL1 as a source wiring or a drain wiring is formed on the first interlayer insulating film, and the wiring electrode HL1 and the gate electrode of the high-withstand voltage MISFET are formed. 10b arranges the points of the wiring HL1 in such a manner that they do not overlap in a plan view. In the conventional LCD driver, wiring was not formed on the first interlayer insulating film in the region with a high breakdown voltage MISFET, and wiring was formed on the second interlayer insulating film for the first time. This is implemented from the viewpoint of ensuring the withstand voltage of the gate electrode and source wiring of the high withstand voltage MISFET or the withstand voltage of the gate electrode and drain wiring of the high withstand voltage MISFET. In this case, the source wiring and the source region or the drain wiring of the high-withstand voltage MISFET are connected by plugs that penetrate the two types of interlayer insulating films of the first interlayer insulating film and the second interlayer insulating film. And the drain region of the high withstand voltage MISFET. Therefore, although there is concern that the plug will penetrate through the first interlayer insulating film and the second interlayer insulating film, the resistance will increase, but because the diameter of the plug is relatively ensured in the past (for example, 0. 24 mm), so the resistance of the plug is not highlighted as a problem. However, due to the miniaturization of the LCD driver, the diameter of the plug is greatly reduced. For example 0. The plug diameter of 24 mm has been reduced to 0. 14 mm plug diameter. In this case, when the plug that penetrates the first interlayer insulating film and the second interlayer insulating film at a time, the aspect ratio becomes large, and the high resistance of the plug is prominent as a problem. Therefore, the plug diameter is reduced and the wiring HL1 as a source wiring or a drain wiring is formed on the first interlayer insulating film. Accordingly, even if the plug diameter is reduced, since the wiring HL1 is formed on the first interlayer insulating film, the aspect ratio of the plug PLG1 can be reduced, and the resistance of the plug PLG1 can be suppressed from being increased. In short, without forming a plug that penetrates the first interlayer insulating film and the second interlayer insulating film at one time, by passing the wiring HL1 on the first interlayer insulating film, it is possible to form only the first interlayer insulating film. Of the plug PLG1. Then, in order to reduce the aspect ratio of the plug PLG1, the first interlayer insulating film is thinned. Further widening the wiring width of the wiring HL1 formed on the first interlayer insulating film, and connecting the wiring HL1 formed on the first interlayer insulating film and the second interlayer insulating film with a plurality of rows of plugs. The wiring is configured to reduce the resistance of the plug and the wiring. That is, since the gate length (gate width) of the gate electrode 10b of the high withstand voltage MISFET is large, about 2 mm to 3 mm, it overlaps with the gate electrode 10b of the high withstand voltage MISFET in a plan view. In this way, the wiring HL1 is formed on the first interlayer insulating film. However, when the wiring HL1 is formed on the first interlayer insulating film so as to overlap the gate electrode 10b of the high-withstand voltage MISFET in a plan view, the gate electrode 10b of the high-withstand voltage MISFET and the constituent source are formed. Between the wirings HL1 of the electrode wiring or the drain wiring, a breakdown voltage may occur. As a cause of this withstand voltage failure, in addition to thinning the film thickness of the first interlayer insulating film, a high-withstand voltage MISFET can be cited. As described above, the gate electrode 10b is placed in an electric field protruding from the semiconductor substrate 1S. The relaxation insulating region 3 further increases the film thickness of the gate insulating film 8. Accordingly, it is judged that the distance between the wiring HL1 having an overlap in a plan view and the gate electrode of the high-withstand voltage MISFET is close to cause a breakdown voltage. It is further judged that the high-withstand voltage MISFET has a higher driving voltage of 20 V to 30 V as one of the reasons. Therefore, this embodiment is formed on the first interlayer insulating film to form a wiring HL1 as a source wiring or a drain wiring, and the wiring electrode HL1 and the gate electrode 10b of the high-withstand voltage MISFET are formed in a plan view. Configure the wiring HL1 in a non-overlapping manner. Therefore, first, even if the semiconductor wafer as the LCD driver is miniaturized, the aspect ratio of the source region or the drain region connecting the high-withstand voltage MISFET and the plug PLG1 of the wiring HL1 can be reduced. In summary, since the wiring HL1 is formed on the first interlayer insulating film, a plug that penetrates the first interlayer insulating film and the second interlayer insulating film is not formed at one time, and only the first interlayer insulating film can be formed. Of the plug PLG1. Therefore, even if the diameter of the plug PLG1 is reduced, the aspect ratio of the plug PLG1 can be suppressed from becoming large. Further, as shown in FIG. 2, the wiring HL1 formed on the first interlayer insulating film is disposed so as not to overlap the gate electrode 10 b of the high-withstand voltage MISFET in a plan view. Therefore, since the wiring HL1 is not formed directly above the gate electrode 10b of the high-withstand voltage MISFET, the distance between the wiring HL1 and the gate electrode 10b can be increased even if the first interlayer insulating film is formed into a thin film. . Therefore, the withstand voltage of the gate electrode 10b of the high-withstand voltage MISFET and the wiring HL1 as a source wiring or a drain wiring can be secured. That is, according to this embodiment mode, it is possible to suppress the increase in resistance of the plug caused by the miniaturization of the semiconductor device, and it is possible to obtain a significant improvement in the breakdown voltage between the gate electrode and the wiring of the high breakdown voltage MISFET. effect. For example, the high-withstand voltage MISFET is caused by the thinning of the first interlayer insulating film or the thickening of the gate insulating film, the existence of the insulating region for electric field mitigation, or the high voltage of the driving voltage, which easily causes the formation of the first interlayer. The structure of the insulation film wiring (source wiring or drain wiring) HL1 and the gate electrode 10b has a poor withstand voltage. However, since the wiring HL1 configured to be formed on the first interlayer insulating film and the gate electrode 10b do not overlap in a plan view, the wiring HL1 can be formed on the first interlayer insulating film while the wiring HL1 is pulled apart Distance from the gate electrode 10b. Therefore, even if the LCD driver is miniaturized, the high resistance of the plug can be suppressed, and a significant effect of improving the breakdown voltage between the gate electrode and the wiring of the high breakdown voltage MISFET can be obtained. Further, by arranging the wiring HL1 formed on the first interlayer insulating film and the gate electrode 10b so as not to overlap in a plan view, the following effects can also be obtained. That is, since the first interlayer insulating film provided with the wiring HL1 is thinned, it is close to the channel region that is the interface between the wiring insulating film HL1 and the high-withstand voltage MISFET and the semiconductor substrate 1S. When the wiring HL1 and the gate electrode 10b are arranged to overlap in a plan view, the wiring HL1 and a channel region of the high-withstand voltage MISFET are overlapped in a plan view. At this time, if a high voltage is applied to the wiring HL1, the first interlayer insulating film is reduced in thickness, so that the wiring HL1 is feared to function as a gate electrode. In summary, the wiring HL1 has an area overlapping with the channel area in a plan view, and if the distance between the wiring HL1 and the channel area becomes closer, the voltage applied to the wiring HL1 overlaps the channel with the wiring HL1 in a plan view. The area is reversed. That is, a region overlapping the wiring HL1 in a plan view in the entire channel region is in an inverted state. Therefore, even when the high-withstand voltage MISFET is turned off, the area where the wiring HL1 and the channel area overlap in a plan view is reversed, and the distance of the substantially uninverted channel area is narrowed. As a result, a problem occurs in that the withstand voltage between the source region and the drain region decreases. However, in this embodiment, the wiring HL1 is arranged so as not to overlap the gate electrode 10b in a plan view. Therefore, the wiring HL1 is arranged so as not to overlap with the channel region formed directly under the gate electrode 10b in a plan view. Therefore, the function of the wiring HL1 as a gate electrode can be suppressed. In short, according to this embodiment, the occurrence of parasitic MISFETs caused by the wiring HL1 can be prevented, and the effect of suppressing a reduction in withstand voltage between the source region and the drain region can be obtained. FIG. 3 is a plan view of the high-withstand voltage MISFET formation region shown in FIG. 2 as viewed from above. The cross section cut along the AA line in FIG. 3 corresponds to the high-withstand voltage MISFET formation region of FIG. 2. As shown in FIG. 3, on both sides of the gate electrode 10b, a high-concentration impurity diffusion region 14 for high withstand voltage is formed as a source region or a drain region, and the high-concentration impurity diffusion region 14 for high withstand voltage and the gate are formed. An electric field relaxation insulating region 3 is formed between the electrode electrodes 10b. On the thus constructed high-withstand voltage MISFET, a first interlayer insulating film (not shown) is interposed to form wiring. Specifically, the wiring HL1 is formed on the intervening plug (first plug or second plug) PLG1 on the high-concentration impurity diffusion region 14 for high withstand voltage, which is a source region or a drain region. As can be seen from FIG. 3, the wiring HL1 is arranged so as not to overlap with the gate electrode 10 b in plan view, and the distance between the gate electrode 10 b and the wiring HL1 is separated. Therefore, it can be seen that the withstand voltage between the gate electrode 10b and the wiring HL1 is ensured. On the other hand, a gate wiring GL is connected to the gate electrode 10b via a plug (third plug) PLG1. The gate wiring GL is formed of wiring on the same layer as the wiring HL1 constituting the source wiring or the drain wiring. That is, the gate wiring GL is formed on the first interlayer insulating film. As shown in FIG. 3, the gate wiring GL is arranged so as to have a region overlapping the gate electrode 10 b in a plan view. In a word, the gate wiring GL is electrically connected to the gate electrode 10b via the plug (third plug) PLG1, and the problem of withstand voltage between the gate electrode 10b and the gate wiring GL does not occur. Thus, in this embodiment mode, the purpose is to ensure the withstand voltage of the wiring formed on the first interlayer insulating film and the gate electrode 10b. Then, those having a problem with the withstand voltage of the gate electrode 10b are source wirings formed in the wiring of the first interlayer insulating film, electrically connected to the source region of the high withstand voltage MISFET, or with high withstand voltage. The drain wiring of the MISFET's drain region is electrically connected. In summary, the characteristic point is that the gate wiring GL and the gate that are arranged so that the gate electrode 10b and the wiring HL1 as a source wiring or a drain wiring do not overlap in a plan view, and are electrically connected to the gate electrode 10b. The electrode electrodes 10b may overlap in a plan view. Here, this embodiment is characterized in that the wiring HL1 formed on the first interlayer insulating film and the gate electrode 10b of the high-withstand voltage MISFET do not overlap in a plan view. At this time, the wiring HL1 formed on the first interlayer insulating film can be referred to as the lowermost wiring. However, when no wiring is formed on the first interlayer insulating film and a wiring is formed on the second interlayer insulating film, the wiring formed on the second interlayer insulating film may also be referred to as a lowermost wiring. Furthermore, even if it is a second interlayer insulating film, since no wiring is formed on the first interlayer insulating film, the first interlayer insulating film and the second interlayer insulating film can be combined into one interlayer. Insulation film. Therefore, in order to specify the target wiring HL1 in this embodiment, a certain definition is required. Explanation about the definition. This embodiment has a problem because the first interlayer insulating film is formed into a thin film. Since the first interlayer insulating film is formed into a thin film, the wiring HL1 and the gate electrode 10b formed on the first interlayer insulating film. The withstand voltage becomes a problem. Therefore, the wiring HL1 formed on the first interlayer insulating film is defined as follows. As shown in FIG. 2, if the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10 b is set to a, from the upper portion of the gate electrode 10 b to the interlayer insulating film where the wiring HL1 is formed. If the distance in the upper part is set to b, the wiring HL1 with a> b is defined as the target wiring in this embodiment. In short, the premise is that the poor voltage resistance between the wiring HL1 and the gate electrode 10b poses a problem. The focus is on the point where the first interlayer insulating film is thinned and the gate insulating film 8 of the high withstand voltage MISFET is thick. The gate electrode 10b is placed at a point where the electric field mitigation insulating region 3 is located. With this, it is possible to clearly define the wiring HL1 disposed at a position of a> b between the gate electrode 10b and the breakdown voltage. Specifically, in a high withstand voltage MISFET, a numerical example is used to explain that the relationship a> b holds. First, in the interlayer insulating film, the thickness of the silicon nitride film 16 is about 50 nm, and the thickness of the silicon oxide film 17 is about 500 nm. Then, the film thickness of the gate insulating film 8 of the high-withstand voltage MISFET is about 80 nm, and the film thickness of the gate electrode 10b is about 250 nm. Therefore, the distance a from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is about 330 nm (80 nm + 250 nm). On the other hand, the distance b from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed is about 220 nm (550 nm-330 nm). Therefore, it can be seen that the relationship a> b holds. Furthermore, since the insulating region 3 for electric field mitigation protrudes from the semiconductor substrate 1S by about 10 nm to 20 nm, it is further known that the relationship a> b is satisfied. Thus, in this embodiment, although the withstand voltage between the gate electrode 10b and the wiring HL1 constitutes a problem, the problem with the withstand voltage constitution is clarified, and the positional relationship between the wiring HL1 and the high withstand voltage MISFET becomes a > B wiring. Therefore, although not shown in FIG. 2, regarding the wiring formed on the interlayer insulating film of the second layer or higher, the relationship of a> b is not established, so it is not the object of this embodiment. That is, the wiring formed on the interlayer insulating film of the second or higher layer is sufficiently separated from the gate electrode 10b of the high-withstand voltage MISFET, so that the breakdown voltage is not a problem. Therefore, the wiring (source wiring or drain wiring) formed on the interlayer insulating film of the second layer or higher does not pose a problem even if it is arranged to overlap the gate electrode 10b in a plan view. The wiring formed on the interlayer insulating film of the second or higher layer is arranged so as to overlap the gate electrode 10b in a plan view, and the wiring can be efficiently arranged. Especially for high-withstand voltage MISFETs, since the gate electrode 10b has a gate length as wide as 2 mm to 3 mm, the wiring formed on the interlayer insulating film above the second layer is arranged to be in contact with the gate electrode 10b. Overlap is useful when looking down. Next, a wiring structure of a low-withstand voltage MISFET will be described. As shown in FIG. 2, a first interlayer insulating film is formed on the low-withstand voltage MISFET. Specifically, the first interlayer insulating film is formed of a laminated film of a silicon nitride film 16 and a silicon oxide film 17. Then, on the first interlayer insulating film composed of the silicon nitride film 16 and the silicon oxide film 17, a plug PLG1 penetrating the interlayer insulating film and reaching the source region of the low-withstand voltage MISFET is formed, and the interlayer insulating film is penetrated. And reach the plug PLG1 of the drain region of the low withstand voltage MISFET. Then, wiring (source wiring, drain wiring) LL1 is formed on the first interlayer insulating film on which the plug PLG1 is formed. In addition, although the wiring LL1 is formed on the first interlayer insulating film, a second interlayer insulating film or a third interlayer insulating film is further formed on the first interlayer insulating film including the wiring LL1. Wiring is formed on each interlayer insulating film. That is, a multilayer wiring is formed on the low-withstand voltage MISFET, but only the first-layer wiring LL1 is shown in FIG. 2. Here, the low-withstand-voltage MISFET is different from the high-withstand-voltage MISFET, and the first-layer wiring LL1 is arranged so as to overlap the low-withstand-voltage MISFET's gate electrode 10a in a plan view. That is, in the low-withstand voltage MISFET, the withstand voltage system between the first-layer wiring LL1 and the gate electrode 10a is different from that of the high-withstand voltage MISFET, and does not pose a problem. As a reason for this, in the low-withstand voltage MISFET, first, the gate insulating film 7 has a thin film thickness and the electric field mitigation insulating region 3 is not formed. Therefore, the gate electrode 10 a is not left in the electric field mitigation insulating region 3. Furthermore, the driving electrode of a low-withstand voltage MISFET is about 5 V to 6 V, which is easier to ensure withstand voltage than a high-withstand voltage MISFET with a driving voltage of 20 V to 30 V. Therefore, the wiring (source wiring or drain wiring) LL1 formed on the first interlayer insulating film may overlap the gate electrode 10a in a plan view. Accordingly, since the gate electrode 10a of the low-withstand voltage MISFET has a gate length of about 160 nm, the space on the gate electrode 10a can be effectively used. Furthermore, as a factor for ensuring a withstand voltage in a low withstand voltage MISFET, if the distance from the interface between the semiconductor substrate 1S and the gate insulating film 7 to the upper portion of the gate electrode 10a is c, and from the upper portion of the gate electrode 10a When the distance to the upper portion of the interlayer insulating film on which the wiring LL1 is formed is d, c <d may be mentioned. That is, the relationship (a> b) established in the high withstand voltage MISFET is not established in the low withstand voltage MISFET, and the distance between the gate electrode 10a and the wiring LL1 can be ensured. As a result, in the low withstand voltage MISFET, the gate electrode 10a and the wiring Poor withstand voltage of LL1 does not pose a problem. Specifically, a numerical example is used for explanation. For example, in the interlayer insulating film, the film thickness of the silicon nitride film 16 is about 50 nm, and the film thickness of the silicon oxide film 17 is about 500 nm. Then, the film thickness of the gate insulating film 7 of the low-withstand voltage MISFET is about 13 nm, and the film thickness of the gate electrode 10a is about 250 nm. Therefore, the distance c from the interface between the semiconductor substrate 1S and the gate insulating film 7 to the upper portion of the gate electrode 10a is about 263 nm (13 nm + 250 nm). On the other hand, the distance d from the upper part of the gate electrode 10a to the upper part of the interlayer insulating film on which the wiring LL1 is formed is about 287 nm (550 nm-263 nm). Therefore, it can be seen that the relationship of c <d holds. That is, the low breakdown voltage MISFET is different from the high breakdown voltage MISFET in that the distance d from the upper portion of the gate electrode 10a to the wiring LL1 is greater than the distance c from the lower portion of the gate insulating film 7 to the upper portion of the gate electrode 10a. Since the driving voltage is low, even if the gate electrode 10a and the wiring LL1 have a region overlapping in a plan view, a breakdown voltage will not occur. As described above, this embodiment is characterized in that a wiring HL1 as a source wiring or a drain wiring is formed on a first interlayer insulating film in a high-withstand voltage MISFET formation region, and the wiring HL1 and the high The wiring electrode HL1 is arranged so that the gate electrode 10b of the withstand voltage MISFET does not overlap in a plan view. As a result, the high resistance of the plug caused by the miniaturization of the LCD driver can be suppressed, and a significant effect of improving the breakdown voltage between the gate electrode and the wiring of the high breakdown voltage MISFET can be obtained. The LCD driver (semiconductor device) of this embodiment is configured as described above, and its manufacturing method will be described below with reference to the drawings. First, a semiconductor substrate 1S composed of a silicon single crystal into which p-type impurities such as boron (B) are introduced is prepared. At this time, the semiconductor substrate 1S is in a state of a semiconductor wafer having an approximately disc shape. Then, as shown in FIG. 4, an element isolation region 2 that separates the low-withstand-voltage MISFET formation region and the high-withstand-voltage MISFET formation region of the semiconductor substrate 1S is formed. The component separation area 2 is provided so that components do not interfere with each other. The element isolation region 2 can be formed by, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method. For example, in the STI method, the element isolation region 2 is formed as follows. That is, on the semiconductor substrate 1S, a photolithography technique and an etching technique are used to form an element isolation trench. Then, a silicon oxide film is formed on the semiconductor substrate 1S by filling the element separation trenches, and then the unnecessary silicon oxide formed on the semiconductor substrate 1S is removed by chemical mechanical polishing (CMP). membrane. Thereby, the element isolation region 2 in which the silicon oxide film is buried can be formed only in the element isolation trench. In this embodiment, the step of forming the element isolation region 2 also forms the electric field relaxation insulating region 3. The insulating region 3 for electric field relaxation is formed in the same manner as the element isolation region 2, and is formed using, for example, the STI method or the selective oxidation method (LOCOS method). The electric field relaxation insulating region 3 is formed in a high-withstand voltage MISFET formation region. In particular, in the high-withstand voltage MISFET formation region, since the electric field relaxation insulating region 3 is formed, the occupancy rates of the element isolation region 2 and the electric field relaxation insulating region 3 become larger. Therefore, for example, if the element isolation region 2 and the electric field mitigation insulating region 3 are formed by the STI method, the element isolation region 2 and the electric field mitigation insulating region 3 easily protrude from the surface of the semiconductor substrate 1S in the high-withstand voltage MISFET formation region. In short, the element isolation region 2 and the electric field relaxation insulating region 3 are configured to protrude, for example, from 10 nm to 20 nm from the surface of the semiconductor substrate 1S. As will be described later, in the high-withstand voltage MISFET, since the end portion of the gate electrode is formed on the insulation region 3 for electric field relaxation, the end portion of the gate electrode is formed on the protruding insulation region 3 for electric field relaxation. Especially in the LOCOS method (selective oxidation method), since the selective oxide film is formed so as to protrude from the surface of the semiconductor substrate 1S, the amount of the gate electrode to be left also becomes large. Next, as shown in FIG. 5, impurities are introduced into the active region separated by the element isolation region 2 to form a p-type well 4. The p-type well 4 is formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by an ion implantation method. Although this p-type well 4 is a well for a high withstand voltage MISFET, it is formed in a high withstand voltage MISFET formation region and a low withstand voltage MISFET formation region. Then, a semiconductor region (not shown) for forming a channel is formed on the surface region of the p-type well 4. The semiconductor region for forming the channel is formed by adjusting a threshold voltage at which the channel is formed. In addition, in this embodiment mode, although the p-type well 4 having a high breakdown voltage MISFET formation region and a low breakdown voltage MISFET formation region is formed in the same step, it may be formed in separate steps. In this case, the impurity concentration introduced into the high-withstand-voltage MISFET formation region and the low-pressure-resistant MISFET-formed region can be formed under optimal conditions, respectively. Next, as shown in FIG. 6, a p-type well 5 is formed in the low-withstand voltage MISFET formation region. The p-type well 5 is formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by an ion implantation method. This p-type well 5 is a well for a low withstand voltage MISFET. Thereafter, a pair of low-concentration impurity diffusion regions 6 for high withstand voltage is formed in the high withstand voltage MISFET formation region. The low-concentration impurity diffusion region 6 for high withstand voltage is an n-type semiconductor region, and is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate 1S by an ion implantation method. The low-concentration impurity diffusion region 6 for high withstand voltage is formed so as to include the insulating region 3 for electric field relaxation. Next, as shown in FIG. 7, a gate insulating film is formed on the semiconductor substrate 1S. At this time, a thin-layer gate insulating film 7 is formed in the low-withstand-voltage MISFET formation region, and a thick-layer gate insulating film 8 is formed in the high-withstand-voltage MISFET formation region. For example, the film thickness of the gate insulating film 7 formed in the low-withstand voltage MISFET formation region is approximately 13 nm, and the film thickness of the gate insulating film 8 formed in the high-withstand voltage MISFET formation region is approximately 80 nm. In order to form such a gate insulating film having a different film thickness depending on the region, for example, a thick gate insulating film 8 is formed on the semiconductor substrate 1S, and then a region with a high breakdown voltage MISFET is masked with a resist film. Then, by using the resist film as a mask to etch, the thickness of the gate insulating film 8 in the exposed low-voltage-resistance MISFET formation region is reduced, and a thin gate insulating film 7 can be formed. In addition, a thin gate insulating film 7 is first formed on the entire semiconductor substrate 1S, and a resist film is formed on the low-withstand voltage MISFET formation region. Then, a thick gate insulating film 8 is formed by the exposed high-withstand voltage MISFET formation area, so that a thin-layer gate insulating film 7 can be formed in the low-withstand voltage MISFET formation area, and a thick layer can be formed in the high-withstand voltage MISFET formation area The gate insulation film 8. The ends of the gate insulating film 8 formed in the high-withstand voltage MISFET formation region are formed so as to be placed on the electric field relaxation insulating region 3. The gate insulating films 7 and 8 are formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating films 7 and 8 are not limited to the silicon oxide film, and various changes can be made. For example, the gate insulating films 7 and 8 may be silicon oxynitride films (SiON). That is, it may be a structure that segregates nitrogen at the interface between the gate insulating films 7 and 8 and the semiconductor substrate 1S. Compared with silicon oxide film, silicon oxynitride film is more effective in suppressing the occurrence of interface states in the film or reducing electron traps. Therefore, the heat carrier resistance of the gate insulating films 7, 8 can be improved, and the insulation resistance can be improved. In addition, compared with a silicon oxide film, a silicon oxynitride film is harder to penetrate impurities. Therefore, by using a silicon oxynitride film for the gate insulating films 7 and 8, it is possible to suppress the variation in the threshold voltage due to the diffusion of impurities in the gate electrode to the semiconductor substrate 1S side. The formation of silicon oxynitride film is based on 2 Or NH 3 In such a nitrogen-like atmosphere, the semiconductor substrate 1S may be heat-treated. Furthermore, on the surface of the semiconductor substrate 1S, a gate insulating film 7 composed of a silicon oxide film is formed, and then the semiconductor substrate 1S is heat-treated in an atmosphere containing nitrogen to segregate nitrogen into the gate insulating film 7, The interface between 8 and the semiconductor substrate 1S can also obtain the same effect. The gate insulating films 7 and 8 may be formed of, for example, a high-dielectric film having a higher dielectric constant than a silicon oxide film. In the past, from the viewpoints of high insulation resistance and good electrical and physical properties of the silicon-silicon oxide interface, silicon oxide films were used as the gate insulating films 7, 8 series. However, along with the miniaturization of devices, the thickness of the gate insulating films 7 and 8 is also required to be extremely thin. If such a thinned silicon oxide film is used as the gate insulating films 7, 8, a so-called channel current will occur, which is an electron flowing in the channel of the MISFET, and a barrier formed by the silicon oxide film is used as a channel Flow to the gate electrode. Therefore, by using a material with a higher dielectric constant than a silicon oxide film, a high-dielectric film with the same capacitance can still increase the physical film thickness. With a high-dielectric film, since the physical film thickness can be increased even with the same capacitance, leakage current can be reduced. For example, as a high-dielectric film, a hafnium oxide film (HfO) 2 Film), but instead of a hafnium oxide film, other materials such as hafnium aluminum oxide film, HfON film (hafnium nitride oxide film), HfSiO film (铪 silicide film), HfSiON film (nitrogen silicon oxide film), HfAlO film, etc Department of insulation film. Furthermore, for these samarium-based insulating films, samarium-based insulating films into which oxides such as tantalum oxide, niobium oxide, titanium oxide, zirconia, lanthanum oxide, and yttrium oxide are introduced may be used. The hafnium-based insulating film is the same as the hafnium oxide film. Since the dielectric constant is higher than that of a silicon oxide film or a silicon oxynitride film, the same effect as that obtained when a hafnium oxide film is used can be obtained. Next, as shown in FIG. 8, a polycrystalline silicon film is formed on the gate insulating films 7 and 8. The polycrystalline silicon film 9 can be formed using, for example, a CVD method. Then, an n-type impurity such as phosphorus or arsenic is introduced into the polycrystalline silicon film 9 using a photolithography technique and an ion implantation method. Next, by etching the patterned resist film as a mask, the polycrystalline silicon film 9 is processed to form a gate electrode 10a in a low-withstand voltage MISFET formation region, and a gate electrode 10b in a high-withstand voltage MISFET formation region. . The gate length of the gate electrode 10a is about 160 nm, and the gate length of the gate electrode 10b is about 2 mm to 3 mm, for example. The end of the gate electrode 10b formed in the high-withstand voltage MISFET formation region is formed by interposing the gate insulating film 8 on the insulating region 3 for electric field relaxation. Here, n-type impurities are introduced into the gate electrodes 10 a and 10 b into the polycrystalline silicon film 9. Therefore, since the working function values of the gate electrodes 10a and 10b can be made near the conduction band of silicon (4. 15 eV), which can reduce the threshold voltage of the low-withstand voltage MISFET and high-withstand voltage MISFET of the n-channel MISFET. Next, as shown in FIG. 9, by using a photolithography technique and an ion implantation method, a low-withstand-voltage low-concentration impurity diffusion region 11 formed in a shallow layer integrated with the gate electrode 10 a of the low-withstand-voltage MISFET is formed. The low-level low-concentration impurity diffusion region 11 for the shallow withstand voltage is an n-type semiconductor region. Then, as shown in FIG. 10, a silicon oxide film is formed on the semiconductor substrate 1S. The silicon oxide film can be formed using, for example, a CVD method. Then, by anisotropically etching the silicon oxide film, a side wall 12 can be formed on the sidewalls of the gate electrodes 10a, 10b. The side wall 12 is formed of a single layer film of a silicon oxide film, but is not limited thereto. For example, the side wall 12 may be formed of a laminated film of a silicon nitride film and a silicon oxide film. Next, as shown in FIG. 11, by using a photolithography technique and an ion implantation method, a low-withstand-voltage high-concentration impurity diffusion region 13 integrated into a deep layer of the side wall 12 is formed in the low-withstand-voltage MISFET formation region. The deep-layer high-concentration impurity diffusion region 13 for low withstand voltage is an n-type semiconductor region. The source region or the drain region of the low-withstand voltage MISFET is formed by the low-withstand-voltage high-concentration impurity diffusion region 13 in the deep layer and the low-layer with-low-impurity impurity diffusion region 11 in the shallow layer. In this way, the source region and the drain region can be formed by forming the source region and the drain region with a shallow low-withstand-voltage low-concentration impurity diffusion region 11 and a deep low-with-high-impurity impurity diffusion region 13. Made into LDD (Lightly Doped Drain: Lightly Doped Drain) structure. By forming a region with a high withstand voltage MISFET, and simultaneously performing ion implantation of n-type impurities to form a high concentration impurity diffusion region 13 with a low withstand voltage, a high concentration impurity diffusion region 14 with a high withstand voltage is also formed. This high-withstand-voltage high-concentration impurity diffusion region 14 is also an n-type semiconductor region, and is formed so as to be outside of the electric field relaxation insulating region 3 and enclosed within the high-withstand-voltage low-concentration impurity diffusion region 6. In a high withstand voltage MISFET, a source region or a drain region is also formed by a high concentration impurity diffusion region 14 for a high withstand voltage and a low concentration impurity diffusion region 6 for a high withstand voltage. In this way, after forming the high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage, heat treatment is performed at about 1000 ° C. This activates the introduced impurities. Thereafter, as shown in FIG. 12, a cobalt film is formed on the semiconductor substrate 1S. At this time, a cobalt film is formed so as to directly contact the gate electrodes 10a, 10b. Similarly, the cobalt film is directly connected to the deep-layer high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage. The cobalt film can be formed using, for example, a sputtering method. After the cobalt film is formed, heat treatment is performed to react the polycrystalline silicon film 9 constituting the gate electrodes 10 a and 10 b with the cobalt film to form a cobalt silicide film 15. Thereby, the gate electrodes 10a and 10b have a laminated structure of the polycrystalline silicon film 9 and the cobalt silicide film 15. The cobalt silicide film 15 is formed to reduce the resistance of the gate electrodes 10a and 10b. Similarly, the silicon and the cobalt film are also reacted on the surfaces of the high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage by the above-mentioned heat treatment to form a cobalt silicide film 15. Therefore, it is possible to reduce the resistance in the high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage. Then, the unreacted cobalt film is removed from the semiconductor substrate 1S. In addition, the present embodiment is configured such that a cobalt silicide film 15 is formed. For example, instead of the cobalt silicide film 15, a nickel silicide film or a titanium silicide film may be formed. In this way, a low withstand voltage MISFET and a high withstand voltage MISFET can be formed on the semiconductor substrate 1S. Next, the wiring steps will be described. First, as shown in FIG. 13, a silicon nitride film 16 as an interlayer insulating film is formed on the main surface of the semiconductor substrate 1S, and a silicon oxide film 17 is formed on the silicon nitride film 16. Thereby, the first interlayer insulating film becomes a laminated film of the silicon nitride film 16 and the silicon oxide film 17. The silicon nitride film 16 can be formed using, for example, a CVD method, and the silicon oxide film 17 can be formed using, for example, a CVD method using TEOS (tetra ethyl ortho silicate) as a raw material. At this time, the film thickness of the silicon nitride film 16 is about 50 nm, and the film thickness of the silicon oxide film 17 is about 1100 nm. Thereafter, as shown in FIG. 14, the surface of the silicon oxide film 17 is planarized using, for example, a CMP (Chemical Mechanical Polishing) method. In this step, the film thickness of the silicon oxide film 17 is reduced to approximately 550 nm, for example. In this way, the film thickness of the silicon oxide film 17 is reduced. Next, as shown in FIG. 15, a contact hole CNT1 is formed in the silicon oxide film 17 using a photolithography technique and an etching technique. The contact hole CNT1 penetrates the first interlayer insulating film composed of the silicon oxide film 17 and the silicon nitride film 16 and reaches the semiconductor substrate 1S. Specifically, the contact hole CNT1 is formed in a high breakdown voltage MISFET formation region and a low breakdown voltage MISFET formation region. A contact hole (first contact hole) CNT1 reaching the source region (cobalt silicide film 15) is formed in the high-withstand voltage MISFET formation region, and a contact hole (second Contact hole) CNT1. In addition, although not shown in FIG. 15, a contact hole reaching the gate electrode 10 b is also formed. Similarly, a contact hole CNT1 reaching the source region (cobalt silicide film 15) is formed in the low-withstand voltage MISFET formation region, and a contact hole CNT1 reaching the drain region (cobalt silicide film 15) is formed. In addition, although not shown, a contact hole reaching the gate electrode 10a is also formed. Next, as shown in FIG. 16, a titanium / titanium nitride film 18 a is formed on the silicon oxide film 17 including the bottom surface and the inner wall of the contact hole CNT1. The titanium / titanium nitride film 18a is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. The titanium / titanium nitride film 18a has a so-called barrier property, which prevents, for example, tungsten, which is a film material buried in a subsequent step, from diffusing into silicon. Thereafter, a tungsten film 18b is formed on the entire surface of the main surface of the semiconductor substrate 1S so as to fill the contact hole CNT1. This tungsten film 18b can be formed using, for example, a CVD method. Next, as shown in FIG. 17, the unnecessary titanium / titanium nitride film 18a and the tungsten film 18b formed on the silicon oxide film 17 are removed by, for example, the CMP method, and the titanium / titanium nitride film remains only in the contact hole CNT1 18a and tungsten film 18b, thereby forming the plug PLG1. The silicon oxide film 17 is cut by the CMP polishing at this time. Specifically, the film thickness of the silicon oxide film 17 is about 550 nm before the CMP polishing, and the film thickness of the silicon oxide film 17 is about 500 nm after the CMP polishing. In the high-voltage MISFET formation region, a plug (first plug) PLG1 electrically connected to the source region of the high-voltage MISFET or a plug (second) electrically connected to the drain region of the high-voltage MISFET is formed. Plug) PLG1. Although not shown, a plug (third plug) electrically connected to the gate electrode 10b is also formed. Similarly, a plug PLG1 electrically connected to the source region of the low withstand voltage MISFET or a PLG1 electrically connected to the drain region of the low withstand voltage MISFET is formed in the low withstand voltage MISFET formation region. In addition, although not shown, a plug electrically connected to the gate electrode 10a is also formed. Next, as shown in FIG. 18, a titanium / titanium nitride film 19a, a copper-containing aluminum film 19b, and a titanium / titanium nitride film 19c are sequentially formed on the silicon oxide film 17 and the plug PLG1. These films can be formed by using, for example, a sputtering method. Next, by using a photolithography technique and an etching technique, the films are patterned to form wirings HL1 and wirings LL1. In this way, the wiring HL1 and the wiring LL1 can be formed on the first interlayer insulating film. Since the wiring HL1 and the wiring LL1 are formed on the first interlayer insulating film, the aspect ratio of the plug PLG1 connected to the wiring HL1 and the wiring LL1 can be reduced. Therefore, even if the diameter of the plug PLG1 is reduced to promote the miniaturization of the wafer area, the resistance of the plug PLG1 can be suppressed from increasing. Further in this embodiment, the wiring (source wiring) HL1 connected to the source region of the high withstand voltage MISFET via the plug PLG1 and the connection to the high withstand voltage MISFET via the plug PLG1 are configured as follows. The wiring of the polar region (drain wiring) HL1. In short, the wiring HL1 and the gate electrode 10b arranged on the first interlayer insulating film are arranged so as not to overlap each other in a plan view. Accordingly, since the wiring HL1 is not formed directly above the gate electrode 10b of the high-withstand voltage MISFET, the distance between the wiring HL1 and the gate electrode 10b can be increased even if the first interlayer insulating film is formed into a thin film. Therefore, the withstand voltage of the gate electrode 10b of the high-withstand voltage MISFET and the wiring HL1 as a source wiring or a drain wiring can be secured. That is, according to this embodiment mode, the high resistance of the plug caused by the miniaturization of the semiconductor device can be suppressed, and a significant effect of improving the poor withstand voltage between the gate electrode and the wiring of the high withstand voltage MISFET can be obtained. . In addition, although not shown, a gate wiring electrically connected to the gate electrode 10b is also formed on the first interlayer insulating film. In other words, the gate wiring is formed in the same layer as the wiring HL1 constituting the source wiring or the drain wiring. Since the gate wiring is electrically connected to the gate electrode 10b, the withstand voltage between the gate wiring and the gate electrode 10b does not pose a problem. Therefore, the gate wiring is arranged so as to overlap the gate electrode 10 b in a plan view. On the other hand, in the low-withstand voltage MISFET formation region, a wiring LL1 is formed on the first interlayer insulating film. In the low-withstand voltage MISFET, since the withstand voltage between the wiring LL1 and the gate electrode 10a does not pose a problem, the wiring LL1 is formed to have a wide wiring width so as to overlap with the gate electrode 10a in a plan view. Thereby, the space on the gate electrode 10a can be effectively utilized, and the resistance of the wiring LL1 can be reduced. Next, as shown in FIG. 19, a silicon oxide film 20 of a second interlayer insulating film is formed on the first interlayer insulating film on which the wiring HL1 and the wiring LL1 are formed. Then, similar to the above steps, a plug PLG2 is formed on the silicon oxide film 20. The plug PLG2 is connected to the wiring HL1 and the wiring LL1. Then, a wiring HL2 and a wiring LL2 are formed on the silicon oxide film 20 on which the plug PLG2 is formed. Here, since the wiring HL1 and the wiring HL2 are connected by a plurality of rows of plugs PLG2, the wiring resistance and the plug resistance can be reduced. Similarly, since the wiring LL1 and the wiring LL2 are connected by a plurality of rows of plugs PLG2, the wiring resistance and the plug resistance can be reduced. In the high-withstand voltage MISFET formation region, the wiring HL2 formed on the silicon oxide film 20 of the second interlayer insulating film may be arranged to overlap the gate electrode 10b in a plan view. This is because the wiring HL2 disposed on the second interlayer insulating film and the gate electrode 10b are sufficiently separated from the distance between the wiring HL1 disposed on the first interlayer insulating film and the gate electrode 10b, so the wiring HL2 The withstand voltage with the gate electrode 10b does not pose a problem. Therefore, as the gate length, the space on the gate electrode 10b having a length of about 2 mm to 3 mm can be effectively utilized, and the wiring width of the wiring HL2 can be enlarged, thereby reducing the resistance of the wiring HL2. Further, a plurality of wirings may be arranged on the second interlayer insulating film in a region overlapping with the gate electrode 10b in a plan view. Further, wiring is formed by the upper layers of the wiring HL2 and the wiring LL2 to form a multilayer wiring. Then, a bump electrode is formed on the uppermost layer of the multilayer wiring. The steps for forming the bump electrode will be described. FIG. 20 shows a silicon oxide film 21 formed on a multilayer wiring, and a pad PAD is formed on the silicon oxide film 21. Although the lower structure of the silicon oxide film 21 is omitted, a low breakdown voltage MISFET, a high breakdown voltage MISFET, and a multilayer wiring as shown in FIG. 19 are formed below the silicon oxide film 21. As shown in FIG. 20, for example, a silicon oxide film 21 is formed. The silicon oxide film 21 can be formed using, for example, a CVD method. Then, on the silicon oxide film 21, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are laminated. Thereafter, the laminated film is patterned using a photolithography technique and an etching technique. With this patterning, a pad PAD can be formed on the silicon oxide film 21. Next, as shown in FIG. 21, a surface protection film 22 is formed on the silicon oxide film 21 on which the pad PAD is formed. The surface protection film 22 is formed by, for example, a silicon nitride film, and can be formed by, for example, a CVD method. Next, an opening is formed in the surface protection film 22 using a photolithography technique and an etching technique. The opening is formed on the pad PAD and exposes the surface of the pad PAD. Next, as shown in FIG. 22, a UBM (Under Bump Metal) film 23 is formed on the surface protection film 22 including the opening. The UBM film 23 can be formed by, for example, a sputtering method, and is formed by a single-layer film or a laminated film such as a titanium film, a nickel film, a palladium film, a titanium-tungsten alloy film, a titanium nitride film, or a gold film. Here, the UBM film 23 has a function of improving the adhesion between the bump electrode and the pad PAD or the surface protective film 22, or functions as an electrode, and also has a barrier function, which suppresses or prevents the formation of subsequent steps. The metal element of the conductor film moves to the multilayer wiring side, or the metal element constituting the multilayer wiring moves to the conductor film side. Next, as shown in FIG. 23, after the resist film RES is coated on the UBM film 23, the resist film RES is subjected to an exposure and development process to perform patterning. The patterning is performed so that the resist film RES does not remain in the bump electrode formation region. Then, as shown in FIG. 24, as the conductor film 24, a gold film is formed using, for example, a plating method. Thereafter, as shown in FIG. 25, the bump electrode BMP composed of the conductor film 24 and the UBM film 23 is formed by removing the patterned resist film RES and the UBM film 23 covering the resist film RES. . Then, by dicing the semiconductor substrate in a semiconductor wafer state, a chipped semiconductor wafer CHP can be obtained. The semiconductor wafer CHP obtained by individual slicing is shown in FIG. 1. Thereafter, a semiconductor wafer CHP obtained by singulating the semiconductor substrate is mounted on a glass substrate. Next, the state of the semiconductor wafer CHP of the LCD driver which is adhered to the mounting substrate and is mounted. FIG. 26 shows a case where a semiconductor wafer CHP is mounted on a glass substrate 30a (COG: Chip On Glass). As shown in FIG. 26, a glass substrate 30b is mounted on the glass substrate 30a, thereby forming a display portion of the LCD. Then, a semiconductor wafer CHP of an LCD driver is mounted on a glass substrate 30a near the display portion of the LCD. A bump electrode BMP is formed on the semiconductor wafer CHP, and the terminals formed on the bump electrode BMP and the glass substrate 30 a are connected via an anisotropic conductive film 32. Moreover, the glass substrate 30a and the flexible printed circuit (Flexible Printed Circuit) 31 are also connected via an anisotropic conductive film. In this way, in the semiconductor wafer CHP mounted on the glass substrate 30a, the bump electrode BMP for output is electrically connected to the display portion of the LCD, and the bump electrode BMP for input is connected to the flexible printed circuit 31. FIG. 27 is a diagram showing the overall structure of an LCD. As shown in FIG. 27, an LCD display portion 33 is formed on a glass substrate, and an image is displayed on the display portion 33. A semiconductor wafer CHP of an LCD driver is mounted on a glass substrate near the display portion 33. A flexible printed circuit board 31 is mounted near the semiconductor wafer CHP, and a semiconductor chip CHP of an LCD driver is mounted between the flexible printed circuit board 31 and the display portion 33 of the LCD. In this way, the semiconductor wafer CHP can be mounted on a glass substrate. By going through the above steps, the LCD driver can be mounted on a glass substrate to manufacture an LCD. (Embodiment Mode 2) As shown in FIG. 28, one of the features of Embodiment Mode 1 described above is formed on the first interlayer insulating film (silicon oxide film 17) as a source wiring or a drain wiring. The line HL1 is arranged such that the wiring HL1 and the gate electrode 10b of the high-withstand voltage MISFET do not overlap in a plan view. FIG. 28 shows a distance e between the gate electrode 10b of the high-withstand voltage MISFET and the wiring HL1 that does not overlap in a plan view. In the second embodiment, a specific numerical example of the distance e will be described. FIG. 28 is a cross-sectional view showing a high-withstand voltage MISFET and a low-withstand voltage MISFET, and is the same diagram as FIG. 2. However, FIG. 28 shows the distance e between the gate electrode 10b of the high-withstand voltage MISFET and the wiring HL1 in a plan view and the diameter z of the plug PLG1. As shown in FIG. 28, the gate electrode 10b of the high-withstand voltage MISFET is separated from the wiring HL1 only by a distance e in a plan view, but the distance e must take into account the dimensional error of the pattern formed by the photolithography step or the misalignment of the pattern. Decide. This is because, for example, even if a sufficient distance e is set to ensure the withstand voltage of the gate electrode 10b and the wiring HL1, it is judged that there may be a size error due to the processing of the gate electrode 10b or the wiring HL1, or The gate electrode 10b is misaligned with the plug PLG1, or the misalignment between the plug PLG1 and the wiring HL1, etc., so that the processing of the gate electrode 10b and the wiring HL1 overlaps in plan view. In this case, the withstand voltage between the gate electrode 10b and the wiring HL1 cannot be secured. Therefore, the distance e must be set in such a way that the distance e between the gate electrode 10b and the wiring HL1 does not overlap in a plan view even if the dimensional error of the pattern in the photolithography step or the alignment deviation of the pattern is generated. . FIG. 29 is a diagram specifically showing a dimensional error of a pattern in a photolithography step or an alignment deviation between patterns. For example, in FIG. 29, it can be seen that when the gate electrode 10 b is formed by the photolithography step, the size error (deviation) of the gate electrode 10 b is 40 nm at the maximum. Furthermore, the alignment deviation (overlapping deviation, deviation) of the plug PLG1 with respect to the gate electrode 10b is 40 nm at the maximum. Similarly, the maximum dimensional error of the wiring HL1 is 40 nm, and the overlap deviation of the wiring HL1 from the plug PLG1 is 70 nm at the maximum. Therefore, when all of these dimensional errors and overlapping deviations act in the direction of narrowing the distance e between the gate electrode 10b and the wiring HL1 in a non-overlapping manner in plan view, the error of the narrowing distance e will become the maximum. In short, when the distance e is less than 190 nm (40 nm + 40 nm + 40 nm + 70 nm), the size error of the pattern in the photolithography step and the size of the overlap and deviation between the patterns will form a gate. The electrode electrode 10b and the wiring HL1 have an overlapping area in a plan view. As a result, a state in which the withstand voltage between the gate electrode 10b and the wiring HL1 cannot be ensured. In other words, when the distance e is separated by more than 190 nm, the dimensional error of the pattern or the overlapping deviation of the pattern caused by the photolithography step can prevent the gate electrode 10b and the wiring HL1 from overlapping in a plan view. Therefore, by setting the distance e to 190 nm or more, even if a dimensional error of the pattern of the photolithography step or an overlap deviation between the patterns occurs, the gate electrode 10b and the wiring HL1 can be reliably prevented from overlapping in a plan view. . As a result, the withstand voltage between the gate electrode 10b and the wiring HL1 can be reliably increased, and the reliability of the semiconductor device can be improved. In addition, in the above description, the distance e that the gate electrode 10b and the wiring HL1 do not overlap in plan view is larger than the value of the dimensional error of the pattern simply adding the photolithography step or the overlap deviation between the patterns (190 nm). Among them, since it is judged that the dimensional error of all patterns or the overlap deviation between the patterns are generated in the direction of narrowing the distance e, the accuracy is very small. Therefore, as a method of evaluating the distance e, other methods of determining the sum of squares may be considered. . That is, the dimensional error of the pattern in the photolithography step or the overlap deviation between the patterns is evaluated by a square power sum. In this case, the distance e becomes √ (40 × 40 + 40 × 40 + 40 × 40 + 70 × 70) = 98 nm. By separating the distance e by 98 nm (about 100 nm) or more, the gate electrode can be sufficiently prevented. 10b overlaps the wiring HL1 in a plan view. (Embodiment Mode 3) One of the features of the aforementioned Embodiment Mode 1 is that it is configured to be formed on the wiring HL1 and the high-withstand voltage MISFET gate formed on the first interlayer insulating film (silicon oxide film 17) shown in FIG. 28. The electrode electrodes 10b do not overlap in a plan view. In a word, in the first embodiment, the focus is on the problems caused by thinning the first interlayer insulating film, that is, the thin interlayer insulating film is formed on the first layer. The problem is that the withstand voltage of the wiring HL1 of the insulating film and the gate electrode 10b poses a problem. At this time, in the first embodiment, it is quantitatively defined that the first interlayer insulating film is thinned. Specifically, as shown in FIG. 28, if the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is set to a, from the upper portion of the gate electrode 10b to the portion where the wiring HL1 is formed. If the distance between the upper portions of the interlayer insulating films is set to b, the wiring HL1 with a> b is defined as the target wiring in the first embodiment. In short, the premise is that the poor voltage resistance between the wiring HL1 and the gate electrode 10b poses a problem. The focus is on the point where the first interlayer insulating film is thinned and the gate insulating film 8 of the high withstand voltage MISFET is thick. The gate electrode 10b is placed at a point where the electric field mitigation insulating region 3 is located. With this, it is possible to clearly define the wiring HL1 disposed at a position of a> b between the gate electrode 10b and the breakdown voltage. In the third embodiment, the condition for rephrasing a> b described above with other conditions will be described. First, as described above, if the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is set to a, from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed. If the distance is set to b, the condition previously mentioned in the present invention is a condition of a> b. Here, as other conditions, the relationship between the diameter z of the plug PLG1 and the thickness f (not shown) (f = a + b) of the interlayer insulating film (silicon oxide film 17 + silicon nitride film 16) can be mentioned. That is, the plug PLG1 is formed by penetrating the interlayer insulating film. However, from the viewpoint of improving the landfill characteristics of the plug PLG1, the aspect ratio must be a specific value or less. Here, the aspect ratio refers to the amount f / z by the thickness f of the interlayer insulating film and the diameter z of the plug PLG1. This aspect ratio becomes large, corresponding to, for example, a plug PLG1 having a small diameter formed in a thick interlayer insulating film, and the landfill characteristics are deteriorated. In short, from the viewpoint of improving the landfill characteristics of the plug PLG1, the aspect ratio must be set to a specific value or less. Specifically, for example, this condition can be expressed as a condition of f / z <5. In short, if the thickness f of the interlayer insulating film and the diameter z of the plug PLG1 are determined so that the aspect ratio f / z becomes 5 or less, the deterioration of the landfill characteristics of the plug PLG1 can be suppressed. Here, the thickness f of the interlayer insulating film is f = a + b, and from this formula, it becomes a = fb. Substituting this into a> b results in f> 2b. On the other hand, from the aspect ratio f / z <5, f <5z. Therefore, from the two relational expressions f <5z and f> 2b, 2b <5z can be obtained. If the 2b <5z is solved for b, it becomes b <2. 5z. As can be seen from the above, the condition of a> b is replaced by the relationship between the thickness f = a + b of the interlayer insulating film and the aspect ratio f / z <5 to b <2. 5z condition. To explain in terms of text, it can be seen that if the distance from the upper part of the gate electrode 10b to the upper part of the interlayer insulating film on which the wiring HL1 is formed is set to b, and the diameter of the plug PLG1 is set to z, then b <2. The condition of 5z is replaced by the distance b from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed, which is less than 2 of the diameter z of the plug PLG1. 5 times the condition. In summary, the feature of the present invention in this embodiment 3 is the distance b from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film where the wiring HL1 is formed, which is less than the diameter z of the plug PLG1 of 2. In the case of five times, the gate electrode 10b and the wiring HL1 may be arranged so as not to overlap in a plan view. In addition, although the diameter of the plug PLG1 is set to z, when the diameter of the plug PLG1 is the same throughout the entire plug PLG1, it does not pose a problem, but actually the diameter of the surface of the interlayer insulating film (silicon oxide film 17) The largest, formed as the diameter of the plug PLG1 progresses toward the bottom. In this case, the problem lies in what depth the diameter PL of the plug PLG1 is. In the third embodiment, the diameter of the bottom of the plug PLG1 is called z. (Embodiment Mode 4) In the foregoing Embodiment Mode 1, the case where the present invention is applied to a high withstand voltage MISFET will be described, but in Embodiment Mode 4, the case where the present invention is applied to a resistance element will be described. That is, in the LCD driver, in addition to the low withstand voltage MISFET or the high withstand voltage MISFET, a plurality of resistive elements constituting a circuit are also formed. In this resistance element, a high voltage is applied in the same manner as a high-withstand voltage MISFET. Therefore, in the case of using a high-voltage resistance element like a high-withstand voltage MISFET, the withstand voltage system poses a problem. FIG. 30 is a plan view showing a resistive element according to the fourth embodiment. As shown in FIG. 30, a gate insulating film 8 is formed on a semiconductor substrate 1S, and a polycrystalline silicon film (conductor film) 40 as a resistance element is formed on the gate insulating film 8. The polycrystalline silicon film 40 as a resistance element is connected to the wiring 43 through a plug (fourth plug) 42. On the other hand, a wiring 44 which is not connected to the resistance element is also formed. The fourth embodiment is characterized in that a wiring 44 and a wiring 44 formed on the polycrystalline silicon film 40 as a resistive element are applied with a wiring 44 having a potential different from that of the polycrystalline silicon film 40, and are arranged in a plan view with the polycrystalline silicon film 40. Do not overlap. In short, since the wiring 43 that is directly electrically connected through the polycrystalline silicon film 40 and the plug 42 is turned on, a voltage withstand problem does not occur with the polycrystalline silicon film 40. Thereby, as shown in FIG. 30, the polycrystalline silicon film 40 and the wiring 43 are arranged so as to overlap each other in a plan view. In contrast, the wiring 44 which is not electrically connected directly by the polycrystalline silicon film 40 and the plug 42 and is applied with a potential different from that of the polycrystalline silicon film 40 is a case where a high potential difference is generated between the polycrystalline silicon film 40 and the polycrystalline silicon film 40 in this case. Between the film 40 and the wiring 44, a breakdown voltage is a problem. Therefore, the wiring 44 that is not directly electrically connected by the polycrystalline silicon film 40 and the plug 42 is disposed so as not to overlap the polycrystalline silicon film 40 as a resistance element in a plan view. With this configuration, even if a high voltage is applied between the polycrystalline silicon film 40 and the wiring 44 as a resistance element, the withstand voltage can be ensured. FIG. 31 is a cross-sectional view taken along the line BB of FIG. 30. In FIG. 31, a resistance element formation region is formed so as to be adjacent to a high-withstand voltage MISFET formation region. The structure of the resistive element formed in the resistive element formation region will be described below. In FIG. 31, an element isolation region 2 is formed on a semiconductor substrate 1S, and a film having the same thickness as a gate insulating film 8 used for a high-voltage MISFET (referred to as gate insulation) is formed on the element isolation region 2. Film 8). Then, a polycrystalline silicon film 40 is formed on the gate insulating film 8. The polycrystalline silicon film 40 is formed using the same film as the polycrystalline silicon film constituting the gate electrode 10b of the high-voltage MISFET. The polycrystalline silicon film 40 functions as a resistance element. A side wall 41 equivalent to the side wall 12 is formed on the sidewall of the polycrystalline silicon film 40 through the step of forming the side wall 12 of the MISFET. Further, a cobalt silicide film 15 is formed on a part of the surface of the polycrystalline silicon film 40. Then, an interlayer insulating film is formed so as to cover the polycrystalline silicon film 40. The interlayer insulating film is formed of a silicon nitride film 16 and a silicon oxide film 17. On the interlayer insulating film, a plug 42 penetrating the interlayer insulating film and reaching the cobalt silicide film 15 formed on the surface of the polycrystalline silicon film 40 is formed, and a wiring 43 directly electrically connected to the plug 42 is formed on the interlayer insulating film. 31 is a cross-sectional view taken along a line BB in FIG. 30, and therefore, the wiring 43 is directly electrically connected to the polycrystalline silicon film 40 through the plug 42. In addition, FIG. 30 illustrates a feature of the fourth embodiment, that is, the wiring 44 and the polycrystalline silicon film 40 do not overlap in a plan view. Here, the resistive element is formed using a step of forming a high-withstand voltage MISFET. That is, the gate insulating film 8 formed on the element isolation region 2 is also the same as the gate insulating film 8 of the high-withstand voltage MISFET, and the polycrystalline silicon film 40 formed on the gate insulating film 8 is also used and configured. The polycrystalline silicon film of the gate electrode 10b of the high-withstand voltage MISFET is the same film. Therefore, the height of the resistance element is the same as the height of the high-withstand voltage MISFET. On the other hand, the thickness of the interlayer insulating film is the same in the high-withstand voltage MISFET formation area and the resistance element formation area, and the interlayer insulation film is considered from the viewpoint of reducing the aspect ratio of the plug PLG1 of the high-withstand voltage MISFET as much as possible. Of thin film. Therefore, if the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b in the high-withstand voltage MISFET formation area is a, the wiring HL1 is formed from the upper portion of the gate electrode 10b. When the distance between the upper portions of the interlayer insulating films is set to b, a condition of a> b is satisfied. Then, a polycrystalline silicon film 40 (resistive element) is formed on the gate insulating film 8, and the polycrystalline silicon film 40 (resistive element) is formed in the same film as the polycrystalline silicon film constituting the gate electrode 10 b of the high-withstand voltage MISFET. Therefore, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the polycrystalline silicon film 40 in the resistive element formation region is also the same as a. From the upper portion of the polycrystalline silicon film 40 to the wiring 43 or the wiring 44 ( The distance between the upper portions of the interlayer insulating films (see FIG. 30) is also the same as b. Therefore, the condition that a> b is satisfied also in the resistance element formation region. From the above, in the resistive element, the thickness of the interlayer insulating film between the polycrystalline silicon film 40 and the wiring 44 (not shown in FIG. 31) is reduced, which is the same as that of the high-withstand voltage MISFET, and the polycrystalline silicon film interposed with the interlayer insulating film. The withstand voltage between 40 and wiring 44 poses a problem. Therefore, as shown in FIG. 30, in the resistive element, a wiring 44 and a wiring 44 formed on the polycrystalline silicon film 40 as a resistive element are applied with a wiring 44 having a potential different from that of the polycrystalline silicon film 40, and are arranged to be polycrystalline silicon. The films 40 do not overlap in a plan view. With this configuration, even if the interlayer insulating film becomes thin, the withstand voltage between the polycrystalline silicon film 40 and the wiring 44 can be ensured. Here, as a method for reducing the height of the resistive element, a case where the polycrystalline silicon film 40 constituting the resistive element is not formed on the thick gate insulating film 8 and is formed directly on the element separation region 2 or a low-resistance element may be considered. Formed on the gate insulation film of a thin layer of the MISFET. In this case, since the height of the polycrystalline silicon film 40 constituting the resistance element becomes low, the thickness of the interlayer insulating film interposed between the polycrystalline silicon film 40 and the wiring 44 can be increased. Therefore, it is judged that the polycrystalline silicon film 40 and the wiring 44 can be increased. Of pressure resistance. However, in the fourth embodiment, a polycrystalline silicon film 40 as a resistance element is formed on the same film as the gate insulating film 8 of the high-withstand voltage MISFET for the reasons described below. The reason will be described with reference to the drawings. 32 and 33 are cross-sectional views showing a step of forming a general element separation region. For example, as shown in FIG. 32, by using a photolithography technique and an etching technique, an element isolation trench 2a is formed on the semiconductor substrate 1S. Then, as shown in FIG. 33, after the device isolation trench 2a is formed by embedding a silicon oxide film, the silicon oxide film formed on the surface of the semiconductor substrate 1S is removed by chemical mechanical polishing (CMP). . Thereby, the silicon oxide film can be left only in the element isolation trench 2a, so that the element isolation region 2 in which only the silicon oxide film is buried can be formed in the element isolation trench 2a. 32 and 33 are steps for forming a normal element separation region 2. However, as shown in FIG. 34, for example, when the element isolation trench 2a is formed on the semiconductor substrate 1S, foreign matter 45a is adhered to the etched area of the semiconductor substrate 1S. In this way, the foreign matter 45a becomes a mask, and the silicon formed on the lower layer of the foreign matter remains without being etched. That is, as shown in FIG. 34, an etching residue 45 is formed on the layer below the foreign matter 45a. Thereafter, as shown in FIG. 35, when the element isolation region 2 in which the element isolation trench 2 a is buried with a silicon oxide film is formed, the etching residue 45 is also maintained. Therefore, if a polycrystalline silicon film 40 as a resistive element is formed on the element isolation region 2 where the etching residue 45 is formed, since the etching residue 45 is formed of silicon, the polycrystalline silicon film 40 and the semiconductor substrate 1S pass through the etching residue 45. The short circuit is inconvenient. This inconvenience is significant when the polycrystalline silicon film 40 is directly formed on the element isolation region 2. However, as shown in FIG. 36, when the polycrystalline silicon film 40 is formed by the intervening thin gate insulating film 7, the Since a high voltage is applied to the polycrystalline silicon film 40, short-circuit failure is also apt to occur. Thus, as shown in FIG. 37, after forming a thick gate insulating film 8 on the element isolation region 2, a polycrystalline silicon film 40 is formed on the thick gate insulating film 8. Since a thick gate insulating film 8 is formed between the polycrystalline silicon film 40 as a resistive element and the element separation region 2, for example, as shown in FIG. 37, the polycrystalline silicon film 40 can be greatly reduced even if an etching residue 45 occurs in the element separation region 2. And the semiconductor substrate 1S is short-circuited through the etching residue 45. For the above reasons, the polycrystalline silicon film 40 constituting the resistance element is formed on the gate insulating film 8 having the same thickness as the gate insulating film 8 of the high-withstand voltage MISFET. Therefore, the polycrystalline silicon film 40 (resistive element) is formed on the gate insulating film 8, and the polycrystalline silicon film 40 (resistive element) is formed with the same film as the polycrystalline silicon film constituting the gate electrode 10 b of the high-withstand voltage MISFET. Therefore, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the polycrystalline silicon film 40 in the resistive element formation region is also the same as a. From the upper portion of the polycrystalline silicon film 40 to the wiring 43 or the wiring 44 ( The distance between the upper portions of the interlayer insulating films (see FIG. 30) is also the same as b. Therefore, the condition that a> b is satisfied also in the resistance element formation region. However, in the fourth embodiment, the wiring 43 and the wiring 44 formed on the polycrystalline silicon film 40 as a resistance element are applied with a wiring 44 having a potential different from that of the polycrystalline silicon film 40, and are arranged so as to be in contact with the polycrystalline silicon film 40. Since they do not overlap in a plan view, even if the interlayer insulating film becomes thin, a significant effect of ensuring the withstand voltage between the polycrystalline silicon film 40 and the wiring 44 is exhibited. (Embodiment Mode 5) In the aforementioned Embodiment Mode 1, the description is made about the formation of an interlayer insulating film to cover the low withstand voltage MISFET and the high withstand voltage MISFET after forming the low withstand voltage MISFET and the high withstand voltage MISFET. A step of forming wiring on the interlayer insulating film. In the fifth embodiment, the steps for forming the interlayer insulating film are further described in detail. 38 is a cross-sectional view showing a state where a low-withstand voltage MISFET, a high-withstand voltage MISFET, and a resistance element are formed on the semiconductor substrate 1S. That is, in FIG. 38, in addition to the low withstand voltage MISFET and the high withstand voltage MISFET, a resistance element is also formed. This resistance element is formed by a step of forming a high-withstand voltage MISFET. Then, as shown in FIG. 38, a silicon nitride film 16 is formed so as to cover the low withstand voltage MISFET, the high withstand voltage MISFET, and the resistance element. The silicon nitride film 16 can be formed using, for example, a CVD method. Next, as shown in FIG. 39, a silicon oxide film 50 is formed on the silicon nitride film 16 formed on the semiconductor substrate 1S. The silicon oxide film 50 can be formed by a high-density plasma CVD method using, for example, a high-density plasma. High-density plasma refers to the use of high-frequency electric and magnetic fields to convert gas into plasma in a high density. The high-density plasma CVD method refers to the conversion of gas introduced into a processing chamber into a high-density plasma, so that high-density plasma A method in which a slurry undergoes a chemical reaction to deposit a film on a semiconductor substrate 1S. Examples of a method for generating a high-density plasma include an induced coupled plasma (ICP) or an electron cyclotron resonance (ECR) method. Induced binding plasma is a type of high-density plasma used in chemical vapor phase growth method. The induced high frequency coil is used to excite the gas introduced into the processing chamber to cause it to generate plasma. On the other hand, the electron cyclotron resonance is a phenomenon shown below. That is, if an electron is subjected to a Lorentz force in a magnetic field, it will perform a swirling motion in a plane perpendicular to the magnetic field. At this time, if an electric field with the same frequency is given in the electron's motion plane, it will cause the swirling motion and the energy of the electric field to resonate. The electric field energy will be absorbed by the electrons, which will supply a large amount of energy to the electrons. Using this phenomenon, various gases can be converted into high-density plasma. The silicon oxide film 50 formed by the high-density plasma CVD method as described above has the advantage of good landfill characteristics. Therefore, since the silicon oxide film 50 formed by the high-density plasma CVD method is formed on the silicon nitride film 16, the miniaturization of memory cells such as SRAM (Static Random Access Memory) is progressing. A device with a smaller interval between the gate electrodes can still make the silicon oxide film have good landfill characteristics between the gate electrodes. In short, SRAM is also mounted on semiconductor devices that are LCD drivers. As the SRAM progresses in miniaturization, the distance between the gate electrodes becomes very narrow. Therefore, with the CVD method using a plasma of ordinary density, when a silicon oxide film is buried between the gate electrodes, the space between the gate electrodes cannot be fully filled, and a "void" occurs in the space between the gate electrodes. ". If "pores" occur between the gate electrodes, the conductor film used in the formation of the plugs in the steps described below will invade the inside of the "pores", the intervening agents will invade the conductive film inside the "pores" and the adjacent plugs will short-circuit and occur bad. Therefore, in the fifth embodiment, a silicon oxide film 50 is formed on the silicon nitride film 16 by using a high-density plasma CVD method with good landfill characteristics. In this way, by depositing the silicon oxide film 50 using a high-density plasma CVD method, the SRAM and other miniaturized components can improve the landfill characteristics for the space between the gate electrodes. As a result, occurrence of "voids" can be suppressed, and short-circuit failures of adjacent plugs can be prevented. Next, as shown in FIG. 40, a silicon oxide film 51 is formed on the silicon oxide film 50. The silicon oxide film 51 can be formed by a plasma CVD method using TEOS (tetra ethyl ortho silicate) as a raw material, for example. The plasma CVD method using TEOS as the raw material is a plasma generally having a lower density than the high-density plasma CVD method. The usual plasma CVD method using TEOS as a raw material has the characteristics of good film thickness controllability of the silicon oxide film 51, and the silicon oxide film 51 is formed to obtain the film thickness of the interlayer insulating film. Next, as shown in FIG. 41, the surface of the silicon oxide film 51 is planarized. The planarization of the surface of the silicon oxide film 51 is performed by, for example, polishing the surface of the silicon oxide film 51 by a chemical mechanical polishing method (CMP). In this step, the thickness of the silicon oxide film 51 becomes thin due to variations in the polishing amount caused by CMP, for fear that the upper portion of the high-withstand voltage MISFET or the upper portion of the resistance element is exposed. Therefore, as shown in FIG. 42, a silicon oxide film (gap insulating film) 52 is formed on the planarized silicon oxide film 51. The silicon oxide film 52 is the same as the silicon oxide film 51, and can be formed by a conventional plasma CVD method using TEOS as a raw material. Next, as shown in FIG. 43, a contact hole is formed in the interlayer insulating film (the silicon oxide film 52, the silicon oxide film 51, the silicon oxide film 50, and the silicon nitride film 16) using a photolithography technique and an etching technique. The contact hole penetrates the interlayer insulating film and reaches the semiconductor substrate 1S. Then, a titanium / titanium nitride film is formed on the interlayer insulating film including the bottom surface and the inner wall of the contact hole. The titanium / titanium nitride film is a laminated film of a titanium film and a titanium nitride film, and can be formed by, for example, using a sputtering method. Thereafter, a tungsten film is formed on the entire surface of the main surface of the semiconductor substrate 1S by filling the contact holes. This tungsten film can be formed using, for example, a CVD method. Next, by removing the unnecessary titanium / titanium nitride film and tungsten film formed on the interlayer insulating film by, for example, the CMP method, and leaving only the titanium / titanium nitride film and tungsten film in the contact hole, a plug PLG1 can be formed. And plug 42. Next, as shown in FIG. 44, a titanium / titanium nitride film, a copper-containing aluminum film, and a titanium / titanium nitride film are sequentially formed on the silicon oxide film 52 and the plug PLG1. These films can be formed by using, for example, a sputtering method. Next, by using the photolithography technology and the etching technology, the films are patterned to form wirings HL1, wirings LL1, wirings 43, and wirings 53. In this way, the wiring HL1, the wiring LL1, the wiring 43 and the wiring 53 can be formed on the first interlayer insulating film. The fifth embodiment is also the same as the first embodiment, and is arranged in such a manner that the wiring HL1 and the gate electrode 10b disposed on the first interlayer insulating film do not overlap in a plan view. Accordingly, since the wiring HL1 is not formed directly above the gate electrode 10b of the high-withstand voltage MISFET, the distance between the wiring HL1 and the gate electrode 10b can be increased even if the first interlayer insulating film is formed into a thin film. Therefore, the withstand voltage of the gate electrode 10b of the high-withstand voltage MISFET and the wiring HL1 as a source wiring or a drain wiring can be secured. On the other hand, in the resistive element formation region, the wiring 43 directly electrically connected to the polycrystalline silicon film 40 as a resistive element through the plug 42 is formed so as to overlap the polycrystalline silicon film 40 in a plan view. However, since the wiring 43 and the wiring 53 formed on the polycrystalline silicon film 40 as a resistance element are not directly connected to the polycrystalline silicon film 40 with the plug 42, and the wiring 53 having a potential different from that of the polycrystalline silicon film 40 is configured, Since it does not overlap with the polycrystalline silicon film 40 in a plan view, even if the interlayer insulating film becomes thin, the withstand voltage between the polycrystalline silicon film 40 and the wiring 53 can be ensured. In the above, the invention realized by the present inventors has been specifically described based on the embodiment. However, the present invention is not limited to the foregoing embodiment, and of course, various changes can be made without departing from the gist thereof. In the foregoing embodiment, an example will be described in which an n-channel MISFET is used as a low-withstand voltage MISFET and a high-withstand voltage MISFET formed in an LCD driver, but a p-channel-type MISFET is used as a low-withstand voltage MISFET and a high-withstand MISFET In some cases, the technical ideas of this implementation form can also be applied. (Industrial Applicability) The present invention can be widely used in manufacturing of semiconductor devices.
1S‧‧‧半導體基板1S‧‧‧Semiconductor substrate
2‧‧‧元件分離區域2‧‧‧ component separation area
2a‧‧‧元件分離溝槽2a‧‧‧Element separation trench
3‧‧‧電場緩和用絕緣區域3‧‧‧ Insulation area for electric field mitigation
4‧‧‧p型井4‧‧‧p well
5‧‧‧p型井5‧‧‧p well
6‧‧‧高耐壓用低濃度雜質擴散區域6‧‧‧ Low concentration impurity diffusion region for high withstand voltage
7‧‧‧閘極絕緣膜7‧‧‧Gate insulation film
8‧‧‧閘極絕緣膜8‧‧‧Gate insulation film
9‧‧‧多晶矽膜9‧‧‧ polycrystalline silicon film
10a‧‧‧閘極電極10a‧‧‧Gate electrode
10b‧‧‧閘極電極10b‧‧‧Gate electrode
11‧‧‧低耐壓用低濃度雜質擴散區域11‧‧‧ Low concentration impurity diffusion region for low withstand voltage
12‧‧‧邊牆12‧‧‧ side wall
13‧‧‧低耐壓用高濃度雜質擴散區域13‧‧‧ High-concentration impurity diffusion region for low withstand voltage
14‧‧‧高耐壓用高濃度雜質擴散區域14‧‧‧ High-concentration impurity diffusion region for high withstand voltage
15‧‧‧鈷矽化物膜15‧‧‧ cobalt silicide film
16‧‧‧氮化矽膜16‧‧‧ Silicon nitride film
17‧‧‧氧化矽膜17‧‧‧ silicon oxide film
18a‧‧‧鈦/氮化鈦膜18a‧‧‧Titanium / Titanium Nitride Film
18b‧‧‧鎢膜18b‧‧‧ tungsten film
19a‧‧‧鈦/氮化鈦膜19a‧‧‧Titanium / Titanium Nitride Film
19b‧‧‧鋁膜19b‧‧‧aluminum film
19c‧‧‧鈦/氮化鈦膜19c‧‧‧Titanium / Titanium Nitride Film
20‧‧‧氧化矽膜20‧‧‧ silicon oxide film
21‧‧‧氧化矽膜21‧‧‧Silicon oxide film
22‧‧‧表面保護膜22‧‧‧ surface protection film
23‧‧‧UBM膜23‧‧‧UBM film
24‧‧‧導體膜24‧‧‧Conductor film
30a‧‧‧玻璃基板30a‧‧‧ glass substrate
30b‧‧‧玻璃基板30b‧‧‧ glass substrate
31‧‧‧可撓性基板31‧‧‧ flexible substrate
32‧‧‧各向異性導電膜32‧‧‧Anisotropic conductive film
33‧‧‧顯示部33‧‧‧Display
40‧‧‧多晶矽膜40‧‧‧polycrystalline silicon film
41‧‧‧邊牆41‧‧‧Sidewall
42‧‧‧插塞42‧‧‧plug
43‧‧‧布線43‧‧‧Wiring
44‧‧‧布線44‧‧‧ Wiring
45‧‧‧蝕刻殘留物45‧‧‧ etching residue
45a‧‧‧異物45a‧‧‧ foreign body
50‧‧‧氧化矽膜50‧‧‧ silicon oxide film
51‧‧‧氧化矽膜51‧‧‧Silicon oxide film
52‧‧‧氧化矽膜52‧‧‧Silicon oxide film
53‧‧‧布線53‧‧‧Wiring
BMP‧‧‧凸塊電極BMP‧‧‧ bump electrode
C1‧‧‧閘極驅動電路C1‧‧‧Gate driving circuit
C2‧‧‧源極驅動電路C2‧‧‧Source driving circuit
C3‧‧‧液晶驅動電路C3‧‧‧LCD driver circuit
C4‧‧‧圖形RAMC4‧‧‧Graphic RAM
C5‧‧‧周邊電路C5‧‧‧ Peripheral circuit
CHP‧‧‧半導體晶片CHP‧‧‧Semiconductor wafer
CNT1‧‧‧接觸孔CNT1‧‧‧ contact hole
GL‧‧‧閘極布線GL‧‧‧Gate wiring
HL1‧‧‧布線HL1‧‧‧Wiring
HL2‧‧‧布線HL2‧‧‧Wiring
LL1‧‧‧布線LL1‧‧‧Wiring
LL2‧‧‧布線LL2‧‧‧Wiring
PAD‧‧‧墊PAD‧‧‧pad
PLG1‧‧‧插塞PLG1‧‧‧plug
PLG2‧‧‧插塞PLG2‧‧‧plug
RES‧‧‧抗蝕劑膜RES‧‧‧resist film
圖1係表示本發明之實施型態之半導體晶片(LCD驅動器)之俯視圖。 圖2係表示圖1所示之半導體晶片之內部構造之一例之剖面圖。 圖3係圖2所示之高耐壓MISFET之俯視圖。 圖4係表示實施型態之半導體裝置之製造步驟之剖面圖。 圖5係表示接續於圖4之半導體裝置之製造步驟之剖面圖。 圖6係表示接續於圖5之半導體裝置之製造步驟之剖面圖。 圖7係表示接續於圖6之半導體裝置之製造步驟之剖面圖。 圖8係表示接續於圖7之半導體裝置之製造步驟之剖面圖。 圖9係表示接續於圖8之半導體裝置之製造步驟之剖面圖。 圖10係表示接續於圖9之半導體裝置之製造步驟之剖面圖。 圖11係表示接續於圖10之半導體裝置之製造步驟之剖面圖。 圖12係表示接續於圖11之半導體裝置之製造步驟之剖面圖。 圖13係表示接續於圖12之半導體裝置之製造步驟之剖面圖。 圖14係表示接續於圖13之半導體裝置之製造步驟之剖面圖。 圖15係表示接續於圖14之半導體裝置之製造步驟之剖面圖。 圖16係表示接續於圖15之半導體裝置之製造步驟之剖面圖。 圖17係表示接續於圖16之半導體裝置之製造步驟之剖面圖。 圖18係表示接續於圖17之半導體裝置之製造步驟之剖面圖。 圖19係表示接續於圖18之半導體裝置之製造步驟之剖面圖。 圖20係表示接續於圖19之半導體裝置之製造步驟之剖面圖。 圖21係表示接續於圖20之半導體裝置之製造步驟之剖面圖。 圖22係表示接續於圖21之半導體裝置之製造步驟之剖面圖。 圖23係表示接續於圖22之半導體裝置之製造步驟之剖面圖。 圖24係表示接續於圖23之半導體裝置之製造步驟之剖面圖。 圖25係表示接續於圖24之半導體裝置之製造步驟之剖面圖。 圖26係表示於玻璃基板實裝半導體晶片之狀況之剖面圖。 圖27係表示LCD之全體結構之圖。 圖28係表示實施型態2及實施型態3之半導體裝置之剖面圖。 圖29係具體表示光微影步驟之圖案之尺寸誤差及圖案間之對齊偏離之圖。 圖30係表示實施型態4之電阻元件之結構之俯視圖。 圖31係包含以圖30之B-B線切斷之剖面之剖面圖。 圖32係表示形成一般之元件分離區域之步驟之剖面圖。 圖33係接續於圖32之形成元件分離區域之步驟之剖面圖。 圖34係表示形成元件分離溝槽時由於異物而產生蝕刻殘留物之狀態之剖面圖。 圖35係接續於圖34之形成元件分離區域之步驟之剖面圖。 圖36係表示於形成有蝕刻殘留物之元件分離區域上中介薄層之閘極絕緣膜來形成電阻元件之例之剖面圖。 圖37係表示於形成有蝕刻殘留物之元件分離區域上中介厚層之閘極絕緣膜來形成電阻元件之例之剖面圖。 圖38係表示實施型態5之半導體裝置之製造步驟之剖面圖。 圖39係表示接續於圖38之半導體裝置之製造步驟之剖面圖。 圖40係表示接續於圖39之半導體裝置之製造步驟之剖面圖。 圖41係表示接續於圖40之半導體裝置之製造步驟之剖面圖。 圖42係表示接續於圖41之半導體裝置之製造步驟之剖面圖。 圖43係表示接續於圖42之半導體裝置之製造步驟之剖面圖。 圖44係表示接續於圖43之半導體裝置之製造步驟之剖面圖。FIG. 1 is a plan view showing a semiconductor wafer (LCD driver) according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of the internal structure of the semiconductor wafer shown in FIG. 1. FIG. FIG. 3 is a top view of the high-withstand voltage MISFET shown in FIG. 2. FIG. 4 is a sectional view showing the manufacturing steps of a semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 4. FIG. 6 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 5. FIG. 7 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 6. FIG. 8 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 7. FIG. 9 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 8. FIG. 10 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 9. FIG. 11 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 10. FIG. 12 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 11. FIG. 13 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 12. FIG. 14 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 13. FIG. 15 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 14. FIG. 16 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 15. FIG. 17 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 16. FIG. 18 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 17. FIG. 19 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 18. FIG. 20 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 19. FIG. 21 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 20. FIG. 22 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 21. FIG. 23 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 22. FIG. 24 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 23. FIG. 25 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 24. FIG. FIG. 26 is a cross-sectional view showing a state where a semiconductor wafer is mounted on a glass substrate. FIG. 27 is a diagram showing the overall structure of an LCD. FIG. 28 is a cross-sectional view showing a semiconductor device according to a second embodiment and a third embodiment. FIG. 29 is a diagram specifically showing a dimensional error of a pattern in a photolithography step and an alignment deviation between the patterns. FIG. 30 is a plan view showing the structure of a resistance element according to the fourth embodiment. Fig. 31 is a cross-sectional view including a cross section taken along a line B-B in Fig. 30. Fig. 32 is a cross-sectional view showing a step of forming a general element separation region. FIG. 33 is a cross-sectional view of a step of forming an element separation region continued from FIG. 32. FIG. FIG. 34 is a cross-sectional view showing a state where an etching residue is generated due to a foreign matter when the element isolation trench is formed. FIG. 35 is a cross-sectional view of a step of forming an element separation region continued from FIG. 34. FIG. FIG. 36 is a cross-sectional view showing an example of forming a resistive element by interposing a thin gate insulating film with an interlayer thin layer on an element separation region where an etching residue is formed. FIG. 37 is a cross-sectional view showing an example of forming a resistive element by interposing a thick gate insulating film on a device isolation region where an etching residue is formed. Fig. 38 is a cross-sectional view showing the manufacturing steps of a semiconductor device according to a fifth embodiment. FIG. 39 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 38. FIG. FIG. 40 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 39. FIG. FIG. 41 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 40. FIG. FIG. 42 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 41. FIG. FIG. 43 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 42. FIG. FIG. 44 is a sectional view showing the manufacturing steps of the semiconductor device continued from FIG. 43. FIG.
Claims (1)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007-153840 | 2007-06-11 | ||
| JP2007153840 | 2007-06-11 | ||
| JP2008071291A JP5280716B2 (en) | 2007-06-11 | 2008-03-19 | Semiconductor device and manufacturing method thereof |
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| JP5968372B2 (en) * | 2014-07-17 | 2016-08-10 | 学校法人 龍谷大学 | Magnetic field sensor |
| US9349719B2 (en) * | 2014-09-11 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device |
| JP6507007B2 (en) * | 2015-03-27 | 2019-04-24 | 東レエンジニアリング株式会社 | LED module and method of manufacturing LED module |
| CN115799342A (en) * | 2016-07-26 | 2023-03-14 | 株式会社半导体能源研究所 | Semiconductor device with a plurality of semiconductor chips |
| TWI716865B (en) * | 2019-05-06 | 2021-01-21 | 世界先進積體電路股份有限公司 | Semiconductor device structures |
| US11476207B2 (en) | 2019-10-23 | 2022-10-18 | Vanguard International Semiconductor Corporation | Semiconductor device structure comprising source and drain protective circuits against electrostatic discharge (ESD) |
| US11282790B1 (en) * | 2020-09-09 | 2022-03-22 | Nanya Technology Corporation | Semiconductor device with composite landing pad for metal plug |
| US11699734B2 (en) * | 2021-02-10 | 2023-07-11 | Nanya Technology Corporation | Semiconductor device with resistance reduction element and method for fabricating the same |
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| TWI361490B (en) * | 2003-09-05 | 2012-04-01 | Renesas Electronics Corp | A semiconductor device and a method of manufacturing the same |
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| JP4881552B2 (en) * | 2004-09-09 | 2012-02-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
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| KR100688552B1 (en) * | 2005-06-08 | 2007-03-02 | 삼성전자주식회사 | Mos field effect transistor having thick edge gate insulating layer pattern and method of fabricating the same |
| JP2007042804A (en) * | 2005-08-02 | 2007-02-15 | Renesas Technology Corp | Semiconductor device and manufacturing method thereof |
| JP5209196B2 (en) * | 2005-11-07 | 2013-06-12 | 三星電子株式会社 | Manufacturing method of semiconductor device |
| JP2007141934A (en) * | 2005-11-15 | 2007-06-07 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
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| JP5280716B2 (en) | 2013-09-04 |
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| TWI563599B (en) | 2016-12-21 |
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