JP4648286B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having a high breakdown voltage field effect transistor and a manufacturing technique thereof.

  In recent years, semiconductor devices have adopted a trench-type isolation structure called STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation), which is advantageous in improving the degree of element integration, such as reducing the isolation width. Has been. However, if the channel region of the low breakdown voltage MIS • FET having a small element size and a low applied voltage is defined by the groove-type isolation part, an abnormal kink phenomenon is likely to occur in addition to the normal turn-on waveform. The kink phenomenon is a phenomenon in which when the drain voltage dependency of the drain current is measured, the drain current changes from a certain voltage value to an irregular hump and a stepped waveform is formed. The main cause of the above-mentioned kink phenomenon in the low-voltage MIS • FET is that the mechanical stress from the groove-type separation part is concentrated on the shoulder formed by the main surface of the semiconductor substrate and the side surface of the groove-type separation part. However, it is known that the mobility of carriers at the shoulder partly increases as a result of the change in the lattice constant of silicon at the shoulder part.

  As described above, the cause of the kinks in the low withstand voltage MIS • FET is because the shape of the shoulder portion of the semiconductor substrate on the side wall of the separation portion is steep, so that the shoulder portion is rounded to prevent the kink phenomenon. It has become mainstream.

  In addition, as a countermeasure against kinks of other low breakdown voltage MIS • FETs, for example, Japanese Patent Laid-Open No. 9-237829 discloses a high-concentration impurity region having the same conductivity type as the well at the boundary between the groove-type isolation portion and the semiconductor substrate. A technique for providing the above is disclosed (see Patent Document 1).

  Also, for example, in Japanese Patent Application Laid-Open No. 2001-144189, in a low breakdown voltage MOSFET partitioned by a trench element isolation region, a central portion of the channel region is a p-type channel region having a low threshold voltage, and the trench element isolation region A technique is disclosed in which both end portions in the vicinity of the boundary are made into p + type channel regions each having a high threshold voltage (see Patent Document 2).

  Further, for example, in Japanese Patent Laid-Open No. 10-65153, the outer periphery of the active region defined by the trench type element isolation film is shallower than the source / drain junction of the low breakdown voltage MIS • FET and has the same conductivity type as the channel region. A technique for providing an impurity layer having a higher concentration than the channel region is disclosed (see Patent Document 3).

  Further, for example, in Japanese Patent Application Laid-Open No. 2001-160623, a low breakdown voltage MOSFET is formed in an active region defined by an element isolation film formed by a trench element isolation method, and a channel edge of the active region under the gate electrode of the MOSFET is disclosed. Disclosed is a technique for preventing the kink phenomenon by disposing the portion outside the implantation region of the high-concentration impurity ions for forming the source / drain regions and by detaching the channel edge from the operating portion. (See Patent Document 4).

As another countermeasure against the kink phenomenon, in an n-channel MOS / FET, an edge is formed by implanting nitrogen into the edge portion of the semiconductor substrate in contact with the groove-type isolation portion to form a SiN region. There have been proposed a method for preventing a decrease in boron concentration at the portion and reducing a leakage current due to the kink phenomenon, a method for improving the kink phenomenon by increasing the thickness of the oxide film in the vicinity of the groove type separation portion, and the like.
Japanese Patent Laid-Open No. 9-237829 JP 2001-144189 A JP-A-10-65153 JP 2001-160623 A

  By the way, the above kink phenomenon occurs even in the high breakdown voltage MIS • FET, but the cause is different from the kink phenomenon generated in the low breakdown voltage MIS • FET. In the case of the high breakdown voltage MIS • FET, the shoulder of the semiconductor substrate is rounded. The present inventor newly found out that there is a problem that the kink phenomenon cannot be sufficiently suppressed only by forming. Therefore, as described later, an important issue is how to suppress the kink phenomenon in the high breakdown voltage MIS • FET.

  An object of the present invention is to provide a technique capable of suppressing or preventing the kink phenomenon of a high breakdown voltage field effect transistor.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a semiconductor region having a conductivity type opposite to the semiconductor region for the drain of the high breakdown voltage field effect transistor at the boundary region between the separation portion at both ends in the gate width direction of the high breakdown voltage field effect transistor and the semiconductor substrate. A region having a higher impurity concentration than the channel region is provided, and the region having a higher impurity concentration is disposed away from the semiconductor region for the drain of the high breakdown voltage field effect transistor.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, the kink phenomenon in the high breakdown voltage field effect transistor can be suppressed or prevented. In addition, the characteristics of a semiconductor device having a high breakdown voltage field effect transistor can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, a field effect transistor MIS • FET (Metal Insulator Semiconductor • Field Effect Transistor) is abbreviated as MIS, n-channel MIS is abbreviated as nMIS, and p-channel MIS is abbreviated as pMIS. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the MIS described above, a MIS driven at a relatively high voltage is referred to as a high breakdown voltage MIS, and a MIS driven at a relatively low voltage is referred to as a low breakdown voltage MIS. The high breakdown voltage MIS is a MIS that operates by applying a potential of, for example, about 40 V to its drain region, and has a structure capable of realizing a breakdown voltage of 100 V. The low breakdown voltage MIS is a MIS that operates by applying a potential of, for example, about 1.5 V to its drain region.

  First, the kink phenomenon in the high withstand voltage MIS newly found by the present inventor will be described. The above kink phenomenon occurs even in a high withstand voltage MIS, but the cause is different from the kink phenomenon that occurs in a low withstand voltage MIS. In the case of a high withstand voltage MIS, the kink phenomenon can be sufficiently achieved by simply forming a rounded shoulder on the semiconductor substrate. The present inventors have found that there is a problem that it cannot be suppressed.

  FIG. 107 shows an example of an actual measurement waveform of the drain current ID with respect to the gate voltage VG of the high breakdown voltage MIS. FIG. 108 shows an explanatory diagram of the measurement waveform of FIG. The solid line A in FIG. 108 indicates the channel current of the high breakdown voltage MIS, and the broken line B indicates the edge current at both ends in the longitudinal direction (gate width direction) of the channel region of the high breakdown voltage MIS. In particular, when the separation part is formed in a groove shape as described above, a minute leak current (~~) along the boundary between the active region and the separation part at both ends due to stress or impurity concentration reduction at both ends in the longitudinal direction of the channel region. μA) flows and a kink phenomenon occurs. The reason why the kink phenomenon in the high withstand voltage MIS cannot be sufficiently suppressed only by forming the round portion in the shoulder portion of the semiconductor substrate as described above is because the cause of the kink phenomenon in the high withstand voltage MIS is a characteristic of the high withstand voltage MIS. This is because there are parts due to the configuration, and there are different parts from the cause of the kink phenomenon of the low withstand voltage MIS.

  The first reason is that in the high breakdown voltage MIS, the thickness of the gate insulating film must be much thicker than that of the low breakdown voltage MIS in order to ensure the gate breakdown voltage. In order to operate normally, the threshold voltage must be lowered, and for this purpose, the impurity concentration of the channel region (concentration of the impurity forming the opposite conductivity type to the drain region) must be set low. . For this reason, the kink phenomenon is likely to occur.

  The second reason will be described with reference to FIGS. 109 and 110. FIG. FIG. 109 is a plan view of an example of the high voltage MIS 50 to which the countermeasure against kink is not applied, and FIG. 110 is a cross-sectional view taken along line Y50-Y50 in FIG. Reference numeral V0 denotes a semiconductor region having an electric field relaxation function of the high breakdown voltage MIS50, S0 denotes a source region, and D0 denotes a drain region. The kink phenomenon is likely to occur in regions C at both ends in the longitudinal direction (gate width direction) of the channel region. This is for the following reason. That is, the upper surface of the groove-type separation portion 51 may be recessed (recessed) from the upper surface of the semiconductor substrate 52 by wet etching or the like. In this case, both ends of the gate electrode 53 and the groove-type separation portion 51 are formed. As a result, the distance E from the side wall of the semiconductor substrate 52 to the semiconductor substrate 52 is shortened. As a result, an electric field by the gate electrode 53 is applied to the semiconductor substrate 52 of the side wall of the trench-type separation part 51, and carriers are induced in the semiconductor substrate 52. A channel is also formed in the semiconductor substrate 52 portion on the side wall of the groove-type separation portion 51. However, in the high breakdown voltage MIS, the impurity concentration profile of the deep well 54 is gradually lowered as it becomes deeper from the main surface of the semiconductor substrate 52, so that the side wall of the trench-type isolation portion 51 at the semiconductor substrate 52 portion is reduced. The threshold voltage is lower than the threshold voltage at the main surface portion of the semiconductor substrate 52. And since the channel width in the semiconductor substrate 52 part of the side wall of the separation part 51 is narrow, there is little saturation current, and two kinds of MIS (main surface part and side wall part of the semiconductor substrate 52 are applied by applying an electric field by the gate electrode 53. ) And a stepped kink waveform is generated.

  Further, as in Patent Documents 1 to 3, there is a method of suppressing or preventing the kink phenomenon in the low withstand voltage MIS by providing high concentration regions at both ends in the gate width direction. However, as described above, the high breakdown voltage MIS and the low breakdown voltage MIS have different configurations, and there is a difference in the cause of the kink phenomenon. Therefore, a technique for forming a high concentration region at both ends in the gate width direction is described. However, it cannot simply be applied to the high voltage MIS as it is. For example, in the techniques disclosed in Patent Documents 1 and 2, since the high concentration region is provided so as to be in contact with the source and the drain, when applied to the high breakdown voltage MIS as it is, the drain breakdown voltage necessary for the high breakdown voltage MIS cannot be secured. This is because a problem occurs.

(Embodiment 1)
FIG. 1 is a plan view of a main part of an example of the high breakdown voltage pMISQHp1 according to the first embodiment, and FIG. 2 is a plan view of the same portion as FIG. 1, particularly a p − type semiconductor region having an electric field relaxation function of the high breakdown voltage pMISQHp1. FIG. 3 is a plan view of the main part showing the positional relationship between PV1 and the n + type semiconductor region NVk. FIG. 3 is a plan view of the same location as FIG. 1, and particularly shows the gate electrode HG, active region L, and n + type of the high breakdown voltage pMISQHp1. FIG. 4 is a plan view of the main portion showing the arrangement relationship with the semiconductor region NVk, FIG. 4 is a plan view of the same portion as FIG. 1 and particularly shows a main portion plan view showing the isolation region and the active region L, and FIG. 4 is a sectional view taken along line X1-X1, FIG. 6 is a sectional view taken along line X2-X2 in FIGS. 1 to 4, and FIG. 7 is a sectional view taken along line Y1-Y1 in FIGS. Although the case where the present invention is applied to the high breakdown voltage pMIS will be described here, the present invention can be applied to the high breakdown voltage nMIS by reversing the conductivity types of p and n. Further, FIG. 4 is a plan view, but hatching is given to the separation region in order to make the drawing easy to see. In addition, the first direction X is the horizontal direction in each figure and indicates the gate length direction (channel length direction) or the short direction of the gate electrode HG, and the second direction Y is a direction orthogonal to the first direction X. In the drawings, the vertical direction is the gate width direction or the longitudinal direction of the gate electrode HG.

  The high breakdown voltage pMIS (first, fifth, and sixth high breakdown voltage field effect transistors) QHp1 of the semiconductor device of the first embodiment is applied to, for example, a driver circuit of a liquid crystal display device, a motor control driver circuit that performs high current control, and the like. Has been. The power supply voltage on the high potential side is about 40 V, for example, and the power supply voltage on the low potential (reference potential) side is 1.5 (zero) V, for example.

A semiconductor substrate (hereinafter simply referred to as a substrate) 1S is made of, for example, p-type silicon (Si) single crystal, and the high breakdown voltage pMISQHp1 is disposed on the main surface (device formation surface). The high withstand voltage pMISQHp1 is cross-sectionally planarly formed by a deep n-type well (third, seventh, and eighth semiconductor regions) DNW and a planar frame-like n ⁺ -type well NW1 electrically connected thereto. Is also surrounded by. Thereby, the high breakdown voltage pMISQHp1 is electrically separated from the substrate 1S. Both the deep n-type well DNW and the n ⁺ -type well NW1 are doped with impurities such as phosphorus (P), but the impurity concentration of the n ⁺ -type well NW1 is deeper than that of the deep n-type well DNW. The impurity concentration is set to be higher than that. In addition, an n ⁺ type semiconductor region N 1 having a higher impurity concentration is formed above the n ⁺ type well NW 1 in order to make ohmic contact with a metal wiring that is a wiring layer. A silicide layer 2 such as cobalt silicide (CoSi ₂ or the like) is formed on the upper surface of the n ⁺ type semiconductor region N1. The silicide layer 2 may use various silicide layers such as titanium silicide (TiSi ₂ ), platinum silicide (PtSi ₂ ), nickel silicide (NiSi ₂ ), or tungsten silicide (WSi ₂ ) instead of cobalt silicide. .

As shown in FIG. 4, on the main surface of the substrate 1S, for example, a trench type isolation portion 3 called STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation) is formed as an element isolation region. Active regions L (L1 to L4) are defined. In FIG. 4, the hatched region is a region where the separation part 3 is formed. The groove-type separation part 3 is formed by embedding an insulating film such as silicon oxide (SiO ₂ or the like) in a groove dug in the main surface of the substrate 1S.

  As shown in FIGS. 5 to 7, the shoulder portion of the substrate 1 </ b> S (the corner formed by the main surface of the substrate 1 </ b> S and the upper side surface of the separation portion 3) in contact with the upper portion of the separation portion 3 is formed to be rounded. ing. When the separation portion 3 has a groove structure, mechanical stress concentrates on the shoulder portion of the substrate 1S, so that the lattice constant of silicon at the shoulder portion changes, and the mobility of carriers increases at the shoulder portion. It is known that the kink effect is likely to occur. Therefore, by forming roundness in the shoulder portion of the substrate 1S, mechanical stress applied to the shoulder portion can be relieved, so that occurrence of a kink phenomenon at the high breakdown voltage pMISQHp1 can be suppressed. However, as described above, this configuration alone cannot sufficiently suppress the kink phenomenon in the high breakdown voltage MIS. Note that the bottom of the groove of the separation part 3 is terminated at a position shallower than the deep n-type well DNW.

  Among the active regions L defined by the isolation portion 3, the central planar band-shaped active region L1 is a region including a region (channel region) where the channel of the high breakdown voltage pMISQHp1 is formed. The deep n-type well DNW is disposed in the channel region of the active region L1. That is, the channel region is n-type when not operating. The threshold voltage of the high breakdown voltage pMISQHp1 is determined by controlling the impurity concentration of the deep n-type well DNW in the channel region of the active region L1 and the impurity concentration introduced therein.

In the left and right active regions L2 and L3 of the central active region L1, p ⁺ type semiconductor regions (first, eleventh and twelfth semiconductor regions) P1 and P1 for the source and drain of the high breakdown voltage pMISQp1 are arranged. ing. The p ⁺ type semiconductor regions P1 and P1 for the source and drain are formed in the channel region of the central active region L1 due to the presence of the isolation part 3 between the central active region L1 and the left and right active regions L2 and L3. Are electrically connected to the channel region through p ⁻ type semiconductor regions (second semiconductor regions) PV1 and PV1 having an electric field relaxation function including the p ⁺ type semiconductor regions P1 and P2. ing.

When viewed in plan, the p ⁻ type semiconductor regions PV1 and PV1 have one end in the first direction X straddling the isolation region 3 between the active region L1 and the active regions L2 and L3, ie, on the active region L1 side (ie, And under the gate electrode HG), the channel region protrudes by a desired length so that a deep n-type well DNW corresponding to the channel region remains between the p ⁻ type semiconductor regions PV1 and PV1. On the other hand, the other ends in the first direction X and the two ends in the second direction Y of the p ⁻ type semiconductor regions PV1 and PV1 are terminated at positions not in contact with the n ⁺ type well NW1. Further, when viewed in cross section, the p ⁻ type semiconductor regions PV1 and PV1 extend to a position deeper than the isolation portion 3, but terminate at a position shallower than the deep n-type well DNW. . With such a configuration, the drain breakdown voltage of the high breakdown voltage pMISQHp1 can be ensured.

The ^{p +} -type semiconductor region for the source and drain P1, P1 and p ^- type semiconductor regions PV1, the PV1 are both, for example, an impurity such as boron (B) is introduced, ^{the p +} -type The impurity concentrations of the semiconductor regions P1 and P1 are made higher than the impurity concentrations of the p ⁻ type semiconductor regions PV1 and PV1 in order to make ohmic contact with the metal wiring. The silicide layer 2 is formed on the upper surfaces of the p ⁺ type semiconductor regions P1 and P1 for the source and drain.

On the central active region L1, the gate electrode HG of the high breakdown voltage pMISQHp1 is disposed so as to cover the entire region of the active region L1. Both ends of the gate electrode HG in the second direction Y (gate width direction) extend to a position where a part thereof overlaps the n ⁺ type well NW1 in plan view, thereby lowering the breakdown voltage of the high breakdown voltage pMISQHp1. In addition, it is possible to suppress or prevent the occurrence of the parasitic MIS on the surface of the deep n-type well DNW opposed to the gate electrode HG. The gate electrode HG is formed of a conductor film, and is made of, for example, low-resistance polycrystalline silicon doped with phosphorus or the like, and the silicide layer 2 is formed on the upper surface thereof. In the first embodiment, the silicide layer 2 is shown in the figure, but it is not necessarily formed. For example, the gate electrode HG is formed only of low resistance polycrystalline silicon doped with phosphorus or the like. May be.

  Further, a sidewall 5 made of, for example, silicon oxide is formed as an insulating film on the side surface of the gate electrode HG. A gate insulating film 6 is formed between the gate electrode HG and the main surface of the substrate 1S. The gate insulating film 6 includes, for example, an insulating film 6a made of silicon oxide or the like formed on the main surface of the substrate 1S by a thermal oxidation method or the like, and a chemical vapor deposition (CVD, here) For example, the insulating film 6b made of silicon oxide or the like deposited by the low pressure CVD method is used. The insulating film 6b formed by the CVD method of the gate insulating film 6 is formed so that the outer periphery thereof slightly protrudes from the outer periphery of the gate electrode HG when viewed in plan.

The n ⁺ type semiconductor region N1 is disposed in the outermost planar frame-like active region L4 in the active region L. In an actual semiconductor device, the active region L4, the n ⁺ type semiconductor region N1 and the n ⁺ type well NW1 generally surround a plurality of high breakdown voltage MISs. Here, for simplicity of explanation, a state in which one high withstand voltage pMISQHp1 is surrounded is illustrated.

By the way, in the case of the high breakdown voltage MIS as described above, the shoulder portion of the substrate 1S in contact with the upper portion of the separation portion 3 (the main surface of the substrate 1S and the upper side surface of the separation portion 3) exemplified as a countermeasure against the kink phenomenon in the low breakdown voltage MIS. The kink phenomenon cannot be sufficiently suppressed only by the technique of rounding the corners formed by Therefore, in the first embodiment, as shown in FIG. 1 to FIG. 5 and FIG. 7, both ends of the central active region L1 in the second direction Y, that is, in the second direction Y of the channel region of the high breakdown voltage pMISQHp1. In the boundary region between the groove-type separation part 3 and the substrate 1S at both ends (particularly the part of the substrate 1S in contact with the side wall of the separation part 3), the source and drain p ⁺ type semiconductor regions P1 and P1 are opposite Conductive n ⁺ -type semiconductor regions (fourth, thirteenth and fourteenth semiconductor regions) NVk were partially formed. Thereby, the threshold voltage at both ends (that is, the side wall portion) of the channel region in the second direction Y is made higher than the threshold voltage at the center of the channel region (that is, the main surface portion). Can do. That is, the MIS easily operates at the center of the channel region, but the MIS hardly operates at both ends in the second direction Y of the channel region. For this reason, even if the upper surface of the separation part 3 is depressed, the occurrence of the kink phenomenon can be suppressed or prevented. Therefore, the characteristics of the high breakdown voltage MIS can be improved. Although the threshold voltage is expressed as being high here, the high breakdown voltage pMIS is described here as an example, so that the negative side is expressed as being high when viewed from the source potential (for example, 0 V).

Further, the technique for forming the high concentration regions at both ends in the channel width direction (second direction Y) as a countermeasure against the kink phenomenon in the low breakdown voltage MIS cannot be directly applied to the high breakdown voltage MIS of the first embodiment. That is, in the high breakdown voltage MIS as in the first embodiment, the countermeasure against the kink phenomenon in the low breakdown voltage MIS is followed as it is, and the n ⁺ type semiconductor region NVk and the p ⁻ type semiconductor regions PV1 and PV1 are brought into contact with each other. This is because the high concentration region is in contact with the drain, so that the drain breakdown voltage necessary for the high breakdown voltage MIS cannot be secured. In particular, in the case of a product having a high target drain breakdown voltage, it is necessary to lower the impurity concentration at both ends in the channel width direction, so that the n ⁺ type semiconductor region NVk cannot simply be arranged. Therefore, in the first embodiment, ^{n +} -type semiconductor region NVk for kink countermeasures, p having the above electric field relaxing function ^- so as not to contact the type semiconductor region PV1, PV1 (especially the drain side), p ^- It is arranged at a position separated from the semiconductor regions PV1 and PV1 of the mold. Thereby, it is possible to prevent the drain breakdown voltage of the high breakdown voltage pMISQHp1 from decreasing. Therefore, according to the first embodiment, it is possible to simultaneously suppress or prevent the kink phenomenon and ensure the drain withstand voltage.

The n ⁺ -type semiconductor region NVk1 for preventing kinks is arranged so as to straddle both the active region L1 and the isolation portion 3. The concentration of the n-type impurity in the n ⁺ -type semiconductor region NVk is set higher than the concentration of the n-type impurity in the n-type well DNW deep in the channel region. Further, when viewed in cross section, the n ⁺ type semiconductor region NVk1 extends from the main surface of the substrate 1S to a position deeper than the bottom of the separation portion 3, and is substantially the same as the bottom of the p ⁺ type semiconductor regions P1 and P1. However, it is terminated at a position shallower than the deep n-type well DNW. In this way, by forming the n ⁺ -type semiconductor region NVk1 for countermeasure against kinks up to a position deeper than the isolation part 3, the ability to suppress or prevent the occurrence of the kink phenomenon can be enhanced. That is, since the threshold value at the shoulder portion of the substrate 1S in contact with the upper portion of the separation portion 3 can be increased, the occurrence of the kink phenomenon can be suppressed.

In the case where the potential of the p ⁺ type semiconductor region P1 for source out of the p ⁺ type semiconductor regions P1 and P1 for source and drain is always used at the same potential as that of the n type well DNW, the above-mentioned countermeasure against kinks The n ⁺ type semiconductor region NVk for use may be brought into contact with the p ⁺ type semiconductor region P1 for the source. As a result, it is possible to increase the alignment margin of the n ⁺ -type semiconductor region NVk for preventing kinks, and thus the arrangement thereof can be facilitated.

  Next, FIGS. 8 and 9 show an example of a circuit using a high breakdown voltage MIS. 8 and 9 show a constant current circuit having a differential circuit using a high breakdown voltage MIS. FIG. 8 shows a constant current source pushing circuit frequently used in an analog circuit. FIG. 8 exemplifies a case where the constant current source pushing circuit is configured by a plurality of high breakdown voltage nMISQHn having a common gate electrode and a high-potential power supply potential Vcc. That is, the power supply potential Vcc is applied to the drain region of the high breakdown voltage nMISQHn. FIG. 9 shows a constant current source drawing circuit frequently used in an analog circuit. FIG. 9 exemplifies a case where the constant current source lead-in circuit is formed with a plurality of high breakdown voltage pMISQHp sharing the gate electrode and the power supply potential GND on the reference potential side. That is, the power supply potential Vcc is applied to the gate electrode and drain region of the high breakdown voltage pMISQHp. The power supply potential Vcc on the high potential side is about 20 to 100 V, for example, and the power supply potential GND on the reference potential side is 0 (zero) V, for example. Reference numerals R1 and R2 in FIGS. 8 and 9 indicate resistances. In these circuits, the kink phenomenon is particularly problematic. In these circuits, if no countermeasure against the kink is taken, even if an attempt is made to design a predetermined current value with the size of the high withstand voltage MIS (channel length and channel width), the actual current value will be in the channel width direction. This is because the current flowing at both end portions (side wall portions of the separation portion 3) deviates from the design value. On the other hand, in the first embodiment, since the kink phenomenon can be suppressed or prevented, the error between the design value of the predetermined current value of the circuit and the actual measurement value can be reduced. Therefore, the characteristics of these circuits can be improved.

Next, FIG. 111 shows an example of a plan view of the main part when a plurality of high breakdown voltage pMISQHp3 are arranged. The high breakdown voltage pMISQHp3 is disposed adjacent to each other in a state where the direction of each channel (the direction in which the current flows) is along the first direction X. The high breakdown voltage pMISQHp3 adjacent to each other is arranged to share the p ⁺ type semiconductor regions P1 and P2 for the source and drain. The n ⁺ -type semiconductor region N1 and the n-type well NW1 are arranged so as to surround a group of the plurality of high breakdown voltage pMISQHp3.

In the first embodiment, even when the reduction of the size of the high breakdown voltage pMISQHp3 is promoted by miniaturization, the kink phenomenon can be suppressed or prevented by providing the n ⁺ type semiconductor region NVk1, so that the size of the high breakdown voltage pMISQHp3 is increased. Effective for reduction. Therefore, even if the size reduction amount of each high withstand voltage pMISQHp3 is small, the overall size can be reduced, so that the size of the semiconductor chip having the high withstand voltage pMISQHp3 can be greatly reduced.

(Embodiment 2)
In the first embodiment, the structure in which both the source and the drain can secure a breakdown voltage between the well and the well has been described. However, in the second embodiment, the high breakdown voltage is not required when a large breakdown voltage is not required between the source and the well. An example of the withstand voltage MIS structure will be described. That is, in the case of nMIS, in a circuit in which the p-type well is connected to a common GND (in the case of pMIS, the n-type well is common Vcc), the source potential is different from the p-type well potential. Since a reverse bias withstand voltage is required to secure a withstand voltage, the source side has the same structure as the drain side. That is, for example, in the case of nMIS, a reverse bias breakdown voltage of about -16.5 V is applied to the p-type well and about 1.5 V is applied to the source of the nMIS, so that the source side is defined as the drain side in order to ensure the breakdown voltage between the source and well. The structure is the same, and can withstand a voltage of 40 V or higher. At this time, the structure is such that the breakdown voltage between the source and well of the low breakdown voltage MIS can be about 10V. That is, the breakdown voltage between the source and well of the high breakdown voltage MIS is formed to be larger than the breakdown voltage between the source and well of the low breakdown voltage MIS. Examples of such a circuit include an output circuit and a booster circuit. However, in a circuit in which a potential difference does not occur between the source and well, a reverse bias withstand voltage is not required to ensure a withstand voltage between the source and well, so that only the drain side can have a high withstand voltage structure. With such a structure, the size of the MIS can be reduced, and the size of the semiconductor chip area can be reduced.

FIG. 10 is a plan view of an essential part of an example of the high breakdown voltage pMISQHp2, and FIG. 11 is a plan view of the same location as FIG. 10, and in particular, a p ⁻ type semiconductor region PV1 having an electric field relaxation function of the high breakdown voltage pMISQHp2 FIG. 12 is a plan view of the main part showing the positional relationship between the p ⁺ type semiconductor region P1s and the n ⁺ type semiconductor region NVk, and FIG. 12 is a plan view of the same location as FIG. 10, and particularly the gate electrode of the high breakdown voltage pMISQHp2 FIG. 13 is a plan view of the main part showing the positional relationship between HG, the active region L, and the n ⁺ type semiconductor region NVk. FIG. 13 is a plan view of the same location as FIG. FIG. 14 is a sectional view taken along line X3-X3 in FIGS. 10 to 13, and FIG. 15 is a sectional view taken along line X4-X4 in FIGS. 10 to 13 is the same as FIG. 7 which is a sectional view taken along the line Y1-Y1 shown in FIGS. Although FIG. 13 is a plan view, the separation region is hatched to make the drawing easy to see. In the second embodiment, the high breakdown voltage pMIS will be described as an example. However, as in the first embodiment, the present invention can also be applied to the high breakdown voltage nMIS.

In the high breakdown voltage pMIS (second, seventh, and eighth field effect transistors) QHp2 of the second embodiment, the p ⁺ -type semiconductor region P1d for drain is interposed between the channel region and the first embodiment. Similarly, the isolation part 3 is interposed, and the drain p ⁺ type semiconductor region P1d is electrically connected to the channel region of the active region L5 through the p ⁻ type semiconductor region PV1 having an electric field relaxation function. In addition, the isolation portion 3 is not interposed between the source p ⁺ type semiconductor region P1s and the channel region, and the source p ⁺ type semiconductor region P1s and the channel region form one active region L5. The p ⁻ type semiconductor regions PV1 arranged adjacent to each other and having an electric field relaxation function are electrically connected to each other without interposing them. The gate electrode HG is not formed so as to cover the entire surface of the active region L5. In the active region L5, a portion where the gate electrode HG overlaps in a plane (p ⁻ type semiconductor region having a drain-side electric field relaxation function). A channel region is formed in a portion excluding a portion where PV1 is disposed), and a p ⁺ type semiconductor region P1s for a source is disposed in a portion where the gate electrode HG does not overlap in a planar manner. In this structure, the supply potentials to the source p ⁺ type semiconductor region P1s and the deep n type well DNW are equal, that is, between the p ⁺ type semiconductor region P1s and the deep n type well DNW. The circuit configuration is such that no potential difference occurs between the two.

In the second embodiment as described above, it is not necessary to provide the separation portion 3 between the p ⁺ type semiconductor region P1s for the source and the channel region, and the electric field relaxation is provided on the p + type semiconductor region P1s side for the source. Since it is not necessary to provide the p ⁻ type semiconductor region PV1 having a function, the size of the high breakdown voltage pMISQHp2 can be reduced. As described above, in an actual semiconductor device, a plurality of high voltage MISs are integrated and arranged on the main surface of the substrate 1S. There are cases where 1000 outputs (1000 pieces) of a high withstand voltage MIS are arranged at a location corresponding to the output of the circuit. Therefore, even if the size of one high withstand voltage pMISQHp2 is small, a large size reduction can be realized as a whole, so that the size of the semiconductor chip having the high withstand voltage pMISQHp2 can be reduced.

In this configuration, the n ⁺ type semiconductor region NVk for preventing kinks may be brought into contact with the p ⁺ type semiconductor region P1s for source. As a result, it is possible to increase the alignment margin of the n ⁺ -type semiconductor region NVk for preventing kinks, and thus the arrangement thereof can be facilitated.

Similarly to the first embodiment described above, the n ⁺ -type semiconductor region NVk1 for countermeasure against kinks is arranged so as to straddle both the active region L1 and the isolation portion 3. The concentration of the n-type impurity in the n ⁺ -type semiconductor region NVk is set higher than the concentration of the n-type impurity in the n-type well DNW deep in the channel region. Further, the n ⁺ -type semiconductor region NVk1 is formed up to a position deeper than the isolation portion 3, and thereby the ability to further suppress or prevent the occurrence of the kink phenomenon can be enhanced.

(Embodiment 3)
In the third embodiment, an example of a method for manufacturing a semiconductor device having the high breakdown voltage MIS having the structure of the first and second embodiments and the low breakdown voltage MIS on the same substrate 1S will be described with reference to FIGS. 16 to 63, reference numeral HR1 is a formation region of the high breakdown voltage MIS having the structure of the first embodiment, reference numeral HR2 is a formation region of the high breakdown voltage MIS having the structure of the second embodiment, and reference numeral LR is a low breakdown voltage. Each of the MIS formation regions is shown. The cross sections of the high breakdown voltage MIS formation regions HR1 and HR2 are cross sectional views corresponding to the X-X1 line in FIG. 1 and the X3-X3 line in FIG.

First, as shown in the cross-sectional view of the main part of the substrate 1S in the same manufacturing process of FIGS. A thin insulating film 8 (see FIG. 19) made of, for example, silicon oxide is formed on the main surface of the substrate 1S by performing a thermal oxidation process on the circular wafer. Subsequently, after an insulating film 9 made of, for example, silicon nitride (Si ₃ N ₄ or the like) is deposited on the insulating film 8 by a CVD method or the like, a photoresist film (hereinafter simply referred to as a resist film) is further formed thereon. Through a series of photolithography (hereinafter simply referred to as lithography) processes such as coating, exposure, and development, a dry etching process is performed to form an overlapping pattern of the insulating films 8 and 9 in the active region formation region. . FIG. 19 shows an enlarged cross-sectional view of the main part of FIGS.

  Next, as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. 20 to 23, the groove 3a is formed on the main surface (device formation surface) of the substrate 1S using the insulating film 9 as an etching mask. At this stage, the shoulder formed by the side wall of the groove 3a and the main surface of the substrate 1S is angular. FIG. 23 shows an enlarged cross-sectional view of the main part of FIGS. Subsequently, as shown in the cross-sectional view of the main part of the substrate 1S in the same manufacturing process of FIGS. 24 to 27, the substrate 1S (ie, the wafer) is subjected to a dry oxidation process, so that the inner surface of the groove 3a, An insulating film 10 made of silicon oxide or the like is formed on the exposed surface of 1S. Thereby, the shoulder formed by the side wall of the groove 3a and the main surface of the substrate 1S is rounded.

  Next, as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. 28 to 30, an insulating film 3b made of, for example, silicon oxide is formed on the main surface of the substrate 1S (ie, wafer) by CVD or the like. After the deposition, this is polished by a chemical mechanical polishing (CMP) method or the like to remove the insulating film 3b outside the groove 3a, and the insulating film 3b is embedded only in the groove 3a to separate the separation portion 3 Form. Subsequently, the insulating film 9 is removed by hot phosphoric acid or the like, the underlying insulating film 8 is removed by a wet etching method, the main surface of the active region is exposed, and then the substrate 1S is subjected to thermal oxidation treatment. Thus, a thin insulating film made of, for example, silicon oxide is formed on the main surface of the active region. This thin insulating film becomes a through film during the ion implantation process.

  Next, for example, phosphorus is selectively ion-implanted into the deep n-type well formation region of the substrate 1S using the resist film as a mask, and then the resist film is removed. Subsequently, for example, boron (B) is selectively ion-implanted into the deep p-type well formation region and the separation p-type semiconductor region of the substrate 1S using another resist film as a mask, and then the resist film is removed. Thereafter, the phosphorus and boron introduced into the substrate 1S are subjected to a heat treatment on the substrate 1S (that is, the wafer) so that, for example, the substrate 1S diffuses to a depth of about 10 μm from the main surface of the substrate 1S. As shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIG. 33, the substrate 1S has a deep n-type well DNW, a deep p-type well (third, seventh, and eighth semiconductor regions) DPW and a separation p. A type semiconductor region PIS is formed.

Next, as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. 34 to 36, the pattern of the resist film PR1 is formed on the main surface of the substrate 1S by the lithography process. The pattern of the resist film PR1 is an n ⁻ type semiconductor region (second, ninth and tenth semiconductor regions) NV1 having an electric field relaxation function in the high breakdown voltage nMIS formation region and n for countermeasures against kinks in the high breakdown voltage pMIS formation region. Both of the formation regions of the ⁺ type semiconductor region NVk are exposed and the other regions are covered. Subsequently, for example, phosphorus is selectively introduced into the substrate 1S by using the pattern of the resist film PR1 as a mask by an ion implantation method or the like. At this time, the semiconductor region NV1 and the semiconductor region NVk are formed so as to be deeper than the isolation part 3. By forming the semiconductor region NV1 in this manner, the ability to suppress or prevent the occurrence of the kink phenomenon can be enhanced. At this stage, the n ⁻ type semiconductor region NV1 having an electric field relaxation function in the high breakdown voltage nMIS formation region and the n ⁺ type semiconductor region NVk for countermeasure against kinking in the high breakdown voltage pMIS formation region are introduced with impurities forming them. Although these regions are not completely formed at the stage of being performed, these regions are also illustrated for easy understanding.

Next, after removing the resist film PR1, the pattern of the resist film PR2 is formed on the main surface of the substrate 1S by the above-described lithography process as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. Form. The pattern of the resist film PR2 includes a p ⁻ type semiconductor region PV1 having an electric field relaxation function in the high breakdown voltage pMIS formation region and a p ⁺ type semiconductor region (fourth, thirteenth, The fourteenth semiconductor region (PVk) is formed so that both the formation regions are exposed and the other regions are covered. Subsequently, for example, boron is selectively introduced into the substrate 1S by using the pattern of the resist film PR2 as a mask by an ion implantation method or the like. At this time, similarly to the semiconductor region NV1 and the semiconductor region NVk, the semiconductor region PV1 and the semiconductor region PVk are formed so as to be deeper than the separation part 3, thereby improving the ability to suppress or prevent the occurrence of the kink phenomenon. it can. At this stage, the n ⁻ type semiconductor region NV1 having an electric field relaxation function in the high breakdown voltage nMIS formation region, the n ⁺ type semiconductor region NVk for countermeasures against kinking in the high breakdown voltage pMIS formation region, and the electric field in the high breakdown voltage pMIS formation region The p ⁻ type semiconductor region PV1 having a relaxation function and the p ⁺ type semiconductor region PVk for preventing kinks in the high breakdown voltage nMIS formation region are not completely formed, but in order to make the explanation easy to understand, The region is also illustrated.

Next, after removing the resist film PR2, the substrate 1S is stretched and subjected to a diffusion treatment (heat treatment), whereby a high breakdown voltage is obtained as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. An n ⁻ type semiconductor region NV1 having an electric field relaxation function in the nMIS formation region, a p ⁺ type semiconductor region PVk for preventing kinks in the high breakdown voltage nMIS formation region, and a p ⁻ type having an electric field relaxation function in the high breakdown voltage pMIS formation region. An n ⁺ -type semiconductor region NVk is formed as a countermeasure against kinks in the semiconductor region PV1 and the high breakdown voltage pMIS formation region. As described above, in the third embodiment, the p ⁺ -type semiconductor region PVk and the n ⁺ -type semiconductor region NVk for preventing kinks are used as the p ⁻ -type semiconductor region PV1 and the n ⁻ -type semiconductor region having an electric field relaxation function. Since it is formed in the same formation process as NV1, the provision of the p ⁺ type semiconductor region PVk and the n ⁺ type semiconductor region NVk for preventing kinks does not increase the number of manufacturing steps. Therefore, a semiconductor device with high performance and reliability can be provided without increasing the manufacturing time and cost of the semiconductor device. Thereafter, the threshold voltage of each high breakdown voltage MIS may be adjusted by implanting a shallow channel into the channel region of the high breakdown voltage MIS. Thereafter, the insulating film for the through film at the time of ion implantation is removed by wet etching. After that, by subjecting the substrate 1S to thermal oxidation treatment, an insulating film made of silicon oxide or the like having a thickness of, for example, about 10 nm in terms of silicon dioxide equivalent thickness is formed on the main surface (main surface of the active region) of the substrate 1S. 6a (in the third embodiment, illustration is omitted for easy understanding of the drawing). At this time, if the required gate withstand voltage is low, it is possible to form the gate insulating film only by the silicon oxide film formed by this thermal oxidation method, but a high voltage similar to that of the drain is applied to the gate electrode. In this case, the insulating film 6b made of silicon oxide or the like formed by the CVD method or the like is deposited on the silicon oxide film by the thermal oxidation method, and the silicon oxide film by the thermal oxidation method and the silicon oxide film by the CVD method are formed. A gate insulating film 6 is formed by a laminated film. Here, a case where the gate insulating film 6 is formed of the laminated film is shown. As a result, a high breakdown voltage MIS and a low breakdown voltage MIS with significantly different gate insulating film thicknesses can coexist on the same substrate 1S. Further, the insulating film 6b formed by such a CVD method is formed not only on the active region but also on the isolation portion 3. By depositing the insulating film 6b by the CVD method, the amount by which the upper portion of the separation portion 3 is etched in a later process can be reduced, so that the breakdown voltage of the separation portion 3 can be secured, and the generation of parasitic MIS is suppressed or prevented. it can. Therefore, the reliability of the semiconductor device can be improved.

Next, in the insulating film 6b of the gate insulating film 6 formed by the CVD method, an n ⁺ type semiconductor region or a p ⁺ type semiconductor that has an ohmic contact in the low breakdown voltage MIS formation region and the high breakdown voltage MIS formation region. Unnecessary portions such as portions where regions are formed are selectively removed through the lithography process and the wet etching process. In this etching process, the insulating film 6b formed by the CVD method for forming the gate insulating film has a higher etching rate than the thermal oxide film (insulating film 6a). When etching proceeds and the thermal oxide film (insulating film 6a) under the insulating film 6b is exposed by the CVD method, the etching rate is remarkably slowed, so that the film thickness of the insulating film 3b in the separation portion 3 is prevented from being reduced. it can. Therefore, the isolation part 3 that is not covered with the resist film, such as the formation region of the low breakdown voltage MIS, only needs to return to the state before the insulating film 6b by the CVD method for the gate insulating film 6 is deposited. That is, in the case where the high breakdown voltage MIS and the low breakdown voltage MIS are formed on the same substrate 1S, the thickness of the separation portion 3 in the low breakdown voltage MIS formation region can be secured, so that adverse effects on the low breakdown voltage MIS can be avoided. Therefore, the reliability of the semiconductor device having the high breakdown voltage MIS and the low breakdown voltage MIS on the same substrate 1S can be improved. Subsequently, by passing through a densification step (heat treatment step), the insulating film 6b formed by the above-described CVD method can trap traps such as electrons, holes, etc., and moisture contained in the film (film composition). Depending on the reaction, the water generated by the reaction also decreases, so that the film is almost the same as the thermal oxide film. Thereafter, a light thermal oxidation process is performed on the substrate 1S.

  Next, a conductive film made of, for example, low-resistance polycrystalline silicon is deposited on the main surface of the substrate 1S (ie, wafer) by the CVD method, the surface is oxidized, and an insulating film made of silicon nitride or the like is then formed thereon. And an insulating film is formed by oxidizing the surface. Subsequently, the laminated film of the conductor film and the insulating film is patterned through the lithography process and the dry etching process, as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. Then, a laminated pattern of the conductor film 13 and the insulating film 14 is formed. The laminated pattern of the conductor film 13 and the insulating film 14 is formed so as to cover the high breakdown voltage MIS formation regions HR1 and HR2 and not the low breakdown voltage MIS formation region LR. This conductor film 13 is a conductor film for forming a gate electrode of a high breakdown voltage MIS. The reason for not patterning each high breakdown voltage MIS as a gate electrode at this stage is to avoid a problem that occurs particularly in the formation region HR2 of the high breakdown voltage MIS when the gate electrode of the low breakdown voltage MIS is formed. This will be described in the process of forming the low breakdown voltage MIS gate electrode.

Next, using the resist film pattern formed in the lithography process as a mask, for example, boron is introduced into the substrate 1S by an ion implantation method or the like, whereby the cross-section of the main part of the substrate 1S in the same manufacturing process of FIGS. As shown in FIG. 2, the p ⁺ type well PW1 in the high breakdown voltage nMIS formation region and the p ⁺ type well PW2 in the low breakdown voltage MIS are formed. Here, on the high breakdown voltage pMIS side, the boron is introduced into the substrate 1S through the conductor film 13. Subsequently, after removing the resist film for forming the p ⁺ -type wells PW1 and PW2, another resist film pattern is formed on the main surface of the substrate 1S by the lithography process, and the resist film pattern is further masked. As an example, phosphorus is introduced into the substrate 1S by ion implantation or the like, thereby forming the n ⁺ type well NW1 in the high breakdown voltage pMIS formation region and the n ⁺ type well NW2 in the low breakdown voltage pMIS formation region. Here, on the high breakdown voltage nMIS side, the phosphorus is introduced into the substrate 1S through the conductor film 13. Thereafter, after removing the resist film, the substrate 1S is heat-treated to activate the p ⁺ type wells PW1 and PW2 and the n ⁺ type wells NW1 and NW2. As described above, in the third embodiment, the formation process of the high breakdown voltage MIS well and the low breakdown voltage MIS well is performed in the same process, so that the high breakdown voltage MIS well and the low breakdown voltage MIS well are formed in different resist films. Compared to the case of forming as a mask, a series of lithography processes such as resist coating, exposure and development can be reduced, so that the manufacturing process of a semiconductor device having a high breakdown voltage MIS and a low breakdown voltage MIS on the same substrate 1S can be reduced. A significant increase can be avoided. The high breakdown voltage MIS and the low breakdown voltage MIS can coexist.

  Next, after the silicon oxide film in the low breakdown voltage MIS formation region LR is removed by a wet etching method or the like, a thermal oxidation process is performed to form the low breakdown voltage MIS gate insulating film 15 in the low breakdown voltage MIS formation region. . The gate insulating film 15 is made of, for example, silicon oxide, and the thickness thereof is a silicon dioxide equivalent film thickness, for example, about 7 nm. Thereafter, for example, a polycrystalline silicon film 16 is deposited on the main surface of the substrate 1S (ie, wafer) by the CVD method or the like. At this time, the polycrystalline silicon film 16 is also deposited on the surface of the laminated pattern of the conductor film 13 and the insulating film 14 in the high breakdown voltage MIS formation region. Thereafter, in the polycrystalline silicon film 16, for example, phosphorus is introduced into the nMIS formation region, and boron is introduced into the pMIS formation region, for example, by using a resist film pattern as a mask. By patterning the silicon film 16 through the lithography process and the dry etching process, as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. 49 to 51, the gate electrode LG (16 ). The gate electrode LG of the low breakdown voltage nMIS is n-type, and the gate electrode LG of the low breakdown voltage pMIS is p-type. In this etching step, the polycrystalline silicon film 16 deposited on the surface of the laminated pattern of the conductor film 13 and the insulating film 14 in the high breakdown voltage MIS formation region is also removed. The reason why the high breakdown voltage MIS gate electrode is not formed as described above is, for example, for the following reason. That is, if the gate electrode of the high withstand voltage MIS is formed before the patterning process of the gate electrode LG of the low withstand voltage MIS, when the gate electrode LG of the low withstand voltage MIS is patterned, the high withstand voltage MIS already formed is patterned. In some cases, the polycrystalline silicon film 16 for forming the gate electrode LG of the low withstand voltage MIS remains on the side wall of the gate electrode. In the high breakdown voltage MIS formation region HR1, even if the polycrystalline silicon film 16 is left on the side surface of the gate electrode, there is no particular problem because there is a thick isolation portion 3 below, but in the high breakdown voltage MIS formation region HR2, The isolation part 3 is not disposed on one side surface of the gate electrode, and only the gate insulating film 6 is provided below the isolation part 3. Therefore, if the polycrystalline silicon film 16 is left on one side of the gate electrode of the high breakdown voltage MIS formation region HR, the source semiconductor region is formed when the high breakdown voltage MIS source semiconductor region is formed. Since there is an etching residue of the polycrystalline silicon film 16, there arises a problem that the polycrystalline silicon film 16 is separated from the side surface of the gate electrode of the high breakdown voltage MIS. In order to avoid such a problem, in the third embodiment, the high breakdown voltage MIS gate electrode is not patterned before the low breakdown voltage MIS gate electrode LG is patterned.

Next, the conductor film 13, the insulating film 14, and the gate insulating film 6 are patterned by the CVD method through the lithography process and the dry etching process, whereby the substrate 1S in the same manufacturing process of FIGS. As shown in the main section, the gate electrode HG (13) is formed in the high breakdown voltage MIS formation regions HR1 and HR2. The insulating film 6b of the gate insulating film 6 formed by the CVD method protrudes from the entire outer periphery of the gate electrode HG in the high breakdown voltage MIS formation region HR1, and the source side edge of the gate electrode HG in the high breakdown voltage MIS formation region HR2. It is formed so as to protrude from the outer periphery excluding. Subsequently, by introducing, for example, boron into the main surface of the substrate 1S by an ion implantation method or the like, the p ⁻ type semiconductor region 18 serving as an extension portion for the high breakdown voltage pMIS is formed in the gate electrode HG in the formation region HR2 of the high breakdown voltage MIS. In a self-aligned manner. Subsequently, after forming a resist film pattern on the main surface of the substrate 1S through the above lithography process, using this as a mask, for example, phosphorus is introduced into the main surface of the substrate 1S by an ion implantation method or the like. In the formation region HR2, an n ⁻ type semiconductor region 19 serving as an extension portion for a high breakdown voltage nMIS is formed in a self-aligned manner with respect to the gate electrode HG. Subsequently, after removing the resist film, a resist film pattern is formed on the main surface of the substrate 1S through the lithography process, and boron, for example, is introduced into the main surface of the substrate 1S by an ion implantation method or the like. Thus, the p ⁻ type semiconductor region 20 serving as an extension portion for the low breakdown voltage pMIS is formed in the low breakdown voltage MIS formation region LR in a self-aligned manner with respect to the gate electrode LG. At this time, phosphorus may be introduced by ion implantation or the like to form an n-type semiconductor region (halo region) for the punch-through stopper of the low breakdown voltage pMIS under the p ⁻ -type semiconductor region 20. . Thereafter, after removing the resist film, the substrate 1S is subjected to heat treatment. Subsequently, a resist film pattern is formed on the main surface of the substrate 1S through the lithography process described above, and using this as a mask, for example, phosphorus is introduced into the main surface of the substrate 1S by an ion implantation method or the like, thereby reducing the low withstand voltage MIS. In the formation region LR, an n ⁻ type semiconductor region 21 serving as an extension portion for a low breakdown voltage nMIS is formed in a self-aligned manner with respect to the gate electrode LG. At this time, boron may be introduced by ion implantation or the like to form a p-type semiconductor region (halo region) for a punch-through stopper for a low breakdown voltage nMIS under the n ⁻ -type semiconductor region 20. .

Next, after an insulating film made of, for example, silicon oxide is deposited on the main surface of the substrate 1S (ie, the wafer) by a CVD method or the like, this is etched back by anisotropic dry etching, whereby FIGS. As shown in the cross section of the main part of the substrate 1S in the same manufacturing process 60, sidewalls 5 made of, for example, silicon oxide are formed on the side surfaces of the gate electrodes HG and LG. At this time, the insulating film 14 on the gate electrode HG is also removed. Subsequently, after forming a pattern of the resist film through the lithography process on the main surface of the substrate 1S, using this as a mask, for example, phosphorus into the main surface of the substrate 1S by introducing by ion implantation or the like, n ⁺ -type The semiconductor regions N1, N2, and N3 are formed. The n ⁺ type semiconductor region N1 is a lead region of the n ⁺ type well NW1. The n ⁺ type semiconductor regions (first, eleventh and twelfth semiconductor regions) N2 are semiconductor regions for the sources and drains of the high breakdown voltage nMISQHn1 and QHn2. The n ⁺ -type semiconductor region N3 is a semiconductor region for the source and drain of the low breakdown voltage nMISQLn1. Subsequently, after removing the resist film, a resist film pattern is formed on the main surface of the substrate 1S through the lithography process, and boron, for example, is introduced into the main surface of the substrate 1S by an ion implantation method or the like. Thus, p ⁺ type semiconductor regions P1, P2, and P3 are formed. The p ⁺ type semiconductor region P1 is a semiconductor region for the source and drain of the high breakdown voltage pMISQHp1 and QHp2. The p ⁺ type semiconductor region P2 is a lead region of the p ⁺ type well PW1. The p ⁺ type semiconductor region P3 is a semiconductor region for the source and drain of the low breakdown voltage pMISQLp1. Thereafter, heat treatment is performed on the substrate 1S to activate the n ⁺ type semiconductor regions N1, N2, and N3 and the p ⁺ type semiconductor regions P1, P2, and P3. In this way, on the same substrate 1S, high breakdown voltage nMIS (fifth high breakdown voltage field effect transistor) QHn1, high breakdown voltage nMIS (seventh high breakdown voltage field effect transistor) QHn2, high breakdown voltage pMIS (sixth high breakdown voltage field effect transistor) QHp1, high breakdown voltage pMIS (eighth high breakdown voltage field effect transistor) QHp2, low breakdown voltage nMISQLn1, and low breakdown voltage pMISQLp1 are formed. Here, a case where the semiconductor regions for the source and drain of the low breakdown voltage nMISQLn1 and the low breakdown voltage pMISQLp1 have an LDD (Lightly Doped Drain) configuration is illustrated. The operating voltages of the low breakdown voltage nMISQLn1 and the low breakdown voltage pMISQLp1 are lower than the high breakdown voltage nMISQHp1, QHp2, QHn1, QHn2, the power supply voltage on the reference potential side is, for example, 0V, and the power supply voltage on the high potential side is, for example, 1.5V Degree.

Next, a light etching process is performed on the main surface of the substrate 1S to expose the main surface (main surface of the active region) of the substrate 1S and the upper surfaces of the gate electrodes HG and LG, and then, as shown in FIGS. As shown in the cross section of the main part of the substrate 1S in the same manufacturing process, a silicide layer 2 such as cobalt silicide is formed on the n ⁺ type semiconductor regions N1, N2, N3 and p ⁺ by a salicide (Self Align Silicide) process. It is formed in a self-aligned manner on the upper surfaces of the type semiconductor regions P1, P2, P3 and the gate electrodes HG, LG. The salicide process is performed as follows, for example. First, after the light etching process, a metal film such as cobalt (Co) is deposited on the main surface of the substrate 1S by a sputtering method or the like. Subsequently, by subjecting the substrate 1S to a heat treatment of, for example, several tens of seconds in a temperature range of 400 to 550 ° C., the cobalt of the metal film reacts with the silicon of the substrate 1S and the gate electrodes HG and LG, A silicide layer formed of a mixed crystal of cobalt and silicon is formed at a contact portion between the metal film, the substrate 1S, and the gate electrodes HG and LG. Thereafter, only unreacted cobalt is selectively wet etched using an aqueous solution such as ammonia peroxide water. At this time, the silicide layer remains without being etched. Thereafter, the substrate 1S is subjected to a heat treatment of, for example, about 800 ° C. for about 90 seconds to change the phase of the mixed crystal of cobalt and silicon into CoSi ₂ to reduce the resistance. In this way, the silicide layer 2 is formed in a self-aligned manner. The metal film is not limited to cobalt and can be variously changed. For example, titanium (Ti), platinum (Pt), nickel (Ni), or tungsten (W) may be used. When titanium is selected as the metal film, the silicide layer 2 is titanium silicide (TiSi ₂ ), and when platinum is selected as the metal film, the silicide layer 2 is platinum silicide (PtSi ₂ ) and nickel is used as the metal film. When selected, the silicide layer 2 is nickel silicide (NiSi ₂ ), and when tungsten is selected as the metal film, the silicide layer 2 is tungsten silicide (WSi ₂ ).

  Thereafter, a normal metal wiring forming process of the semiconductor device is performed. That is, a wiring layer that requires an interlayer insulating film deposition process, an interlayer insulating film flattening process, a contact hole or through hole forming process, a plug forming process, a wiring metal deposition process, a wiring metal patterning process, etc. It repeats according to number, and passes through the formation process of a protective film, and a pad opening part formation process after that. Thereafter, through an inspection process and a wafer dicing process, the wafer is divided into individual semiconductor chips, and a semiconductor device having both a high breakdown voltage MIS and a low breakdown voltage MIS is manufactured on the same substrate 1S.

  Thus, according to the third embodiment, in addition to the effects obtained in the first and second embodiments, the following effects can be obtained.

  That is, the low breakdown voltage MIS and the high breakdown voltage MIS can be formed on the same substrate 1S. In addition, a semiconductor device having the low breakdown voltage MIS and the high breakdown voltage MIS on the same substrate 1S can be manufactured without causing a significant increase in the manufacturing process. In other words, the manufacturing process can be reduced by sharing the low withstand voltage MIS manufacturing process and the high withstand voltage MIS manufacturing process in the manufacturing process, and the manufacturing process of the semiconductor device having the low withstand voltage MIS and the high withstand voltage MIS on the same substrate 1S. Can be reduced.

(Embodiment 4)
In the fourth embodiment, a modified example of the high breakdown voltage MIS will be described. FIG. 64 is a plan view of the main part of an example of the high breakdown voltage pMISQHp3, and FIG. 65 is a plan view of the same location as FIG. 64. FIG. 66 is a plan view of the main part showing the arrangement relationship with DR, FIG. 66 is a plan view of the same part as FIG. FIG. 68 is a plan view of the main part showing the state of the semiconductor region in the active region L, FIG. 68 is a cross-sectional view taken along line X5-X5 of FIGS. 64-67, and FIG. 67 is a cross-sectional view taken along line X6-X6 in FIG. 67, and FIG. 70 is a cross-sectional view taken along line Y4-Y4 in FIGS. Here, the case where the present invention is applied to the high breakdown voltage pMIS will be described here, but the present invention can also be applied to the high breakdown voltage nMIS by reversing the conductivity types of p and n. Same as 1. 66 and 67 are plan views, but hatching is given to each semiconductor region for easy viewing of the drawings.

The high breakdown voltage pMIS (third, ninth, and tenth high breakdown voltage field effect transistors) QHp3 of the semiconductor device of the fourth embodiment has a structure capable of realizing a breakdown voltage of 60V, for example. The power supply voltage on the high potential side is, for example, about 37 V, and the power supply voltage on the low potential (reference potential) side is, for example, 0 (zero) V. In this high breakdown voltage pMISQHp3, n ⁺ type semiconductor regions (fifth, fifteenth and seventeenth semiconductor regions) including a channel region (active region L1) in the element region other than the p ⁻ type semiconductor region PV1 having an electric field relaxation function. ) NV1p is formed. The n ⁺ type semiconductor region NV1p forms an n type well having a high breakdown voltage pMISQHp3. The threshold voltage of the high breakdown voltage pMISQHp3 is mainly determined by the impurity concentration of the n-type well in the channel region (the sum of impurity concentrations of the n ⁻ -type semiconductor region NV1 and the deep n-type well DNW, ie, n ⁺ -type). The impurity concentration of the semiconductor region NV1p), the concentration of the counter-doping impurity (for example, boron) introduced into the channel region of the substrate 1S, and the thickness of the gate insulating film 6 are determined. The counter-doped region DR indicates a region into which the counter-doping impurity is introduced. In the fourth embodiment, the impurity for counter-doping is the substrate 1S at both ends in the second direction Y of the active region L1 (that is, the boundary between the active region L1 and the separation portion 3 and the side wall of the separation portion 3 is in contact). It is not introduced into (part), but is introduced into the active region L1 sandwiched between them. As a result, the region where the counter-doping impurity is not introduced is the n + type semiconductor region NV1p, whereas the region into which the counter-doping impurity is introduced (the electric field relaxation function of the active region L1 is provided). The n ⁻ type semiconductor regions (sixth, sixteenth, and eighteenth semiconductor regions) NV1m are excluding the regions where the p ⁻ type semiconductor regions PV1 and PV1 are disposed. That is, the n ⁻ type semiconductor region NV1m becomes an effective channel region of the high breakdown voltage pMISQHp3. The n ⁻ type semiconductor region NV1m is formed near the surface of the semiconductor substrate, and is formed on the n ⁺ type semiconductor region NV1p. That is, the n ⁻ type semiconductor region NV1m is formed at a shallower position than the n ⁺ type semiconductor region NV1p. As a result, the threshold voltage at the center of the channel region of the active region L1 (the main surface portion of the substrate 1S) is changed at both ends in the second direction Y of the active region L1 (the portion of the substrate 1S in contact with the side wall of the separation portion 3). The threshold voltage can be lowered. That is, the MIS easily operates at the center of the channel region, but the MIS hardly operates at both ends in the second direction Y of the channel region. For this reason, even if the upper surface of the separation part 3 is depressed, the occurrence of the kink phenomenon can be suppressed or prevented (the threshold voltage is the same as that described in the first embodiment).

Here, as shown in FIG. 70, in the width direction (second direction Y) of the gate electrode in the active region L1, the length of the n ⁻ type semiconductor region NV1m forming the channel region under the gate electrode HG and n ⁺ The type semiconductor region NV1p is formed such that the length of the n ⁻ type semiconductor region NV1m is longer. That is, the semiconductor region NV1m in the low concentration region is formed so as to occupy more than half of the channel region. As a result, it is possible to reduce the MIS regions that are difficult to operate formed at both ends of the channel region in the second direction Y. Therefore, the effective operating speed of the high breakdown voltage MIS (for example, the high breakdown voltage pMISQHp3) in the present embodiment. Can be prevented.

  At this time, in the gate width direction of the gate electrode HG, the relatively low concentration semiconductor region NV1m is surrounded by the relatively high concentration semiconductor region NV1p, and the high concentration semiconductor region NV1p is the main surface of the substrate 1S. To a position deeper than the low concentration semiconductor region NV1m.

The n ⁺ type semiconductor region NVp1 is formed deeper than the isolation portion 3. By forming the semiconductor region NVp1 in this manner, the threshold value at the shoulder portion of the substrate 1S in contact with the upper portion of the separation portion 3 can be increased. Thereby, generation | occurrence | production of a kink phenomenon can be suppressed.

Further, in the high breakdown voltage pMISQHp3 of the fourth embodiment, when viewed in cross section, the n ⁺ type semiconductor region NV1p is arranged under the n ⁻ type semiconductor region NV1m where the channel is formed. Thereby, the ability to suppress or prevent punch-through between the p ⁺ type semiconductor regions P1 and P1 (p ⁻ type semiconductor regions PV1 and PV1) for the source and drain can be improved. That is, it is possible to suppress an effective channel length reduction during the operation of the high breakdown voltage pMISQHp3. For this reason, the designed channel length (length in the first direction X) of the high breakdown voltage pMISQHp3 can be shortened. The counter-doped region DR has a large pattern and the left and right regions are p-type semiconductor regions PV1 and PV1 having the same conductivity type as the counter-doping impurities are formed. There is no problem, and the alignment margin can be made larger than in the case of the first embodiment. That is, this counter-doping technique can sufficiently cope with a reduction in the size of the high breakdown voltage pMISQHp3. Accordingly, in the fourth embodiment, the size of the high breakdown voltage pMISQHp3 can be reduced as compared with the case of the first embodiment. Therefore, the size of the semiconductor chip having the high breakdown voltage pMISQHp3 of the fourth embodiment can be reduced.

Next, FIG. 71 shows an example of a plan view of the main part when a plurality of high breakdown voltage pMISQHp3 are arranged. The high breakdown voltage pMISQHp3 is disposed adjacent to each other in a state where the direction of each channel (the direction in which the current flows) is along the first direction X. The high breakdown voltage pMISQHp3 adjacent to each other is arranged to share the p ⁺ type semiconductor regions P1 and P2 for the source and drain. The n ⁺ -type semiconductor region N1 and the n-type well NW1 are arranged so as to surround a group of the plurality of high breakdown voltage pMISQHp3. Therefore, even if the size reduction amount of each high withstand voltage pMISQHp3 is small, the overall size can be reduced, so that the size of the semiconductor chip having the high withstand voltage pMISQHp3 can be greatly reduced.

(Embodiment 5)
In the fifth embodiment, an example of a high withstand voltage MIS structure in the case where a large withstand voltage is not required between the source and well will be described as a modification of the high withstand voltage MIS of the fourth embodiment.

  72 is a plan view of an essential part of an example of the high breakdown voltage pMISQHp4, and FIG. 73 is a plan view of the same location as FIG. 72. FIG. 74 is a plan view of the main part showing the arrangement relationship with DR, FIG. 74 is a plan view of the same part as FIG. 72, and particularly shows a plan view of the main part showing the state of each semiconductor region of the high breakdown voltage pMISQHp4. FIG. 76 is a cross-sectional view taken along the line X7-X7 in FIGS. 72 to 75, and FIG. 77 is a plan view of the same portion of FIG. 75 is a sectional view taken along line X8-X8. 72 to 75, the sectional view taken along the line Y5-Y5 is the same as FIG. 74 and 75 are plan views, but hatching is given to the separation region for easy viewing of the drawings. In the fifth embodiment, the high breakdown voltage pMIS will be described as an example, but the present invention can also be applied to the high breakdown voltage nMIS as in the first to fourth embodiments.

The high breakdown voltage pMIS (fourth, eleventh and twelfth high breakdown voltage field effect transistors) QHp4 of the semiconductor device of the fifth embodiment has a structure capable of realizing a breakdown voltage of 60V, for example. The power supply voltage on the high potential side is, for example, about 37 V, and the power supply voltage on the low potential (reference potential) side is, for example, 0 (zero) V. In the fifth embodiment, the countermeasure against kinks is the same as that in the fourth embodiment, and the description thereof is omitted. The difference from the fourth embodiment is as follows. That is, in the fifth embodiment, the isolation portion 3 is interposed between the p ⁺ type semiconductor region P1d for drain and the channel region, as in the fourth embodiment, and the p ⁺ type semiconductor for drain is provided. The region P1d is electrically connected to the channel region of the active region L5 through the p ⁻ type semiconductor region PV1 having an electric field relaxation function, whereas the p ⁺ type semiconductor region P1s for the source and the channel region are electrically connected. No p ^- type semiconductor having an electric field relaxation function in which no isolation portion 3 is interposed between the source p ⁺ -type semiconductor region P1s and the channel region adjacent to each other in one active region L5. They are electrically connected to each other without interposing the region PV1. The gate electrode HG is not formed so as to cover the entire surface of the active region L5. In the active region L5, a portion where the gate electrode HG overlaps in a plane (p ⁻ type semiconductor region having a drain-side electric field relaxation function). A channel region is formed in a portion excluding a portion where PV1 is disposed), and a p ⁺ type semiconductor region P1s for a source is disposed in a portion where the gate electrode HG does not overlap in a planar manner. However, in the fifth embodiment, as in the fourth embodiment, the regions at both ends in the second direction Y of the active region L5 into which no impurity for counter-doping is introduced in the active region L5 are n ⁺ type semiconductors. On the other hand, the region into which the impurity for counter-doping is introduced (except for the region where the p ⁻ type semiconductor regions PV1 and PV1 having the electric field relaxation function are arranged) is an n ⁻ type semiconductor region NV1m. Has been. The n ⁻ type semiconductor region NV1m is formed in the vicinity of the surface of the substrate 1S, and is formed above the n ⁺ type semiconductor region NV1p. That is, the n ⁻ type semiconductor region NV1m is formed at a shallower position than the n ⁺ type semiconductor region NV1p. Therefore, even in the active region L5 where the gate electrode HG overlaps in a plane, the threshold voltage at the center of the channel region of the active region L5 (the main surface portion of the substrate 1S) is set in the second direction of the active region L5. Since it can be made lower than the threshold voltage at both ends of Y (part of the substrate 1S in contact with the side wall of the separation portion 3), the occurrence of the kink phenomenon can be suppressed or prevented as in the fourth embodiment. (The threshold voltage is the same as that described in the first embodiment).

Here, as in the above-described fourth embodiment, as shown in FIG. 70, n ⁻ that forms a channel region under the gate electrode HG in the width direction (second direction Y) of the gate electrode in the active region L5. The length of the n-type semiconductor region NV1m and the length of the n ⁺ -type semiconductor region NV1p are formed so that the length of the n ⁻ -type semiconductor region NV1m is longer. That is, the n ⁻ type semiconductor region NV1m is formed to occupy more than half of the channel region. As a result, it is possible to reduce the MIS regions that are difficult to operate formed at both ends of the channel region in the second direction Y. Therefore, the effective operating speed of the high breakdown voltage MIS (for example, the high breakdown voltage pMISQHp3) in the present embodiment. Can be prevented.

  At this time, in the gate width direction of the gate electrode HG, the relatively low concentration semiconductor region NV1m is surrounded by the relatively high concentration semiconductor region NV1p, and the high concentration semiconductor region NV1p is the main surface of the substrate 1S. To a position deeper than the low concentration semiconductor region NV1m.

The n ⁺ type semiconductor region NVp1 is formed deeper than the isolation portion 3. By forming the semiconductor region NVp1 in this manner, the threshold value at the shoulder portion of the substrate 1S in contact with the upper portion of the separation portion 3 can be increased. Thereby, generation | occurrence | production of a kink phenomenon can be suppressed.

In the structure of the fifth embodiment, the supply potentials to the source p ⁺ type semiconductor region P1s, the deep n type well DNW, the n ⁺ type semiconductor region NV1p, and the n ⁻ type semiconductor region NV1m are equal. In other words, the circuit configuration is such that no potential difference occurs between the p ⁺ type semiconductor region P1s for source, the deep n type well DNW, the n ⁺ type semiconductor region NV1p, and the n ⁻ type semiconductor region NV1m. The

  In the fifth embodiment, the size of the high breakdown voltage pMISQHp4 can be reduced for the same reason as described in the second embodiment. In particular, in the fifth embodiment, as described in the fourth embodiment, since the ability to suppress or prevent punch through can be improved, the size of the high breakdown voltage pMISQHp4 can be further reduced as compared with the second embodiment. Can do. Therefore, the size of the semiconductor chip having the high breakdown voltage pMISQHp4 of the fifth embodiment can be further reduced as compared with the second embodiment.

(Embodiment 6)
In the sixth embodiment, an example of a method of manufacturing a semiconductor device having the high breakdown voltage MIS and the low breakdown voltage MIS having the structures of the fourth and fifth embodiments on the same substrate 1S will be described with reference to FIGS. 78 to 101, reference numeral HR3 denotes a high breakdown voltage MIS formation region (X5-X5) having the structure of the fourth embodiment, and reference numeral HR4 denotes a high breakdown voltage MIS formation region (the structure of the fifth embodiment). X7-X7) and symbol LR indicate regions where the low breakdown voltage MIS is formed.

First, after going through the same steps as described in FIGS. 16 to 33 of the third embodiment, the main part of the substrate 1S is shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. A pattern of the resist film PR3 is formed on the surface by the lithography process. In the pattern of the resist film PR3, the formation regions of both the n ⁻ type semiconductor region having the electric field relaxation function of the high breakdown voltage nMIS formation region and the n ⁺ type semiconductor region of the high breakdown voltage pMIS formation region are exposed. Is formed to be covered. Subsequently, for example, phosphorus is selectively introduced into the substrate 1S by using the pattern of the resist film PR3 as a mask by an ion implantation method or the like. Accordingly, since the deep p-type well DPW is formed in the high breakdown voltage nMIS formation region, the n ⁻ type semiconductor region NV1 is formed, and in the high breakdown voltage pMIS formation region, the deep n-type well DNW is formed. Therefore, the n ⁺ type semiconductor region NV1p is formed. At this time, the semiconductor region NV1 and the semiconductor region NV1p are formed to be deeper than the isolation part 3. By forming the semiconductor region NV1p in this way, the ability to suppress or prevent the occurrence of the kink phenomenon can be enhanced. At this stage, the n ⁻ type semiconductor region NV1 having the electric field relaxation function of the high breakdown voltage nMIS formation region and the n ⁺ type semiconductor region NV1p of the high breakdown voltage pMIS formation region are at the stage where impurities forming them are introduced. Although these regions are not completely formed, these regions are also shown for ease of explanation.

Next, after removing the resist film PR3, the pattern of the resist film PR4 is formed on the main surface of the substrate 1S by the lithography process as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. Form. In the pattern of the resist film PR4, both the p ⁻ type semiconductor region having the electric field relaxation function of the high breakdown voltage pMIS formation region and the p ⁺ type semiconductor region of the high breakdown voltage nMIS formation region are exposed. Is formed to be covered. Subsequently, for example, boron is selectively introduced into the substrate 1S by using the pattern of the resist film PR4 as a mask by an ion implantation method or the like. Thus, since the deep n-type well DNW is formed in the high breakdown voltage pMIS formation region, the p ⁻ type semiconductor region PV1 is formed, and in the high breakdown voltage nMIS formation region, the deep p-type well DPW is formed. Therefore, the p ⁺ type semiconductor region (fifth, fifteenth, and seventeenth semiconductor regions) PV1p is formed. At this time, the semiconductor region PV1 and the semiconductor region PV1p are formed so as to be deeper than the separation part 3. By forming the semiconductor region NV1p in this way, the ability to suppress or prevent the occurrence of the kink phenomenon can be enhanced. At this stage, the n ⁻ type semiconductor region NV1 having an electric field relaxation function in the high breakdown voltage nMIS formation region, the n ⁺ type semiconductor region NV1p in the high breakdown voltage pMIS formation region, and the electric field relaxation function in the high breakdown voltage pMIS formation region are provided. The p ⁻ type semiconductor region PV1 and the p ⁺ type semiconductor region PV1p of the high breakdown voltage nMIS formation region are not completely formed, but these regions are also illustrated for easy understanding.

Next, after removing the resist film PR4, the substrate 1S is stretched and subjected to a diffusion process (heat treatment), whereby a high breakdown voltage is obtained as shown in the cross section of the main part of the substrate 1S in the same manufacturing process of FIGS. n having an electric field relaxing function of nMIS formation region ^- -type semiconductor regions PV1 and ^- -type semiconductor regions NV1, high breakdown voltage nMIS formation region of the ^{p +} -type semiconductor region PV1p, p having an electric field relaxing function of the high breakdown voltage pMIS formation region The n ⁺ type semiconductor region NV1p in the high breakdown voltage pMIS formation region is formed in a state where it is extended to a position deeper than the isolation portion 3 and shallower than the deep n-type well DNW and the deep p-type well DPW. Thus, in the sixth embodiment, the p ⁺ type semiconductor region PV1p and the n ⁺ type semiconductor region NV1p are formed in the same manner as the p ⁻ type semiconductor region PV1 and the n ⁻ type semiconductor region NV1 having the electric field relaxation function. Since the p ⁺ type semiconductor region PV1p and the n ⁺ type semiconductor region NV1p are formed, the number of manufacturing steps of the semiconductor device is not increased. Therefore, a semiconductor device having high performance and reliability can be provided without significantly increasing the manufacturing time and cost of the semiconductor device.

  Next, the process proceeds to a counter dope process. 87 to 92 are fragmentary cross-sectional views of the substrate 1S during the counter-doping process for the high breakdown voltage nMIS formation region. 87 is a cross-sectional view including a portion corresponding to the line X5-X5 in FIGS. 64-67, FIG. 88 is a cross-sectional view including a portion corresponding to the line X6-X6 in FIGS. 64-67, and FIG. 75 is a cross-sectional view including a portion corresponding to line X7-X7 in FIG. 75, FIG. 90 is a cross-sectional view including a portion corresponding to line X8-X8 in FIGS. 72 to 75, and FIG. 91 is Y4-Y4 in FIGS. FIG. 92 is a sectional view corresponding to the line Y5-Y5 in FIGS. 72 to 75, and FIG. 92 is a sectional view of the main part of the low breakdown voltage MIS formation region in the counter doping process. Note that the cross-sectional views corresponding to the Y4-Y4 line in FIGS. 64 to 67 and the Y5-Y5 line in FIGS. 72 to 75 at the time of the counter-doping step are the same, so that in FIG. The sectional view is shown only in the figure.

First, a pattern of the resist film PR5 is formed on the main surface of the substrate 1S (ie, wafer) through the lithography process. The pattern of the resist film PR5 is formed such that the counter-doped region DR in the high breakdown voltage nMIS formation region is opened and the other portions are covered. That is, in the formation region HR3, as shown in FIGS. 87 and 91, both ends of the active region L1 on the high breakdown voltage nMIS side in the second direction Y are covered with the resist film PR5, as shown in FIGS. In addition, the other active region L1 on the high breakdown voltage nMIS side is exposed from the resist film PR5. In the formation region HR4, as shown in FIGS. 89 and 91, both ends of the active region L5 on the high breakdown voltage nMIS side in the second direction Y are covered with the resist film PR5, as shown in FIGS. In addition, the other active region L5 on the high breakdown voltage nMIS side is exposed from the resist film PR5. Subsequently, for example, phosphorus or arsenic (As) is selectively and shallowly introduced into the substrate 1S using the pattern of the resist film PR5 as a mask, by ion implantation or the like. As a result, the p ⁻ type semiconductor region (sixth, sixteenth, and eighteenth semiconductor regions) PV1m is formed above the p ⁺ type semiconductor region PV1p of the active regions L1 and L5 on the high breakdown voltage nMIS side exposed from the resist film PR5. Form. On the other hand, the same high withstand voltage nMIS side of the active region L1, L5 any ^{p +} -type upper portion of the semiconductor region PV1p of region covered with the resist film PR5 of both ends of the second direction Y will remain the ^{p +} -type. The p ⁻ type semiconductor region PV1m is formed in the vicinity of the surface of the semiconductor substrate 1S, and is formed above the p ⁺ type semiconductor region PV1p. That is, the p ⁻ type semiconductor region PV1m is formed at a shallower position than the p ⁺ type semiconductor region PV1p. For this reason, the threshold voltage at the center (main surface portion of the substrate 1S) of the channel regions of the active regions L1 and L5 on the high breakdown voltage nMIS side is set at both ends (in the separation portion 3) of the active regions L1 and L5 in the second direction Y. Since the threshold voltage at the substrate 1S portion in contact with the side wall) can be lowered, the occurrence of the kink phenomenon can be suppressed or prevented.

  Here, in the width direction (second direction Y) of the gate electrode formed later, the length of the semiconductor region PV1m and the length of the semiconductor region PV1p forming the channel region under the gate electrode HG are the length of the semiconductor region PV1m. Is formed to be longer. As a result, it is possible to reduce the MIS regions that are difficult to operate formed at both ends of the channel region in the second direction Y, and thus it is possible to prevent a reduction in the effective operating speed of the high breakdown voltage nMIS in the present embodiment. it can.

  At this time, the semiconductor region PVp <b> 1 is formed to be deeper than the isolation part 3. By forming the semiconductor region PVp1 in this way, the threshold value at the shoulder portion of the substrate 1S in contact with the upper portion of the separation portion 3 can be increased. Thereby, generation | occurrence | production of a kink phenomenon can be suppressed.

  Next, after removing the resist film PR5, the process proceeds to a counter-doping step for the high breakdown voltage pMIS formation region. 93 to 98 are cross-sectional views of the main part of the substrate 1S during the counter-doping process for the high breakdown voltage pMIS formation region. 93 is a cross-sectional view including a portion corresponding to the X5-X5 line in FIGS. 64-67, FIG. 94 is a cross-sectional view including a portion corresponding to the X6-X6 line in FIGS. 64-67, and FIG. 75 is a cross-sectional view including a portion corresponding to line X7-X7 in FIG. 75, FIG. 96 is a cross-sectional view including a portion corresponding to line X8-X8 in FIGS. 72 to 75, and FIG. 97 is Y4-Y4 in FIGS. And a cross-sectional view corresponding to the line Y5-Y5 in FIGS. 72 to 75, and FIG. 98 shows a cross-sectional view of the main part of the low breakdown voltage MIS formation region during the counter-doping step. The cross-sectional views corresponding to the Y4-Y4 line in FIGS. 64 to 67 and the Y5-Y5 line in FIGS. 72 to 75 at the time of the counter-doping step are also the same. The sectional view is shown only in the figure.

First, a pattern of the resist film PR6 is formed on the main surface of the substrate 1S (ie, wafer) through the lithography process. The pattern of the resist film PR6 is formed so that the counter-doped region DR in the high breakdown voltage pMIS formation region is opened and the others are covered. That is, in the formation region HR3, as shown in FIGS. 93 and 97, both ends of the active region L1 on the high breakdown voltage pMIS side in the second direction Y are covered with the resist film PR6, as shown in FIGS. In addition, the other active region L1 on the high breakdown voltage pMIS side is exposed from the resist film PR6. In the formation region HR4, as shown in FIGS. 95 and 97, both ends of the active region L5 on the high breakdown voltage pMIS side in the second direction Y are covered with the resist film PR6, as shown in FIGS. 96 and 97. In addition, the other active region L5 on the high breakdown voltage pMIS side is exposed from the resist film PR6. Subsequently, using the pattern of the resist film PR6 as a mask, boron, for example, is selectively and shallowly introduced into the substrate 1S by an ion implantation method or the like. As a result, an n ⁻ type semiconductor region NV1m is formed above the n ⁺ type semiconductor region NV1p of the active regions L1 and L5 on the high breakdown voltage pMIS side exposed from the resist film PR6. On the other hand, the same high withstand voltage pMIS side of the active region L1, L5 even upper portion of the semiconductor region NV1p the ^{n +} -type region covered with the resist film PR6 of both ends of the second direction Y will remain the ^{n +} -type. The n ⁻ type semiconductor region NV1m is formed in the vicinity of the surface of the semiconductor substrate 1S, and is formed above the n ⁺ type semiconductor region NV1p. That is, the n ⁻ type semiconductor region NV1m is formed at a shallower position than the n ⁺ type semiconductor region NV1p. For this reason, the threshold voltage at the center (main surface portion of the substrate 1S) of the channel regions of the active regions L1 and L5 of the high breakdown voltage pMIS is set to both ends (separation) of the active regions L1 and L5 of the high breakdown voltage pMIS in the second direction Y. Since the threshold voltage at the substrate 1S portion in contact with the side wall of the portion 3 can be made lower than the threshold voltage, the occurrence of the kink phenomenon can be suppressed or prevented.

  Here, in the width direction (second direction Y) of the gate electrode formed later, the length of the semiconductor region NV1m and the length of the semiconductor region NV1p forming the channel region under the gate electrode HG are the length of the semiconductor region NV1m. Is formed to be longer. That is, the semiconductor region NV1m is formed to occupy more than half of the channel region. As a result, it is possible to reduce the MIS regions that are difficult to operate formed at both ends of the channel region in the second direction Y. Therefore, it is possible to prevent a reduction in the effective operating speed of the high breakdown voltage pMIS in the present embodiment. it can.

  At this time, the semiconductor region NVp <b> 1 is formed to be deeper than the isolation part 3. By forming the semiconductor region NVp1 in this manner, the threshold value at the shoulder portion of the substrate 1S in contact with the upper portion of the separation portion 3 can be increased. Thereby, generation | occurrence | production of a kink phenomenon can be suppressed.

  Thereafter, after removing the resist film PR6, the same substrate 1S as shown in the cross-sectional view of the main part of the substrate 1S in the same manufacturing process of FIGS. High breakdown voltage nMIS (9th, 10th high breakdown voltage field effect transistor) QHn3, high breakdown voltage nMIS (11th, 12th high breakdown voltage field effect transistor) QHn4, high breakdown voltage pMISQHp3, QHp4, low breakdown voltage nMISQLn1, and low breakdown voltage pMISQLp1 are formed. . Also in the sixth embodiment, the illustration of the insulating film 6a is omitted for easy understanding of the drawing. Thus, in the manufacturing process, the low breakdown voltage MIS manufacturing process and the high breakdown voltage MIS manufacturing process are shared, thereby reducing the manufacturing process of the semiconductor device having the low breakdown voltage MIS and the high breakdown voltage MIS on the same substrate 1S. Can do.

(Embodiment 7)
In the seventh embodiment, a case will be described in which the groove-type isolation portion 3 of the semiconductor device of the fourth embodiment is replaced with an isolation portion formed by a LOCOS (Local Oxidization of Silicon) method.

  102 to 104 are main part sectional views of an example of the high withstand voltage MIS of the seventh embodiment. The plan view is the same as FIGS. 64 to 67 of the fourth embodiment. 102 is a cross-sectional view of a portion corresponding to the X5-X5 line in FIGS. 64 to 67, FIG. 103 is a cross-sectional view of a portion corresponding to the X6-X6 line in FIGS. 64-67, and FIG. Sectional drawing of the location corresponded to Y4-Y4 line of each is shown. Here, the case where the present invention is applied to the high breakdown voltage pMISQHp5 will be described here, but the present invention can also be applied to the high breakdown voltage nMIS.

  The high breakdown voltage pMISQHp5 of the seventh embodiment is the same as that of the fourth embodiment, except that the separation unit 3 is formed by the LOCOS method. That is, the isolation portion is not formed by digging a groove in the main surface of the substrate 1S and filling it with an insulating film, but in the active region on the main surface of the substrate 1S, an insulating film made of thin silicon oxide and the like After forming a laminated pattern with an oxidation-resistant insulating film made of deposited silicon nitride or the like, the substrate 1S is subjected to a thermal oxidation process, so that the isolation region exposed from the laminated pattern is made of silicon oxide or the like. The separation part 3 is formed.

Also in the seventh embodiment, as described in the fourth embodiment, punch-through between the p ⁺ type semiconductor regions P1 and P1 (p ⁻ type semiconductor regions PV1 and PV1) for the source and drain is suppressed. Alternatively, the ability to prevent can be improved, so that the designed channel length (length in the first direction X) of the high breakdown voltage pMISQHp5 can be shortened. That is, even if the isolation part 3 is the high breakdown voltage pMISQH5 formed by the LOCOS method, the size can be reduced, and the size of the semiconductor chip having the high breakdown voltage pMISQHp5 can be reduced.

  The structure and the manufacturing method other than the separation unit 3 are the same as those in the above-described fourth and sixth embodiments, and the same effect can be obtained, so that the description thereof is omitted.

(Embodiment 8)
In the present eighth embodiment, a case will be described in which the groove-type separation portion 3 of the semiconductor device of the fifth embodiment is replaced with a separation portion formed by a LOCOS method.

  105 and 106 are cross-sectional views of main parts of an example of the high voltage MIS of the eighth embodiment. The plan view is the same as FIGS. 72 to 75 of the fifth embodiment. 105 is a cross-sectional view taken along line X7-X7 in FIGS. 72 to 75, and FIG. 106 is a cross-sectional view taken along line X8-X8 in FIGS. The sectional view taken along line Y5-Y5 in FIGS. 72 to 75 is the same as that in FIG. Here, the case where the present invention is applied to the high breakdown voltage pMISQHp5 will be described here, but the present invention can also be applied to the high breakdown voltage nMIS.

  The high breakdown voltage pMISQHp6 of the eighth embodiment is the same as that of the fifth embodiment, except that the separation unit 3 is formed by the LOCOS method. That is, in the same manner as in the seventh embodiment, the active region on the main surface of the substrate 1S includes an insulating film made of thin silicon oxide or the like and an oxidation-resistant insulating film made of silicon nitride or the like deposited thereon. After forming the laminated pattern, the substrate 1S is subjected to a thermal oxidation process to form the separation portion 3 made of silicon oxide or the like in the separation region exposed from the laminated pattern.

  Also in the eighth embodiment, as in the fourth to sixth embodiments, the ability to suppress or prevent punch-through of the high breakdown voltage pMISQHp6 can be improved. Therefore, the design channel length of the high breakdown voltage pMISQHp6 (first (Length in one direction X) can be shortened. Therefore, since the size of the high breakdown voltage pMISQH6 formed by the LOCOS method in the isolation part 3 can be reduced, the size of the semiconductor chip having the high breakdown voltage pMISQHp6 can be reduced.

  The structure and the manufacturing method other than the separation unit 3 are the same as those in the above-described fifth and sixth embodiments, and the same effects can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to eighth embodiments, the case where the high-breakdown-voltage MIS gate electrode and the low-breakdown-voltage MIS gate electrode are formed in separate processes has been described. However, the present invention is not limited to this. The electrode and the gate electrode of the low withstand voltage MIS may be formed in the same process. In this case, for example, the following is performed. First, after patterning the insulating film 6b by the high breakdown voltage MIS CVD method as in the third and sixth embodiments, the formation region of the high breakdown voltage MIS is covered with a resist film. Subsequently, after etching so that silicon in the active region of the main surface of the substrate 1S in the formation region of the low breakdown voltage MIS is exposed, the resist film is removed. Thereafter, after forming a gate insulating film of low withstand voltage MIS by a thermal oxidation method or the like, a conductor film for forming a gate electrode is deposited on the entire main surface of the substrate 1S, and this is patterned through the lithography process and the dry etching process. As a result, a gate electrode is formed in the formation region of the high breakdown voltage MIS and the low breakdown voltage MIS.

  Further, when the drain withstand voltage of the high withstand voltage MIS is relatively low, for example, about 7 to 30 V, impurities are introduced by ion implantation or the like for forming the well with the low withstand voltage MIS, and the semiconductor having the electric field relaxation function of the high withstand voltage MIS. It may also serve as impurity introduction by an ion implantation method for forming the regions (PV1, NV1) and the channel stopper. In this case, a low breakdown voltage MIS well, a high breakdown voltage MIS semiconductor region having an electric field relaxation function, and a channel stopper can be formed in a single introduction step. That is, since a lithography process involving a series of processes such as resist coating, development, and exposure can be reduced, the manufacturing process of the semiconductor device can be greatly reduced.

  In the above description, the invention made mainly by the present inventor is applied to a manufacturing method of a semiconductor device applied to a driver circuit of a liquid crystal display device, a motor control driver circuit that performs high current control, and the like, which are the fields of use behind it. However, the present invention is not limited to this, and can be applied in various ways. For example, the present invention can be applied to a method of manufacturing a semiconductor device of another electronic device such as use in various circuits of an automobile.

  The present invention can be applied to the semiconductor device manufacturing industry.

It is a principal part top view of the high voltage | pressure-resistant field effect transistor of the semiconductor device which is one embodiment of this invention. FIG. 2 is a plan view of the same part as in FIG. 1, and is a plan view of a principal part showing an arrangement relationship between a semiconductor region for electric field relaxation and a main semiconductor region, particularly in a high breakdown voltage field effect transistor. FIG. 2 is a plan view of the same part as in FIG. 1, particularly a main part plan view showing an arrangement relationship among a gate electrode, an active region, and a main semiconductor region of a high breakdown voltage field effect transistor. It is the top view of the same location as FIG. 1, Comprising: It is the principal part top view which showed the isolation | separation area | region and the active region especially. It is sectional drawing of the X1-X1 line | wire of FIGS. It is sectional drawing of the X2-X2 line | wire of FIGS. It is sectional drawing of the Y1-Y1 line | wire of FIGS. It is a circuit diagram of an example of the circuit using a high voltage | pressure-resistant field effect transistor. It is a circuit diagram of the other example of the circuit using a high voltage | pressure-resistant field effect transistor. It is a principal part top view of an example of the high voltage | pressure-resistant field effect transistor of the semiconductor device which is other embodiment of this invention. FIG. 11 is a plan view of the same location as FIG. 10, and particularly shows an arrangement relationship between a semiconductor region having a field relaxation function of a high breakdown voltage field effect transistor, a p ⁺ type semiconductor region for a source, and an n ⁺ type semiconductor region. FIG. FIG. 11 is a plan view of the same portion as FIG. 10, and particularly a plan view of a main part showing an arrangement relationship among a gate electrode, an active region, and an n ⁺ type semiconductor region of a high voltage field effect transistor. It is the top view of the same location as FIG. 10, Comprising: It is the principal part top view which showed the isolation | separation area | region and the active region especially. It is sectional drawing of the X3-X3 line | wire of FIGS. It is sectional drawing of the X4-X4 line | wire of FIGS. It is principal part sectional drawing of the 1st formation area of the high voltage | pressure-resistant field effect transistor in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 17 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 16; FIG. 17 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 16; It is a principal part expanded sectional view of FIGS. FIG. 20 is a fragmentary cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 16 to 19; FIG. 21 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 20; FIG. 21 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 20; It is principal part expanded sectional drawing of FIGS. FIG. 23 is a fragmentary cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 20 to 22; FIG. 25 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 24; FIG. 25 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 24; It is principal part expanded sectional drawing of FIGS. 24-26. FIG. 28 is a fragmentary cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIG. 23 to FIG. 27; FIG. 29 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 28; FIG. 29 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 28; FIG. 31 is a fragmentary cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 28 to 30; FIG. 32 is a main-portion cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 31; FIG. 32 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 31; FIG. 34 is a main part cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 31 to 33; FIG. 35 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 34; FIG. 35 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 34; FIG. 37 is a fragmentary cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during a manufacturing step of the semiconductor device following that of FIGS. 34 to 36; FIG. 38 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 37; FIG. 38 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 37; FIG. 40 is a main-portion cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during a manufacturing step of the semiconductor device following that of FIGS. 37 to 39; FIG. 41 is a main-portion cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 40; 41 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 40; FIG. 43 is a fragmentary cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 40 to 42; FIG. FIG. 44 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 43; FIG. 44 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 43. FIG. 46 is an essential part cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following FIGS. 43 to 45; 47 is a fragmentary cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 46; FIG. FIG. 47 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 46; FIG. 49 is an essential part cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following FIGS. 46 to 48; FIG. 50 is a main-portion cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 49; FIG. 50 is a main-portion cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 49; FIG. 52 is an essential part cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following FIGS. 49 to 51; FIG. 53 is a main-portion cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 52; FIG. 53 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 52; FIG. 55 is a main-portion cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 52 to 54; FIG. 56 is a main-portion cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 55; FIG. 56 is a fragmentary cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 55. FIG. 58 is a main-portion cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 55 to 57; FIG. 59 is a main-portion cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 58; FIG. 59 is a main-portion cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 58; FIG. 61 is a main-portion cross-sectional view of the first formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 58 to 60; FIG. 62 is a main-portion cross-sectional view of the second formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 61; FIG. 62 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 61; It is a principal part top view of an example of the high voltage | pressure-resistant field effect transistor of the semiconductor device which is other embodiment of this invention. FIG. 65 is a plan view of the same portion as FIG. 64, and is a plan view of relevant parts showing a positional relationship between a p ⁻ type semiconductor region having a field relaxation function of a high breakdown voltage field effect transistor and a counter doped region. FIG. 65 is a plan view of the same portion as FIG. 64, particularly a plan view of relevant parts showing the state of each semiconductor region of the high breakdown voltage field effect transistor. FIG. 65 is a plan view of the same portion as FIG. 64 and is a plan view of relevant parts showing the state of the semiconductor region in the active region. It is sectional drawing of the X5-X5 line | wire of FIGS. It is sectional drawing of the X6-X6 line | wire of FIGS. FIG. 68 is a cross-sectional view taken along line Y4-Y4 of FIGS. 64-67. FIG. 65 is a plan view of a principal part of an example when a plurality of high voltage field effect transistors of FIG. 64 are arranged. It is a principal part top view of an example of the high voltage | pressure-resistant field effect transistor of the semiconductor device which is further another embodiment of this invention. FIG. 73 is a plan view of the same portion as FIG. 72, and particularly shows a plan view of relevant parts showing a positional relationship between a p ⁻ type semiconductor region having a field relaxation function of a high breakdown voltage field effect transistor and a counter-doped region. FIG. 73 is a plan view of the same portion as FIG. 72, particularly a plan view of relevant parts showing the state of each semiconductor region of the high breakdown voltage field effect transistor. FIG. 73 is a plan view of the same portion as FIG. 72, particularly a plan view of relevant parts showing a state of a semiconductor region in an active region. FIG. 76 is a cross-sectional view taken along line X7-X7 of FIGS. FIG. 76 is a cross-sectional view taken along line X8-X8 of FIGS. It is principal part sectional drawing of the 3rd formation area | region of the high voltage | pressure-resistant field effect transistor in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 79 is an essential part cross-sectional view of the fourth formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 78; FIG. 79 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 78; FIG. 81 is a fragmentary cross-sectional view of the third formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 78 to 80; FIG. 82 is an essential part cross-sectional view of the fourth formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 81; FIG. 82 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 81; FIG. 84 is a fragmentary cross-sectional view of the third formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following that of FIGS. 81 to 83; FIG. 85 is an essential part cross-sectional view of the fourth formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 84; FIG. 85 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 84; FIG. 68 is a cross-sectional view including a portion corresponding to the X5-X5 line in FIGS. 64 to 67 of the third formation region of the high breakdown voltage field effect transistor in the manufacturing process of the semiconductor device following FIGS. 84 to 86; FIG. 68 is a cross-sectional view that includes the same manufacturing process as FIG. 87 and includes a portion corresponding to line X6-X6 in FIGS. FIG. 76 is a cross-sectional view including the same manufacturing process as FIG. 87 and including a portion corresponding to line X7-X7 in FIGS. 72 to 75; FIG. 76 is a cross-sectional view including the same manufacturing process as FIG. 87 and including a portion corresponding to line X8-X8 in FIGS. 72 to 75; FIG. 78 is a cross-sectional view of the same manufacturing process as FIG. 87 and corresponding to the Y4-Y4 line in FIGS. 64 to 67 or the Y5-Y5 line in FIGS. 72 to 75. FIG. 88 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 87. FIG. 69 is a cross-sectional view including a portion corresponding to the X5-X5 line in FIGS. 64 to 67 of the third formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following FIGS. 87 to 92; FIG. 68 is a cross-sectional view including the same manufacturing process as FIG. 93 but including a portion corresponding to line X6-X6 in FIGS. FIG. 76 is a cross-sectional view including the same manufacturing process as FIG. 93 and including a portion corresponding to line X7-X7 in FIGS. 72 to 75; FIG. 76 is a cross-sectional view including the same manufacturing process as FIG. 93 and including a portion corresponding to line X8-X8 in FIGS. 72 to 75. It is the same manufacturing process as FIG. 93, Comprising: It is sectional drawing equivalent to the Y4-Y4 line | wire of FIGS. 64-67, or the Y5-Y5 line | wire of FIGS. FIG. 94 is an essential part cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 93; FIG. 68 is a cross-sectional view including a portion corresponding to the X5-X5 line in FIGS. 64 to 67 of the third formation region of the high breakdown voltage field effect transistor during the manufacturing process of the semiconductor device following FIGS. 93 to 99; 99 is a fragmentary cross-sectional view of the fourth formation region of the high breakdown voltage field effect transistor of the semiconductor device in the same manufacturing process as FIG. 99; FIG. FIG. 99 is a main-portion cross-sectional view of the formation region of the low breakdown voltage field effect transistor of the semiconductor device, which is the same manufacturing process as FIG. 99; FIG. 68 is a cross-sectional view of a portion corresponding to line X5-X5 in FIGS. 64 to 67, which is an example of a high breakdown voltage field effect transistor of a semiconductor device according to still another embodiment of the present invention. FIG. 68 is a cross-sectional view of a portion corresponding to the line X6-X6 of FIGS. FIG. 68 is a cross-sectional view of a portion corresponding to the line Y4-Y4 in FIGS. FIG. 76 is a cross-sectional view of a portion corresponding to line X7-X7 in FIGS. 72 to 75, which is an example of a high breakdown voltage field effect transistor of a semiconductor device which is still another embodiment of the present invention. FIG. 76 is a cross-sectional view of the high breakdown voltage field effect transistor of FIG. 105 and corresponding to the X8-X8 line of FIGS. 72 to 75. It is a wave form diagram of the kink waveform which arose in the high voltage | pressure-resistant field effect transistor. It is explanatory drawing of the kink waveform of FIG. It is a principal part top view of the high voltage | pressure-resistant field effect transistor without a kink countermeasure. It is sectional drawing of the Y50-Y50 line | wire of FIG. FIG. 2 is a plan view of an essential part of an example in which a plurality of high breakdown voltage field effect transistors of FIG. 1 of a semiconductor device according to an embodiment of the present invention are arranged.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1S Semiconductor substrate 2 Silicide layer 3 Separation part 3a Groove 3b Insulating film 5 Side wall 6 Gate insulating film 6a, 6b Insulating film 8 Insulating film 9 Insulating film 10 Insulating film 13 Conductive film 14 Insulating film 15 Gate insulating film 16 Polycrystalline silicon film 18 p ⁻ type semiconductor region 19 n ⁻ type semiconductor region 20 p ⁻ type semiconductor region 21 n ⁻ type semiconductor region 50 high breakdown voltage MIS • FET
51 Groove-type isolation portion 52 Semiconductor substrate 53 Gate electrode 54 Deep well QHp, QHp1, QHp2, QHp3, QHp4 High breakdown voltage p-channel MIS • FET
QHp5, QHp6 High voltage p-channel MIS • FET
QHn, QHn1, QHn2, QHn3, QHn4 High breakdown voltage n-channel MIS • FET
QLn1 Low breakdown voltage n-channel MIS • FET
QLp1 Low breakdown voltage p-channel MIS • FET
DNW Deep n-type well DPW Deep p-type well PIS p-type semiconductor regions PW1, PW2 p for isolation ⁺ type wells NW1, NW2 n ⁺ -type wells P1, P1s, P1d, P2, P3 p ⁺ -type semiconductor regions PV1 p ⁻ Type semiconductor region PV1p p ⁺ type semiconductor region PV1m p ⁻ type semiconductor region N1, N1s, N1d, N2, N3 n ⁺ type semiconductor region NV1 n ⁻ type semiconductor region NV1p n ⁺ type semiconductor region NV1m n ⁻ Type semiconductor region L, L1 to L5 active region HG gate electrode LG gate electrode NVkn ⁺ type semiconductor region PVk p ⁺ type semiconductor region Vcc high potential side power supply potential GND reference potential side power supply potential R1, R2 resistance PR1 to PR6 Photoresist film DR Counter doped region S0 Source region D0 Drain region V0 Semiconductor region

Claims (16)

A method of manufacturing a semiconductor device comprising a step of forming fifth and sixth high breakdown voltage field effect transistors on a semiconductor substrate,
(A) forming a groove-type isolation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the groove-type isolation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) after the step (a) , forming a second conductivity type eighth semiconductor region opposite to the first conductivity type on the semiconductor substrate;
(D) After the step (b) , forming a second conductive type ninth semiconductor region for the source and drain of the fifth high breakdown voltage field effect transistor in the seventh semiconductor region;
(E) After the step (c) , forming a first conductivity type tenth semiconductor region for the source and drain of the sixth high breakdown voltage field effect transistor in the eighth semiconductor region;
(F) after the step (d) and the step (e) , forming a gate insulating film on the semiconductor substrate;
(G) after the step (f) , forming a gate electrode on the gate insulating film;
(H) After the step (g), the ninth semiconductor region is a semiconductor region having a higher impurity concentration than the ninth semiconductor region, and is used for the source and drain of the fifth high breakdown voltage field effect transistor. Forming an eleventh semiconductor region of the second conductivity type;
(I) After the step (g), the tenth semiconductor region is a semiconductor region having a higher impurity concentration than the tenth semiconductor region, and is used for the source and drain of the sixth high breakdown voltage field effect transistor. Forming a twelfth semiconductor region of the first conductivity type,
The eleventh semiconductor regions of the second conductivity type for the source and drain of the fifth high breakdown voltage field effect transistor are on both sides in the gate length direction of the active region where the channel region of the fifth high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the groove-type separation part,
The ninth semiconductor region of the second conductivity type for the source and drain of the fifth high breakdown voltage field effect transistor includes the eleventh semiconductor region of the second conductivity type for the source and drain and the fifth high breakdown voltage field effect. Formed so as to be electrically connected to the channel region of the transistor,
The twelfth conductive type twelfth semiconductor regions for the source and drain of the sixth high breakdown voltage field effect transistor are located on both sides in the gate length direction of the active region where the channel region of the sixth high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the groove-type separation part,
The tenth semiconductor region of the first conductivity type for the source and drain of the sixth high breakdown voltage field effect transistor includes the twelfth semiconductor region of the first conductivity type for the source and drain and the sixth high breakdown voltage field effect. Formed so as to be electrically connected to the channel region of the transistor,
When forming the second conductive type ninth semiconductor region for the source and drain of the fifth high withstand voltage field effect transistor, the trench type separation portions at both ends in the gate width direction of the sixth high withstand voltage field effect transistor In the boundary region between the semiconductor substrate and the semiconductor substrate, the thirteenth semiconductor region of the second conductivity type having a higher impurity concentration than the eighth semiconductor region is provided. Formed so as to be away from the tenth and twelfth semiconductor regions so as not to contact the tenth and twelfth semiconductor regions,
When forming the tenth semiconductor region of the first conductivity type for the source and drain of the sixth high withstand voltage field effect transistor, the trench type isolation portions at both ends in the gate width direction of the fifth high withstand voltage field effect transistor In the boundary region between the semiconductor substrate and the semiconductor substrate, a fourteenth semiconductor region of a first conductivity type having a higher impurity concentration than the seventh semiconductor region is provided, and a second conductivity type for the source and drain of the fifth high breakdown voltage field effect transistor. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed away from the ninth and eleventh semiconductor regions so as not to contact the ninth and eleventh semiconductor regions. A method of manufacturing a semiconductor device comprising a step of forming seventh and eighth high breakdown voltage field effect transistors on a semiconductor substrate,
(A) forming a groove-type isolation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the groove-type isolation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) after the step (a) , forming a second conductivity type eighth semiconductor region opposite to the first conductivity type on the semiconductor substrate;
(D) after the step (b) , forming a second conductive type ninth semiconductor region for the drain of the seventh high breakdown voltage field effect transistor in the seventh semiconductor region;
(E) after the step (c) , forming a first conductivity type tenth semiconductor region for a drain of the eighth high breakdown voltage field effect transistor in the eighth semiconductor region;
(F) after the step (d) and the step (e) , forming a gate insulating film on the semiconductor substrate;
(G) after the step (f) , forming a gate electrode on the gate insulating film;
(H) After the step (g), in the ninth semiconductor region, a second semiconductor region having a higher impurity concentration than the ninth semiconductor region and serving as a drain for the seventh high breakdown voltage field effect transistor. An eleventh conductivity type semiconductor region is formed, and the seventh semiconductor region is a semiconductor region having a higher impurity concentration than the ninth semiconductor region, and is a source region for the seventh high breakdown voltage field effect transistor. Forming a second conductivity type eleventh semiconductor region;
(I) After the step (g), in the tenth semiconductor region, a semiconductor region having a higher impurity concentration than the tenth semiconductor region, the first for drain of the eighth high breakdown voltage field effect transistor A conductive type twelfth semiconductor region is formed, and a semiconductor region having a higher impurity concentration than the tenth semiconductor region is formed in the eighth semiconductor region, and is used for the source of the eighth high breakdown voltage field effect transistor. Forming a twelfth semiconductor region of one conductivity type,
The eleventh semiconductor region of the second conductivity type for the drain of the seventh high breakdown voltage field effect transistor is located on one side in the gate length direction of the active region in which the channel region of the seventh high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the groove-type separation part,
The eleventh semiconductor region of the second conductivity type for the source of the seventh high withstand voltage field effect transistor is located on the other side in the gate length direction of the active region in which the channel region of the seventh high withstand voltage field effect transistor is disposed. Formed adjacent to each other without a groove-shaped separation part,
The ninth semiconductor region of the second conductivity type for the drain of the seventh high withstand voltage field effect transistor includes an eleventh semiconductor region of the second conductivity type for the drain and a channel region of the seventh high withstand voltage field effect transistor. Formed to connect electrically,
The twelfth semiconductor region of the first conductivity type for the drain of the eighth high withstand voltage field effect transistor is on one side in the gate length direction of the active region in which the channel region of the eighth high withstand voltage field effect transistor is disposed. Formed in the active region arranged through the groove-type separation part,
The twelfth semiconductor region of the first conductivity type for the source of the eighth high withstand voltage field effect transistor is on the other side in the gate length direction of the active region in which the channel region of the eighth high withstand voltage field effect transistor is disposed. Formed adjacent to each other without a groove-shaped separation part,
The tenth semiconductor region of the first conductivity type for the drain of the eighth high withstand voltage field effect transistor includes a twelfth semiconductor region of the first conductivity type for the drain and a channel region of the eighth high withstand voltage field effect transistor. Formed to connect electrically,
When forming the second conductive type ninth semiconductor region for the drain of the seventh high withstand voltage field effect transistor, the groove type isolation portions at both ends in the gate width direction of the eighth high withstand voltage field effect transistor and the In a boundary region with the semiconductor substrate, a second conductivity type thirteenth semiconductor region having a higher impurity concentration than that of the eighth semiconductor region, and a first conductivity type tenth for the drain of the eighth high breakdown voltage field effect transistor, Forming so as not to contact the twelfth semiconductor region, away from the tenth and twelfth semiconductor regions,
When forming the tenth semiconductor region of the first conductivity type for the drain of the eighth high withstand voltage field effect transistor, the trench type isolation portions at both ends in the gate width direction of the seventh high withstand voltage field effect transistor and the In the boundary region with the semiconductor substrate, the 14th semiconductor region of the first conductivity type having a higher impurity concentration than the 7th semiconductor region, the 9th of the second conductivity type for the drain of the 7th high breakdown voltage field effect transistor, A method of manufacturing a semiconductor device, wherein the semiconductor device is formed away from the ninth and eleventh semiconductor regions so as not to contact the eleventh semiconductor region. A method of manufacturing a semiconductor device, comprising: forming seventh and eighth high breakdown voltage field effect transistors and a low breakdown voltage field effect transistor having a lower operating voltage than the seventh and eighth high breakdown voltage field effect transistors on a semiconductor substrate. ,
(A) forming a groove-type isolation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the groove-type isolation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) after the step (a) , forming a second conductivity type eighth semiconductor region opposite to the first conductivity type on the semiconductor substrate;
(D) after the step (b) , forming a second conductive type ninth semiconductor region for the drain of the seventh high breakdown voltage field effect transistor in the seventh semiconductor region;
(E) after the step (c) , forming a first conductivity type tenth semiconductor region for a drain of the eighth high breakdown voltage field effect transistor in the eighth semiconductor region;
(F) After the step (d) and the step (e) , forming a gate insulating film for the seventh and eighth high breakdown voltage field effect transistors on the semiconductor substrate;
(G) After the step (f) , forming a gate electrode for the seventh and eighth high breakdown voltage field effect transistors on the gate insulating film for the seventh and eighth high breakdown voltage field effect transistors;
(H) After the step (d), in the ninth semiconductor region, there is a semiconductor region having a higher impurity concentration than that of the ninth semiconductor region, and a second region for the drain of the seventh high breakdown voltage field effect transistor. An eleventh conductivity type semiconductor region is formed, and the seventh semiconductor region is a semiconductor region having a higher impurity concentration than the ninth semiconductor region, and is a source region for the seventh high breakdown voltage field effect transistor. Forming a second conductivity type eleventh semiconductor region;
(I) After the step (e), in the tenth semiconductor region, a semiconductor region having a higher impurity concentration than the tenth semiconductor region, and a first drain drain for the eighth high withstand voltage field effect transistor A conductive-type twelfth semiconductor region is formed, and the eighth semiconductor region is a semiconductor region having a higher impurity concentration than the tenth semiconductor region, and is a source region for the eighth high-voltage field effect transistor. Forming a twelfth semiconductor region of one conductivity type;
(J) forming a gate insulating film of the low breakdown voltage field effect transistor;
(K) After the step (j) , forming a gate electrode of the low breakdown voltage field effect transistor;
(L) After the step (k) , forming a fifteenth semiconductor region for the source and drain of the low breakdown voltage field effect transistor,
The eleventh semiconductor region of the second conductivity type for the drain of the seventh high breakdown voltage field effect transistor is located on one side in the gate length direction of the active region in which the channel region of the seventh high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the groove-type separation part,
The eleventh semiconductor region of the second conductivity type for the source of the seventh high withstand voltage field effect transistor is located on the other side in the gate length direction of the active region in which the channel region of the seventh high withstand voltage field effect transistor is disposed. Formed adjacent to each other without a groove-shaped separation part,
The ninth semiconductor region of the second conductivity type for the drain of the seventh high withstand voltage field effect transistor includes an eleventh semiconductor region of the second conductivity type for the drain and a channel region of the seventh high withstand voltage field effect transistor. Formed to connect electrically,
The twelfth semiconductor region of the first conductivity type for the drain of the eighth high withstand voltage field effect transistor is on one side in the gate length direction of the active region in which the channel region of the eighth high withstand voltage field effect transistor is disposed. Formed in the active region arranged through the groove-type separation part,
The twelfth semiconductor region of the first conductivity type for the source of the eighth high withstand voltage field effect transistor is on the other side in the gate length direction of the active region in which the channel region of the eighth high withstand voltage field effect transistor is disposed. Formed adjacent to each other without a groove-shaped separation part,
The tenth semiconductor region of the first conductivity type for the drain of the eighth high withstand voltage field effect transistor includes a twelfth semiconductor region of the first conductivity type for the drain and a channel region of the eighth high withstand voltage field effect transistor. Formed to connect electrically,
When forming the second conductive type ninth semiconductor region for the drain of the seventh high withstand voltage field effect transistor, the groove type isolation portions at both ends in the gate width direction of the eighth high withstand voltage field effect transistor and the In a boundary region with the semiconductor substrate, a second conductivity type thirteenth semiconductor region having a higher impurity concentration than that of the eighth semiconductor region, and a first conductivity type tenth for the drain of the eighth high breakdown voltage field effect transistor, Forming so as not to contact the twelfth semiconductor region, away from the tenth and twelfth semiconductor regions,
When forming the tenth semiconductor region of the first conductivity type for the drain of the eighth high withstand voltage field effect transistor, the groove type isolation portions at both ends in the gate width direction of the seventh high withstand voltage field effect transistor and the In the boundary region with the semiconductor substrate, the 14th semiconductor region of the first conductivity type having a higher impurity concentration than the 7th semiconductor region, the 9th of the second conductivity type for the drain of the 7th high breakdown voltage field effect transistor, Forming away from the ninth and eleventh semiconductor regions so as not to contact the eleventh semiconductor region,
A method of manufacturing a semiconductor device, comprising: forming gate electrodes of the seventh and eighth high breakdown voltage field effect transistors after forming a gate electrode of the low breakdown voltage field effect transistor.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the thirteenth and fourteenth semiconductor regions are formed so as to extend from a main surface of the semiconductor substrate to a position deeper than the separation portion. A method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device comprising a step of forming a high breakdown voltage field effect transistor and a low breakdown voltage field effect transistor having an operating voltage lower than that of the high breakdown voltage field effect transistor on a semiconductor substrate,
(A) forming a groove-type isolation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the groove-type isolation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) After the step (b), the seventh semiconductor region is a semiconductor region of a second conductivity type opposite to the first conductivity type, and is a second region for the drain of the high breakdown voltage field effect transistor. Forming a conductive type ninth semiconductor region;
(D) After the step (b), an impurity concentration higher than that of the seventh semiconductor region is present in a boundary region between the trench-type isolation portion and the semiconductor substrate at both ends in the gate width direction of the high breakdown voltage field effect transistor. Forming the first conductivity type fourteenth semiconductor region away from the ninth semiconductor region so as not to contact the second conductivity type ninth semiconductor region for the drain of the high breakdown voltage field effect transistor; ,
(E) after the step (c) and the step (d) , forming a gate insulating film for the high breakdown voltage field effect transistor on the semiconductor substrate;
(F) After the step (e) , forming a gate electrode for the high breakdown voltage field effect transistor on the gate insulating film for the high breakdown voltage field effect transistor;
(G) After the step (c), in the ninth semiconductor region, a second semiconductor region having a higher impurity concentration than the ninth semiconductor region and serving as a drain for the seventh high breakdown voltage field effect transistor. A conductive type eleventh semiconductor region is formed, and a semiconductor region having a higher impurity concentration than the ninth semiconductor region in the seventh semiconductor region, the second conductive for the source of the high breakdown voltage field effect transistor. Forming an eleventh semiconductor region of the mold;
(H) forming a gate insulating film of the low breakdown voltage field effect transistor;
(I) after the step (h) , forming a gate electrode of the low breakdown voltage field effect transistor;
(J) after the step (i) , forming a fifteenth semiconductor region for the source and drain of the low breakdown voltage field effect transistor,
The eleventh semiconductor region of the second conductivity type for the drain of the high breakdown voltage field effect transistor has the groove type isolation on one side in the gate length direction of the active region where the channel region of the high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the part,
The eleventh semiconductor region of the second conductivity type for the source of the high breakdown voltage field effect transistor has the groove type isolation on the other side in the gate length direction of the active region where the channel region of the high breakdown voltage field effect transistor is disposed. Formed in an adjacent state without intervening parts,
The ninth semiconductor region of the second conductivity type for the drain of the high breakdown voltage field effect transistor electrically connects the eleventh semiconductor region of the second conductivity type for the drain and the channel region of the high breakdown voltage field effect transistor. Formed to
A method of manufacturing a semiconductor device, comprising: forming a gate electrode of the high breakdown voltage field effect transistor after forming a gate electrode of the low breakdown voltage field effect transistor.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the fourteenth semiconductor region is formed so as to extend from a main surface of the semiconductor substrate to a position deeper than the isolation portion. Method. A method for manufacturing a semiconductor device, comprising: forming ninth and tenth high breakdown voltage field effect transistors on a semiconductor substrate,
(A) forming a groove-type separation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the separation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) after the step (a) , forming a second conductivity type eighth semiconductor region opposite to the first conductivity type on the semiconductor substrate;
(D) After the step (b) , forming a second conductive type ninth semiconductor region for the source and drain of the ninth high breakdown voltage field effect transistor in the seventh semiconductor region;
(E) After the step (c) , forming a first conductivity type tenth semiconductor region for the source and drain of the tenth high breakdown voltage field effect transistor in the eighth semiconductor region;
(F) after the step (d) and the step (e) , forming a gate insulating film on the semiconductor substrate;
(G) after the step (f) , forming a gate electrode on the gate insulating film;
(H) After the step (g), the ninth semiconductor region is a semiconductor region having a higher impurity concentration than the ninth semiconductor region, and is used for the source and drain of the ninth high breakdown voltage field effect transistor. Forming an eleventh semiconductor region of the second conductivity type;
(I) After the step (g), the tenth semiconductor region is a semiconductor region having a higher impurity concentration than the tenth semiconductor region, and is used for the source and drain of the tenth high breakdown voltage field effect transistor. Forming a twelfth semiconductor region of the first conductivity type,
The eleventh semiconductor regions of the second conductivity type for the source and drain of the ninth high breakdown voltage field effect transistor are on both sides in the gate length direction of the active region where the channel region of the ninth high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the separation part,
The ninth conductive region of the second conductivity type for the source and drain of the ninth high breakdown voltage field effect transistor includes the eleventh semiconductor region of the second conductivity type for the source and drain and the ninth high breakdown voltage field effect. Formed so as to be electrically connected to the channel region of the transistor,
The twelfth conductive type twelfth semiconductor regions for the source and drain of the tenth high breakdown voltage field effect transistor are located on both sides in the gate length direction of the active region where the channel region of the tenth high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the separation part,
The tenth semiconductor region of the first conductivity type for the source and drain of the tenth high breakdown voltage field effect transistor is the same as each of the twelfth semiconductor regions of the first conductivity type for the source and drain and the tenth high breakdown voltage field effect. Formed so as to be electrically connected to the channel region of the transistor,
When forming the ninth semiconductor region of the second conductivity type for the source and drain of the ninth high breakdown voltage field effect transistor, the eighth high breakdown voltage field effect transistor is formed in the region where the channel region is disposed. Forming a second conductivity type fifteenth semiconductor region having a higher impurity concentration than the semiconductor region;
After forming the fifteenth semiconductor region in the step (d) and before the step (f) , a conductivity type opposite to that of the fifteenth semiconductor region is formed on the fifteenth semiconductor region. By introducing the impurity, a second conductivity type sixteenth semiconductor region having a lower impurity concentration than the fifteenth semiconductor region is formed on the fifteenth semiconductor region,
When the tenth semiconductor region of the first conductivity type for the source and drain of the tenth high breakdown voltage field effect transistor is formed, the seventh high breakdown voltage field effect transistor is formed in the region where the channel region is disposed. Forming a seventeenth semiconductor region of a first conductivity type having a higher impurity concentration than the semiconductor region;
After forming the seventeenth semiconductor region in the step (e) and before the step (f) , a conductivity type opposite to the seventeenth semiconductor region is formed on the seventeenth semiconductor region. A method of manufacturing a semiconductor device, comprising introducing an impurity to form a first conductivity type 18th semiconductor region having a lower impurity concentration than the 17th semiconductor region above the 17th semiconductor region. A method of manufacturing a semiconductor device comprising a step of forming eleventh and twelfth high breakdown voltage field effect transistors on a semiconductor substrate,
(A) forming a groove-type separation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the separation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) after the step (a) , forming a second conductivity type eighth semiconductor region opposite to the first conductivity type on the semiconductor substrate;
(D) after the step (b) , forming a second conductive type ninth semiconductor region for the drain of the eleventh high breakdown voltage field effect transistor in the seventh semiconductor region;
(E) after the step (c) , forming a tenth semiconductor region of the first conductivity type for the drain of the twelfth high breakdown voltage field effect transistor in the eighth semiconductor region;
(F) after the step (d) and the step (e) , forming a gate insulating film on the semiconductor substrate;
(G) after the step (f) , forming a gate electrode on the gate insulating film;
(H) After the step (g), in the ninth semiconductor region, a second semiconductor region having a higher impurity concentration than the ninth semiconductor region and serving as a drain for the eleventh high breakdown voltage field effect transistor. An eleventh conductivity type semiconductor region is formed, and the seventh semiconductor region is a semiconductor region having a higher impurity concentration than the ninth semiconductor region, and is a source region for the eleventh high breakdown voltage field effect transistor. Forming a second conductivity type eleventh semiconductor region;
(I) After the step (g), in the tenth semiconductor region, a semiconductor region having a higher impurity concentration than the tenth semiconductor region, the first for drain of the twelfth high breakdown voltage field effect transistor A conductive type twelfth semiconductor region is formed, and a semiconductor region having a higher impurity concentration than the tenth semiconductor region is formed in the eighth semiconductor region and is used for the source of the twelfth high breakdown voltage field effect transistor. Forming a twelfth semiconductor region of one conductivity type,
The eleventh semiconductor region of the second conductivity type for the drain of the eleventh high breakdown voltage field effect transistor is located on one side in the gate length direction of the active region where the channel region of the eleventh high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the separation part,
The eleventh semiconductor region of the second conductivity type for the source of the eleventh high breakdown voltage field effect transistor is located on the other side in the gate length direction of the active region where the channel region of the eleventh high breakdown voltage field effect transistor is disposed. Formed in a state adjacent to each other without a separation part,
The ninth semiconductor region of the second conductivity type for the drain of the eleventh high withstand voltage field effect transistor includes an eleventh semiconductor region of the second conductivity type for the drain and a channel region of the eleventh high withstand voltage field effect transistor. Formed to connect electrically,
The twelfth conductive type twelfth semiconductor region for the drain of the twelfth high breakdown voltage field effect transistor is located on one side in the gate length direction of the active region where the channel region of the twelfth high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the separation part,
The twelfth conductive type twelfth semiconductor region for the source of the twelfth high breakdown voltage field effect transistor is located on the other side in the gate length direction of the active region where the channel region of the twelfth high breakdown voltage field effect transistor is disposed. Formed in a state adjacent to each other without a separation part,
The tenth semiconductor region of the first conductivity type for the drain of the twelfth high breakdown voltage field effect transistor includes a twelfth semiconductor region of the first conductivity type for the drain and a channel region of the twelfth high breakdown voltage field effect transistor. Formed to connect electrically,
In forming the second conductive type ninth semiconductor region for the drain of the eleventh high breakdown voltage field effect transistor, the eighth semiconductor region is formed in the region where the channel region of the twelfth high breakdown voltage field effect transistor is disposed. Forming a fifteenth semiconductor region of the second conductivity type having a higher impurity concentration than
After forming the fifteenth semiconductor region in the step (d) and before the step (f) , a conductivity type opposite to that of the fifteenth semiconductor region is formed on the fifteenth semiconductor region. By introducing the impurity, a second conductivity type sixteenth semiconductor region having a lower impurity concentration than the fifteenth semiconductor region is formed on the fifteenth semiconductor region,
When forming the tenth semiconductor region of the first conductivity type for the drain of the twelfth high breakdown voltage field effect transistor, the seventh semiconductor region is formed in a region where the channel region of the eleventh high breakdown voltage field effect transistor is disposed. Forming a seventeenth semiconductor region of the first conductivity type having a higher impurity concentration than
After forming the seventeenth semiconductor region in the step (e) and before the step (f) , a conductivity type opposite to the seventeenth semiconductor region is formed on the seventeenth semiconductor region. A method of manufacturing a semiconductor device, comprising introducing an impurity to form a first conductivity type 18th semiconductor region having a lower impurity concentration than the 17th semiconductor region above the 17th semiconductor region. A method of manufacturing a semiconductor device, comprising: forming eleventh and twelfth high breakdown voltage field effect transistors and a low breakdown voltage field effect transistor having an operating voltage lower than that of the eleventh and twelfth high breakdown voltage field effect transistors on a semiconductor substrate. Because
(A) forming a groove-type separation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the separation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) after the step (a) , forming a second conductivity type eighth semiconductor region opposite to the first conductivity type on the semiconductor substrate;
(D) after the step (b) , forming a second conductive type ninth semiconductor region for the drain of the eleventh high breakdown voltage field effect transistor in the seventh semiconductor region;
(E) after the step (c) , forming a tenth semiconductor region of the first conductivity type for the drain of the twelfth high breakdown voltage field effect transistor in the eighth semiconductor region;
(F) After the step (d) and the step (e) , forming a gate insulating film of the eleventh and twelfth high withstand voltage field effect transistors on the semiconductor substrate;
(G) After the step (f) , forming a gate electrode of the eleventh and twelfth high breakdown voltage field effect transistors on the gate insulating film of the eleventh and twelfth high breakdown voltage field effect transistors;
(H) After the step (g), in the ninth semiconductor region, a second semiconductor region having a higher impurity concentration than the ninth semiconductor region and serving as a drain for the eleventh high breakdown voltage field effect transistor. An eleventh conductivity type semiconductor region is formed, and the seventh semiconductor region is a semiconductor region having a higher impurity concentration than the ninth semiconductor region, and is a source region for the eleventh high breakdown voltage field effect transistor. Forming a second conductivity type eleventh semiconductor region;
(I) After the step (g), in the tenth semiconductor region, a semiconductor region having a higher impurity concentration than the tenth semiconductor region, the first for drain of the twelfth high breakdown voltage field effect transistor A conductive type twelfth semiconductor region is formed, and a semiconductor region having a higher impurity concentration than the tenth semiconductor region is formed in the eighth semiconductor region and is used for the source of the twelfth high breakdown voltage field effect transistor. Forming a twelfth semiconductor region of one conductivity type;
(J) forming a gate insulating film of the low breakdown voltage field effect transistor;
(K) After the step (j) , forming a gate electrode of the low breakdown voltage field effect transistor;
(L) After the step (k) , forming a nineteenth semiconductor region for the source and drain of the low breakdown voltage field effect transistor,
The eleventh semiconductor region of the second conductivity type for the drain of the eleventh high breakdown voltage field effect transistor is located on one side in the gate length direction of the active region where the channel region of the eleventh high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the separation part,
The eleventh semiconductor region of the second conductivity type for the source of the eleventh high breakdown voltage field effect transistor is located on the other side in the gate length direction of the active region where the channel region of the eleventh high breakdown voltage field effect transistor is disposed. Formed in a state adjacent to each other without a separation part,
The ninth semiconductor region of the second conductivity type for the drain of the eleventh high withstand voltage field effect transistor includes an eleventh semiconductor region of the second conductivity type for the drain and a channel region of the eleventh high withstand voltage field effect transistor. Formed to connect electrically,
The twelfth conductive type twelfth semiconductor region for the drain of the twelfth high breakdown voltage field effect transistor is located on one side in the gate length direction of the active region where the channel region of the twelfth high breakdown voltage field effect transistor is disposed. Formed in the active region arranged through the separation part,
The twelfth conductive type twelfth semiconductor region for the source of the twelfth high breakdown voltage field effect transistor is located on the other side in the gate length direction of the active region where the channel region of the twelfth high breakdown voltage field effect transistor is disposed. Formed in a state adjacent to each other without a separation part,
The tenth semiconductor region of the first conductivity type for the drain of the twelfth high breakdown voltage field effect transistor includes a twelfth semiconductor region of the first conductivity type for the drain and a channel region of the twelfth high breakdown voltage field effect transistor. Formed to connect electrically,
In forming the second conductive type ninth semiconductor region for the drain of the eleventh high breakdown voltage field effect transistor, the eighth semiconductor region is formed in the region where the channel region of the twelfth high breakdown voltage field effect transistor is disposed. Forming a fifteenth semiconductor region of the second conductivity type having a higher impurity concentration than
After forming the fifteenth semiconductor region in the step (d) and before the step (f) , a conductivity type opposite to that of the fifteenth semiconductor region is formed on the fifteenth semiconductor region. By introducing the impurity, a second conductivity type sixteenth semiconductor region having a lower impurity concentration than the fifteenth semiconductor region is formed on the fifteenth semiconductor region,
When forming the tenth semiconductor region of the first conductivity type for the drain of the twelfth high breakdown voltage field effect transistor, the seventh semiconductor region is formed in a region where the channel region of the eleventh high breakdown voltage field effect transistor is disposed. Forming a seventeenth semiconductor region of the first conductivity type having a higher impurity concentration than
After forming the seventeenth semiconductor region in the step (e) and before the step (f) , a conductivity type opposite to the seventeenth semiconductor region is formed on the seventeenth semiconductor region. By introducing an impurity, an eighteenth semiconductor region of a first conductivity type having a lower impurity concentration than the seventeenth semiconductor region is formed on the seventeenth semiconductor region;
A method of manufacturing a semiconductor device, comprising: forming gate electrodes of the eleventh and twelfth high breakdown voltage field effect transistors after forming a gate electrode of the low breakdown voltage field effect transistor.   10. The method of manufacturing a semiconductor device according to claim 7, wherein the fifteenth and seventeenth semiconductor regions are formed so as to extend from a main surface of the semiconductor substrate to a position deeper than the separation portion. A method of manufacturing a semiconductor device.   10. The method for manufacturing a semiconductor device according to claim 7, wherein the fifteenth and seventeenth semiconductor regions are formed so as to occupy half or more of the channel region. A method for manufacturing a semiconductor device, comprising: forming a high breakdown voltage field effect transistor and a low breakdown voltage field effect transistor having an operating voltage lower than that of the high breakdown voltage field effect transistor on a semiconductor substrate,
(A) forming a groove-type separation portion on the main surface of the semiconductor substrate, and forming a plurality of active regions defined by the separation portion;
(B) after the step (a) , forming a first conductivity type seventh semiconductor region on the semiconductor substrate;
(C) after the step (b) , forming a second conductivity type ninth semiconductor region for the drain of the high breakdown voltage field effect transistor in the seventh semiconductor region;
(D) After the step (b), a step of forming a first conductivity type seventeenth semiconductor region having a higher impurity concentration than the seventh semiconductor region in a region where the channel region of the high breakdown voltage field effect transistor is disposed. When,
(E) After the step (d), by introducing an impurity forming a conductivity type opposite to that of the seventeenth semiconductor region into the upper portion of the seventeenth semiconductor region, Forming an eighteenth semiconductor region of a first conductivity type having a lower impurity concentration than the seventeenth semiconductor region;
(F) After the step (c) and the step (e) , forming a gate insulating film of the high breakdown voltage field effect transistor on the semiconductor substrate;
(G) after the step (f) , forming a gate electrode of the high voltage field effect transistor on the gate insulating film of the high voltage field effect transistor;
(H) After the step (g), in the ninth semiconductor region, a semiconductor region having a higher impurity concentration than the ninth semiconductor region, the second conductivity type for the drain of the high breakdown voltage field effect transistor The semiconductor region having a higher impurity concentration than the ninth semiconductor region and having a second conductivity type for the source of the high breakdown voltage field effect transistor. Forming an eleventh semiconductor region;
(I) forming a gate insulating film of the low breakdown voltage field effect transistor;
(J) after the step (i) , forming a gate electrode of the low breakdown voltage field effect transistor;
(K) after the step (k) , forming a fifteenth semiconductor region for the source and drain of the low breakdown voltage field effect transistor,
The eleventh semiconductor region of the second conductivity type for the drain of the high withstand voltage field effect transistor is provided on one side in the gate length direction of the active region where the channel region of the high withstand voltage field effect transistor is disposed via the isolation part. Formed in the active region,
The eleventh semiconductor region of the second conductivity type for the source of the high breakdown voltage field effect transistor is interposed on the other side in the gate length direction of the active region where the channel region of the high breakdown voltage field effect transistor is disposed via the isolation portion. Without being adjacent,
Ninth semiconductor region of a second conductivity type for the drain of the high breakdown voltage field effect transistor is electrically the channel region of the eleventh semiconductor region and the front Symbol high breakdown voltage field effect transistor of the second conductivity type for said drain Formed to connect,
A method of manufacturing a semiconductor device, comprising: forming a gate electrode of the high breakdown voltage field effect transistor after forming a gate electrode of the low breakdown voltage field effect transistor.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the seventeenth semiconductor region is formed so as to extend from a main surface of the semiconductor substrate to a position deeper than the separation portion. Method. In the manufacturing method of the semiconductor device of Claim 7, 8, 9 or 12,
The step (a)
(A1) forming a groove in the semiconductor substrate;
(A2) depositing an insulating film on the semiconductor substrate including the trench;
(A3) removing the insulating film outside the trench, and embedding the insulating film in the trench to form a trench-type isolation part. In the manufacturing method of the semiconductor device of Claim 7, 8, 9 or 12,
The step (a)
(A1) forming a pattern of an oxidation-resistant insulating film in an active region on the semiconductor substrate;
(A2) forming a separation portion by forming an insulating film in a region having no pattern of the oxidation-resistant insulating film by performing a thermal oxidation process on the semiconductor substrate. A method for manufacturing a semiconductor device.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the seventeenth semiconductor region is formed so as to occupy more than half of the channel region.

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